2 * OMAP4 Power Management Routines
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/suspend.h>
15 #include <linux/module.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
21 #include "clockdomain.h"
22 #include "powerdomain.h"
26 struct powerdomain
*pwrdm
;
30 u32 saved_logic_state
;
32 struct list_head node
;
35 static LIST_HEAD(pwrst_list
);
38 static int omap4_pm_suspend(void)
40 struct power_state
*pwrst
;
42 u32 cpu_id
= smp_processor_id();
44 /* Save current powerdomain state */
45 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
46 pwrst
->saved_state
= pwrdm_read_next_pwrst(pwrst
->pwrdm
);
47 pwrst
->saved_logic_state
= pwrdm_read_logic_retst(pwrst
->pwrdm
);
50 /* Set targeted power domain states by suspend */
51 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
52 omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
53 pwrdm_set_logic_retst(pwrst
->pwrdm
, PWRDM_POWER_OFF
);
57 * For MPUSS to hit power domain retention(CSWR or OSWR),
58 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
59 * since CPU power domain CSWR is not supported by hardware
60 * Only master CPU follows suspend path. All other CPUs follow
61 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
62 * domain CSWR is not supported by hardware.
63 * More details can be found in OMAP4430 TRM section 4.3.4.2.
65 omap4_enter_lowpower(cpu_id
, PWRDM_POWER_OFF
);
67 /* Restore next powerdomain state */
68 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
69 state
= pwrdm_read_prev_pwrst(pwrst
->pwrdm
);
70 if (state
> pwrst
->next_state
) {
71 pr_info("Powerdomain (%s) didn't enter "
73 pwrst
->pwrdm
->name
, pwrst
->next_state
);
76 omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->saved_state
);
77 pwrdm_set_logic_retst(pwrst
->pwrdm
, pwrst
->saved_logic_state
);
80 pr_crit("Could not enter target state in pm_suspend\n");
82 pr_info("Successfully put all powerdomains to target state\n");
87 static int omap4_pm_enter(suspend_state_t suspend_state
)
91 switch (suspend_state
) {
92 case PM_SUSPEND_STANDBY
:
94 ret
= omap4_pm_suspend();
103 static int omap4_pm_begin(suspend_state_t state
)
109 static void omap4_pm_end(void)
115 static const struct platform_suspend_ops omap_pm_ops
= {
116 .begin
= omap4_pm_begin
,
118 .enter
= omap4_pm_enter
,
119 .valid
= suspend_valid_only_mem
,
121 #endif /* CONFIG_SUSPEND */
123 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *unused
)
125 struct power_state
*pwrst
;
131 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
132 * through hotplug path and CPU0 explicitly programmed
133 * further down in the code path
135 if (!strncmp(pwrdm
->name
, "cpu", 3))
139 * FIXME: Remove this check when core retention is supported
140 * Only MPUSS power domain is added in the list.
142 if (strcmp(pwrdm
->name
, "mpu_pwrdm"))
145 pwrst
= kmalloc(sizeof(struct power_state
), GFP_ATOMIC
);
149 pwrst
->pwrdm
= pwrdm
;
150 pwrst
->next_state
= PWRDM_POWER_RET
;
151 list_add(&pwrst
->node
, &pwrst_list
);
153 return omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
157 * omap_default_idle - OMAP4 default ilde routine.'
159 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
160 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
161 * by secondary CPU with CONFIG_CPUIDLE.
163 static void omap_default_idle(void)
173 * omap4_pm_init - Init routine for OMAP4 PM
175 * Initializes all powerdomain and clockdomain target states
176 * and all PRCM settings.
178 static int __init
omap4_pm_init(void)
181 struct clockdomain
*emif_clkdm
, *mpuss_clkdm
, *l3_1_clkdm
;
182 struct clockdomain
*ducati_clkdm
, *l3_2_clkdm
, *l4_per_clkdm
;
184 if (!cpu_is_omap44xx())
187 if (omap_rev() == OMAP4430_REV_ES1_0
) {
188 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
192 pr_err("Power Management for TI OMAP4.\n");
194 ret
= pwrdm_for_each(pwrdms_setup
, NULL
);
196 pr_err("Failed to setup powerdomains\n");
201 * The dynamic dependency between MPUSS -> MEMIF and
202 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
203 * expected. The hardware recommendation is to enable static
204 * dependencies for these to avoid system lock ups or random crashes.
206 mpuss_clkdm
= clkdm_lookup("mpuss_clkdm");
207 emif_clkdm
= clkdm_lookup("l3_emif_clkdm");
208 l3_1_clkdm
= clkdm_lookup("l3_1_clkdm");
209 l3_2_clkdm
= clkdm_lookup("l3_2_clkdm");
210 l4_per_clkdm
= clkdm_lookup("l4_per_clkdm");
211 ducati_clkdm
= clkdm_lookup("ducati_clkdm");
212 if ((!mpuss_clkdm
) || (!emif_clkdm
) || (!l3_1_clkdm
) ||
213 (!l3_2_clkdm
) || (!ducati_clkdm
) || (!l4_per_clkdm
))
216 ret
= clkdm_add_wkdep(mpuss_clkdm
, emif_clkdm
);
217 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l3_1_clkdm
);
218 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l3_2_clkdm
);
219 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l4_per_clkdm
);
220 ret
|= clkdm_add_wkdep(ducati_clkdm
, l3_1_clkdm
);
221 ret
|= clkdm_add_wkdep(ducati_clkdm
, l3_2_clkdm
);
223 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
224 "wakeup dependency\n");
228 ret
= omap4_mpuss_init();
230 pr_err("Failed to initialise OMAP4 MPUSS\n");
234 (void) clkdm_for_each(omap_pm_clkdms_setup
, NULL
);
236 #ifdef CONFIG_SUSPEND
237 suspend_set_ops(&omap_pm_ops
);
238 #endif /* CONFIG_SUSPEND */
240 /* Overwrite the default cpu_do_idle() */
241 arm_pm_idle
= omap_default_idle
;
248 late_initcall(omap4_pm_init
);