arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/irq.h>
  30 #include <linux/time.h>
  31 #include <linux/gpio.h>
  32
  33 #include <asm/mach/time.h>
  34 #include <asm/mach/irq.h>
  35 #include <asm/mach-types.h>
  36
  37 #include <plat/clock.h>
  38 #include <plat/sram.h>
  39 #include <plat/dma.h>
  40 #include <plat/board.h>
  41
  42 #include <mach/irqs.h>
  43
  44 #include "common.h"
  45 #include "prm2xxx_3xxx.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm2xxx_3xxx.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51 #include "control.h"
  52 #include "powerdomain.h"
  53 #include "clockdomain.h"
  54
  55 #ifdef CONFIG_SUSPEND
  56 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  57 static inline bool is_suspending(void)
  58 {
  59         return (suspend_state != PM_SUSPEND_ON);
  60 }
  61 #else
  62 static inline bool is_suspending(void)
  63 {
  64         return false;
  65 }
  66 #endif
  67
  68 static void (*omap2_sram_idle)(void);
  69 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  70                                   void __iomem *sdrc_power);
  71
  72 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  73 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  74
  75 static struct clk *osc_ck, *emul_ck;
  76
  77 static int omap2_fclks_active(void)
  78 {
  79         u32 f1, f2;
  80
  81         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  82         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  83
  84         return (f1 | f2) ? 1 : 0;
  85 }
  86
  87 static void omap2_enter_full_retention(void)
  88 {
  89         u32 l;
  90
  91         /* There is 1 reference hold for all children of the oscillator
  92          * clock, the following will remove it. If no one else uses the
  93          * oscillator itself it will be disabled if/when we enter retention
  94          * mode.
  95          */
  96         clk_disable(osc_ck);
  97
  98         /* Clear old wake-up events */
  99         /* REVISIT: These write to reserved bits? */
 100         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 101         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 102         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 103
 104         /*
 105          * Set MPU powerdomain's next power state to RETENTION;
 106          * preserve logic state during retention
 107          */
 108         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 109         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 110
 111         /* Workaround to kill USB */
 112         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 113         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 114
 115         omap2_gpio_prepare_for_idle(0);
 116
 117         /* One last check for pending IRQs to avoid extra latency due
 118          * to sleeping unnecessarily. */
 119         if (omap_irq_pending())
 120                 goto no_sleep;
 121
 122         /* Jump to SRAM suspend code */
 123         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 124                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 125                            OMAP_SDRC_REGADDR(SDRC_POWER));
 126
 127 no_sleep:
 128         omap2_gpio_resume_after_idle();
 129
 130         clk_enable(osc_ck);
 131
 132         /* clear CORE wake-up events */
 133         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 134         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 135
 136         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 137         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 138
 139         /* MPU domain wake events */
 140         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 141         if (l & 0x01)
 142                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 143                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 144         if (l & 0x20)
 145                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 146                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 147
 148         /* Mask future PRCM-to-MPU interrupts */
 149         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 150 }
 151
 152 static int omap2_i2c_active(void)
 153 {
 154         u32 l;
 155
 156         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 157         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 158 }
 159
 160 static int sti_console_enabled;
 161
 162 static int omap2_allow_mpu_retention(void)
 163 {
 164         u32 l;
 165
 166         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 167         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 168         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 169                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 170                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 171                 return 0;
 172         /* Check for UART3. */
 173         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 174         if (l & OMAP24XX_EN_UART3_MASK)
 175                 return 0;
 176         if (sti_console_enabled)
 177                 return 0;
 178
 179         return 1;
 180 }
 181
 182 static void omap2_enter_mpu_retention(void)
 183 {
 184         int only_idle = 0;
 185
 186         /* Putting MPU into the WFI state while a transfer is active
 187          * seems to cause the I2C block to timeout. Why? Good question. */
 188         if (omap2_i2c_active())
 189                 return;
 190
 191         /* The peripherals seem not to be able to wake up the MPU when
 192          * it is in retention mode. */
 193         if (omap2_allow_mpu_retention()) {
 194                 /* REVISIT: These write to reserved bits? */
 195                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 196                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 197                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 198
 199                 /* Try to enter MPU retention */
 200                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 201                                   OMAP_LOGICRETSTATE_MASK,
 202                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 203         } else {
 204                 /* Block MPU retention */
 205
 206                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 207                                                  OMAP2_PM_PWSTCTRL);
 208                 only_idle = 1;
 209         }
 210
 211         omap2_sram_idle();
 212 }
 213
 214 static int omap2_can_sleep(void)
 215 {
 216         if (omap2_fclks_active())
 217                 return 0;
 218         if (osc_ck->usecount > 1)
 219                 return 0;
 220         if (omap_dma_running())
 221                 return 0;
 222
 223         return 1;
 224 }
 225
 226 static void omap2_pm_idle(void)
 227 {
 228         local_fiq_disable();
 229
 230         if (!omap2_can_sleep()) {
 231                 if (omap_irq_pending())
 232                         goto out;
 233                 omap2_enter_mpu_retention();
 234                 goto out;
 235         }
 236
 237         if (omap_irq_pending())
 238                 goto out;
 239
 240         omap2_enter_full_retention();
 241
 242 out:
 243         local_fiq_enable();
 244 }
 245
 246 #ifdef CONFIG_SUSPEND
 247 static int omap2_pm_begin(suspend_state_t state)
 248 {
 249         disable_hlt();
 250         suspend_state = state;
 251         return 0;
 252 }
 253
 254 static int omap2_pm_enter(suspend_state_t state)
 255 {
 256         int ret = 0;
 257
 258         switch (state) {
 259         case PM_SUSPEND_STANDBY:
 260         case PM_SUSPEND_MEM:
 261                 omap2_enter_full_retention();
 262                 break;
 263         default:
 264                 ret = -EINVAL;
 265         }
 266
 267         return ret;
 268 }
 269
 270 static void omap2_pm_end(void)
 271 {
 272         suspend_state = PM_SUSPEND_ON;
 273         enable_hlt();
 274 }
 275
 276 static const struct platform_suspend_ops omap_pm_ops = {
 277         .begin          = omap2_pm_begin,
 278         .enter          = omap2_pm_enter,
 279         .end            = omap2_pm_end,
 280         .valid          = suspend_valid_only_mem,
 281 };
 282 #else
 283 static const struct platform_suspend_ops __initdata omap_pm_ops;
 284 #endif /* CONFIG_SUSPEND */
 285
 286 static void __init prcm_setup_regs(void)
 287 {
 288         int i, num_mem_banks;
 289         struct powerdomain *pwrdm;
 290
 291         /*
 292          * Enable autoidle
 293          * XXX This should be handled by hwmod code or PRCM init code
 294          */
 295         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 296                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 297
 298         /*
 299          * Set CORE powerdomain memory banks to retain their contents
 300          * during RETENTION
 301          */
 302         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 303         for (i = 0; i < num_mem_banks; i++)
 304                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 305
 306         /* Set CORE powerdomain's next power state to RETENTION */
 307         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 308
 309         /*
 310          * Set MPU powerdomain's next power state to RETENTION;
 311          * preserve logic state during retention
 312          */
 313         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 314         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 315
 316         /* Force-power down DSP, GFX powerdomains */
 317
 318         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 319         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 320         clkdm_sleep(dsp_clkdm);
 321
 322         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 323         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 324         clkdm_sleep(gfx_clkdm);
 325
 326         /* Enable hardware-supervised idle for all clkdms */
 327         clkdm_for_each(omap_pm_clkdms_setup, NULL);
 328         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 329
 330         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 331          * stabilisation */
 332         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 333                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 334
 335         /* Configure automatic voltage transition */
 336         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 337                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 338         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 339                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 340                                 OMAP24XX_MEMRETCTRL_MASK |
 341                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 342                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 343                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 344
 345         /* Enable wake-up events */
 346         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 347                                 WKUP_MOD, PM_WKEN);
 348 }
 349
 350 static int __init omap2_pm_init(void)
 351 {
 352         u32 l;
 353
 354         if (!cpu_is_omap24xx())
 355                 return -ENODEV;
 356
 357         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 358         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 359         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 360
 361         /* Look up important powerdomains */
 362
 363         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 364         if (!mpu_pwrdm)
 365                 pr_err("PM: mpu_pwrdm not found\n");
 366
 367         core_pwrdm = pwrdm_lookup("core_pwrdm");
 368         if (!core_pwrdm)
 369                 pr_err("PM: core_pwrdm not found\n");
 370
 371         /* Look up important clockdomains */
 372
 373         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 374         if (!mpu_clkdm)
 375                 pr_err("PM: mpu_clkdm not found\n");
 376
 377         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 378         if (!wkup_clkdm)
 379                 pr_err("PM: wkup_clkdm not found\n");
 380
 381         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 382         if (!dsp_clkdm)
 383                 pr_err("PM: dsp_clkdm not found\n");
 384
 385         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 386         if (!gfx_clkdm)
 387                 pr_err("PM: gfx_clkdm not found\n");
 388
 389
 390         osc_ck = clk_get(NULL, "osc_ck");
 391         if (IS_ERR(osc_ck)) {
 392                 printk(KERN_ERR "could not get osc_ck\n");
 393                 return -ENODEV;
 394         }
 395
 396         if (cpu_is_omap242x()) {
 397                 emul_ck = clk_get(NULL, "emul_ck");
 398                 if (IS_ERR(emul_ck)) {
 399                         printk(KERN_ERR "could not get emul_ck\n");
 400                         clk_put(osc_ck);
 401                         return -ENODEV;
 402                 }
 403         }
 404
 405         prcm_setup_regs();
 406
 407         /* Hack to prevent MPU retention when STI console is enabled. */
 408         {
 409                 const struct omap_sti_console_config *sti;
 410
 411                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 412                                       struct omap_sti_console_config);
 413                 if (sti != NULL && sti->enable)
 414                         sti_console_enabled = 1;
 415         }
 416
 417         /*
 418          * We copy the assembler sleep/wakeup routines to SRAM.
 419          * These routines need to be in SRAM as that's the only
 420          * memory the MPU can see when it wakes up.
 421          */
 422         if (cpu_is_omap24xx()) {
 423                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 424                                                  omap24xx_idle_loop_suspend_sz);
 425
 426                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 427                                                     omap24xx_cpu_suspend_sz);
 428         }
 429
 430         suspend_set_ops(&omap_pm_ops);
 431         arm_pm_idle = omap2_pm_idle;
 432
 433         return 0;
 434 }
 435
 436 late_initcall(omap2_pm_init);