arch/sh/kernel/cpu/sh4a/clock-sh7722.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
   3  *
   4  * SH7722 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <asm/clkdev.h>
  25 #include <asm/clock.h>
  26 #include <asm/hwblk.h>
  27 #include <cpu/sh7722.h>
  28
  29 /* SH7722 registers */
  30 #define FRQCR           0xa4150000
  31 #define VCLKCR          0xa4150004
  32 #define SCLKACR         0xa4150008
  33 #define SCLKBCR         0xa415000c
  34 #define IRDACLKCR       0xa4150018
  35 #define PLLCR           0xa4150024
  36 #define DLLFRQ          0xa4150050
  37
  38 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  39 static struct clk r_clk = {
  40         .name           = "rclk",
  41         .id             = -1,
  42         .rate           = 32768,
  43 };
  44
  45 /*
  46  * Default rate for the root input clock, reset this with clk_set_rate()
  47  * from the platform code.
  48  */
  49 struct clk extal_clk = {
  50         .name           = "extal",
  51         .id             = -1,
  52         .rate           = 33333333,
  53 };
  54
  55 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
  56 static unsigned long dll_recalc(struct clk *clk)
  57 {
  58         unsigned long mult;
  59
  60         if (__raw_readl(PLLCR) & 0x1000)
  61                 mult = __raw_readl(DLLFRQ);
  62         else
  63                 mult = 0;
  64
  65         return clk->parent->rate * mult;
  66 }
  67
  68 static struct clk_ops dll_clk_ops = {
  69         .recalc         = dll_recalc,
  70 };
  71
  72 static struct clk dll_clk = {
  73         .name           = "dll_clk",
  74         .id             = -1,
  75         .ops            = &dll_clk_ops,
  76         .parent         = &r_clk,
  77         .flags          = CLK_ENABLE_ON_INIT,
  78 };
  79
  80 static unsigned long pll_recalc(struct clk *clk)
  81 {
  82         unsigned long mult = 1;
  83         unsigned long div = 1;
  84
  85         if (__raw_readl(PLLCR) & 0x4000)
  86                 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
  87         else
  88                 div = 2;
  89
  90         return (clk->parent->rate * mult) / div;
  91 }
  92
  93 static struct clk_ops pll_clk_ops = {
  94         .recalc         = pll_recalc,
  95 };
  96
  97 static struct clk pll_clk = {
  98         .name           = "pll_clk",
  99         .id             = -1,
 100         .ops            = &pll_clk_ops,
 101         .flags          = CLK_ENABLE_ON_INIT,
 102 };
 103
 104 struct clk *main_clks[] = {
 105         &r_clk,
 106         &extal_clk,
 107         &dll_clk,
 108         &pll_clk,
 109 };
 110
 111 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 112 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 113
 114 static struct clk_div_mult_table div4_div_mult_table = {
 115         .divisors = divisors,
 116         .nr_divisors = ARRAY_SIZE(divisors),
 117         .multipliers = multipliers,
 118         .nr_multipliers = ARRAY_SIZE(multipliers),
 119 };
 120
 121 static struct clk_div4_table div4_table = {
 122         .div_mult_table = &div4_div_mult_table,
 123 };
 124
 125 #define DIV4(_reg, _bit, _mask, _flags) \
 126   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 127
 128 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 129
 130 struct clk div4_clks[DIV4_NR] = {
 131         [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
 132         [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
 133         [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
 134         [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
 135         [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
 136         [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
 137 };
 138
 139 enum { DIV4_IRDA, DIV4_ENABLE_NR };
 140
 141 struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
 142         [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
 143 };
 144
 145 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
 146
 147 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
 148         [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
 149         [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
 150 };
 151
 152 enum { DIV6_V, DIV6_NR };
 153
 154 struct clk div6_clks[DIV6_NR] = {
 155         [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 156 };
 157
 158 static struct clk mstp_clks[HWBLK_NR] = {
 159         SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
 160         SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
 161         SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
 162         SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
 163         SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
 164         SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
 165         SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
 166         SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
 167         SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
 168
 169         SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
 170         SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
 171
 172         SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
 173         SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
 174         SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
 175         SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
 176         SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
 177         SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
 178         SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
 179         SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
 180         SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
 181         SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
 182         SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
 183         SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
 184 };
 185
 186 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 187
 188 static struct clk_lookup lookups[] = {
 189         /* DIV4 clocks */
 190         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 191         CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
 192         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 193         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 194         CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
 195         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 196         CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
 197         CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
 198         CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
 199
 200         /* DIV6 clocks */
 201         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
 202
 203         /* MSTP clocks */
 204         CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
 205         CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
 206         {
 207                 /* TMU0 */
 208                 .dev_id         = "sh_tmu.0",
 209                 .con_id         = "tmu_fck",
 210                 .clk            = &mstp_clks[HWBLK_TMU],
 211         }, {
 212                 /* TMU1 */
 213                 .dev_id         = "sh_tmu.1",
 214                 .con_id         = "tmu_fck",
 215                 .clk            = &mstp_clks[HWBLK_TMU],
 216         }, {
 217                 /* TMU2 */
 218                 .dev_id         = "sh_tmu.2",
 219                 .con_id         = "tmu_fck",
 220                 .clk            = &mstp_clks[HWBLK_TMU],
 221         },
 222         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
 223         CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
 224         CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
 225         {
 226                 /* SCIF0 */
 227                 .dev_id         = "sh-sci.0",
 228                 .con_id         = "sci_fck",
 229                 .clk            = &mstp_clks[HWBLK_SCIF0],
 230         }, {
 231                 /* SCIF1 */
 232                 .dev_id         = "sh-sci.1",
 233                 .con_id         = "sci_fck",
 234                 .clk            = &mstp_clks[HWBLK_SCIF1],
 235         }, {
 236                 /* SCIF2 */
 237                 .dev_id         = "sh-sci.2",
 238                 .con_id         = "sci_fck",
 239                 .clk            = &mstp_clks[HWBLK_SCIF2],
 240         },
 241         CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
 242         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
 243         CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
 244         CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
 245         CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
 246         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
 247         CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
 248         CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
 249         CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
 250         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
 251         CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
 252         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
 253         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
 254         CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 255 };
 256
 257 int __init arch_clk_init(void)
 258 {
 259         int k, ret = 0;
 260
 261         /* autodetect extal or dll configuration */
 262         if (__raw_readl(PLLCR) & 0x1000)
 263                 pll_clk.parent = &dll_clk;
 264         else
 265                 pll_clk.parent = &extal_clk;
 266
 267         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 268                 ret = clk_register(main_clks[k]);
 269
 270         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 271
 272         if (!ret)
 273                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 274
 275         if (!ret)
 276                 ret = sh_clk_div4_enable_register(div4_enable_clks,
 277                                         DIV4_ENABLE_NR, &div4_table);
 278
 279         if (!ret)
 280                 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
 281                                         DIV4_REPARENT_NR, &div4_table);
 282
 283         if (!ret)
 284                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 285
 286         if (!ret)
 287                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 288
 289         return ret;
 290 }