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omap-serial: Use default clock speed (48Mhz) if not specified
[linux-2.6/cjktty.git] / drivers / tty / serial / omap-serial.c
blobc5b545f19a164025d2c2bd878970905b032bc7ac
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41
42 #include <plat/dma.h>
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
45
46 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
47
48 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
49
50 /* Forward declaration of functions */
51 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
52 static void serial_omap_rxdma_poll(unsigned long uart_no);
53 static int serial_omap_start_rxdma(struct uart_omap_port *up);
54 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
55
56 static struct workqueue_struct *serial_omap_uart_wq;
57
58 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
59 {
60 offset <<= up->port.regshift;
61 return readw(up->port.membase + offset);
62 }
63
64 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
65 {
66 offset <<= up->port.regshift;
67 writew(value, up->port.membase + offset);
68 }
69
70 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
71 {
72 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
73 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
74 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
75 serial_out(up, UART_FCR, 0);
76 }
77
78 /*
79 * serial_omap_get_divisor - calculate divisor value
80 * @port: uart port info
81 * @baud: baudrate for which divisor needs to be calculated.
82 *
83 * We have written our own function to get the divisor so as to support
84 * 13x mode. 3Mbps Baudrate as an different divisor.
85 * Reference OMAP TRM Chapter 17:
86 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
87 * referring to oversampling - divisor value
88 * baudrate 460,800 to 3,686,400 all have divisor 13
89 * except 3,000,000 which has divisor value 16
90 */
91 static unsigned int
92 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
93 {
94 unsigned int divisor;
95
96 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
97 divisor = 13;
98 else
99 divisor = 16;
100 return port->uartclk/(baud * divisor);
101 }
102
103 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
104 {
105 if (up->uart_dma.rx_dma_used) {
106 del_timer(&up->uart_dma.rx_timer);
107 omap_stop_dma(up->uart_dma.rx_dma_channel);
108 omap_free_dma(up->uart_dma.rx_dma_channel);
109 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
110 up->uart_dma.rx_dma_used = false;
111 pm_runtime_mark_last_busy(&up->pdev->dev);
112 pm_runtime_put_autosuspend(&up->pdev->dev);
113 }
114 }
115
116 static void serial_omap_enable_ms(struct uart_port *port)
117 {
118 struct uart_omap_port *up = (struct uart_omap_port *)port;
119
120 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
121
122 pm_runtime_get_sync(&up->pdev->dev);
123 up->ier |= UART_IER_MSI;
124 serial_out(up, UART_IER, up->ier);
125 pm_runtime_put(&up->pdev->dev);
126 }
127
128 static void serial_omap_stop_tx(struct uart_port *port)
129 {
130 struct uart_omap_port *up = (struct uart_omap_port *)port;
131
132 if (up->use_dma &&
133 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
134 /*
135 * Check if dma is still active. If yes do nothing,
136 * return. Else stop dma
137 */
138 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
139 return;
140 omap_stop_dma(up->uart_dma.tx_dma_channel);
141 omap_free_dma(up->uart_dma.tx_dma_channel);
142 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
143 pm_runtime_mark_last_busy(&up->pdev->dev);
144 pm_runtime_put_autosuspend(&up->pdev->dev);
145 }
146
147 pm_runtime_get_sync(&up->pdev->dev);
148 if (up->ier & UART_IER_THRI) {
149 up->ier &= ~UART_IER_THRI;
150 serial_out(up, UART_IER, up->ier);
151 }
152
153 pm_runtime_mark_last_busy(&up->pdev->dev);
154 pm_runtime_put_autosuspend(&up->pdev->dev);
155 }
156
157 static void serial_omap_stop_rx(struct uart_port *port)
158 {
159 struct uart_omap_port *up = (struct uart_omap_port *)port;
160
161 pm_runtime_get_sync(&up->pdev->dev);
162 if (up->use_dma)
163 serial_omap_stop_rxdma(up);
164 up->ier &= ~UART_IER_RLSI;
165 up->port.read_status_mask &= ~UART_LSR_DR;
166 serial_out(up, UART_IER, up->ier);
167 pm_runtime_mark_last_busy(&up->pdev->dev);
168 pm_runtime_put_autosuspend(&up->pdev->dev);
169 }
170
171 static inline void receive_chars(struct uart_omap_port *up,
172 unsigned int *status)
173 {
174 struct tty_struct *tty = up->port.state->port.tty;
175 unsigned int flag, lsr = *status;
176 unsigned char ch = 0;
177 int max_count = 256;
178
179 do {
180 if (likely(lsr & UART_LSR_DR))
181 ch = serial_in(up, UART_RX);
182 flag = TTY_NORMAL;
183 up->port.icount.rx++;
184
185 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
186 /*
187 * For statistics only
188 */
189 if (lsr & UART_LSR_BI) {
190 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
191 up->port.icount.brk++;
192 /*
193 * We do the SysRQ and SAK checking
194 * here because otherwise the break
195 * may get masked by ignore_status_mask
196 * or read_status_mask.
197 */
198 if (uart_handle_break(&up->port))
199 goto ignore_char;
200 } else if (lsr & UART_LSR_PE) {
201 up->port.icount.parity++;
202 } else if (lsr & UART_LSR_FE) {
203 up->port.icount.frame++;
204 }
205
206 if (lsr & UART_LSR_OE)
207 up->port.icount.overrun++;
208
209 /*
210 * Mask off conditions which should be ignored.
211 */
212 lsr &= up->port.read_status_mask;
213
214 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
215 if (up->port.line == up->port.cons->index) {
216 /* Recover the break flag from console xmit */
217 lsr |= up->lsr_break_flag;
218 }
219 #endif
220 if (lsr & UART_LSR_BI)
221 flag = TTY_BREAK;
222 else if (lsr & UART_LSR_PE)
223 flag = TTY_PARITY;
224 else if (lsr & UART_LSR_FE)
225 flag = TTY_FRAME;
226 }
227
228 if (uart_handle_sysrq_char(&up->port, ch))
229 goto ignore_char;
230 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
231 ignore_char:
232 lsr = serial_in(up, UART_LSR);
233 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
234 spin_unlock(&up->port.lock);
235 tty_flip_buffer_push(tty);
236 spin_lock(&up->port.lock);
237 }
238
239 static void transmit_chars(struct uart_omap_port *up)
240 {
241 struct circ_buf *xmit = &up->port.state->xmit;
242 int count;
243
244 if (up->port.x_char) {
245 serial_out(up, UART_TX, up->port.x_char);
246 up->port.icount.tx++;
247 up->port.x_char = 0;
248 return;
249 }
250 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
251 serial_omap_stop_tx(&up->port);
252 return;
253 }
254 count = up->port.fifosize / 4;
255 do {
256 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
257 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
258 up->port.icount.tx++;
259 if (uart_circ_empty(xmit))
260 break;
261 } while (--count > 0);
262
263 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
264 uart_write_wakeup(&up->port);
265
266 if (uart_circ_empty(xmit))
267 serial_omap_stop_tx(&up->port);
268 }
269
270 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
271 {
272 if (!(up->ier & UART_IER_THRI)) {
273 up->ier |= UART_IER_THRI;
274 serial_out(up, UART_IER, up->ier);
275 }
276 }
277
278 static void serial_omap_start_tx(struct uart_port *port)
279 {
280 struct uart_omap_port *up = (struct uart_omap_port *)port;
281 struct circ_buf *xmit;
282 unsigned int start;
283 int ret = 0;
284
285 if (!up->use_dma) {
286 pm_runtime_get_sync(&up->pdev->dev);
287 serial_omap_enable_ier_thri(up);
288 pm_runtime_mark_last_busy(&up->pdev->dev);
289 pm_runtime_put_autosuspend(&up->pdev->dev);
290 return;
291 }
292
293 if (up->uart_dma.tx_dma_used)
294 return;
295
296 xmit = &up->port.state->xmit;
297
298 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
299 pm_runtime_get_sync(&up->pdev->dev);
300 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
301 "UART Tx DMA",
302 (void *)uart_tx_dma_callback, up,
303 &(up->uart_dma.tx_dma_channel));
304
305 if (ret < 0) {
306 serial_omap_enable_ier_thri(up);
307 return;
308 }
309 }
310 spin_lock(&(up->uart_dma.tx_lock));
311 up->uart_dma.tx_dma_used = true;
312 spin_unlock(&(up->uart_dma.tx_lock));
313
314 start = up->uart_dma.tx_buf_dma_phys +
315 (xmit->tail & (UART_XMIT_SIZE - 1));
316
317 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
318 /*
319 * It is a circular buffer. See if the buffer has wounded back.
320 * If yes it will have to be transferred in two separate dma
321 * transfers
322 */
323 if (start + up->uart_dma.tx_buf_size >=
324 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
325 up->uart_dma.tx_buf_size =
326 (up->uart_dma.tx_buf_dma_phys +
327 UART_XMIT_SIZE) - start;
328
329 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
330 OMAP_DMA_AMODE_CONSTANT,
331 up->uart_dma.uart_base, 0, 0);
332 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
333 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
334 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
335 OMAP_DMA_DATA_TYPE_S8,
336 up->uart_dma.tx_buf_size, 1,
337 OMAP_DMA_SYNC_ELEMENT,
338 up->uart_dma.uart_dma_tx, 0);
339 /* FIXME: Cache maintenance needed here? */
340 omap_start_dma(up->uart_dma.tx_dma_channel);
341 }
342
343 static unsigned int check_modem_status(struct uart_omap_port *up)
344 {
345 unsigned int status;
346
347 status = serial_in(up, UART_MSR);
348 status |= up->msr_saved_flags;
349 up->msr_saved_flags = 0;
350 if ((status & UART_MSR_ANY_DELTA) == 0)
351 return status;
352
353 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
354 up->port.state != NULL) {
355 if (status & UART_MSR_TERI)
356 up->port.icount.rng++;
357 if (status & UART_MSR_DDSR)
358 up->port.icount.dsr++;
359 if (status & UART_MSR_DDCD)
360 uart_handle_dcd_change
361 (&up->port, status & UART_MSR_DCD);
362 if (status & UART_MSR_DCTS)
363 uart_handle_cts_change
364 (&up->port, status & UART_MSR_CTS);
365 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
366 }
367
368 return status;
369 }
370
371 /**
372 * serial_omap_irq() - This handles the interrupt from one port
373 * @irq: uart port irq number
374 * @dev_id: uart port info
375 */
376 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
377 {
378 struct uart_omap_port *up = dev_id;
379 unsigned int iir, lsr;
380 unsigned long flags;
381
382 pm_runtime_get_sync(&up->pdev->dev);
383 iir = serial_in(up, UART_IIR);
384 if (iir & UART_IIR_NO_INT) {
385 pm_runtime_mark_last_busy(&up->pdev->dev);
386 pm_runtime_put_autosuspend(&up->pdev->dev);
387 return IRQ_NONE;
388 }
389
390 spin_lock_irqsave(&up->port.lock, flags);
391 lsr = serial_in(up, UART_LSR);
392 if (iir & UART_IIR_RLSI) {
393 if (!up->use_dma) {
394 if (lsr & UART_LSR_DR)
395 receive_chars(up, &lsr);
396 } else {
397 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
398 serial_out(up, UART_IER, up->ier);
399 if ((serial_omap_start_rxdma(up) != 0) &&
400 (lsr & UART_LSR_DR))
401 receive_chars(up, &lsr);
402 }
403 }
404
405 check_modem_status(up);
406 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
407 transmit_chars(up);
408
409 spin_unlock_irqrestore(&up->port.lock, flags);
410 pm_runtime_mark_last_busy(&up->pdev->dev);
411 pm_runtime_put_autosuspend(&up->pdev->dev);
412
413 up->port_activity = jiffies;
414 return IRQ_HANDLED;
415 }
416
417 static unsigned int serial_omap_tx_empty(struct uart_port *port)
418 {
419 struct uart_omap_port *up = (struct uart_omap_port *)port;
420 unsigned long flags = 0;
421 unsigned int ret = 0;
422
423 pm_runtime_get_sync(&up->pdev->dev);
424 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
425 spin_lock_irqsave(&up->port.lock, flags);
426 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
427 spin_unlock_irqrestore(&up->port.lock, flags);
428 pm_runtime_put(&up->pdev->dev);
429 return ret;
430 }
431
432 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
433 {
434 struct uart_omap_port *up = (struct uart_omap_port *)port;
435 unsigned char status;
436 unsigned int ret = 0;
437
438 pm_runtime_get_sync(&up->pdev->dev);
439 status = check_modem_status(up);
440 pm_runtime_put(&up->pdev->dev);
441
442 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
443
444 if (status & UART_MSR_DCD)
445 ret |= TIOCM_CAR;
446 if (status & UART_MSR_RI)
447 ret |= TIOCM_RNG;
448 if (status & UART_MSR_DSR)
449 ret |= TIOCM_DSR;
450 if (status & UART_MSR_CTS)
451 ret |= TIOCM_CTS;
452 return ret;
453 }
454
455 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
456 {
457 struct uart_omap_port *up = (struct uart_omap_port *)port;
458 unsigned char mcr = 0;
459
460 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
461 if (mctrl & TIOCM_RTS)
462 mcr |= UART_MCR_RTS;
463 if (mctrl & TIOCM_DTR)
464 mcr |= UART_MCR_DTR;
465 if (mctrl & TIOCM_OUT1)
466 mcr |= UART_MCR_OUT1;
467 if (mctrl & TIOCM_OUT2)
468 mcr |= UART_MCR_OUT2;
469 if (mctrl & TIOCM_LOOP)
470 mcr |= UART_MCR_LOOP;
471
472 pm_runtime_get_sync(&up->pdev->dev);
473 up->mcr = serial_in(up, UART_MCR);
474 up->mcr |= mcr;
475 serial_out(up, UART_MCR, up->mcr);
476 pm_runtime_put(&up->pdev->dev);
477 }
478
479 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
480 {
481 struct uart_omap_port *up = (struct uart_omap_port *)port;
482 unsigned long flags = 0;
483
484 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
485 pm_runtime_get_sync(&up->pdev->dev);
486 spin_lock_irqsave(&up->port.lock, flags);
487 if (break_state == -1)
488 up->lcr |= UART_LCR_SBC;
489 else
490 up->lcr &= ~UART_LCR_SBC;
491 serial_out(up, UART_LCR, up->lcr);
492 spin_unlock_irqrestore(&up->port.lock, flags);
493 pm_runtime_put(&up->pdev->dev);
494 }
495
496 static int serial_omap_startup(struct uart_port *port)
497 {
498 struct uart_omap_port *up = (struct uart_omap_port *)port;
499 unsigned long flags = 0;
500 int retval;
501
502 /*
503 * Allocate the IRQ
504 */
505 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
506 up->name, up);
507 if (retval)
508 return retval;
509
510 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
511
512 pm_runtime_get_sync(&up->pdev->dev);
513 /*
514 * Clear the FIFO buffers and disable them.
515 * (they will be reenabled in set_termios())
516 */
517 serial_omap_clear_fifos(up);
518 /* For Hardware flow control */
519 serial_out(up, UART_MCR, UART_MCR_RTS);
520
521 /*
522 * Clear the interrupt registers.
523 */
524 (void) serial_in(up, UART_LSR);
525 if (serial_in(up, UART_LSR) & UART_LSR_DR)
526 (void) serial_in(up, UART_RX);
527 (void) serial_in(up, UART_IIR);
528 (void) serial_in(up, UART_MSR);
529
530 /*
531 * Now, initialize the UART
532 */
533 serial_out(up, UART_LCR, UART_LCR_WLEN8);
534 spin_lock_irqsave(&up->port.lock, flags);
535 /*
536 * Most PC uarts need OUT2 raised to enable interrupts.
537 */
538 up->port.mctrl |= TIOCM_OUT2;
539 serial_omap_set_mctrl(&up->port, up->port.mctrl);
540 spin_unlock_irqrestore(&up->port.lock, flags);
541
542 up->msr_saved_flags = 0;
543 if (up->use_dma) {
544 free_page((unsigned long)up->port.state->xmit.buf);
545 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
546 UART_XMIT_SIZE,
547 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
548 0);
549 init_timer(&(up->uart_dma.rx_timer));
550 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
551 up->uart_dma.rx_timer.data = up->port.line;
552 /* Currently the buffer size is 4KB. Can increase it */
553 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
554 up->uart_dma.rx_buf_size,
555 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
556 }
557 /*
558 * Finally, enable interrupts. Note: Modem status interrupts
559 * are set via set_termios(), which will be occurring imminently
560 * anyway, so we don't enable them here.
561 */
562 up->ier = UART_IER_RLSI | UART_IER_RDI;
563 serial_out(up, UART_IER, up->ier);
564
565 /* Enable module level wake up */
566 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
567
568 pm_runtime_mark_last_busy(&up->pdev->dev);
569 pm_runtime_put_autosuspend(&up->pdev->dev);
570 up->port_activity = jiffies;
571 return 0;
572 }
573
574 static void serial_omap_shutdown(struct uart_port *port)
575 {
576 struct uart_omap_port *up = (struct uart_omap_port *)port;
577 unsigned long flags = 0;
578
579 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
580
581 pm_runtime_get_sync(&up->pdev->dev);
582 /*
583 * Disable interrupts from this port
584 */
585 up->ier = 0;
586 serial_out(up, UART_IER, 0);
587
588 spin_lock_irqsave(&up->port.lock, flags);
589 up->port.mctrl &= ~TIOCM_OUT2;
590 serial_omap_set_mctrl(&up->port, up->port.mctrl);
591 spin_unlock_irqrestore(&up->port.lock, flags);
592
593 /*
594 * Disable break condition and FIFOs
595 */
596 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
597 serial_omap_clear_fifos(up);
598
599 /*
600 * Read data port to reset things, and then free the irq
601 */
602 if (serial_in(up, UART_LSR) & UART_LSR_DR)
603 (void) serial_in(up, UART_RX);
604 if (up->use_dma) {
605 dma_free_coherent(up->port.dev,
606 UART_XMIT_SIZE, up->port.state->xmit.buf,
607 up->uart_dma.tx_buf_dma_phys);
608 up->port.state->xmit.buf = NULL;
609 serial_omap_stop_rx(port);
610 dma_free_coherent(up->port.dev,
611 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
612 up->uart_dma.rx_buf_dma_phys);
613 up->uart_dma.rx_buf = NULL;
614 }
615
616 pm_runtime_put(&up->pdev->dev);
617 free_irq(up->port.irq, up);
618 }
619
620 static inline void
621 serial_omap_configure_xonxoff
622 (struct uart_omap_port *up, struct ktermios *termios)
623 {
624 up->lcr = serial_in(up, UART_LCR);
625 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
626 up->efr = serial_in(up, UART_EFR);
627 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
628
629 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
630 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
631
632 /* clear SW control mode bits */
633 up->efr &= OMAP_UART_SW_CLR;
634
635 /*
636 * IXON Flag:
637 * Enable XON/XOFF flow control on output.
638 * Transmit XON1, XOFF1
639 */
640 if (termios->c_iflag & IXON)
641 up->efr |= OMAP_UART_SW_TX;
642
643 /*
644 * IXOFF Flag:
645 * Enable XON/XOFF flow control on input.
646 * Receiver compares XON1, XOFF1.
647 */
648 if (termios->c_iflag & IXOFF)
649 up->efr |= OMAP_UART_SW_RX;
650
651 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
652 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
653
654 up->mcr = serial_in(up, UART_MCR);
655
656 /*
657 * IXANY Flag:
658 * Enable any character to restart output.
659 * Operation resumes after receiving any
660 * character after recognition of the XOFF character
661 */
662 if (termios->c_iflag & IXANY)
663 up->mcr |= UART_MCR_XONANY;
664
665 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
666 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
667 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
668 /* Enable special char function UARTi.EFR_REG[5] and
669 * load the new software flow control mode IXON or IXOFF
670 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
671 */
672 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
673 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
674
675 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
676 serial_out(up, UART_LCR, up->lcr);
677 }
678
679 static void serial_omap_uart_qos_work(struct work_struct *work)
680 {
681 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
682 qos_work);
683
684 pm_qos_update_request(&up->pm_qos_request, up->latency);
685 }
686
687 static void
688 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
689 struct ktermios *old)
690 {
691 struct uart_omap_port *up = (struct uart_omap_port *)port;
692 unsigned char cval = 0;
693 unsigned char efr = 0;
694 unsigned long flags = 0;
695 unsigned int baud, quot;
696
697 switch (termios->c_cflag & CSIZE) {
698 case CS5:
699 cval = UART_LCR_WLEN5;
700 break;
701 case CS6:
702 cval = UART_LCR_WLEN6;
703 break;
704 case CS7:
705 cval = UART_LCR_WLEN7;
706 break;
707 default:
708 case CS8:
709 cval = UART_LCR_WLEN8;
710 break;
711 }
712
713 if (termios->c_cflag & CSTOPB)
714 cval |= UART_LCR_STOP;
715 if (termios->c_cflag & PARENB)
716 cval |= UART_LCR_PARITY;
717 if (!(termios->c_cflag & PARODD))
718 cval |= UART_LCR_EPAR;
719
720 /*
721 * Ask the core to calculate the divisor for us.
722 */
723
724 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
725 quot = serial_omap_get_divisor(port, baud);
726
727 /* calculate wakeup latency constraint */
728 up->calc_latency = (1000000 * up->port.fifosize) /
729 (1000 * baud / 8);
730 up->latency = up->calc_latency;
731 schedule_work(&up->qos_work);
732
733 up->dll = quot & 0xff;
734 up->dlh = quot >> 8;
735 up->mdr1 = UART_OMAP_MDR1_DISABLE;
736
737 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
738 UART_FCR_ENABLE_FIFO;
739 if (up->use_dma)
740 up->fcr |= UART_FCR_DMA_SELECT;
741
742 /*
743 * Ok, we're now changing the port state. Do it with
744 * interrupts disabled.
745 */
746 pm_runtime_get_sync(&up->pdev->dev);
747 spin_lock_irqsave(&up->port.lock, flags);
748
749 /*
750 * Update the per-port timeout.
751 */
752 uart_update_timeout(port, termios->c_cflag, baud);
753
754 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
755 if (termios->c_iflag & INPCK)
756 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
757 if (termios->c_iflag & (BRKINT | PARMRK))
758 up->port.read_status_mask |= UART_LSR_BI;
759
760 /*
761 * Characters to ignore
762 */
763 up->port.ignore_status_mask = 0;
764 if (termios->c_iflag & IGNPAR)
765 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
766 if (termios->c_iflag & IGNBRK) {
767 up->port.ignore_status_mask |= UART_LSR_BI;
768 /*
769 * If we're ignoring parity and break indicators,
770 * ignore overruns too (for real raw support).
771 */
772 if (termios->c_iflag & IGNPAR)
773 up->port.ignore_status_mask |= UART_LSR_OE;
774 }
775
776 /*
777 * ignore all characters if CREAD is not set
778 */
779 if ((termios->c_cflag & CREAD) == 0)
780 up->port.ignore_status_mask |= UART_LSR_DR;
781
782 /*
783 * Modem status interrupts
784 */
785 up->ier &= ~UART_IER_MSI;
786 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
787 up->ier |= UART_IER_MSI;
788 serial_out(up, UART_IER, up->ier);
789 serial_out(up, UART_LCR, cval); /* reset DLAB */
790 up->lcr = cval;
791 up->scr = OMAP_UART_SCR_TX_EMPTY;
792
793 /* FIFOs and DMA Settings */
794
795 /* FCR can be changed only when the
796 * baud clock is not running
797 * DLL_REG and DLH_REG set to 0.
798 */
799 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
800 serial_out(up, UART_DLL, 0);
801 serial_out(up, UART_DLM, 0);
802 serial_out(up, UART_LCR, 0);
803
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
805
806 up->efr = serial_in(up, UART_EFR);
807 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
808
809 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
810 up->mcr = serial_in(up, UART_MCR);
811 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
812 /* FIFO ENABLE, DMA MODE */
813 serial_out(up, UART_FCR, up->fcr);
814 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
815
816 if (up->use_dma) {
817 serial_out(up, UART_TI752_TLR, 0);
818 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
819 }
820
821 serial_out(up, UART_OMAP_SCR, up->scr);
822
823 serial_out(up, UART_EFR, up->efr);
824 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
825 serial_out(up, UART_MCR, up->mcr);
826
827 /* Protocol, Baud Rate, and Interrupt Settings */
828
829 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
830 serial_omap_mdr1_errataset(up, up->mdr1);
831 else
832 serial_out(up, UART_OMAP_MDR1, up->mdr1);
833
834 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
835
836 up->efr = serial_in(up, UART_EFR);
837 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
838
839 serial_out(up, UART_LCR, 0);
840 serial_out(up, UART_IER, 0);
841 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
842
843 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
844 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
845
846 serial_out(up, UART_LCR, 0);
847 serial_out(up, UART_IER, up->ier);
848 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
849
850 serial_out(up, UART_EFR, up->efr);
851 serial_out(up, UART_LCR, cval);
852
853 if (baud > 230400 && baud != 3000000)
854 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
855 else
856 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
857
858 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
859 serial_omap_mdr1_errataset(up, up->mdr1);
860 else
861 serial_out(up, UART_OMAP_MDR1, up->mdr1);
862
863 /* Hardware Flow Control Configuration */
864
865 if (termios->c_cflag & CRTSCTS) {
866 efr |= (UART_EFR_CTS | UART_EFR_RTS);
867 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
868
869 up->mcr = serial_in(up, UART_MCR);
870 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
871
872 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
873 up->efr = serial_in(up, UART_EFR);
874 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
875
876 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
877 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
878 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
879 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
880 serial_out(up, UART_LCR, cval);
881 }
882
883 serial_omap_set_mctrl(&up->port, up->port.mctrl);
884 /* Software Flow Control Configuration */
885 serial_omap_configure_xonxoff(up, termios);
886
887 spin_unlock_irqrestore(&up->port.lock, flags);
888 pm_runtime_put(&up->pdev->dev);
889 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
890 }
891
892 static void
893 serial_omap_pm(struct uart_port *port, unsigned int state,
894 unsigned int oldstate)
895 {
896 struct uart_omap_port *up = (struct uart_omap_port *)port;
897 unsigned char efr;
898
899 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
900
901 pm_runtime_get_sync(&up->pdev->dev);
902 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
903 efr = serial_in(up, UART_EFR);
904 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
905 serial_out(up, UART_LCR, 0);
906
907 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
908 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
909 serial_out(up, UART_EFR, efr);
910 serial_out(up, UART_LCR, 0);
911
912 if (!device_may_wakeup(&up->pdev->dev)) {
913 if (!state)
914 pm_runtime_forbid(&up->pdev->dev);
915 else
916 pm_runtime_allow(&up->pdev->dev);
917 }
918
919 pm_runtime_put(&up->pdev->dev);
920 }
921
922 static void serial_omap_release_port(struct uart_port *port)
923 {
924 dev_dbg(port->dev, "serial_omap_release_port+\n");
925 }
926
927 static int serial_omap_request_port(struct uart_port *port)
928 {
929 dev_dbg(port->dev, "serial_omap_request_port+\n");
930 return 0;
931 }
932
933 static void serial_omap_config_port(struct uart_port *port, int flags)
934 {
935 struct uart_omap_port *up = (struct uart_omap_port *)port;
936
937 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
938 up->port.line);
939 up->port.type = PORT_OMAP;
940 }
941
942 static int
943 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
944 {
945 /* we don't want the core code to modify any port params */
946 dev_dbg(port->dev, "serial_omap_verify_port+\n");
947 return -EINVAL;
948 }
949
950 static const char *
951 serial_omap_type(struct uart_port *port)
952 {
953 struct uart_omap_port *up = (struct uart_omap_port *)port;
954
955 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
956 return up->name;
957 }
958
959 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
960
961 static inline void wait_for_xmitr(struct uart_omap_port *up)
962 {
963 unsigned int status, tmout = 10000;
964
965 /* Wait up to 10ms for the character(s) to be sent. */
966 do {
967 status = serial_in(up, UART_LSR);
968
969 if (status & UART_LSR_BI)
970 up->lsr_break_flag = UART_LSR_BI;
971
972 if (--tmout == 0)
973 break;
974 udelay(1);
975 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
976
977 /* Wait up to 1s for flow control if necessary */
978 if (up->port.flags & UPF_CONS_FLOW) {
979 tmout = 1000000;
980 for (tmout = 1000000; tmout; tmout--) {
981 unsigned int msr = serial_in(up, UART_MSR);
982
983 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
984 if (msr & UART_MSR_CTS)
985 break;
986
987 udelay(1);
988 }
989 }
990 }
991
992 #ifdef CONFIG_CONSOLE_POLL
993
994 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
995 {
996 struct uart_omap_port *up = (struct uart_omap_port *)port;
997
998 pm_runtime_get_sync(&up->pdev->dev);
999 wait_for_xmitr(up);
1000 serial_out(up, UART_TX, ch);
1001 pm_runtime_put(&up->pdev->dev);
1002 }
1003
1004 static int serial_omap_poll_get_char(struct uart_port *port)
1005 {
1006 struct uart_omap_port *up = (struct uart_omap_port *)port;
1007 unsigned int status;
1008
1009 pm_runtime_get_sync(&up->pdev->dev);
1010 status = serial_in(up, UART_LSR);
1011 if (!(status & UART_LSR_DR))
1012 return NO_POLL_CHAR;
1013
1014 status = serial_in(up, UART_RX);
1015 pm_runtime_put(&up->pdev->dev);
1016 return status;
1017 }
1018
1019 #endif /* CONFIG_CONSOLE_POLL */
1020
1021 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1022
1023 static struct uart_omap_port *serial_omap_console_ports[4];
1024
1025 static struct uart_driver serial_omap_reg;
1026
1027 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1028 {
1029 struct uart_omap_port *up = (struct uart_omap_port *)port;
1030
1031 wait_for_xmitr(up);
1032 serial_out(up, UART_TX, ch);
1033 }
1034
1035 static void
1036 serial_omap_console_write(struct console *co, const char *s,
1037 unsigned int count)
1038 {
1039 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1040 unsigned long flags;
1041 unsigned int ier;
1042 int locked = 1;
1043
1044 pm_runtime_get_sync(&up->pdev->dev);
1045
1046 local_irq_save(flags);
1047 if (up->port.sysrq)
1048 locked = 0;
1049 else if (oops_in_progress)
1050 locked = spin_trylock(&up->port.lock);
1051 else
1052 spin_lock(&up->port.lock);
1053
1054 /*
1055 * First save the IER then disable the interrupts
1056 */
1057 ier = serial_in(up, UART_IER);
1058 serial_out(up, UART_IER, 0);
1059
1060 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1061
1062 /*
1063 * Finally, wait for transmitter to become empty
1064 * and restore the IER
1065 */
1066 wait_for_xmitr(up);
1067 serial_out(up, UART_IER, ier);
1068 /*
1069 * The receive handling will happen properly because the
1070 * receive ready bit will still be set; it is not cleared
1071 * on read. However, modem control will not, we must
1072 * call it if we have saved something in the saved flags
1073 * while processing with interrupts off.
1074 */
1075 if (up->msr_saved_flags)
1076 check_modem_status(up);
1077
1078 pm_runtime_mark_last_busy(&up->pdev->dev);
1079 pm_runtime_put_autosuspend(&up->pdev->dev);
1080 if (locked)
1081 spin_unlock(&up->port.lock);
1082 local_irq_restore(flags);
1083 }
1084
1085 static int __init
1086 serial_omap_console_setup(struct console *co, char *options)
1087 {
1088 struct uart_omap_port *up;
1089 int baud = 115200;
1090 int bits = 8;
1091 int parity = 'n';
1092 int flow = 'n';
1093
1094 if (serial_omap_console_ports[co->index] == NULL)
1095 return -ENODEV;
1096 up = serial_omap_console_ports[co->index];
1097
1098 if (options)
1099 uart_parse_options(options, &baud, &parity, &bits, &flow);
1100
1101 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1102 }
1103
1104 static struct console serial_omap_console = {
1105 .name = OMAP_SERIAL_NAME,
1106 .write = serial_omap_console_write,
1107 .device = uart_console_device,
1108 .setup = serial_omap_console_setup,
1109 .flags = CON_PRINTBUFFER,
1110 .index = -1,
1111 .data = &serial_omap_reg,
1112 };
1113
1114 static void serial_omap_add_console_port(struct uart_omap_port *up)
1115 {
1116 serial_omap_console_ports[up->port.line] = up;
1117 }
1118
1119 #define OMAP_CONSOLE (&serial_omap_console)
1120
1121 #else
1122
1123 #define OMAP_CONSOLE NULL
1124
1125 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1126 {}
1127
1128 #endif
1129
1130 static struct uart_ops serial_omap_pops = {
1131 .tx_empty = serial_omap_tx_empty,
1132 .set_mctrl = serial_omap_set_mctrl,
1133 .get_mctrl = serial_omap_get_mctrl,
1134 .stop_tx = serial_omap_stop_tx,
1135 .start_tx = serial_omap_start_tx,
1136 .stop_rx = serial_omap_stop_rx,
1137 .enable_ms = serial_omap_enable_ms,
1138 .break_ctl = serial_omap_break_ctl,
1139 .startup = serial_omap_startup,
1140 .shutdown = serial_omap_shutdown,
1141 .set_termios = serial_omap_set_termios,
1142 .pm = serial_omap_pm,
1143 .type = serial_omap_type,
1144 .release_port = serial_omap_release_port,
1145 .request_port = serial_omap_request_port,
1146 .config_port = serial_omap_config_port,
1147 .verify_port = serial_omap_verify_port,
1148 #ifdef CONFIG_CONSOLE_POLL
1149 .poll_put_char = serial_omap_poll_put_char,
1150 .poll_get_char = serial_omap_poll_get_char,
1151 #endif
1152 };
1153
1154 static struct uart_driver serial_omap_reg = {
1155 .owner = THIS_MODULE,
1156 .driver_name = "OMAP-SERIAL",
1157 .dev_name = OMAP_SERIAL_NAME,
1158 .nr = OMAP_MAX_HSUART_PORTS,
1159 .cons = OMAP_CONSOLE,
1160 };
1161
1162 #ifdef CONFIG_SUSPEND
1163 static int serial_omap_suspend(struct device *dev)
1164 {
1165 struct uart_omap_port *up = dev_get_drvdata(dev);
1166
1167 if (up) {
1168 uart_suspend_port(&serial_omap_reg, &up->port);
1169 flush_work_sync(&up->qos_work);
1170 }
1171
1172 return 0;
1173 }
1174
1175 static int serial_omap_resume(struct device *dev)
1176 {
1177 struct uart_omap_port *up = dev_get_drvdata(dev);
1178
1179 if (up)
1180 uart_resume_port(&serial_omap_reg, &up->port);
1181 return 0;
1182 }
1183 #endif
1184
1185 static void serial_omap_rxdma_poll(unsigned long uart_no)
1186 {
1187 struct uart_omap_port *up = ui[uart_no];
1188 unsigned int curr_dma_pos, curr_transmitted_size;
1189 int ret = 0;
1190
1191 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1192 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1193 (curr_dma_pos == 0)) {
1194 if (jiffies_to_msecs(jiffies - up->port_activity) <
1195 up->uart_dma.rx_timeout) {
1196 mod_timer(&up->uart_dma.rx_timer, jiffies +
1197 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1198 } else {
1199 serial_omap_stop_rxdma(up);
1200 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1201 serial_out(up, UART_IER, up->ier);
1202 }
1203 return;
1204 }
1205
1206 curr_transmitted_size = curr_dma_pos -
1207 up->uart_dma.prev_rx_dma_pos;
1208 up->port.icount.rx += curr_transmitted_size;
1209 tty_insert_flip_string(up->port.state->port.tty,
1210 up->uart_dma.rx_buf +
1211 (up->uart_dma.prev_rx_dma_pos -
1212 up->uart_dma.rx_buf_dma_phys),
1213 curr_transmitted_size);
1214 tty_flip_buffer_push(up->port.state->port.tty);
1215 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1216 if (up->uart_dma.rx_buf_size +
1217 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1218 ret = serial_omap_start_rxdma(up);
1219 if (ret < 0) {
1220 serial_omap_stop_rxdma(up);
1221 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1222 serial_out(up, UART_IER, up->ier);
1223 }
1224 } else {
1225 mod_timer(&up->uart_dma.rx_timer, jiffies +
1226 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1227 }
1228 up->port_activity = jiffies;
1229 }
1230
1231 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1232 {
1233 return;
1234 }
1235
1236 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1237 {
1238 int ret = 0;
1239
1240 if (up->uart_dma.rx_dma_channel == -1) {
1241 pm_runtime_get_sync(&up->pdev->dev);
1242 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1243 "UART Rx DMA",
1244 (void *)uart_rx_dma_callback, up,
1245 &(up->uart_dma.rx_dma_channel));
1246 if (ret < 0)
1247 return ret;
1248
1249 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1250 OMAP_DMA_AMODE_CONSTANT,
1251 up->uart_dma.uart_base, 0, 0);
1252 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1253 OMAP_DMA_AMODE_POST_INC,
1254 up->uart_dma.rx_buf_dma_phys, 0, 0);
1255 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1256 OMAP_DMA_DATA_TYPE_S8,
1257 up->uart_dma.rx_buf_size, 1,
1258 OMAP_DMA_SYNC_ELEMENT,
1259 up->uart_dma.uart_dma_rx, 0);
1260 }
1261 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1262 /* FIXME: Cache maintenance needed here? */
1263 omap_start_dma(up->uart_dma.rx_dma_channel);
1264 mod_timer(&up->uart_dma.rx_timer, jiffies +
1265 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1266 up->uart_dma.rx_dma_used = true;
1267 return ret;
1268 }
1269
1270 static void serial_omap_continue_tx(struct uart_omap_port *up)
1271 {
1272 struct circ_buf *xmit = &up->port.state->xmit;
1273 unsigned int start = up->uart_dma.tx_buf_dma_phys
1274 + (xmit->tail & (UART_XMIT_SIZE - 1));
1275
1276 if (uart_circ_empty(xmit))
1277 return;
1278
1279 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1280 /*
1281 * It is a circular buffer. See if the buffer has wounded back.
1282 * If yes it will have to be transferred in two separate dma
1283 * transfers
1284 */
1285 if (start + up->uart_dma.tx_buf_size >=
1286 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1287 up->uart_dma.tx_buf_size =
1288 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1289 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1290 OMAP_DMA_AMODE_CONSTANT,
1291 up->uart_dma.uart_base, 0, 0);
1292 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1293 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1294 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1295 OMAP_DMA_DATA_TYPE_S8,
1296 up->uart_dma.tx_buf_size, 1,
1297 OMAP_DMA_SYNC_ELEMENT,
1298 up->uart_dma.uart_dma_tx, 0);
1299 /* FIXME: Cache maintenance needed here? */
1300 omap_start_dma(up->uart_dma.tx_dma_channel);
1301 }
1302
1303 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1304 {
1305 struct uart_omap_port *up = (struct uart_omap_port *)data;
1306 struct circ_buf *xmit = &up->port.state->xmit;
1307
1308 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1309 (UART_XMIT_SIZE - 1);
1310 up->port.icount.tx += up->uart_dma.tx_buf_size;
1311
1312 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1313 uart_write_wakeup(&up->port);
1314
1315 if (uart_circ_empty(xmit)) {
1316 spin_lock(&(up->uart_dma.tx_lock));
1317 serial_omap_stop_tx(&up->port);
1318 up->uart_dma.tx_dma_used = false;
1319 spin_unlock(&(up->uart_dma.tx_lock));
1320 } else {
1321 omap_stop_dma(up->uart_dma.tx_dma_channel);
1322 serial_omap_continue_tx(up);
1323 }
1324 up->port_activity = jiffies;
1325 return;
1326 }
1327
1328 static int serial_omap_probe(struct platform_device *pdev)
1329 {
1330 struct uart_omap_port *up;
1331 struct resource *mem, *irq, *dma_tx, *dma_rx;
1332 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1333 int ret = -ENOSPC;
1334
1335 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1336 if (!mem) {
1337 dev_err(&pdev->dev, "no mem resource?\n");
1338 return -ENODEV;
1339 }
1340
1341 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1342 if (!irq) {
1343 dev_err(&pdev->dev, "no irq resource?\n");
1344 return -ENODEV;
1345 }
1346
1347 if (!request_mem_region(mem->start, resource_size(mem),
1348 pdev->dev.driver->name)) {
1349 dev_err(&pdev->dev, "memory region already claimed\n");
1350 return -EBUSY;
1351 }
1352
1353 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1354 if (!dma_rx) {
1355 ret = -EINVAL;
1356 goto err;
1357 }
1358
1359 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1360 if (!dma_tx) {
1361 ret = -EINVAL;
1362 goto err;
1363 }
1364
1365 up = kzalloc(sizeof(*up), GFP_KERNEL);
1366 if (up == NULL) {
1367 ret = -ENOMEM;
1368 goto do_release_region;
1369 }
1370 up->pdev = pdev;
1371 up->port.dev = &pdev->dev;
1372 up->port.type = PORT_OMAP;
1373 up->port.iotype = UPIO_MEM;
1374 up->port.irq = irq->start;
1375
1376 up->port.regshift = 2;
1377 up->port.fifosize = 64;
1378 up->port.ops = &serial_omap_pops;
1379 up->port.line = pdev->id;
1380 sprintf(up->name, "OMAP UART%d", up->port.line);
1381
1382 up->port.mapbase = mem->start;
1383 up->port.membase = ioremap(mem->start, resource_size(mem));
1384 if (!up->port.membase) {
1385 dev_err(&pdev->dev, "can't ioremap UART\n");
1386 ret = -ENOMEM;
1387 goto err;
1388 }
1389
1390 up->port.flags = omap_up_info->flags;
1391 up->port.uartclk = omap_up_info->uartclk;
1392 if (!up->port.uartclk) {
1393 up->port.uartclk = DEFAULT_CLK_SPEED;
1394 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1395 "%d\n", DEFAULT_CLK_SPEED);
1396 }
1397 up->uart_dma.uart_base = mem->start;
1398 up->errata = omap_up_info->errata;
1399
1400 if (omap_up_info->dma_enabled) {
1401 up->uart_dma.uart_dma_tx = dma_tx->start;
1402 up->uart_dma.uart_dma_rx = dma_rx->start;
1403 up->use_dma = 1;
1404 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1405 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1406 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1407 spin_lock_init(&(up->uart_dma.tx_lock));
1408 spin_lock_init(&(up->uart_dma.rx_lock));
1409 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1410 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1411 }
1412
1413 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1414 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1415 pm_qos_add_request(&up->pm_qos_request,
1416 PM_QOS_CPU_DMA_LATENCY, up->latency);
1417 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1418 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1419
1420 pm_runtime_use_autosuspend(&pdev->dev);
1421 pm_runtime_set_autosuspend_delay(&pdev->dev,
1422 omap_up_info->autosuspend_timeout);
1423
1424 pm_runtime_irq_safe(&pdev->dev);
1425 pm_runtime_enable(&pdev->dev);
1426 pm_runtime_get_sync(&pdev->dev);
1427
1428 ui[up->port.line] = up;
1429 serial_omap_add_console_port(up);
1430
1431 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1432 if (ret != 0)
1433 goto do_release_region;
1434
1435 pm_runtime_put(&pdev->dev);
1436 platform_set_drvdata(pdev, up);
1437 return 0;
1438 err:
1439 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1440 pdev->id, __func__, ret);
1441 do_release_region:
1442 release_mem_region(mem->start, resource_size(mem));
1443 return ret;
1444 }
1445
1446 static int serial_omap_remove(struct platform_device *dev)
1447 {
1448 struct uart_omap_port *up = platform_get_drvdata(dev);
1449
1450 if (up) {
1451 pm_runtime_disable(&up->pdev->dev);
1452 uart_remove_one_port(&serial_omap_reg, &up->port);
1453 pm_qos_remove_request(&up->pm_qos_request);
1454
1455 kfree(up);
1456 }
1457
1458 platform_set_drvdata(dev, NULL);
1459 return 0;
1460 }
1461
1462 /*
1463 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1464 * The access to uart register after MDR1 Access
1465 * causes UART to corrupt data.
1466 *
1467 * Need a delay =
1468 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1469 * give 10 times as much
1470 */
1471 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1472 {
1473 u8 timeout = 255;
1474
1475 serial_out(up, UART_OMAP_MDR1, mdr1);
1476 udelay(2);
1477 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1478 UART_FCR_CLEAR_RCVR);
1479 /*
1480 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1481 * TX_FIFO_E bit is 1.
1482 */
1483 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1484 (UART_LSR_THRE | UART_LSR_DR))) {
1485 timeout--;
1486 if (!timeout) {
1487 /* Should *never* happen. we warn and carry on */
1488 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1489 serial_in(up, UART_LSR));
1490 break;
1491 }
1492 udelay(1);
1493 }
1494 }
1495
1496 static void serial_omap_restore_context(struct uart_omap_port *up)
1497 {
1498 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1499 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1500 else
1501 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1502
1503 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1504 serial_out(up, UART_EFR, UART_EFR_ECB);
1505 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1506 serial_out(up, UART_IER, 0x0);
1507 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1508 serial_out(up, UART_DLL, up->dll);
1509 serial_out(up, UART_DLM, up->dlh);
1510 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1511 serial_out(up, UART_IER, up->ier);
1512 serial_out(up, UART_FCR, up->fcr);
1513 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1514 serial_out(up, UART_MCR, up->mcr);
1515 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1516 serial_out(up, UART_OMAP_SCR, up->scr);
1517 serial_out(up, UART_EFR, up->efr);
1518 serial_out(up, UART_LCR, up->lcr);
1519 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1520 serial_omap_mdr1_errataset(up, up->mdr1);
1521 else
1522 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1523 }
1524
1525 #ifdef CONFIG_PM_RUNTIME
1526 static int serial_omap_runtime_suspend(struct device *dev)
1527 {
1528 struct uart_omap_port *up = dev_get_drvdata(dev);
1529 struct omap_uart_port_info *pdata = dev->platform_data;
1530
1531 if (!up)
1532 return -EINVAL;
1533
1534 if (!pdata->enable_wakeup)
1535 return 0;
1536
1537 if (pdata->get_context_loss_count)
1538 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1539
1540 if (device_may_wakeup(dev)) {
1541 if (!up->wakeups_enabled) {
1542 pdata->enable_wakeup(up->pdev, true);
1543 up->wakeups_enabled = true;
1544 }
1545 } else {
1546 if (up->wakeups_enabled) {
1547 pdata->enable_wakeup(up->pdev, false);
1548 up->wakeups_enabled = false;
1549 }
1550 }
1551
1552 /* Errata i291 */
1553 if (up->use_dma && pdata->set_forceidle &&
1554 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1555 pdata->set_forceidle(up->pdev);
1556
1557 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1558 schedule_work(&up->qos_work);
1559
1560 return 0;
1561 }
1562
1563 static int serial_omap_runtime_resume(struct device *dev)
1564 {
1565 struct uart_omap_port *up = dev_get_drvdata(dev);
1566 struct omap_uart_port_info *pdata = dev->platform_data;
1567
1568 if (up) {
1569 if (pdata->get_context_loss_count) {
1570 u32 loss_cnt = pdata->get_context_loss_count(dev);
1571
1572 if (up->context_loss_cnt != loss_cnt)
1573 serial_omap_restore_context(up);
1574 }
1575
1576 /* Errata i291 */
1577 if (up->use_dma && pdata->set_noidle &&
1578 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1579 pdata->set_noidle(up->pdev);
1580
1581 up->latency = up->calc_latency;
1582 schedule_work(&up->qos_work);
1583 }
1584
1585 return 0;
1586 }
1587 #endif
1588
1589 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1590 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1591 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1592 serial_omap_runtime_resume, NULL)
1593 };
1594
1595 static struct platform_driver serial_omap_driver = {
1596 .probe = serial_omap_probe,
1597 .remove = serial_omap_remove,
1598 .driver = {
1599 .name = DRIVER_NAME,
1600 .pm = &serial_omap_dev_pm_ops,
1601 },
1602 };
1603
1604 static int __init serial_omap_init(void)
1605 {
1606 int ret;
1607
1608 ret = uart_register_driver(&serial_omap_reg);
1609 if (ret != 0)
1610 return ret;
1611 ret = platform_driver_register(&serial_omap_driver);
1612 if (ret != 0)
1613 uart_unregister_driver(&serial_omap_reg);
1614 return ret;
1615 }
1616
1617 static void __exit serial_omap_exit(void)
1618 {
1619 platform_driver_unregister(&serial_omap_driver);
1620 uart_unregister_driver(&serial_omap_reg);
1621 }
1622
1623 module_init(serial_omap_init);
1624 module_exit(serial_omap_exit);
1625
1626 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1627 MODULE_LICENSE("GPL");
1628 MODULE_AUTHOR("Texas Instruments Inc");
CJK support for tty framebuffer vt