2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
46 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
48 static struct uart_omap_port
*ui
[OMAP_MAX_HSUART_PORTS
];
50 /* Forward declaration of functions */
51 static void uart_tx_dma_callback(int lch
, u16 ch_status
, void *data
);
52 static void serial_omap_rxdma_poll(unsigned long uart_no
);
53 static int serial_omap_start_rxdma(struct uart_omap_port
*up
);
54 static void serial_omap_mdr1_errataset(struct uart_omap_port
*up
, u8 mdr1
);
56 static struct workqueue_struct
*serial_omap_uart_wq
;
58 static inline unsigned int serial_in(struct uart_omap_port
*up
, int offset
)
60 offset
<<= up
->port
.regshift
;
61 return readw(up
->port
.membase
+ offset
);
64 static inline void serial_out(struct uart_omap_port
*up
, int offset
, int value
)
66 offset
<<= up
->port
.regshift
;
67 writew(value
, up
->port
.membase
+ offset
);
70 static inline void serial_omap_clear_fifos(struct uart_omap_port
*up
)
72 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
73 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
74 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
75 serial_out(up
, UART_FCR
, 0);
79 * serial_omap_get_divisor - calculate divisor value
80 * @port: uart port info
81 * @baud: baudrate for which divisor needs to be calculated.
83 * We have written our own function to get the divisor so as to support
84 * 13x mode. 3Mbps Baudrate as an different divisor.
85 * Reference OMAP TRM Chapter 17:
86 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
87 * referring to oversampling - divisor value
88 * baudrate 460,800 to 3,686,400 all have divisor 13
89 * except 3,000,000 which has divisor value 16
92 serial_omap_get_divisor(struct uart_port
*port
, unsigned int baud
)
96 if (baud
> OMAP_MODE13X_SPEED
&& baud
!= 3000000)
100 return port
->uartclk
/(baud
* divisor
);
103 static void serial_omap_stop_rxdma(struct uart_omap_port
*up
)
105 if (up
->uart_dma
.rx_dma_used
) {
106 del_timer(&up
->uart_dma
.rx_timer
);
107 omap_stop_dma(up
->uart_dma
.rx_dma_channel
);
108 omap_free_dma(up
->uart_dma
.rx_dma_channel
);
109 up
->uart_dma
.rx_dma_channel
= OMAP_UART_DMA_CH_FREE
;
110 up
->uart_dma
.rx_dma_used
= false;
111 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
112 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
116 static void serial_omap_enable_ms(struct uart_port
*port
)
118 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
120 dev_dbg(up
->port
.dev
, "serial_omap_enable_ms+%d\n", up
->port
.line
);
122 pm_runtime_get_sync(&up
->pdev
->dev
);
123 up
->ier
|= UART_IER_MSI
;
124 serial_out(up
, UART_IER
, up
->ier
);
125 pm_runtime_put(&up
->pdev
->dev
);
128 static void serial_omap_stop_tx(struct uart_port
*port
)
130 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
133 up
->uart_dma
.tx_dma_channel
!= OMAP_UART_DMA_CH_FREE
) {
135 * Check if dma is still active. If yes do nothing,
136 * return. Else stop dma
138 if (omap_get_dma_active_status(up
->uart_dma
.tx_dma_channel
))
140 omap_stop_dma(up
->uart_dma
.tx_dma_channel
);
141 omap_free_dma(up
->uart_dma
.tx_dma_channel
);
142 up
->uart_dma
.tx_dma_channel
= OMAP_UART_DMA_CH_FREE
;
143 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
144 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
147 pm_runtime_get_sync(&up
->pdev
->dev
);
148 if (up
->ier
& UART_IER_THRI
) {
149 up
->ier
&= ~UART_IER_THRI
;
150 serial_out(up
, UART_IER
, up
->ier
);
153 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
154 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
157 static void serial_omap_stop_rx(struct uart_port
*port
)
159 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
161 pm_runtime_get_sync(&up
->pdev
->dev
);
163 serial_omap_stop_rxdma(up
);
164 up
->ier
&= ~UART_IER_RLSI
;
165 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
166 serial_out(up
, UART_IER
, up
->ier
);
167 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
168 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
171 static inline void receive_chars(struct uart_omap_port
*up
,
172 unsigned int *status
)
174 struct tty_struct
*tty
= up
->port
.state
->port
.tty
;
175 unsigned int flag
, lsr
= *status
;
176 unsigned char ch
= 0;
180 if (likely(lsr
& UART_LSR_DR
))
181 ch
= serial_in(up
, UART_RX
);
183 up
->port
.icount
.rx
++;
185 if (unlikely(lsr
& UART_LSR_BRK_ERROR_BITS
)) {
187 * For statistics only
189 if (lsr
& UART_LSR_BI
) {
190 lsr
&= ~(UART_LSR_FE
| UART_LSR_PE
);
191 up
->port
.icount
.brk
++;
193 * We do the SysRQ and SAK checking
194 * here because otherwise the break
195 * may get masked by ignore_status_mask
196 * or read_status_mask.
198 if (uart_handle_break(&up
->port
))
200 } else if (lsr
& UART_LSR_PE
) {
201 up
->port
.icount
.parity
++;
202 } else if (lsr
& UART_LSR_FE
) {
203 up
->port
.icount
.frame
++;
206 if (lsr
& UART_LSR_OE
)
207 up
->port
.icount
.overrun
++;
210 * Mask off conditions which should be ignored.
212 lsr
&= up
->port
.read_status_mask
;
214 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
215 if (up
->port
.line
== up
->port
.cons
->index
) {
216 /* Recover the break flag from console xmit */
217 lsr
|= up
->lsr_break_flag
;
220 if (lsr
& UART_LSR_BI
)
222 else if (lsr
& UART_LSR_PE
)
224 else if (lsr
& UART_LSR_FE
)
228 if (uart_handle_sysrq_char(&up
->port
, ch
))
230 uart_insert_char(&up
->port
, lsr
, UART_LSR_OE
, ch
, flag
);
232 lsr
= serial_in(up
, UART_LSR
);
233 } while ((lsr
& (UART_LSR_DR
| UART_LSR_BI
)) && (max_count
-- > 0));
234 spin_unlock(&up
->port
.lock
);
235 tty_flip_buffer_push(tty
);
236 spin_lock(&up
->port
.lock
);
239 static void transmit_chars(struct uart_omap_port
*up
)
241 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
244 if (up
->port
.x_char
) {
245 serial_out(up
, UART_TX
, up
->port
.x_char
);
246 up
->port
.icount
.tx
++;
250 if (uart_circ_empty(xmit
) || uart_tx_stopped(&up
->port
)) {
251 serial_omap_stop_tx(&up
->port
);
254 count
= up
->port
.fifosize
/ 4;
256 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
257 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
258 up
->port
.icount
.tx
++;
259 if (uart_circ_empty(xmit
))
261 } while (--count
> 0);
263 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
264 uart_write_wakeup(&up
->port
);
266 if (uart_circ_empty(xmit
))
267 serial_omap_stop_tx(&up
->port
);
270 static inline void serial_omap_enable_ier_thri(struct uart_omap_port
*up
)
272 if (!(up
->ier
& UART_IER_THRI
)) {
273 up
->ier
|= UART_IER_THRI
;
274 serial_out(up
, UART_IER
, up
->ier
);
278 static void serial_omap_start_tx(struct uart_port
*port
)
280 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
281 struct circ_buf
*xmit
;
286 pm_runtime_get_sync(&up
->pdev
->dev
);
287 serial_omap_enable_ier_thri(up
);
288 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
289 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
293 if (up
->uart_dma
.tx_dma_used
)
296 xmit
= &up
->port
.state
->xmit
;
298 if (up
->uart_dma
.tx_dma_channel
== OMAP_UART_DMA_CH_FREE
) {
299 pm_runtime_get_sync(&up
->pdev
->dev
);
300 ret
= omap_request_dma(up
->uart_dma
.uart_dma_tx
,
302 (void *)uart_tx_dma_callback
, up
,
303 &(up
->uart_dma
.tx_dma_channel
));
306 serial_omap_enable_ier_thri(up
);
310 spin_lock(&(up
->uart_dma
.tx_lock
));
311 up
->uart_dma
.tx_dma_used
= true;
312 spin_unlock(&(up
->uart_dma
.tx_lock
));
314 start
= up
->uart_dma
.tx_buf_dma_phys
+
315 (xmit
->tail
& (UART_XMIT_SIZE
- 1));
317 up
->uart_dma
.tx_buf_size
= uart_circ_chars_pending(xmit
);
319 * It is a circular buffer. See if the buffer has wounded back.
320 * If yes it will have to be transferred in two separate dma
323 if (start
+ up
->uart_dma
.tx_buf_size
>=
324 up
->uart_dma
.tx_buf_dma_phys
+ UART_XMIT_SIZE
)
325 up
->uart_dma
.tx_buf_size
=
326 (up
->uart_dma
.tx_buf_dma_phys
+
327 UART_XMIT_SIZE
) - start
;
329 omap_set_dma_dest_params(up
->uart_dma
.tx_dma_channel
, 0,
330 OMAP_DMA_AMODE_CONSTANT
,
331 up
->uart_dma
.uart_base
, 0, 0);
332 omap_set_dma_src_params(up
->uart_dma
.tx_dma_channel
, 0,
333 OMAP_DMA_AMODE_POST_INC
, start
, 0, 0);
334 omap_set_dma_transfer_params(up
->uart_dma
.tx_dma_channel
,
335 OMAP_DMA_DATA_TYPE_S8
,
336 up
->uart_dma
.tx_buf_size
, 1,
337 OMAP_DMA_SYNC_ELEMENT
,
338 up
->uart_dma
.uart_dma_tx
, 0);
339 /* FIXME: Cache maintenance needed here? */
340 omap_start_dma(up
->uart_dma
.tx_dma_channel
);
343 static unsigned int check_modem_status(struct uart_omap_port
*up
)
347 status
= serial_in(up
, UART_MSR
);
348 status
|= up
->msr_saved_flags
;
349 up
->msr_saved_flags
= 0;
350 if ((status
& UART_MSR_ANY_DELTA
) == 0)
353 if (status
& UART_MSR_ANY_DELTA
&& up
->ier
& UART_IER_MSI
&&
354 up
->port
.state
!= NULL
) {
355 if (status
& UART_MSR_TERI
)
356 up
->port
.icount
.rng
++;
357 if (status
& UART_MSR_DDSR
)
358 up
->port
.icount
.dsr
++;
359 if (status
& UART_MSR_DDCD
)
360 uart_handle_dcd_change
361 (&up
->port
, status
& UART_MSR_DCD
);
362 if (status
& UART_MSR_DCTS
)
363 uart_handle_cts_change
364 (&up
->port
, status
& UART_MSR_CTS
);
365 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
372 * serial_omap_irq() - This handles the interrupt from one port
373 * @irq: uart port irq number
374 * @dev_id: uart port info
376 static inline irqreturn_t
serial_omap_irq(int irq
, void *dev_id
)
378 struct uart_omap_port
*up
= dev_id
;
379 unsigned int iir
, lsr
;
382 pm_runtime_get_sync(&up
->pdev
->dev
);
383 iir
= serial_in(up
, UART_IIR
);
384 if (iir
& UART_IIR_NO_INT
) {
385 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
386 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
390 spin_lock_irqsave(&up
->port
.lock
, flags
);
391 lsr
= serial_in(up
, UART_LSR
);
392 if (iir
& UART_IIR_RLSI
) {
394 if (lsr
& UART_LSR_DR
)
395 receive_chars(up
, &lsr
);
397 up
->ier
&= ~(UART_IER_RDI
| UART_IER_RLSI
);
398 serial_out(up
, UART_IER
, up
->ier
);
399 if ((serial_omap_start_rxdma(up
) != 0) &&
401 receive_chars(up
, &lsr
);
405 check_modem_status(up
);
406 if ((lsr
& UART_LSR_THRE
) && (iir
& UART_IIR_THRI
))
409 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
410 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
411 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
413 up
->port_activity
= jiffies
;
417 static unsigned int serial_omap_tx_empty(struct uart_port
*port
)
419 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
420 unsigned long flags
= 0;
421 unsigned int ret
= 0;
423 pm_runtime_get_sync(&up
->pdev
->dev
);
424 dev_dbg(up
->port
.dev
, "serial_omap_tx_empty+%d\n", up
->port
.line
);
425 spin_lock_irqsave(&up
->port
.lock
, flags
);
426 ret
= serial_in(up
, UART_LSR
) & UART_LSR_TEMT
? TIOCSER_TEMT
: 0;
427 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
428 pm_runtime_put(&up
->pdev
->dev
);
432 static unsigned int serial_omap_get_mctrl(struct uart_port
*port
)
434 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
435 unsigned char status
;
436 unsigned int ret
= 0;
438 pm_runtime_get_sync(&up
->pdev
->dev
);
439 status
= check_modem_status(up
);
440 pm_runtime_put(&up
->pdev
->dev
);
442 dev_dbg(up
->port
.dev
, "serial_omap_get_mctrl+%d\n", up
->port
.line
);
444 if (status
& UART_MSR_DCD
)
446 if (status
& UART_MSR_RI
)
448 if (status
& UART_MSR_DSR
)
450 if (status
& UART_MSR_CTS
)
455 static void serial_omap_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
457 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
458 unsigned char mcr
= 0;
460 dev_dbg(up
->port
.dev
, "serial_omap_set_mctrl+%d\n", up
->port
.line
);
461 if (mctrl
& TIOCM_RTS
)
463 if (mctrl
& TIOCM_DTR
)
465 if (mctrl
& TIOCM_OUT1
)
466 mcr
|= UART_MCR_OUT1
;
467 if (mctrl
& TIOCM_OUT2
)
468 mcr
|= UART_MCR_OUT2
;
469 if (mctrl
& TIOCM_LOOP
)
470 mcr
|= UART_MCR_LOOP
;
472 pm_runtime_get_sync(&up
->pdev
->dev
);
473 up
->mcr
= serial_in(up
, UART_MCR
);
475 serial_out(up
, UART_MCR
, up
->mcr
);
476 pm_runtime_put(&up
->pdev
->dev
);
479 static void serial_omap_break_ctl(struct uart_port
*port
, int break_state
)
481 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
482 unsigned long flags
= 0;
484 dev_dbg(up
->port
.dev
, "serial_omap_break_ctl+%d\n", up
->port
.line
);
485 pm_runtime_get_sync(&up
->pdev
->dev
);
486 spin_lock_irqsave(&up
->port
.lock
, flags
);
487 if (break_state
== -1)
488 up
->lcr
|= UART_LCR_SBC
;
490 up
->lcr
&= ~UART_LCR_SBC
;
491 serial_out(up
, UART_LCR
, up
->lcr
);
492 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
493 pm_runtime_put(&up
->pdev
->dev
);
496 static int serial_omap_startup(struct uart_port
*port
)
498 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
499 unsigned long flags
= 0;
505 retval
= request_irq(up
->port
.irq
, serial_omap_irq
, up
->port
.irqflags
,
510 dev_dbg(up
->port
.dev
, "serial_omap_startup+%d\n", up
->port
.line
);
512 pm_runtime_get_sync(&up
->pdev
->dev
);
514 * Clear the FIFO buffers and disable them.
515 * (they will be reenabled in set_termios())
517 serial_omap_clear_fifos(up
);
518 /* For Hardware flow control */
519 serial_out(up
, UART_MCR
, UART_MCR_RTS
);
522 * Clear the interrupt registers.
524 (void) serial_in(up
, UART_LSR
);
525 if (serial_in(up
, UART_LSR
) & UART_LSR_DR
)
526 (void) serial_in(up
, UART_RX
);
527 (void) serial_in(up
, UART_IIR
);
528 (void) serial_in(up
, UART_MSR
);
531 * Now, initialize the UART
533 serial_out(up
, UART_LCR
, UART_LCR_WLEN8
);
534 spin_lock_irqsave(&up
->port
.lock
, flags
);
536 * Most PC uarts need OUT2 raised to enable interrupts.
538 up
->port
.mctrl
|= TIOCM_OUT2
;
539 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
540 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
542 up
->msr_saved_flags
= 0;
544 free_page((unsigned long)up
->port
.state
->xmit
.buf
);
545 up
->port
.state
->xmit
.buf
= dma_alloc_coherent(NULL
,
547 (dma_addr_t
*)&(up
->uart_dma
.tx_buf_dma_phys
),
549 init_timer(&(up
->uart_dma
.rx_timer
));
550 up
->uart_dma
.rx_timer
.function
= serial_omap_rxdma_poll
;
551 up
->uart_dma
.rx_timer
.data
= up
->port
.line
;
552 /* Currently the buffer size is 4KB. Can increase it */
553 up
->uart_dma
.rx_buf
= dma_alloc_coherent(NULL
,
554 up
->uart_dma
.rx_buf_size
,
555 (dma_addr_t
*)&(up
->uart_dma
.rx_buf_dma_phys
), 0);
558 * Finally, enable interrupts. Note: Modem status interrupts
559 * are set via set_termios(), which will be occurring imminently
560 * anyway, so we don't enable them here.
562 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
;
563 serial_out(up
, UART_IER
, up
->ier
);
565 /* Enable module level wake up */
566 serial_out(up
, UART_OMAP_WER
, OMAP_UART_WER_MOD_WKUP
);
568 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
569 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
570 up
->port_activity
= jiffies
;
574 static void serial_omap_shutdown(struct uart_port
*port
)
576 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
577 unsigned long flags
= 0;
579 dev_dbg(up
->port
.dev
, "serial_omap_shutdown+%d\n", up
->port
.line
);
581 pm_runtime_get_sync(&up
->pdev
->dev
);
583 * Disable interrupts from this port
586 serial_out(up
, UART_IER
, 0);
588 spin_lock_irqsave(&up
->port
.lock
, flags
);
589 up
->port
.mctrl
&= ~TIOCM_OUT2
;
590 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
591 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
594 * Disable break condition and FIFOs
596 serial_out(up
, UART_LCR
, serial_in(up
, UART_LCR
) & ~UART_LCR_SBC
);
597 serial_omap_clear_fifos(up
);
600 * Read data port to reset things, and then free the irq
602 if (serial_in(up
, UART_LSR
) & UART_LSR_DR
)
603 (void) serial_in(up
, UART_RX
);
605 dma_free_coherent(up
->port
.dev
,
606 UART_XMIT_SIZE
, up
->port
.state
->xmit
.buf
,
607 up
->uart_dma
.tx_buf_dma_phys
);
608 up
->port
.state
->xmit
.buf
= NULL
;
609 serial_omap_stop_rx(port
);
610 dma_free_coherent(up
->port
.dev
,
611 up
->uart_dma
.rx_buf_size
, up
->uart_dma
.rx_buf
,
612 up
->uart_dma
.rx_buf_dma_phys
);
613 up
->uart_dma
.rx_buf
= NULL
;
616 pm_runtime_put(&up
->pdev
->dev
);
617 free_irq(up
->port
.irq
, up
);
621 serial_omap_configure_xonxoff
622 (struct uart_omap_port
*up
, struct ktermios
*termios
)
624 up
->lcr
= serial_in(up
, UART_LCR
);
625 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
626 up
->efr
= serial_in(up
, UART_EFR
);
627 serial_out(up
, UART_EFR
, up
->efr
& ~UART_EFR_ECB
);
629 serial_out(up
, UART_XON1
, termios
->c_cc
[VSTART
]);
630 serial_out(up
, UART_XOFF1
, termios
->c_cc
[VSTOP
]);
632 /* clear SW control mode bits */
633 up
->efr
&= OMAP_UART_SW_CLR
;
637 * Enable XON/XOFF flow control on output.
638 * Transmit XON1, XOFF1
640 if (termios
->c_iflag
& IXON
)
641 up
->efr
|= OMAP_UART_SW_TX
;
645 * Enable XON/XOFF flow control on input.
646 * Receiver compares XON1, XOFF1.
648 if (termios
->c_iflag
& IXOFF
)
649 up
->efr
|= OMAP_UART_SW_RX
;
651 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
652 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
654 up
->mcr
= serial_in(up
, UART_MCR
);
658 * Enable any character to restart output.
659 * Operation resumes after receiving any
660 * character after recognition of the XOFF character
662 if (termios
->c_iflag
& IXANY
)
663 up
->mcr
|= UART_MCR_XONANY
;
665 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
666 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
667 serial_out(up
, UART_TI752_TCR
, OMAP_UART_TCR_TRIG
);
668 /* Enable special char function UARTi.EFR_REG[5] and
669 * load the new software flow control mode IXON or IXOFF
670 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
672 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_SCD
);
673 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
675 serial_out(up
, UART_MCR
, up
->mcr
& ~UART_MCR_TCRTLR
);
676 serial_out(up
, UART_LCR
, up
->lcr
);
679 static void serial_omap_uart_qos_work(struct work_struct
*work
)
681 struct uart_omap_port
*up
= container_of(work
, struct uart_omap_port
,
684 pm_qos_update_request(&up
->pm_qos_request
, up
->latency
);
688 serial_omap_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
689 struct ktermios
*old
)
691 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
692 unsigned char cval
= 0;
693 unsigned char efr
= 0;
694 unsigned long flags
= 0;
695 unsigned int baud
, quot
;
697 switch (termios
->c_cflag
& CSIZE
) {
699 cval
= UART_LCR_WLEN5
;
702 cval
= UART_LCR_WLEN6
;
705 cval
= UART_LCR_WLEN7
;
709 cval
= UART_LCR_WLEN8
;
713 if (termios
->c_cflag
& CSTOPB
)
714 cval
|= UART_LCR_STOP
;
715 if (termios
->c_cflag
& PARENB
)
716 cval
|= UART_LCR_PARITY
;
717 if (!(termios
->c_cflag
& PARODD
))
718 cval
|= UART_LCR_EPAR
;
721 * Ask the core to calculate the divisor for us.
724 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/13);
725 quot
= serial_omap_get_divisor(port
, baud
);
727 /* calculate wakeup latency constraint */
728 up
->calc_latency
= (1000000 * up
->port
.fifosize
) /
730 up
->latency
= up
->calc_latency
;
731 schedule_work(&up
->qos_work
);
733 up
->dll
= quot
& 0xff;
735 up
->mdr1
= UART_OMAP_MDR1_DISABLE
;
737 up
->fcr
= UART_FCR_R_TRIG_01
| UART_FCR_T_TRIG_01
|
738 UART_FCR_ENABLE_FIFO
;
740 up
->fcr
|= UART_FCR_DMA_SELECT
;
743 * Ok, we're now changing the port state. Do it with
744 * interrupts disabled.
746 pm_runtime_get_sync(&up
->pdev
->dev
);
747 spin_lock_irqsave(&up
->port
.lock
, flags
);
750 * Update the per-port timeout.
752 uart_update_timeout(port
, termios
->c_cflag
, baud
);
754 up
->port
.read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
755 if (termios
->c_iflag
& INPCK
)
756 up
->port
.read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
757 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
758 up
->port
.read_status_mask
|= UART_LSR_BI
;
761 * Characters to ignore
763 up
->port
.ignore_status_mask
= 0;
764 if (termios
->c_iflag
& IGNPAR
)
765 up
->port
.ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
766 if (termios
->c_iflag
& IGNBRK
) {
767 up
->port
.ignore_status_mask
|= UART_LSR_BI
;
769 * If we're ignoring parity and break indicators,
770 * ignore overruns too (for real raw support).
772 if (termios
->c_iflag
& IGNPAR
)
773 up
->port
.ignore_status_mask
|= UART_LSR_OE
;
777 * ignore all characters if CREAD is not set
779 if ((termios
->c_cflag
& CREAD
) == 0)
780 up
->port
.ignore_status_mask
|= UART_LSR_DR
;
783 * Modem status interrupts
785 up
->ier
&= ~UART_IER_MSI
;
786 if (UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
787 up
->ier
|= UART_IER_MSI
;
788 serial_out(up
, UART_IER
, up
->ier
);
789 serial_out(up
, UART_LCR
, cval
); /* reset DLAB */
791 up
->scr
= OMAP_UART_SCR_TX_EMPTY
;
793 /* FIFOs and DMA Settings */
795 /* FCR can be changed only when the
796 * baud clock is not running
797 * DLL_REG and DLH_REG set to 0.
799 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
800 serial_out(up
, UART_DLL
, 0);
801 serial_out(up
, UART_DLM
, 0);
802 serial_out(up
, UART_LCR
, 0);
804 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
806 up
->efr
= serial_in(up
, UART_EFR
);
807 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
809 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
810 up
->mcr
= serial_in(up
, UART_MCR
);
811 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
812 /* FIFO ENABLE, DMA MODE */
813 serial_out(up
, UART_FCR
, up
->fcr
);
814 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
817 serial_out(up
, UART_TI752_TLR
, 0);
818 up
->scr
|= (UART_FCR_TRIGGER_4
| UART_FCR_TRIGGER_8
);
821 serial_out(up
, UART_OMAP_SCR
, up
->scr
);
823 serial_out(up
, UART_EFR
, up
->efr
);
824 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
825 serial_out(up
, UART_MCR
, up
->mcr
);
827 /* Protocol, Baud Rate, and Interrupt Settings */
829 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
830 serial_omap_mdr1_errataset(up
, up
->mdr1
);
832 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
834 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
836 up
->efr
= serial_in(up
, UART_EFR
);
837 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
839 serial_out(up
, UART_LCR
, 0);
840 serial_out(up
, UART_IER
, 0);
841 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
843 serial_out(up
, UART_DLL
, up
->dll
); /* LS of divisor */
844 serial_out(up
, UART_DLM
, up
->dlh
); /* MS of divisor */
846 serial_out(up
, UART_LCR
, 0);
847 serial_out(up
, UART_IER
, up
->ier
);
848 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
850 serial_out(up
, UART_EFR
, up
->efr
);
851 serial_out(up
, UART_LCR
, cval
);
853 if (baud
> 230400 && baud
!= 3000000)
854 up
->mdr1
= UART_OMAP_MDR1_13X_MODE
;
856 up
->mdr1
= UART_OMAP_MDR1_16X_MODE
;
858 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
859 serial_omap_mdr1_errataset(up
, up
->mdr1
);
861 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
863 /* Hardware Flow Control Configuration */
865 if (termios
->c_cflag
& CRTSCTS
) {
866 efr
|= (UART_EFR_CTS
| UART_EFR_RTS
);
867 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
869 up
->mcr
= serial_in(up
, UART_MCR
);
870 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
872 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
873 up
->efr
= serial_in(up
, UART_EFR
);
874 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
876 serial_out(up
, UART_TI752_TCR
, OMAP_UART_TCR_TRIG
);
877 serial_out(up
, UART_EFR
, efr
); /* Enable AUTORTS and AUTOCTS */
878 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
879 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_RTS
);
880 serial_out(up
, UART_LCR
, cval
);
883 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
884 /* Software Flow Control Configuration */
885 serial_omap_configure_xonxoff(up
, termios
);
887 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
888 pm_runtime_put(&up
->pdev
->dev
);
889 dev_dbg(up
->port
.dev
, "serial_omap_set_termios+%d\n", up
->port
.line
);
893 serial_omap_pm(struct uart_port
*port
, unsigned int state
,
894 unsigned int oldstate
)
896 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
899 dev_dbg(up
->port
.dev
, "serial_omap_pm+%d\n", up
->port
.line
);
901 pm_runtime_get_sync(&up
->pdev
->dev
);
902 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
903 efr
= serial_in(up
, UART_EFR
);
904 serial_out(up
, UART_EFR
, efr
| UART_EFR_ECB
);
905 serial_out(up
, UART_LCR
, 0);
907 serial_out(up
, UART_IER
, (state
!= 0) ? UART_IERX_SLEEP
: 0);
908 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
909 serial_out(up
, UART_EFR
, efr
);
910 serial_out(up
, UART_LCR
, 0);
912 if (!device_may_wakeup(&up
->pdev
->dev
)) {
914 pm_runtime_forbid(&up
->pdev
->dev
);
916 pm_runtime_allow(&up
->pdev
->dev
);
919 pm_runtime_put(&up
->pdev
->dev
);
922 static void serial_omap_release_port(struct uart_port
*port
)
924 dev_dbg(port
->dev
, "serial_omap_release_port+\n");
927 static int serial_omap_request_port(struct uart_port
*port
)
929 dev_dbg(port
->dev
, "serial_omap_request_port+\n");
933 static void serial_omap_config_port(struct uart_port
*port
, int flags
)
935 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
937 dev_dbg(up
->port
.dev
, "serial_omap_config_port+%d\n",
939 up
->port
.type
= PORT_OMAP
;
943 serial_omap_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
945 /* we don't want the core code to modify any port params */
946 dev_dbg(port
->dev
, "serial_omap_verify_port+\n");
951 serial_omap_type(struct uart_port
*port
)
953 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
955 dev_dbg(up
->port
.dev
, "serial_omap_type+%d\n", up
->port
.line
);
959 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
961 static inline void wait_for_xmitr(struct uart_omap_port
*up
)
963 unsigned int status
, tmout
= 10000;
965 /* Wait up to 10ms for the character(s) to be sent. */
967 status
= serial_in(up
, UART_LSR
);
969 if (status
& UART_LSR_BI
)
970 up
->lsr_break_flag
= UART_LSR_BI
;
975 } while ((status
& BOTH_EMPTY
) != BOTH_EMPTY
);
977 /* Wait up to 1s for flow control if necessary */
978 if (up
->port
.flags
& UPF_CONS_FLOW
) {
980 for (tmout
= 1000000; tmout
; tmout
--) {
981 unsigned int msr
= serial_in(up
, UART_MSR
);
983 up
->msr_saved_flags
|= msr
& MSR_SAVE_FLAGS
;
984 if (msr
& UART_MSR_CTS
)
992 #ifdef CONFIG_CONSOLE_POLL
994 static void serial_omap_poll_put_char(struct uart_port
*port
, unsigned char ch
)
996 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
998 pm_runtime_get_sync(&up
->pdev
->dev
);
1000 serial_out(up
, UART_TX
, ch
);
1001 pm_runtime_put(&up
->pdev
->dev
);
1004 static int serial_omap_poll_get_char(struct uart_port
*port
)
1006 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
1007 unsigned int status
;
1009 pm_runtime_get_sync(&up
->pdev
->dev
);
1010 status
= serial_in(up
, UART_LSR
);
1011 if (!(status
& UART_LSR_DR
))
1012 return NO_POLL_CHAR
;
1014 status
= serial_in(up
, UART_RX
);
1015 pm_runtime_put(&up
->pdev
->dev
);
1019 #endif /* CONFIG_CONSOLE_POLL */
1021 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1023 static struct uart_omap_port
*serial_omap_console_ports
[4];
1025 static struct uart_driver serial_omap_reg
;
1027 static void serial_omap_console_putchar(struct uart_port
*port
, int ch
)
1029 struct uart_omap_port
*up
= (struct uart_omap_port
*)port
;
1032 serial_out(up
, UART_TX
, ch
);
1036 serial_omap_console_write(struct console
*co
, const char *s
,
1039 struct uart_omap_port
*up
= serial_omap_console_ports
[co
->index
];
1040 unsigned long flags
;
1044 pm_runtime_get_sync(&up
->pdev
->dev
);
1046 local_irq_save(flags
);
1049 else if (oops_in_progress
)
1050 locked
= spin_trylock(&up
->port
.lock
);
1052 spin_lock(&up
->port
.lock
);
1055 * First save the IER then disable the interrupts
1057 ier
= serial_in(up
, UART_IER
);
1058 serial_out(up
, UART_IER
, 0);
1060 uart_console_write(&up
->port
, s
, count
, serial_omap_console_putchar
);
1063 * Finally, wait for transmitter to become empty
1064 * and restore the IER
1067 serial_out(up
, UART_IER
, ier
);
1069 * The receive handling will happen properly because the
1070 * receive ready bit will still be set; it is not cleared
1071 * on read. However, modem control will not, we must
1072 * call it if we have saved something in the saved flags
1073 * while processing with interrupts off.
1075 if (up
->msr_saved_flags
)
1076 check_modem_status(up
);
1078 pm_runtime_mark_last_busy(&up
->pdev
->dev
);
1079 pm_runtime_put_autosuspend(&up
->pdev
->dev
);
1081 spin_unlock(&up
->port
.lock
);
1082 local_irq_restore(flags
);
1086 serial_omap_console_setup(struct console
*co
, char *options
)
1088 struct uart_omap_port
*up
;
1094 if (serial_omap_console_ports
[co
->index
] == NULL
)
1096 up
= serial_omap_console_ports
[co
->index
];
1099 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1101 return uart_set_options(&up
->port
, co
, baud
, parity
, bits
, flow
);
1104 static struct console serial_omap_console
= {
1105 .name
= OMAP_SERIAL_NAME
,
1106 .write
= serial_omap_console_write
,
1107 .device
= uart_console_device
,
1108 .setup
= serial_omap_console_setup
,
1109 .flags
= CON_PRINTBUFFER
,
1111 .data
= &serial_omap_reg
,
1114 static void serial_omap_add_console_port(struct uart_omap_port
*up
)
1116 serial_omap_console_ports
[up
->port
.line
] = up
;
1119 #define OMAP_CONSOLE (&serial_omap_console)
1123 #define OMAP_CONSOLE NULL
1125 static inline void serial_omap_add_console_port(struct uart_omap_port
*up
)
1130 static struct uart_ops serial_omap_pops
= {
1131 .tx_empty
= serial_omap_tx_empty
,
1132 .set_mctrl
= serial_omap_set_mctrl
,
1133 .get_mctrl
= serial_omap_get_mctrl
,
1134 .stop_tx
= serial_omap_stop_tx
,
1135 .start_tx
= serial_omap_start_tx
,
1136 .stop_rx
= serial_omap_stop_rx
,
1137 .enable_ms
= serial_omap_enable_ms
,
1138 .break_ctl
= serial_omap_break_ctl
,
1139 .startup
= serial_omap_startup
,
1140 .shutdown
= serial_omap_shutdown
,
1141 .set_termios
= serial_omap_set_termios
,
1142 .pm
= serial_omap_pm
,
1143 .type
= serial_omap_type
,
1144 .release_port
= serial_omap_release_port
,
1145 .request_port
= serial_omap_request_port
,
1146 .config_port
= serial_omap_config_port
,
1147 .verify_port
= serial_omap_verify_port
,
1148 #ifdef CONFIG_CONSOLE_POLL
1149 .poll_put_char
= serial_omap_poll_put_char
,
1150 .poll_get_char
= serial_omap_poll_get_char
,
1154 static struct uart_driver serial_omap_reg
= {
1155 .owner
= THIS_MODULE
,
1156 .driver_name
= "OMAP-SERIAL",
1157 .dev_name
= OMAP_SERIAL_NAME
,
1158 .nr
= OMAP_MAX_HSUART_PORTS
,
1159 .cons
= OMAP_CONSOLE
,
1162 #ifdef CONFIG_SUSPEND
1163 static int serial_omap_suspend(struct device
*dev
)
1165 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1168 uart_suspend_port(&serial_omap_reg
, &up
->port
);
1169 flush_work_sync(&up
->qos_work
);
1175 static int serial_omap_resume(struct device
*dev
)
1177 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1180 uart_resume_port(&serial_omap_reg
, &up
->port
);
1185 static void serial_omap_rxdma_poll(unsigned long uart_no
)
1187 struct uart_omap_port
*up
= ui
[uart_no
];
1188 unsigned int curr_dma_pos
, curr_transmitted_size
;
1191 curr_dma_pos
= omap_get_dma_dst_pos(up
->uart_dma
.rx_dma_channel
);
1192 if ((curr_dma_pos
== up
->uart_dma
.prev_rx_dma_pos
) ||
1193 (curr_dma_pos
== 0)) {
1194 if (jiffies_to_msecs(jiffies
- up
->port_activity
) <
1195 up
->uart_dma
.rx_timeout
) {
1196 mod_timer(&up
->uart_dma
.rx_timer
, jiffies
+
1197 usecs_to_jiffies(up
->uart_dma
.rx_poll_rate
));
1199 serial_omap_stop_rxdma(up
);
1200 up
->ier
|= (UART_IER_RDI
| UART_IER_RLSI
);
1201 serial_out(up
, UART_IER
, up
->ier
);
1206 curr_transmitted_size
= curr_dma_pos
-
1207 up
->uart_dma
.prev_rx_dma_pos
;
1208 up
->port
.icount
.rx
+= curr_transmitted_size
;
1209 tty_insert_flip_string(up
->port
.state
->port
.tty
,
1210 up
->uart_dma
.rx_buf
+
1211 (up
->uart_dma
.prev_rx_dma_pos
-
1212 up
->uart_dma
.rx_buf_dma_phys
),
1213 curr_transmitted_size
);
1214 tty_flip_buffer_push(up
->port
.state
->port
.tty
);
1215 up
->uart_dma
.prev_rx_dma_pos
= curr_dma_pos
;
1216 if (up
->uart_dma
.rx_buf_size
+
1217 up
->uart_dma
.rx_buf_dma_phys
== curr_dma_pos
) {
1218 ret
= serial_omap_start_rxdma(up
);
1220 serial_omap_stop_rxdma(up
);
1221 up
->ier
|= (UART_IER_RDI
| UART_IER_RLSI
);
1222 serial_out(up
, UART_IER
, up
->ier
);
1225 mod_timer(&up
->uart_dma
.rx_timer
, jiffies
+
1226 usecs_to_jiffies(up
->uart_dma
.rx_poll_rate
));
1228 up
->port_activity
= jiffies
;
1231 static void uart_rx_dma_callback(int lch
, u16 ch_status
, void *data
)
1236 static int serial_omap_start_rxdma(struct uart_omap_port
*up
)
1240 if (up
->uart_dma
.rx_dma_channel
== -1) {
1241 pm_runtime_get_sync(&up
->pdev
->dev
);
1242 ret
= omap_request_dma(up
->uart_dma
.uart_dma_rx
,
1244 (void *)uart_rx_dma_callback
, up
,
1245 &(up
->uart_dma
.rx_dma_channel
));
1249 omap_set_dma_src_params(up
->uart_dma
.rx_dma_channel
, 0,
1250 OMAP_DMA_AMODE_CONSTANT
,
1251 up
->uart_dma
.uart_base
, 0, 0);
1252 omap_set_dma_dest_params(up
->uart_dma
.rx_dma_channel
, 0,
1253 OMAP_DMA_AMODE_POST_INC
,
1254 up
->uart_dma
.rx_buf_dma_phys
, 0, 0);
1255 omap_set_dma_transfer_params(up
->uart_dma
.rx_dma_channel
,
1256 OMAP_DMA_DATA_TYPE_S8
,
1257 up
->uart_dma
.rx_buf_size
, 1,
1258 OMAP_DMA_SYNC_ELEMENT
,
1259 up
->uart_dma
.uart_dma_rx
, 0);
1261 up
->uart_dma
.prev_rx_dma_pos
= up
->uart_dma
.rx_buf_dma_phys
;
1262 /* FIXME: Cache maintenance needed here? */
1263 omap_start_dma(up
->uart_dma
.rx_dma_channel
);
1264 mod_timer(&up
->uart_dma
.rx_timer
, jiffies
+
1265 usecs_to_jiffies(up
->uart_dma
.rx_poll_rate
));
1266 up
->uart_dma
.rx_dma_used
= true;
1270 static void serial_omap_continue_tx(struct uart_omap_port
*up
)
1272 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
1273 unsigned int start
= up
->uart_dma
.tx_buf_dma_phys
1274 + (xmit
->tail
& (UART_XMIT_SIZE
- 1));
1276 if (uart_circ_empty(xmit
))
1279 up
->uart_dma
.tx_buf_size
= uart_circ_chars_pending(xmit
);
1281 * It is a circular buffer. See if the buffer has wounded back.
1282 * If yes it will have to be transferred in two separate dma
1285 if (start
+ up
->uart_dma
.tx_buf_size
>=
1286 up
->uart_dma
.tx_buf_dma_phys
+ UART_XMIT_SIZE
)
1287 up
->uart_dma
.tx_buf_size
=
1288 (up
->uart_dma
.tx_buf_dma_phys
+ UART_XMIT_SIZE
) - start
;
1289 omap_set_dma_dest_params(up
->uart_dma
.tx_dma_channel
, 0,
1290 OMAP_DMA_AMODE_CONSTANT
,
1291 up
->uart_dma
.uart_base
, 0, 0);
1292 omap_set_dma_src_params(up
->uart_dma
.tx_dma_channel
, 0,
1293 OMAP_DMA_AMODE_POST_INC
, start
, 0, 0);
1294 omap_set_dma_transfer_params(up
->uart_dma
.tx_dma_channel
,
1295 OMAP_DMA_DATA_TYPE_S8
,
1296 up
->uart_dma
.tx_buf_size
, 1,
1297 OMAP_DMA_SYNC_ELEMENT
,
1298 up
->uart_dma
.uart_dma_tx
, 0);
1299 /* FIXME: Cache maintenance needed here? */
1300 omap_start_dma(up
->uart_dma
.tx_dma_channel
);
1303 static void uart_tx_dma_callback(int lch
, u16 ch_status
, void *data
)
1305 struct uart_omap_port
*up
= (struct uart_omap_port
*)data
;
1306 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
1308 xmit
->tail
= (xmit
->tail
+ up
->uart_dma
.tx_buf_size
) & \
1309 (UART_XMIT_SIZE
- 1);
1310 up
->port
.icount
.tx
+= up
->uart_dma
.tx_buf_size
;
1312 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1313 uart_write_wakeup(&up
->port
);
1315 if (uart_circ_empty(xmit
)) {
1316 spin_lock(&(up
->uart_dma
.tx_lock
));
1317 serial_omap_stop_tx(&up
->port
);
1318 up
->uart_dma
.tx_dma_used
= false;
1319 spin_unlock(&(up
->uart_dma
.tx_lock
));
1321 omap_stop_dma(up
->uart_dma
.tx_dma_channel
);
1322 serial_omap_continue_tx(up
);
1324 up
->port_activity
= jiffies
;
1328 static int serial_omap_probe(struct platform_device
*pdev
)
1330 struct uart_omap_port
*up
;
1331 struct resource
*mem
, *irq
, *dma_tx
, *dma_rx
;
1332 struct omap_uart_port_info
*omap_up_info
= pdev
->dev
.platform_data
;
1335 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1337 dev_err(&pdev
->dev
, "no mem resource?\n");
1341 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1343 dev_err(&pdev
->dev
, "no irq resource?\n");
1347 if (!request_mem_region(mem
->start
, resource_size(mem
),
1348 pdev
->dev
.driver
->name
)) {
1349 dev_err(&pdev
->dev
, "memory region already claimed\n");
1353 dma_rx
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "rx");
1359 dma_tx
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "tx");
1365 up
= kzalloc(sizeof(*up
), GFP_KERNEL
);
1368 goto do_release_region
;
1371 up
->port
.dev
= &pdev
->dev
;
1372 up
->port
.type
= PORT_OMAP
;
1373 up
->port
.iotype
= UPIO_MEM
;
1374 up
->port
.irq
= irq
->start
;
1376 up
->port
.regshift
= 2;
1377 up
->port
.fifosize
= 64;
1378 up
->port
.ops
= &serial_omap_pops
;
1379 up
->port
.line
= pdev
->id
;
1380 sprintf(up
->name
, "OMAP UART%d", up
->port
.line
);
1382 up
->port
.mapbase
= mem
->start
;
1383 up
->port
.membase
= ioremap(mem
->start
, resource_size(mem
));
1384 if (!up
->port
.membase
) {
1385 dev_err(&pdev
->dev
, "can't ioremap UART\n");
1390 up
->port
.flags
= omap_up_info
->flags
;
1391 up
->port
.uartclk
= omap_up_info
->uartclk
;
1392 if (!up
->port
.uartclk
) {
1393 up
->port
.uartclk
= DEFAULT_CLK_SPEED
;
1394 dev_warn(&pdev
->dev
, "No clock speed specified: using default:"
1395 "%d\n", DEFAULT_CLK_SPEED
);
1397 up
->uart_dma
.uart_base
= mem
->start
;
1398 up
->errata
= omap_up_info
->errata
;
1400 if (omap_up_info
->dma_enabled
) {
1401 up
->uart_dma
.uart_dma_tx
= dma_tx
->start
;
1402 up
->uart_dma
.uart_dma_rx
= dma_rx
->start
;
1404 up
->uart_dma
.rx_buf_size
= omap_up_info
->dma_rx_buf_size
;
1405 up
->uart_dma
.rx_timeout
= omap_up_info
->dma_rx_timeout
;
1406 up
->uart_dma
.rx_poll_rate
= omap_up_info
->dma_rx_poll_rate
;
1407 spin_lock_init(&(up
->uart_dma
.tx_lock
));
1408 spin_lock_init(&(up
->uart_dma
.rx_lock
));
1409 up
->uart_dma
.tx_dma_channel
= OMAP_UART_DMA_CH_FREE
;
1410 up
->uart_dma
.rx_dma_channel
= OMAP_UART_DMA_CH_FREE
;
1413 up
->latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1414 up
->calc_latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1415 pm_qos_add_request(&up
->pm_qos_request
,
1416 PM_QOS_CPU_DMA_LATENCY
, up
->latency
);
1417 serial_omap_uart_wq
= create_singlethread_workqueue(up
->name
);
1418 INIT_WORK(&up
->qos_work
, serial_omap_uart_qos_work
);
1420 pm_runtime_use_autosuspend(&pdev
->dev
);
1421 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
1422 omap_up_info
->autosuspend_timeout
);
1424 pm_runtime_irq_safe(&pdev
->dev
);
1425 pm_runtime_enable(&pdev
->dev
);
1426 pm_runtime_get_sync(&pdev
->dev
);
1428 ui
[up
->port
.line
] = up
;
1429 serial_omap_add_console_port(up
);
1431 ret
= uart_add_one_port(&serial_omap_reg
, &up
->port
);
1433 goto do_release_region
;
1435 pm_runtime_put(&pdev
->dev
);
1436 platform_set_drvdata(pdev
, up
);
1439 dev_err(&pdev
->dev
, "[UART%d]: failure [%s]: %d\n",
1440 pdev
->id
, __func__
, ret
);
1442 release_mem_region(mem
->start
, resource_size(mem
));
1446 static int serial_omap_remove(struct platform_device
*dev
)
1448 struct uart_omap_port
*up
= platform_get_drvdata(dev
);
1451 pm_runtime_disable(&up
->pdev
->dev
);
1452 uart_remove_one_port(&serial_omap_reg
, &up
->port
);
1453 pm_qos_remove_request(&up
->pm_qos_request
);
1458 platform_set_drvdata(dev
, NULL
);
1463 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1464 * The access to uart register after MDR1 Access
1465 * causes UART to corrupt data.
1468 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1469 * give 10 times as much
1471 static void serial_omap_mdr1_errataset(struct uart_omap_port
*up
, u8 mdr1
)
1475 serial_out(up
, UART_OMAP_MDR1
, mdr1
);
1477 serial_out(up
, UART_FCR
, up
->fcr
| UART_FCR_CLEAR_XMIT
|
1478 UART_FCR_CLEAR_RCVR
);
1480 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1481 * TX_FIFO_E bit is 1.
1483 while (UART_LSR_THRE
!= (serial_in(up
, UART_LSR
) &
1484 (UART_LSR_THRE
| UART_LSR_DR
))) {
1487 /* Should *never* happen. we warn and carry on */
1488 dev_crit(&up
->pdev
->dev
, "Errata i202: timedout %x\n",
1489 serial_in(up
, UART_LSR
));
1496 static void serial_omap_restore_context(struct uart_omap_port
*up
)
1498 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
1499 serial_omap_mdr1_errataset(up
, UART_OMAP_MDR1_DISABLE
);
1501 serial_out(up
, UART_OMAP_MDR1
, UART_OMAP_MDR1_DISABLE
);
1503 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1504 serial_out(up
, UART_EFR
, UART_EFR_ECB
);
1505 serial_out(up
, UART_LCR
, 0x0); /* Operational mode */
1506 serial_out(up
, UART_IER
, 0x0);
1507 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1508 serial_out(up
, UART_DLL
, up
->dll
);
1509 serial_out(up
, UART_DLM
, up
->dlh
);
1510 serial_out(up
, UART_LCR
, 0x0); /* Operational mode */
1511 serial_out(up
, UART_IER
, up
->ier
);
1512 serial_out(up
, UART_FCR
, up
->fcr
);
1513 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1514 serial_out(up
, UART_MCR
, up
->mcr
);
1515 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1516 serial_out(up
, UART_OMAP_SCR
, up
->scr
);
1517 serial_out(up
, UART_EFR
, up
->efr
);
1518 serial_out(up
, UART_LCR
, up
->lcr
);
1519 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
1520 serial_omap_mdr1_errataset(up
, up
->mdr1
);
1522 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
1525 #ifdef CONFIG_PM_RUNTIME
1526 static int serial_omap_runtime_suspend(struct device
*dev
)
1528 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1529 struct omap_uart_port_info
*pdata
= dev
->platform_data
;
1534 if (!pdata
->enable_wakeup
)
1537 if (pdata
->get_context_loss_count
)
1538 up
->context_loss_cnt
= pdata
->get_context_loss_count(dev
);
1540 if (device_may_wakeup(dev
)) {
1541 if (!up
->wakeups_enabled
) {
1542 pdata
->enable_wakeup(up
->pdev
, true);
1543 up
->wakeups_enabled
= true;
1546 if (up
->wakeups_enabled
) {
1547 pdata
->enable_wakeup(up
->pdev
, false);
1548 up
->wakeups_enabled
= false;
1553 if (up
->use_dma
&& pdata
->set_forceidle
&&
1554 (up
->errata
& UART_ERRATA_i291_DMA_FORCEIDLE
))
1555 pdata
->set_forceidle(up
->pdev
);
1557 up
->latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1558 schedule_work(&up
->qos_work
);
1563 static int serial_omap_runtime_resume(struct device
*dev
)
1565 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1566 struct omap_uart_port_info
*pdata
= dev
->platform_data
;
1569 if (pdata
->get_context_loss_count
) {
1570 u32 loss_cnt
= pdata
->get_context_loss_count(dev
);
1572 if (up
->context_loss_cnt
!= loss_cnt
)
1573 serial_omap_restore_context(up
);
1577 if (up
->use_dma
&& pdata
->set_noidle
&&
1578 (up
->errata
& UART_ERRATA_i291_DMA_FORCEIDLE
))
1579 pdata
->set_noidle(up
->pdev
);
1581 up
->latency
= up
->calc_latency
;
1582 schedule_work(&up
->qos_work
);
1589 static const struct dev_pm_ops serial_omap_dev_pm_ops
= {
1590 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend
, serial_omap_resume
)
1591 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend
,
1592 serial_omap_runtime_resume
, NULL
)
1595 static struct platform_driver serial_omap_driver
= {
1596 .probe
= serial_omap_probe
,
1597 .remove
= serial_omap_remove
,
1599 .name
= DRIVER_NAME
,
1600 .pm
= &serial_omap_dev_pm_ops
,
1604 static int __init
serial_omap_init(void)
1608 ret
= uart_register_driver(&serial_omap_reg
);
1611 ret
= platform_driver_register(&serial_omap_driver
);
1613 uart_unregister_driver(&serial_omap_reg
);
1617 static void __exit
serial_omap_exit(void)
1619 platform_driver_unregister(&serial_omap_driver
);
1620 uart_unregister_driver(&serial_omap_reg
);
1623 module_init(serial_omap_init
);
1624 module_exit(serial_omap_exit
);
1626 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1627 MODULE_LICENSE("GPL");
1628 MODULE_AUTHOR("Texas Instruments Inc");