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[MIPS] Lasat: Fix overlap of interrupt number ranges.
[linux-2.6/cjktty.git] / drivers / net / qla3xxx.c
bloba5791114b7bde59eddd6aed9c0dc79c590a8d688
1 /*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/delay.h>
35 #include <linux/mm.h>
36
37 #include "qla3xxx.h"
38
39 #define DRV_NAME "qla3xxx"
40 #define DRV_STRING "QLogic ISP3XXX Network Driver"
41 #define DRV_VERSION "v2.03.00-k4"
42 #define PFX DRV_NAME " "
43
44 static const char ql3xxx_driver_name[] = DRV_NAME;
45 static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47 MODULE_AUTHOR("QLogic Corporation");
48 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
49 MODULE_LICENSE("GPL");
50 MODULE_VERSION(DRV_VERSION);
51
52 static const u32 default_msg
53 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
54 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
55
56 static int debug = -1; /* defaults above */
57 module_param(debug, int, 0);
58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60 static int msi;
61 module_param(msi, int, 0);
62 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
63
64 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
65 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
67 /* required last entry */
68 {0,}
69 };
70
71 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
72
73 /*
74 * These are the known PHY's which are used
75 */
76 typedef enum {
77 PHY_TYPE_UNKNOWN = 0,
78 PHY_VITESSE_VSC8211,
79 PHY_AGERE_ET1011C,
80 MAX_PHY_DEV_TYPES
81 } PHY_DEVICE_et;
82
83 typedef struct {
84 PHY_DEVICE_et phyDevice;
85 u32 phyIdOUI;
86 u16 phyIdModel;
87 char *name;
88 } PHY_DEVICE_INFO_t;
89
90 static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
91 {{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
92 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
93 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
94 };
95
96
97 /*
98 * Caller must take hw_lock.
99 */
100 static int ql_sem_spinlock(struct ql3_adapter *qdev,
101 u32 sem_mask, u32 sem_bits)
102 {
103 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
104 u32 value;
105 unsigned int seconds = 3;
106
107 do {
108 writel((sem_mask | sem_bits),
109 &port_regs->CommonRegs.semaphoreReg);
110 value = readl(&port_regs->CommonRegs.semaphoreReg);
111 if ((value & (sem_mask >> 16)) == sem_bits)
112 return 0;
113 ssleep(1);
114 } while(--seconds);
115 return -1;
116 }
117
118 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
119 {
120 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
121 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
122 readl(&port_regs->CommonRegs.semaphoreReg);
123 }
124
125 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
126 {
127 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
128 u32 value;
129
130 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
131 value = readl(&port_regs->CommonRegs.semaphoreReg);
132 return ((value & (sem_mask >> 16)) == sem_bits);
133 }
134
135 /*
136 * Caller holds hw_lock.
137 */
138 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
139 {
140 int i = 0;
141
142 while (1) {
143 if (!ql_sem_lock(qdev,
144 QL_DRVR_SEM_MASK,
145 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
146 * 2) << 1)) {
147 if (i < 10) {
148 ssleep(1);
149 i++;
150 } else {
151 printk(KERN_ERR PFX "%s: Timed out waiting for "
152 "driver lock...\n",
153 qdev->ndev->name);
154 return 0;
155 }
156 } else {
157 printk(KERN_DEBUG PFX
158 "%s: driver lock acquired.\n",
159 qdev->ndev->name);
160 return 1;
161 }
162 }
163 }
164
165 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
166 {
167 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
168
169 writel(((ISP_CONTROL_NP_MASK << 16) | page),
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
172 qdev->current_page = page;
173 }
174
175 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
176 u32 __iomem * reg)
177 {
178 u32 value;
179 unsigned long hw_flags;
180
181 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
182 value = readl(reg);
183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
184
185 return value;
186 }
187
188 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
189 u32 __iomem * reg)
190 {
191 return readl(reg);
192 }
193
194 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
195 {
196 u32 value;
197 unsigned long hw_flags;
198
199 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
200
201 if (qdev->current_page != 0)
202 ql_set_register_page(qdev,0);
203 value = readl(reg);
204
205 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
206 return value;
207 }
208
209 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
210 {
211 if (qdev->current_page != 0)
212 ql_set_register_page(qdev,0);
213 return readl(reg);
214 }
215
216 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
217 u32 __iomem *reg, u32 value)
218 {
219 unsigned long hw_flags;
220
221 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
222 writel(value, reg);
223 readl(reg);
224 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
225 return;
226 }
227
228 static void ql_write_common_reg(struct ql3_adapter *qdev,
229 u32 __iomem *reg, u32 value)
230 {
231 writel(value, reg);
232 readl(reg);
233 return;
234 }
235
236 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
238 {
239 writel(value, reg);
240 readl(reg);
241 udelay(1);
242 return;
243 }
244
245 static void ql_write_page0_reg(struct ql3_adapter *qdev,
246 u32 __iomem *reg, u32 value)
247 {
248 if (qdev->current_page != 0)
249 ql_set_register_page(qdev,0);
250 writel(value, reg);
251 readl(reg);
252 return;
253 }
254
255 /*
256 * Caller holds hw_lock. Only called during init.
257 */
258 static void ql_write_page1_reg(struct ql3_adapter *qdev,
259 u32 __iomem *reg, u32 value)
260 {
261 if (qdev->current_page != 1)
262 ql_set_register_page(qdev,1);
263 writel(value, reg);
264 readl(reg);
265 return;
266 }
267
268 /*
269 * Caller holds hw_lock. Only called during init.
270 */
271 static void ql_write_page2_reg(struct ql3_adapter *qdev,
272 u32 __iomem *reg, u32 value)
273 {
274 if (qdev->current_page != 2)
275 ql_set_register_page(qdev,2);
276 writel(value, reg);
277 readl(reg);
278 return;
279 }
280
281 static void ql_disable_interrupts(struct ql3_adapter *qdev)
282 {
283 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
284
285 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
286 (ISP_IMR_ENABLE_INT << 16));
287
288 }
289
290 static void ql_enable_interrupts(struct ql3_adapter *qdev)
291 {
292 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
293
294 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
295 ((0xff << 16) | ISP_IMR_ENABLE_INT));
296
297 }
298
299 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
300 struct ql_rcv_buf_cb *lrg_buf_cb)
301 {
302 dma_addr_t map;
303 int err;
304 lrg_buf_cb->next = NULL;
305
306 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
307 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
308 } else {
309 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
310 qdev->lrg_buf_free_tail = lrg_buf_cb;
311 }
312
313 if (!lrg_buf_cb->skb) {
314 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
315 qdev->lrg_buffer_len);
316 if (unlikely(!lrg_buf_cb->skb)) {
317 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
318 qdev->ndev->name);
319 qdev->lrg_buf_skb_check++;
320 } else {
321 /*
322 * We save some space to copy the ethhdr from first
323 * buffer
324 */
325 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
326 map = pci_map_single(qdev->pdev,
327 lrg_buf_cb->skb->data,
328 qdev->lrg_buffer_len -
329 QL_HEADER_SPACE,
330 PCI_DMA_FROMDEVICE);
331 err = pci_dma_mapping_error(map);
332 if(err) {
333 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
334 qdev->ndev->name, err);
335 dev_kfree_skb(lrg_buf_cb->skb);
336 lrg_buf_cb->skb = NULL;
337
338 qdev->lrg_buf_skb_check++;
339 return;
340 }
341
342 lrg_buf_cb->buf_phy_addr_low =
343 cpu_to_le32(LS_64BITS(map));
344 lrg_buf_cb->buf_phy_addr_high =
345 cpu_to_le32(MS_64BITS(map));
346 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
347 pci_unmap_len_set(lrg_buf_cb, maplen,
348 qdev->lrg_buffer_len -
349 QL_HEADER_SPACE);
350 }
351 }
352
353 qdev->lrg_buf_free_count++;
354 }
355
356 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
357 *qdev)
358 {
359 struct ql_rcv_buf_cb *lrg_buf_cb;
360
361 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
362 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
363 qdev->lrg_buf_free_tail = NULL;
364 qdev->lrg_buf_free_count--;
365 }
366
367 return lrg_buf_cb;
368 }
369
370 static u32 addrBits = EEPROM_NO_ADDR_BITS;
371 static u32 dataBits = EEPROM_NO_DATA_BITS;
372
373 static void fm93c56a_deselect(struct ql3_adapter *qdev);
374 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
375 unsigned short *value);
376
377 /*
378 * Caller holds hw_lock.
379 */
380 static void fm93c56a_select(struct ql3_adapter *qdev)
381 {
382 struct ql3xxx_port_registers __iomem *port_regs =
383 qdev->mem_map_registers;
384
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
386 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
387 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
388 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
389 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
390 }
391
392 /*
393 * Caller holds hw_lock.
394 */
395 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
396 {
397 int i;
398 u32 mask;
399 u32 dataBit;
400 u32 previousBit;
401 struct ql3xxx_port_registers __iomem *port_regs =
402 qdev->mem_map_registers;
403
404 /* Clock in a zero, then do the start bit */
405 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
406 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1);
408 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
409 ISP_NVRAM_MASK | qdev->
410 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
411 AUBURN_EEPROM_CLK_RISE);
412 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
413 ISP_NVRAM_MASK | qdev->
414 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
415 AUBURN_EEPROM_CLK_FALL);
416
417 mask = 1 << (FM93C56A_CMD_BITS - 1);
418 /* Force the previous data bit to be different */
419 previousBit = 0xffff;
420 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
421 dataBit =
422 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
423 if (previousBit != dataBit) {
424 /*
425 * If the bit changed, then change the DO state to
426 * match
427 */
428 ql_write_nvram_reg(qdev,
429 &port_regs->CommonRegs.
430 serialPortInterfaceReg,
431 ISP_NVRAM_MASK | qdev->
432 eeprom_cmd_data | dataBit);
433 previousBit = dataBit;
434 }
435 ql_write_nvram_reg(qdev,
436 &port_regs->CommonRegs.
437 serialPortInterfaceReg,
438 ISP_NVRAM_MASK | qdev->
439 eeprom_cmd_data | dataBit |
440 AUBURN_EEPROM_CLK_RISE);
441 ql_write_nvram_reg(qdev,
442 &port_regs->CommonRegs.
443 serialPortInterfaceReg,
444 ISP_NVRAM_MASK | qdev->
445 eeprom_cmd_data | dataBit |
446 AUBURN_EEPROM_CLK_FALL);
447 cmd = cmd << 1;
448 }
449
450 mask = 1 << (addrBits - 1);
451 /* Force the previous data bit to be different */
452 previousBit = 0xffff;
453 for (i = 0; i < addrBits; i++) {
454 dataBit =
455 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
456 AUBURN_EEPROM_DO_0;
457 if (previousBit != dataBit) {
458 /*
459 * If the bit changed, then change the DO state to
460 * match
461 */
462 ql_write_nvram_reg(qdev,
463 &port_regs->CommonRegs.
464 serialPortInterfaceReg,
465 ISP_NVRAM_MASK | qdev->
466 eeprom_cmd_data | dataBit);
467 previousBit = dataBit;
468 }
469 ql_write_nvram_reg(qdev,
470 &port_regs->CommonRegs.
471 serialPortInterfaceReg,
472 ISP_NVRAM_MASK | qdev->
473 eeprom_cmd_data | dataBit |
474 AUBURN_EEPROM_CLK_RISE);
475 ql_write_nvram_reg(qdev,
476 &port_regs->CommonRegs.
477 serialPortInterfaceReg,
478 ISP_NVRAM_MASK | qdev->
479 eeprom_cmd_data | dataBit |
480 AUBURN_EEPROM_CLK_FALL);
481 eepromAddr = eepromAddr << 1;
482 }
483 }
484
485 /*
486 * Caller holds hw_lock.
487 */
488 static void fm93c56a_deselect(struct ql3_adapter *qdev)
489 {
490 struct ql3xxx_port_registers __iomem *port_regs =
491 qdev->mem_map_registers;
492 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
493 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
494 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
495 }
496
497 /*
498 * Caller holds hw_lock.
499 */
500 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
501 {
502 int i;
503 u32 data = 0;
504 u32 dataBit;
505 struct ql3xxx_port_registers __iomem *port_regs =
506 qdev->mem_map_registers;
507
508 /* Read the data bits */
509 /* The first bit is a dummy. Clock right over it. */
510 for (i = 0; i < dataBits; i++) {
511 ql_write_nvram_reg(qdev,
512 &port_regs->CommonRegs.
513 serialPortInterfaceReg,
514 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
515 AUBURN_EEPROM_CLK_RISE);
516 ql_write_nvram_reg(qdev,
517 &port_regs->CommonRegs.
518 serialPortInterfaceReg,
519 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
520 AUBURN_EEPROM_CLK_FALL);
521 dataBit =
522 (ql_read_common_reg
523 (qdev,
524 &port_regs->CommonRegs.
525 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
526 data = (data << 1) | dataBit;
527 }
528 *value = (u16) data;
529 }
530
531 /*
532 * Caller holds hw_lock.
533 */
534 static void eeprom_readword(struct ql3_adapter *qdev,
535 u32 eepromAddr, unsigned short *value)
536 {
537 fm93c56a_select(qdev);
538 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
539 fm93c56a_datain(qdev, value);
540 fm93c56a_deselect(qdev);
541 }
542
543 static void ql_swap_mac_addr(u8 * macAddress)
544 {
545 #ifdef __BIG_ENDIAN
546 u8 temp;
547 temp = macAddress[0];
548 macAddress[0] = macAddress[1];
549 macAddress[1] = temp;
550 temp = macAddress[2];
551 macAddress[2] = macAddress[3];
552 macAddress[3] = temp;
553 temp = macAddress[4];
554 macAddress[4] = macAddress[5];
555 macAddress[5] = temp;
556 #endif
557 }
558
559 static int ql_get_nvram_params(struct ql3_adapter *qdev)
560 {
561 u16 *pEEPROMData;
562 u16 checksum = 0;
563 u32 index;
564 unsigned long hw_flags;
565
566 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
567
568 pEEPROMData = (u16 *) & qdev->nvram_data;
569 qdev->eeprom_cmd_data = 0;
570 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
571 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
572 2) << 10)) {
573 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
574 __func__);
575 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
576 return -1;
577 }
578
579 for (index = 0; index < EEPROM_SIZE; index++) {
580 eeprom_readword(qdev, index, pEEPROMData);
581 checksum += *pEEPROMData;
582 pEEPROMData++;
583 }
584 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
585
586 if (checksum != 0) {
587 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
588 qdev->ndev->name, checksum);
589 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
590 return -1;
591 }
592
593 /*
594 * We have a problem with endianness for the MAC addresses
595 * and the two 8-bit values version, and numPorts. We
596 * have to swap them on big endian systems.
597 */
598 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
599 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
600 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
601 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
602 pEEPROMData = (u16 *) & qdev->nvram_data.version;
603 *pEEPROMData = le16_to_cpu(*pEEPROMData);
604
605 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
606 return checksum;
607 }
608
609 static const u32 PHYAddr[2] = {
610 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
611 };
612
613 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
614 {
615 struct ql3xxx_port_registers __iomem *port_regs =
616 qdev->mem_map_registers;
617 u32 temp;
618 int count = 1000;
619
620 while (count) {
621 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
622 if (!(temp & MAC_MII_STATUS_BSY))
623 return 0;
624 udelay(10);
625 count--;
626 }
627 return -1;
628 }
629
630 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
631 {
632 struct ql3xxx_port_registers __iomem *port_regs =
633 qdev->mem_map_registers;
634 u32 scanControl;
635
636 if (qdev->numPorts > 1) {
637 /* Auto scan will cycle through multiple ports */
638 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
639 } else {
640 scanControl = MAC_MII_CONTROL_SC;
641 }
642
643 /*
644 * Scan register 1 of PHY/PETBI,
645 * Set up to scan both devices
646 * The autoscan starts from the first register, completes
647 * the last one before rolling over to the first
648 */
649 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
650 PHYAddr[0] | MII_SCAN_REGISTER);
651
652 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
653 (scanControl) |
654 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
655 }
656
657 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
658 {
659 u8 ret;
660 struct ql3xxx_port_registers __iomem *port_regs =
661 qdev->mem_map_registers;
662
663 /* See if scan mode is enabled before we turn it off */
664 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
665 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
666 /* Scan is enabled */
667 ret = 1;
668 } else {
669 /* Scan is disabled */
670 ret = 0;
671 }
672
673 /*
674 * When disabling scan mode you must first change the MII register
675 * address
676 */
677 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
678 PHYAddr[0] | MII_SCAN_REGISTER);
679
680 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
681 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
682 MAC_MII_CONTROL_RC) << 16));
683
684 return ret;
685 }
686
687 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
688 u16 regAddr, u16 value, u32 phyAddr)
689 {
690 struct ql3xxx_port_registers __iomem *port_regs =
691 qdev->mem_map_registers;
692 u8 scanWasEnabled;
693
694 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
695
696 if (ql_wait_for_mii_ready(qdev)) {
697 if (netif_msg_link(qdev))
698 printk(KERN_WARNING PFX
699 "%s Timed out waiting for management port to "
700 "get free before issuing command.\n",
701 qdev->ndev->name);
702 return -1;
703 }
704
705 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
706 phyAddr | regAddr);
707
708 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
709
710 /* Wait for write to complete 9/10/04 SJP */
711 if (ql_wait_for_mii_ready(qdev)) {
712 if (netif_msg_link(qdev))
713 printk(KERN_WARNING PFX
714 "%s: Timed out waiting for management port to"
715 "get free before issuing command.\n",
716 qdev->ndev->name);
717 return -1;
718 }
719
720 if (scanWasEnabled)
721 ql_mii_enable_scan_mode(qdev);
722
723 return 0;
724 }
725
726 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
727 u16 * value, u32 phyAddr)
728 {
729 struct ql3xxx_port_registers __iomem *port_regs =
730 qdev->mem_map_registers;
731 u8 scanWasEnabled;
732 u32 temp;
733
734 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
735
736 if (ql_wait_for_mii_ready(qdev)) {
737 if (netif_msg_link(qdev))
738 printk(KERN_WARNING PFX
739 "%s: Timed out waiting for management port to "
740 "get free before issuing command.\n",
741 qdev->ndev->name);
742 return -1;
743 }
744
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
746 phyAddr | regAddr);
747
748 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
749 (MAC_MII_CONTROL_RC << 16));
750
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
752 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
753
754 /* Wait for the read to complete */
755 if (ql_wait_for_mii_ready(qdev)) {
756 if (netif_msg_link(qdev))
757 printk(KERN_WARNING PFX
758 "%s: Timed out waiting for management port to "
759 "get free after issuing command.\n",
760 qdev->ndev->name);
761 return -1;
762 }
763
764 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
765 *value = (u16) temp;
766
767 if (scanWasEnabled)
768 ql_mii_enable_scan_mode(qdev);
769
770 return 0;
771 }
772
773 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
774 {
775 struct ql3xxx_port_registers __iomem *port_regs =
776 qdev->mem_map_registers;
777
778 ql_mii_disable_scan_mode(qdev);
779
780 if (ql_wait_for_mii_ready(qdev)) {
781 if (netif_msg_link(qdev))
782 printk(KERN_WARNING PFX
783 "%s: Timed out waiting for management port to "
784 "get free before issuing command.\n",
785 qdev->ndev->name);
786 return -1;
787 }
788
789 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
790 qdev->PHYAddr | regAddr);
791
792 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
793
794 /* Wait for write to complete. */
795 if (ql_wait_for_mii_ready(qdev)) {
796 if (netif_msg_link(qdev))
797 printk(KERN_WARNING PFX
798 "%s: Timed out waiting for management port to "
799 "get free before issuing command.\n",
800 qdev->ndev->name);
801 return -1;
802 }
803
804 ql_mii_enable_scan_mode(qdev);
805
806 return 0;
807 }
808
809 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
810 {
811 u32 temp;
812 struct ql3xxx_port_registers __iomem *port_regs =
813 qdev->mem_map_registers;
814
815 ql_mii_disable_scan_mode(qdev);
816
817 if (ql_wait_for_mii_ready(qdev)) {
818 if (netif_msg_link(qdev))
819 printk(KERN_WARNING PFX
820 "%s: Timed out waiting for management port to "
821 "get free before issuing command.\n",
822 qdev->ndev->name);
823 return -1;
824 }
825
826 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
827 qdev->PHYAddr | regAddr);
828
829 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
830 (MAC_MII_CONTROL_RC << 16));
831
832 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
833 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
834
835 /* Wait for the read to complete */
836 if (ql_wait_for_mii_ready(qdev)) {
837 if (netif_msg_link(qdev))
838 printk(KERN_WARNING PFX
839 "%s: Timed out waiting for management port to "
840 "get free before issuing command.\n",
841 qdev->ndev->name);
842 return -1;
843 }
844
845 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
846 *value = (u16) temp;
847
848 ql_mii_enable_scan_mode(qdev);
849
850 return 0;
851 }
852
853 static void ql_petbi_reset(struct ql3_adapter *qdev)
854 {
855 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
856 }
857
858 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
859 {
860 u16 reg;
861
862 /* Enable Auto-negotiation sense */
863 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
864 reg |= PETBI_TBI_AUTO_SENSE;
865 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
866
867 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
868 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
869
870 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
871 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
872 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
873
874 }
875
876 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
877 {
878 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
879 PHYAddr[qdev->mac_index]);
880 }
881
882 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
883 {
884 u16 reg;
885
886 /* Enable Auto-negotiation sense */
887 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
888 PHYAddr[qdev->mac_index]);
889 reg |= PETBI_TBI_AUTO_SENSE;
890 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
891 PHYAddr[qdev->mac_index]);
892
893 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
894 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
895 PHYAddr[qdev->mac_index]);
896
897 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
898 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
899 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
900 PHYAddr[qdev->mac_index]);
901 }
902
903 static void ql_petbi_init(struct ql3_adapter *qdev)
904 {
905 ql_petbi_reset(qdev);
906 ql_petbi_start_neg(qdev);
907 }
908
909 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
910 {
911 ql_petbi_reset_ex(qdev);
912 ql_petbi_start_neg_ex(qdev);
913 }
914
915 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
916 {
917 u16 reg;
918
919 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
920 return 0;
921
922 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
923 }
924
925 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
926 {
927 printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
928 /* power down device bit 11 = 1 */
929 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
930 /* enable diagnostic mode bit 2 = 1 */
931 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
932 /* 1000MB amplitude adjust (see Agere errata) */
933 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
934 /* 1000MB amplitude adjust (see Agere errata) */
935 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
936 /* 100MB amplitude adjust (see Agere errata) */
937 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
938 /* 100MB amplitude adjust (see Agere errata) */
939 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
940 /* 10MB amplitude adjust (see Agere errata) */
941 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
942 /* 10MB amplitude adjust (see Agere errata) */
943 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
944 /* point to hidden reg 0x2806 */
945 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
946 /* Write new PHYAD w/bit 5 set */
947 ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
948 /*
949 * Disable diagnostic mode bit 2 = 0
950 * Power up device bit 11 = 0
951 * Link up (on) and activity (blink)
952 */
953 ql_mii_write_reg(qdev, 0x12, 0x840a);
954 ql_mii_write_reg(qdev, 0x00, 0x1140);
955 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
956 }
957
958 static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
959 u16 phyIdReg0, u16 phyIdReg1)
960 {
961 PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
962 u32 oui;
963 u16 model;
964 int i;
965
966 if (phyIdReg0 == 0xffff) {
967 return result;
968 }
969
970 if (phyIdReg1 == 0xffff) {
971 return result;
972 }
973
974 /* oui is split between two registers */
975 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
976
977 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
978
979 /* Scan table for this PHY */
980 for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
981 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
982 {
983 result = PHY_DEVICES[i].phyDevice;
984
985 printk(KERN_INFO "%s: Phy: %s\n",
986 qdev->ndev->name, PHY_DEVICES[i].name);
987
988 break;
989 }
990 }
991
992 return result;
993 }
994
995 static int ql_phy_get_speed(struct ql3_adapter *qdev)
996 {
997 u16 reg;
998
999 switch(qdev->phyType) {
1000 case PHY_AGERE_ET1011C:
1001 {
1002 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
1003 return 0;
1004
1005 reg = (reg >> 8) & 3;
1006 break;
1007 }
1008 default:
1009 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1010 return 0;
1011
1012 reg = (((reg & 0x18) >> 3) & 3);
1013 }
1014
1015 switch(reg) {
1016 case 2:
1017 return SPEED_1000;
1018 case 1:
1019 return SPEED_100;
1020 case 0:
1021 return SPEED_10;
1022 default:
1023 return -1;
1024 }
1025 }
1026
1027 static int ql_is_full_dup(struct ql3_adapter *qdev)
1028 {
1029 u16 reg;
1030
1031 switch(qdev->phyType) {
1032 case PHY_AGERE_ET1011C:
1033 {
1034 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1035 return 0;
1036
1037 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1038 }
1039 case PHY_VITESSE_VSC8211:
1040 default:
1041 {
1042 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1043 return 0;
1044 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1045 }
1046 }
1047 }
1048
1049 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1050 {
1051 u16 reg;
1052
1053 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1054 return 0;
1055
1056 return (reg & PHY_NEG_PAUSE) != 0;
1057 }
1058
1059 static int PHY_Setup(struct ql3_adapter *qdev)
1060 {
1061 u16 reg1;
1062 u16 reg2;
1063 bool agereAddrChangeNeeded = false;
1064 u32 miiAddr = 0;
1065 int err;
1066
1067 /* Determine the PHY we are using by reading the ID's */
1068 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1069 if(err != 0) {
1070 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1071 qdev->ndev->name);
1072 return err;
1073 }
1074
1075 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1076 if(err != 0) {
1077 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1078 qdev->ndev->name);
1079 return err;
1080 }
1081
1082 /* Check if we have a Agere PHY */
1083 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1084
1085 /* Determine which MII address we should be using
1086 determined by the index of the card */
1087 if (qdev->mac_index == 0) {
1088 miiAddr = MII_AGERE_ADDR_1;
1089 } else {
1090 miiAddr = MII_AGERE_ADDR_2;
1091 }
1092
1093 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1094 if(err != 0) {
1095 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1096 qdev->ndev->name);
1097 return err;
1098 }
1099
1100 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1101 if(err != 0) {
1102 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1103 qdev->ndev->name);
1104 return err;
1105 }
1106
1107 /* We need to remember to initialize the Agere PHY */
1108 agereAddrChangeNeeded = true;
1109 }
1110
1111 /* Determine the particular PHY we have on board to apply
1112 PHY specific initializations */
1113 qdev->phyType = getPhyType(qdev, reg1, reg2);
1114
1115 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1116 /* need this here so address gets changed */
1117 phyAgereSpecificInit(qdev, miiAddr);
1118 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1119 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1120 return -EIO;
1121 }
1122
1123 return 0;
1124 }
1125
1126 /*
1127 * Caller holds hw_lock.
1128 */
1129 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1130 {
1131 struct ql3xxx_port_registers __iomem *port_regs =
1132 qdev->mem_map_registers;
1133 u32 value;
1134
1135 if (enable)
1136 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1137 else
1138 value = (MAC_CONFIG_REG_PE << 16);
1139
1140 if (qdev->mac_index)
1141 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1142 else
1143 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1144 }
1145
1146 /*
1147 * Caller holds hw_lock.
1148 */
1149 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1150 {
1151 struct ql3xxx_port_registers __iomem *port_regs =
1152 qdev->mem_map_registers;
1153 u32 value;
1154
1155 if (enable)
1156 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1157 else
1158 value = (MAC_CONFIG_REG_SR << 16);
1159
1160 if (qdev->mac_index)
1161 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1162 else
1163 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1164 }
1165
1166 /*
1167 * Caller holds hw_lock.
1168 */
1169 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1170 {
1171 struct ql3xxx_port_registers __iomem *port_regs =
1172 qdev->mem_map_registers;
1173 u32 value;
1174
1175 if (enable)
1176 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1177 else
1178 value = (MAC_CONFIG_REG_GM << 16);
1179
1180 if (qdev->mac_index)
1181 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1182 else
1183 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1184 }
1185
1186 /*
1187 * Caller holds hw_lock.
1188 */
1189 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1190 {
1191 struct ql3xxx_port_registers __iomem *port_regs =
1192 qdev->mem_map_registers;
1193 u32 value;
1194
1195 if (enable)
1196 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1197 else
1198 value = (MAC_CONFIG_REG_FD << 16);
1199
1200 if (qdev->mac_index)
1201 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1202 else
1203 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1204 }
1205
1206 /*
1207 * Caller holds hw_lock.
1208 */
1209 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1210 {
1211 struct ql3xxx_port_registers __iomem *port_regs =
1212 qdev->mem_map_registers;
1213 u32 value;
1214
1215 if (enable)
1216 value =
1217 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1218 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1219 else
1220 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1221
1222 if (qdev->mac_index)
1223 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1224 else
1225 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1226 }
1227
1228 /*
1229 * Caller holds hw_lock.
1230 */
1231 static int ql_is_fiber(struct ql3_adapter *qdev)
1232 {
1233 struct ql3xxx_port_registers __iomem *port_regs =
1234 qdev->mem_map_registers;
1235 u32 bitToCheck = 0;
1236 u32 temp;
1237
1238 switch (qdev->mac_index) {
1239 case 0:
1240 bitToCheck = PORT_STATUS_SM0;
1241 break;
1242 case 1:
1243 bitToCheck = PORT_STATUS_SM1;
1244 break;
1245 }
1246
1247 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1248 return (temp & bitToCheck) != 0;
1249 }
1250
1251 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1252 {
1253 u16 reg;
1254 ql_mii_read_reg(qdev, 0x00, &reg);
1255 return (reg & 0x1000) != 0;
1256 }
1257
1258 /*
1259 * Caller holds hw_lock.
1260 */
1261 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1262 {
1263 struct ql3xxx_port_registers __iomem *port_regs =
1264 qdev->mem_map_registers;
1265 u32 bitToCheck = 0;
1266 u32 temp;
1267
1268 switch (qdev->mac_index) {
1269 case 0:
1270 bitToCheck = PORT_STATUS_AC0;
1271 break;
1272 case 1:
1273 bitToCheck = PORT_STATUS_AC1;
1274 break;
1275 }
1276
1277 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1278 if (temp & bitToCheck) {
1279 if (netif_msg_link(qdev))
1280 printk(KERN_INFO PFX
1281 "%s: Auto-Negotiate complete.\n",
1282 qdev->ndev->name);
1283 return 1;
1284 } else {
1285 if (netif_msg_link(qdev))
1286 printk(KERN_WARNING PFX
1287 "%s: Auto-Negotiate incomplete.\n",
1288 qdev->ndev->name);
1289 return 0;
1290 }
1291 }
1292
1293 /*
1294 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1295 */
1296 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1297 {
1298 if (ql_is_fiber(qdev))
1299 return ql_is_petbi_neg_pause(qdev);
1300 else
1301 return ql_is_phy_neg_pause(qdev);
1302 }
1303
1304 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1305 {
1306 struct ql3xxx_port_registers __iomem *port_regs =
1307 qdev->mem_map_registers;
1308 u32 bitToCheck = 0;
1309 u32 temp;
1310
1311 switch (qdev->mac_index) {
1312 case 0:
1313 bitToCheck = PORT_STATUS_AE0;
1314 break;
1315 case 1:
1316 bitToCheck = PORT_STATUS_AE1;
1317 break;
1318 }
1319 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1320 return (temp & bitToCheck) != 0;
1321 }
1322
1323 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1324 {
1325 if (ql_is_fiber(qdev))
1326 return SPEED_1000;
1327 else
1328 return ql_phy_get_speed(qdev);
1329 }
1330
1331 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1332 {
1333 if (ql_is_fiber(qdev))
1334 return 1;
1335 else
1336 return ql_is_full_dup(qdev);
1337 }
1338
1339 /*
1340 * Caller holds hw_lock.
1341 */
1342 static int ql_link_down_detect(struct ql3_adapter *qdev)
1343 {
1344 struct ql3xxx_port_registers __iomem *port_regs =
1345 qdev->mem_map_registers;
1346 u32 bitToCheck = 0;
1347 u32 temp;
1348
1349 switch (qdev->mac_index) {
1350 case 0:
1351 bitToCheck = ISP_CONTROL_LINK_DN_0;
1352 break;
1353 case 1:
1354 bitToCheck = ISP_CONTROL_LINK_DN_1;
1355 break;
1356 }
1357
1358 temp =
1359 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1360 return (temp & bitToCheck) != 0;
1361 }
1362
1363 /*
1364 * Caller holds hw_lock.
1365 */
1366 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1367 {
1368 struct ql3xxx_port_registers __iomem *port_regs =
1369 qdev->mem_map_registers;
1370
1371 switch (qdev->mac_index) {
1372 case 0:
1373 ql_write_common_reg(qdev,
1374 &port_regs->CommonRegs.ispControlStatus,
1375 (ISP_CONTROL_LINK_DN_0) |
1376 (ISP_CONTROL_LINK_DN_0 << 16));
1377 break;
1378
1379 case 1:
1380 ql_write_common_reg(qdev,
1381 &port_regs->CommonRegs.ispControlStatus,
1382 (ISP_CONTROL_LINK_DN_1) |
1383 (ISP_CONTROL_LINK_DN_1 << 16));
1384 break;
1385
1386 default:
1387 return 1;
1388 }
1389
1390 return 0;
1391 }
1392
1393 /*
1394 * Caller holds hw_lock.
1395 */
1396 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1397 {
1398 struct ql3xxx_port_registers __iomem *port_regs =
1399 qdev->mem_map_registers;
1400 u32 bitToCheck = 0;
1401 u32 temp;
1402
1403 switch (qdev->mac_index) {
1404 case 0:
1405 bitToCheck = PORT_STATUS_F1_ENABLED;
1406 break;
1407 case 1:
1408 bitToCheck = PORT_STATUS_F3_ENABLED;
1409 break;
1410 default:
1411 break;
1412 }
1413
1414 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1415 if (temp & bitToCheck) {
1416 if (netif_msg_link(qdev))
1417 printk(KERN_DEBUG PFX
1418 "%s: is not link master.\n", qdev->ndev->name);
1419 return 0;
1420 } else {
1421 if (netif_msg_link(qdev))
1422 printk(KERN_DEBUG PFX
1423 "%s: is link master.\n", qdev->ndev->name);
1424 return 1;
1425 }
1426 }
1427
1428 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1429 {
1430 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1431 PHYAddr[qdev->mac_index]);
1432 }
1433
1434 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1435 {
1436 u16 reg;
1437 u16 portConfiguration;
1438
1439 if(qdev->phyType == PHY_AGERE_ET1011C) {
1440 /* turn off external loopback */
1441 ql_mii_write_reg(qdev, 0x13, 0x0000);
1442 }
1443
1444 if(qdev->mac_index == 0)
1445 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1446 else
1447 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1448
1449 /* Some HBA's in the field are set to 0 and they need to
1450 be reinterpreted with a default value */
1451 if(portConfiguration == 0)
1452 portConfiguration = PORT_CONFIG_DEFAULT;
1453
1454 /* Set the 1000 advertisements */
1455 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
1456 PHYAddr[qdev->mac_index]);
1457 reg &= ~PHY_GIG_ALL_PARAMS;
1458
1459 if(portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1460 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1461 reg |= PHY_GIG_ADV_1000F;
1462 else
1463 reg |= PHY_GIG_ADV_1000H;
1464 }
1465
1466 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1467 PHYAddr[qdev->mac_index]);
1468
1469 /* Set the 10/100 & pause negotiation advertisements */
1470 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1471 PHYAddr[qdev->mac_index]);
1472 reg &= ~PHY_NEG_ALL_PARAMS;
1473
1474 if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1475 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1476
1477 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1478 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1479 reg |= PHY_NEG_ADV_100F;
1480
1481 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1482 reg |= PHY_NEG_ADV_10F;
1483 }
1484
1485 if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1486 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1487 reg |= PHY_NEG_ADV_100H;
1488
1489 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1490 reg |= PHY_NEG_ADV_10H;
1491 }
1492
1493 if(portConfiguration &
1494 PORT_CONFIG_1000MB_SPEED) {
1495 reg |= 1;
1496 }
1497
1498 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1499 PHYAddr[qdev->mac_index]);
1500
1501 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1502
1503 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1504 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1505 PHYAddr[qdev->mac_index]);
1506 }
1507
1508 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1509 {
1510 ql_phy_reset_ex(qdev);
1511 PHY_Setup(qdev);
1512 ql_phy_start_neg_ex(qdev);
1513 }
1514
1515 /*
1516 * Caller holds hw_lock.
1517 */
1518 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1519 {
1520 struct ql3xxx_port_registers __iomem *port_regs =
1521 qdev->mem_map_registers;
1522 u32 bitToCheck = 0;
1523 u32 temp, linkState;
1524
1525 switch (qdev->mac_index) {
1526 case 0:
1527 bitToCheck = PORT_STATUS_UP0;
1528 break;
1529 case 1:
1530 bitToCheck = PORT_STATUS_UP1;
1531 break;
1532 }
1533 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1534 if (temp & bitToCheck) {
1535 linkState = LS_UP;
1536 } else {
1537 linkState = LS_DOWN;
1538 if (netif_msg_link(qdev))
1539 printk(KERN_WARNING PFX
1540 "%s: Link is down.\n", qdev->ndev->name);
1541 }
1542 return linkState;
1543 }
1544
1545 static int ql_port_start(struct ql3_adapter *qdev)
1546 {
1547 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1548 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1549 2) << 7)) {
1550 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1551 qdev->ndev->name);
1552 return -1;
1553 }
1554
1555 if (ql_is_fiber(qdev)) {
1556 ql_petbi_init(qdev);
1557 } else {
1558 /* Copper port */
1559 ql_phy_init_ex(qdev);
1560 }
1561
1562 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1563 return 0;
1564 }
1565
1566 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1567 {
1568
1569 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1570 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1571 2) << 7))
1572 return -1;
1573
1574 if (!ql_auto_neg_error(qdev)) {
1575 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1576 /* configure the MAC */
1577 if (netif_msg_link(qdev))
1578 printk(KERN_DEBUG PFX
1579 "%s: Configuring link.\n",
1580 qdev->ndev->
1581 name);
1582 ql_mac_cfg_soft_reset(qdev, 1);
1583 ql_mac_cfg_gig(qdev,
1584 (ql_get_link_speed
1585 (qdev) ==
1586 SPEED_1000));
1587 ql_mac_cfg_full_dup(qdev,
1588 ql_is_link_full_dup
1589 (qdev));
1590 ql_mac_cfg_pause(qdev,
1591 ql_is_neg_pause
1592 (qdev));
1593 ql_mac_cfg_soft_reset(qdev, 0);
1594
1595 /* enable the MAC */
1596 if (netif_msg_link(qdev))
1597 printk(KERN_DEBUG PFX
1598 "%s: Enabling mac.\n",
1599 qdev->ndev->
1600 name);
1601 ql_mac_enable(qdev, 1);
1602 }
1603
1604 if (netif_msg_link(qdev))
1605 printk(KERN_DEBUG PFX
1606 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1607 qdev->ndev->name);
1608 qdev->port_link_state = LS_UP;
1609 netif_start_queue(qdev->ndev);
1610 netif_carrier_on(qdev->ndev);
1611 if (netif_msg_link(qdev))
1612 printk(KERN_INFO PFX
1613 "%s: Link is up at %d Mbps, %s duplex.\n",
1614 qdev->ndev->name,
1615 ql_get_link_speed(qdev),
1616 ql_is_link_full_dup(qdev)
1617 ? "full" : "half");
1618
1619 } else { /* Remote error detected */
1620
1621 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1622 if (netif_msg_link(qdev))
1623 printk(KERN_DEBUG PFX
1624 "%s: Remote error detected. "
1625 "Calling ql_port_start().\n",
1626 qdev->ndev->
1627 name);
1628 /*
1629 * ql_port_start() is shared code and needs
1630 * to lock the PHY on it's own.
1631 */
1632 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1633 if(ql_port_start(qdev)) {/* Restart port */
1634 return -1;
1635 } else
1636 return 0;
1637 }
1638 }
1639 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1640 return 0;
1641 }
1642
1643 static void ql_link_state_machine_work(struct work_struct *work)
1644 {
1645 struct ql3_adapter *qdev =
1646 container_of(work, struct ql3_adapter, link_state_work.work);
1647
1648 u32 curr_link_state;
1649 unsigned long hw_flags;
1650
1651 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1652
1653 curr_link_state = ql_get_link_state(qdev);
1654
1655 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1656 if (netif_msg_link(qdev))
1657 printk(KERN_INFO PFX
1658 "%s: Reset in progress, skip processing link "
1659 "state.\n", qdev->ndev->name);
1660
1661 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1662
1663 /* Restart timer on 2 second interval. */
1664 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);\
1665
1666 return;
1667 }
1668
1669 switch (qdev->port_link_state) {
1670 default:
1671 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1672 ql_port_start(qdev);
1673 }
1674 qdev->port_link_state = LS_DOWN;
1675 /* Fall Through */
1676
1677 case LS_DOWN:
1678 if (netif_msg_link(qdev))
1679 printk(KERN_DEBUG PFX
1680 "%s: port_link_state = LS_DOWN.\n",
1681 qdev->ndev->name);
1682 if (curr_link_state == LS_UP) {
1683 if (netif_msg_link(qdev))
1684 printk(KERN_DEBUG PFX
1685 "%s: curr_link_state = LS_UP.\n",
1686 qdev->ndev->name);
1687 if (ql_is_auto_neg_complete(qdev))
1688 ql_finish_auto_neg(qdev);
1689
1690 if (qdev->port_link_state == LS_UP)
1691 ql_link_down_detect_clear(qdev);
1692
1693 }
1694 break;
1695
1696 case LS_UP:
1697 /*
1698 * See if the link is currently down or went down and came
1699 * back up
1700 */
1701 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1702 if (netif_msg_link(qdev))
1703 printk(KERN_INFO PFX "%s: Link is down.\n",
1704 qdev->ndev->name);
1705 qdev->port_link_state = LS_DOWN;
1706 }
1707 break;
1708 }
1709 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1710
1711 /* Restart timer on 2 second interval. */
1712 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1713 }
1714
1715 /*
1716 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1717 */
1718 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1719 {
1720 if (ql_this_adapter_controls_port(qdev))
1721 set_bit(QL_LINK_MASTER,&qdev->flags);
1722 else
1723 clear_bit(QL_LINK_MASTER,&qdev->flags);
1724 }
1725
1726 /*
1727 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1728 */
1729 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1730 {
1731 ql_mii_enable_scan_mode(qdev);
1732
1733 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1734 if (ql_this_adapter_controls_port(qdev))
1735 ql_petbi_init_ex(qdev);
1736 } else {
1737 if (ql_this_adapter_controls_port(qdev))
1738 ql_phy_init_ex(qdev);
1739 }
1740 }
1741
1742 /*
1743 * MII_Setup needs to be called before taking the PHY out of reset so that the
1744 * management interface clock speed can be set properly. It would be better if
1745 * we had a way to disable MDC until after the PHY is out of reset, but we
1746 * don't have that capability.
1747 */
1748 static int ql_mii_setup(struct ql3_adapter *qdev)
1749 {
1750 u32 reg;
1751 struct ql3xxx_port_registers __iomem *port_regs =
1752 qdev->mem_map_registers;
1753
1754 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1755 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1756 2) << 7))
1757 return -1;
1758
1759 if (qdev->device_id == QL3032_DEVICE_ID)
1760 ql_write_page0_reg(qdev,
1761 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1762
1763 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1764 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1765
1766 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1767 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1768
1769 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1770 return 0;
1771 }
1772
1773 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1774 {
1775 u32 supported;
1776
1777 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1778 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1779 | SUPPORTED_Autoneg;
1780 } else {
1781 supported = SUPPORTED_10baseT_Half
1782 | SUPPORTED_10baseT_Full
1783 | SUPPORTED_100baseT_Half
1784 | SUPPORTED_100baseT_Full
1785 | SUPPORTED_1000baseT_Half
1786 | SUPPORTED_1000baseT_Full
1787 | SUPPORTED_Autoneg | SUPPORTED_TP;
1788 }
1789
1790 return supported;
1791 }
1792
1793 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1794 {
1795 int status;
1796 unsigned long hw_flags;
1797 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1798 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1799 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1800 2) << 7)) {
1801 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1802 return 0;
1803 }
1804 status = ql_is_auto_cfg(qdev);
1805 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1806 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1807 return status;
1808 }
1809
1810 static u32 ql_get_speed(struct ql3_adapter *qdev)
1811 {
1812 u32 status;
1813 unsigned long hw_flags;
1814 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1815 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1816 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1817 2) << 7)) {
1818 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1819 return 0;
1820 }
1821 status = ql_get_link_speed(qdev);
1822 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1823 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1824 return status;
1825 }
1826
1827 static int ql_get_full_dup(struct ql3_adapter *qdev)
1828 {
1829 int status;
1830 unsigned long hw_flags;
1831 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1832 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1833 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1834 2) << 7)) {
1835 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1836 return 0;
1837 }
1838 status = ql_is_link_full_dup(qdev);
1839 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1840 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1841 return status;
1842 }
1843
1844
1845 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1846 {
1847 struct ql3_adapter *qdev = netdev_priv(ndev);
1848
1849 ecmd->transceiver = XCVR_INTERNAL;
1850 ecmd->supported = ql_supported_modes(qdev);
1851
1852 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1853 ecmd->port = PORT_FIBRE;
1854 } else {
1855 ecmd->port = PORT_TP;
1856 ecmd->phy_address = qdev->PHYAddr;
1857 }
1858 ecmd->advertising = ql_supported_modes(qdev);
1859 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1860 ecmd->speed = ql_get_speed(qdev);
1861 ecmd->duplex = ql_get_full_dup(qdev);
1862 return 0;
1863 }
1864
1865 static void ql_get_drvinfo(struct net_device *ndev,
1866 struct ethtool_drvinfo *drvinfo)
1867 {
1868 struct ql3_adapter *qdev = netdev_priv(ndev);
1869 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1870 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1871 strncpy(drvinfo->fw_version, "N/A", 32);
1872 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1873 drvinfo->regdump_len = 0;
1874 drvinfo->eedump_len = 0;
1875 }
1876
1877 static u32 ql_get_msglevel(struct net_device *ndev)
1878 {
1879 struct ql3_adapter *qdev = netdev_priv(ndev);
1880 return qdev->msg_enable;
1881 }
1882
1883 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1884 {
1885 struct ql3_adapter *qdev = netdev_priv(ndev);
1886 qdev->msg_enable = value;
1887 }
1888
1889 static void ql_get_pauseparam(struct net_device *ndev,
1890 struct ethtool_pauseparam *pause)
1891 {
1892 struct ql3_adapter *qdev = netdev_priv(ndev);
1893 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1894
1895 u32 reg;
1896 if(qdev->mac_index == 0)
1897 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1898 else
1899 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1900
1901 pause->autoneg = ql_get_auto_cfg_status(qdev);
1902 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1903 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1904 }
1905
1906 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1907 .get_settings = ql_get_settings,
1908 .get_drvinfo = ql_get_drvinfo,
1909 .get_link = ethtool_op_get_link,
1910 .get_msglevel = ql_get_msglevel,
1911 .set_msglevel = ql_set_msglevel,
1912 .get_pauseparam = ql_get_pauseparam,
1913 };
1914
1915 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1916 {
1917 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1918 dma_addr_t map;
1919 int err;
1920
1921 while (lrg_buf_cb) {
1922 if (!lrg_buf_cb->skb) {
1923 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1924 qdev->lrg_buffer_len);
1925 if (unlikely(!lrg_buf_cb->skb)) {
1926 printk(KERN_DEBUG PFX
1927 "%s: Failed netdev_alloc_skb().\n",
1928 qdev->ndev->name);
1929 break;
1930 } else {
1931 /*
1932 * We save some space to copy the ethhdr from
1933 * first buffer
1934 */
1935 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1936 map = pci_map_single(qdev->pdev,
1937 lrg_buf_cb->skb->data,
1938 qdev->lrg_buffer_len -
1939 QL_HEADER_SPACE,
1940 PCI_DMA_FROMDEVICE);
1941
1942 err = pci_dma_mapping_error(map);
1943 if(err) {
1944 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1945 qdev->ndev->name, err);
1946 dev_kfree_skb(lrg_buf_cb->skb);
1947 lrg_buf_cb->skb = NULL;
1948 break;
1949 }
1950
1951
1952 lrg_buf_cb->buf_phy_addr_low =
1953 cpu_to_le32(LS_64BITS(map));
1954 lrg_buf_cb->buf_phy_addr_high =
1955 cpu_to_le32(MS_64BITS(map));
1956 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1957 pci_unmap_len_set(lrg_buf_cb, maplen,
1958 qdev->lrg_buffer_len -
1959 QL_HEADER_SPACE);
1960 --qdev->lrg_buf_skb_check;
1961 if (!qdev->lrg_buf_skb_check)
1962 return 1;
1963 }
1964 }
1965 lrg_buf_cb = lrg_buf_cb->next;
1966 }
1967 return 0;
1968 }
1969
1970 /*
1971 * Caller holds hw_lock.
1972 */
1973 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1974 {
1975 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1976 if (qdev->small_buf_release_cnt >= 16) {
1977 while (qdev->small_buf_release_cnt >= 16) {
1978 qdev->small_buf_q_producer_index++;
1979
1980 if (qdev->small_buf_q_producer_index ==
1981 NUM_SBUFQ_ENTRIES)
1982 qdev->small_buf_q_producer_index = 0;
1983 qdev->small_buf_release_cnt -= 8;
1984 }
1985 wmb();
1986 writel(qdev->small_buf_q_producer_index,
1987 &port_regs->CommonRegs.rxSmallQProducerIndex);
1988 }
1989 }
1990
1991 /*
1992 * Caller holds hw_lock.
1993 */
1994 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1995 {
1996 struct bufq_addr_element *lrg_buf_q_ele;
1997 int i;
1998 struct ql_rcv_buf_cb *lrg_buf_cb;
1999 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2000
2001 if ((qdev->lrg_buf_free_count >= 8)
2002 && (qdev->lrg_buf_release_cnt >= 16)) {
2003
2004 if (qdev->lrg_buf_skb_check)
2005 if (!ql_populate_free_queue(qdev))
2006 return;
2007
2008 lrg_buf_q_ele = qdev->lrg_buf_next_free;
2009
2010 while ((qdev->lrg_buf_release_cnt >= 16)
2011 && (qdev->lrg_buf_free_count >= 8)) {
2012
2013 for (i = 0; i < 8; i++) {
2014 lrg_buf_cb =
2015 ql_get_from_lrg_buf_free_list(qdev);
2016 lrg_buf_q_ele->addr_high =
2017 lrg_buf_cb->buf_phy_addr_high;
2018 lrg_buf_q_ele->addr_low =
2019 lrg_buf_cb->buf_phy_addr_low;
2020 lrg_buf_q_ele++;
2021
2022 qdev->lrg_buf_release_cnt--;
2023 }
2024
2025 qdev->lrg_buf_q_producer_index++;
2026
2027 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
2028 qdev->lrg_buf_q_producer_index = 0;
2029
2030 if (qdev->lrg_buf_q_producer_index ==
2031 (qdev->num_lbufq_entries - 1)) {
2032 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2033 }
2034 }
2035 wmb();
2036 qdev->lrg_buf_next_free = lrg_buf_q_ele;
2037 writel(qdev->lrg_buf_q_producer_index,
2038 &port_regs->CommonRegs.rxLargeQProducerIndex);
2039 }
2040 }
2041
2042 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2043 struct ob_mac_iocb_rsp *mac_rsp)
2044 {
2045 struct ql_tx_buf_cb *tx_cb;
2046 int i;
2047 int retval = 0;
2048
2049 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2050 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2051 }
2052
2053 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
2054
2055 /* Check the transmit response flags for any errors */
2056 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2057 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2058
2059 qdev->ndev->stats.tx_errors++;
2060 retval = -EIO;
2061 goto frame_not_sent;
2062 }
2063
2064 if(tx_cb->seg_count == 0) {
2065 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2066
2067 qdev->ndev->stats.tx_errors++;
2068 retval = -EIO;
2069 goto invalid_seg_count;
2070 }
2071
2072 pci_unmap_single(qdev->pdev,
2073 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2074 pci_unmap_len(&tx_cb->map[0], maplen),
2075 PCI_DMA_TODEVICE);
2076 tx_cb->seg_count--;
2077 if (tx_cb->seg_count) {
2078 for (i = 1; i < tx_cb->seg_count; i++) {
2079 pci_unmap_page(qdev->pdev,
2080 pci_unmap_addr(&tx_cb->map[i],
2081 mapaddr),
2082 pci_unmap_len(&tx_cb->map[i], maplen),
2083 PCI_DMA_TODEVICE);
2084 }
2085 }
2086 qdev->ndev->stats.tx_packets++;
2087 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
2088
2089 frame_not_sent:
2090 dev_kfree_skb_irq(tx_cb->skb);
2091 tx_cb->skb = NULL;
2092
2093 invalid_seg_count:
2094 atomic_inc(&qdev->tx_count);
2095 }
2096
2097 static void ql_get_sbuf(struct ql3_adapter *qdev)
2098 {
2099 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2100 qdev->small_buf_index = 0;
2101 qdev->small_buf_release_cnt++;
2102 }
2103
2104 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
2105 {
2106 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2107 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2108 qdev->lrg_buf_release_cnt++;
2109 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2110 qdev->lrg_buf_index = 0;
2111 return(lrg_buf_cb);
2112 }
2113
2114 /*
2115 * The difference between 3022 and 3032 for inbound completions:
2116 * 3022 uses two buffers per completion. The first buffer contains
2117 * (some) header info, the second the remainder of the headers plus
2118 * the data. For this chip we reserve some space at the top of the
2119 * receive buffer so that the header info in buffer one can be
2120 * prepended to the buffer two. Buffer two is the sent up while
2121 * buffer one is returned to the hardware to be reused.
2122 * 3032 receives all of it's data and headers in one buffer for a
2123 * simpler process. 3032 also supports checksum verification as
2124 * can be seen in ql_process_macip_rx_intr().
2125 */
2126 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2127 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2128 {
2129 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2130 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2131 struct sk_buff *skb;
2132 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2133
2134 /*
2135 * Get the inbound address list (small buffer).
2136 */
2137 ql_get_sbuf(qdev);
2138
2139 if (qdev->device_id == QL3022_DEVICE_ID)
2140 lrg_buf_cb1 = ql_get_lbuf(qdev);
2141
2142 /* start of second buffer */
2143 lrg_buf_cb2 = ql_get_lbuf(qdev);
2144 skb = lrg_buf_cb2->skb;
2145
2146 qdev->ndev->stats.rx_packets++;
2147 qdev->ndev->stats.rx_bytes += length;
2148
2149 skb_put(skb, length);
2150 pci_unmap_single(qdev->pdev,
2151 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2152 pci_unmap_len(lrg_buf_cb2, maplen),
2153 PCI_DMA_FROMDEVICE);
2154 prefetch(skb->data);
2155 skb->ip_summed = CHECKSUM_NONE;
2156 skb->protocol = eth_type_trans(skb, qdev->ndev);
2157
2158 netif_receive_skb(skb);
2159 qdev->ndev->last_rx = jiffies;
2160 lrg_buf_cb2->skb = NULL;
2161
2162 if (qdev->device_id == QL3022_DEVICE_ID)
2163 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2164 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2165 }
2166
2167 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2168 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2169 {
2170 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2171 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2172 struct sk_buff *skb1 = NULL, *skb2;
2173 struct net_device *ndev = qdev->ndev;
2174 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2175 u16 size = 0;
2176
2177 /*
2178 * Get the inbound address list (small buffer).
2179 */
2180
2181 ql_get_sbuf(qdev);
2182
2183 if (qdev->device_id == QL3022_DEVICE_ID) {
2184 /* start of first buffer on 3022 */
2185 lrg_buf_cb1 = ql_get_lbuf(qdev);
2186 skb1 = lrg_buf_cb1->skb;
2187 size = ETH_HLEN;
2188 if (*((u16 *) skb1->data) != 0xFFFF)
2189 size += VLAN_ETH_HLEN - ETH_HLEN;
2190 }
2191
2192 /* start of second buffer */
2193 lrg_buf_cb2 = ql_get_lbuf(qdev);
2194 skb2 = lrg_buf_cb2->skb;
2195
2196 skb_put(skb2, length); /* Just the second buffer length here. */
2197 pci_unmap_single(qdev->pdev,
2198 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2199 pci_unmap_len(lrg_buf_cb2, maplen),
2200 PCI_DMA_FROMDEVICE);
2201 prefetch(skb2->data);
2202
2203 skb2->ip_summed = CHECKSUM_NONE;
2204 if (qdev->device_id == QL3022_DEVICE_ID) {
2205 /*
2206 * Copy the ethhdr from first buffer to second. This
2207 * is necessary for 3022 IP completions.
2208 */
2209 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2210 skb_push(skb2, size), size);
2211 } else {
2212 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2213 if (checksum &
2214 (IB_IP_IOCB_RSP_3032_ICE |
2215 IB_IP_IOCB_RSP_3032_CE)) {
2216 printk(KERN_ERR
2217 "%s: Bad checksum for this %s packet, checksum = %x.\n",
2218 __func__,
2219 ((checksum &
2220 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2221 "UDP"),checksum);
2222 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2223 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2224 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2225 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2226 }
2227 }
2228 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2229
2230 netif_receive_skb(skb2);
2231 ndev->stats.rx_packets++;
2232 ndev->stats.rx_bytes += length;
2233 ndev->last_rx = jiffies;
2234 lrg_buf_cb2->skb = NULL;
2235
2236 if (qdev->device_id == QL3022_DEVICE_ID)
2237 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2238 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2239 }
2240
2241 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2242 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2243 {
2244 struct net_rsp_iocb *net_rsp;
2245 struct net_device *ndev = qdev->ndev;
2246 int work_done = 0;
2247
2248 /* While there are entries in the completion queue. */
2249 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2250 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2251
2252 net_rsp = qdev->rsp_current;
2253 rmb();
2254 /*
2255 * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2256 * inbound completion is for a VLAN.
2257 */
2258 if (qdev->device_id == QL3032_DEVICE_ID)
2259 net_rsp->opcode &= 0x7f;
2260 switch (net_rsp->opcode) {
2261
2262 case OPCODE_OB_MAC_IOCB_FN0:
2263 case OPCODE_OB_MAC_IOCB_FN2:
2264 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2265 net_rsp);
2266 (*tx_cleaned)++;
2267 break;
2268
2269 case OPCODE_IB_MAC_IOCB:
2270 case OPCODE_IB_3032_MAC_IOCB:
2271 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2272 net_rsp);
2273 (*rx_cleaned)++;
2274 break;
2275
2276 case OPCODE_IB_IP_IOCB:
2277 case OPCODE_IB_3032_IP_IOCB:
2278 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2279 net_rsp);
2280 (*rx_cleaned)++;
2281 break;
2282 default:
2283 {
2284 u32 *tmp = (u32 *) net_rsp;
2285 printk(KERN_ERR PFX
2286 "%s: Hit default case, not "
2287 "handled!\n"
2288 " dropping the packet, opcode = "
2289 "%x.\n",
2290 ndev->name, net_rsp->opcode);
2291 printk(KERN_ERR PFX
2292 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2293 (unsigned long int)tmp[0],
2294 (unsigned long int)tmp[1],
2295 (unsigned long int)tmp[2],
2296 (unsigned long int)tmp[3]);
2297 }
2298 }
2299
2300 qdev->rsp_consumer_index++;
2301
2302 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2303 qdev->rsp_consumer_index = 0;
2304 qdev->rsp_current = qdev->rsp_q_virt_addr;
2305 } else {
2306 qdev->rsp_current++;
2307 }
2308
2309 work_done = *tx_cleaned + *rx_cleaned;
2310 }
2311
2312 return work_done;
2313 }
2314
2315 static int ql_poll(struct napi_struct *napi, int budget)
2316 {
2317 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2318 struct net_device *ndev = qdev->ndev;
2319 int rx_cleaned = 0, tx_cleaned = 0;
2320 unsigned long hw_flags;
2321 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2322
2323 if (!netif_carrier_ok(ndev))
2324 goto quit_polling;
2325
2326 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2327
2328 if (tx_cleaned + rx_cleaned != budget ||
2329 !netif_running(ndev)) {
2330 quit_polling:
2331 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2332 __netif_rx_complete(ndev, napi);
2333 ql_update_small_bufq_prod_index(qdev);
2334 ql_update_lrg_bufq_prod_index(qdev);
2335 writel(qdev->rsp_consumer_index,
2336 &port_regs->CommonRegs.rspQConsumerIndex);
2337 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2338
2339 ql_enable_interrupts(qdev);
2340 }
2341 return tx_cleaned + rx_cleaned;
2342 }
2343
2344 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2345 {
2346
2347 struct net_device *ndev = dev_id;
2348 struct ql3_adapter *qdev = netdev_priv(ndev);
2349 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2350 u32 value;
2351 int handled = 1;
2352 u32 var;
2353
2354 port_regs = qdev->mem_map_registers;
2355
2356 value =
2357 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2358
2359 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2360 spin_lock(&qdev->adapter_lock);
2361 netif_stop_queue(qdev->ndev);
2362 netif_carrier_off(qdev->ndev);
2363 ql_disable_interrupts(qdev);
2364 qdev->port_link_state = LS_DOWN;
2365 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2366
2367 if (value & ISP_CONTROL_FE) {
2368 /*
2369 * Chip Fatal Error.
2370 */
2371 var =
2372 ql_read_page0_reg_l(qdev,
2373 &port_regs->PortFatalErrStatus);
2374 printk(KERN_WARNING PFX
2375 "%s: Resetting chip. PortFatalErrStatus "
2376 "register = 0x%x\n", ndev->name, var);
2377 set_bit(QL_RESET_START,&qdev->flags) ;
2378 } else {
2379 /*
2380 * Soft Reset Requested.
2381 */
2382 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2383 printk(KERN_ERR PFX
2384 "%s: Another function issued a reset to the "
2385 "chip. ISR value = %x.\n", ndev->name, value);
2386 }
2387 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2388 spin_unlock(&qdev->adapter_lock);
2389 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2390 ql_disable_interrupts(qdev);
2391 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2392 __netif_rx_schedule(ndev, &qdev->napi);
2393 }
2394 } else {
2395 return IRQ_NONE;
2396 }
2397
2398 return IRQ_RETVAL(handled);
2399 }
2400
2401 /*
2402 * Get the total number of segments needed for the
2403 * given number of fragments. This is necessary because
2404 * outbound address lists (OAL) will be used when more than
2405 * two frags are given. Each address list has 5 addr/len
2406 * pairs. The 5th pair in each AOL is used to point to
2407 * the next AOL if more frags are coming.
2408 * That is why the frags:segment count ratio is not linear.
2409 */
2410 static int ql_get_seg_count(struct ql3_adapter *qdev,
2411 unsigned short frags)
2412 {
2413 if (qdev->device_id == QL3022_DEVICE_ID)
2414 return 1;
2415
2416 switch(frags) {
2417 case 0: return 1; /* just the skb->data seg */
2418 case 1: return 2; /* skb->data + 1 frag */
2419 case 2: return 3; /* skb->data + 2 frags */
2420 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2421 case 4: return 6;
2422 case 5: return 7;
2423 case 6: return 8;
2424 case 7: return 10;
2425 case 8: return 11;
2426 case 9: return 12;
2427 case 10: return 13;
2428 case 11: return 15;
2429 case 12: return 16;
2430 case 13: return 17;
2431 case 14: return 18;
2432 case 15: return 20;
2433 case 16: return 21;
2434 case 17: return 22;
2435 case 18: return 23;
2436 }
2437 return -1;
2438 }
2439
2440 static void ql_hw_csum_setup(const struct sk_buff *skb,
2441 struct ob_mac_iocb_req *mac_iocb_ptr)
2442 {
2443 const struct iphdr *ip = ip_hdr(skb);
2444
2445 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2446 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2447
2448 if (ip->protocol == IPPROTO_TCP) {
2449 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2450 OB_3032MAC_IOCB_REQ_IC;
2451 } else {
2452 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2453 OB_3032MAC_IOCB_REQ_IC;
2454 }
2455
2456 }
2457
2458 /*
2459 * Map the buffers for this transmit. This will return
2460 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2461 */
2462 static int ql_send_map(struct ql3_adapter *qdev,
2463 struct ob_mac_iocb_req *mac_iocb_ptr,
2464 struct ql_tx_buf_cb *tx_cb,
2465 struct sk_buff *skb)
2466 {
2467 struct oal *oal;
2468 struct oal_entry *oal_entry;
2469 int len = skb_headlen(skb);
2470 dma_addr_t map;
2471 int err;
2472 int completed_segs, i;
2473 int seg_cnt, seg = 0;
2474 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2475
2476 seg_cnt = tx_cb->seg_count;
2477 /*
2478 * Map the skb buffer first.
2479 */
2480 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2481
2482 err = pci_dma_mapping_error(map);
2483 if(err) {
2484 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2485 qdev->ndev->name, err);
2486
2487 return NETDEV_TX_BUSY;
2488 }
2489
2490 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2491 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2492 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2493 oal_entry->len = cpu_to_le32(len);
2494 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2495 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2496 seg++;
2497
2498 if (seg_cnt == 1) {
2499 /* Terminate the last segment. */
2500 oal_entry->len =
2501 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2502 } else {
2503 oal = tx_cb->oal;
2504 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2505 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2506 oal_entry++;
2507 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2508 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2509 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2510 (seg == 17 && seg_cnt > 18)) {
2511 /* Continuation entry points to outbound address list. */
2512 map = pci_map_single(qdev->pdev, oal,
2513 sizeof(struct oal),
2514 PCI_DMA_TODEVICE);
2515
2516 err = pci_dma_mapping_error(map);
2517 if(err) {
2518
2519 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2520 qdev->ndev->name, err);
2521 goto map_error;
2522 }
2523
2524 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2525 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2526 oal_entry->len =
2527 cpu_to_le32(sizeof(struct oal) |
2528 OAL_CONT_ENTRY);
2529 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2530 map);
2531 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2532 sizeof(struct oal));
2533 oal_entry = (struct oal_entry *)oal;
2534 oal++;
2535 seg++;
2536 }
2537
2538 map =
2539 pci_map_page(qdev->pdev, frag->page,
2540 frag->page_offset, frag->size,
2541 PCI_DMA_TODEVICE);
2542
2543 err = pci_dma_mapping_error(map);
2544 if(err) {
2545 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2546 qdev->ndev->name, err);
2547 goto map_error;
2548 }
2549
2550 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2551 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2552 oal_entry->len = cpu_to_le32(frag->size);
2553 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2554 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2555 frag->size);
2556 }
2557 /* Terminate the last segment. */
2558 oal_entry->len =
2559 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2560 }
2561
2562 return NETDEV_TX_OK;
2563
2564 map_error:
2565 /* A PCI mapping failed and now we will need to back out
2566 * We need to traverse through the oal's and associated pages which
2567 * have been mapped and now we must unmap them to clean up properly
2568 */
2569
2570 seg = 1;
2571 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2572 oal = tx_cb->oal;
2573 for (i=0; i<completed_segs; i++,seg++) {
2574 oal_entry++;
2575
2576 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2577 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2578 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2579 (seg == 17 && seg_cnt > 18)) {
2580 pci_unmap_single(qdev->pdev,
2581 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2582 pci_unmap_len(&tx_cb->map[seg], maplen),
2583 PCI_DMA_TODEVICE);
2584 oal++;
2585 seg++;
2586 }
2587
2588 pci_unmap_page(qdev->pdev,
2589 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2590 pci_unmap_len(&tx_cb->map[seg], maplen),
2591 PCI_DMA_TODEVICE);
2592 }
2593
2594 pci_unmap_single(qdev->pdev,
2595 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2596 pci_unmap_addr(&tx_cb->map[0], maplen),
2597 PCI_DMA_TODEVICE);
2598
2599 return NETDEV_TX_BUSY;
2600
2601 }
2602
2603 /*
2604 * The difference between 3022 and 3032 sends:
2605 * 3022 only supports a simple single segment transmission.
2606 * 3032 supports checksumming and scatter/gather lists (fragments).
2607 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2608 * in the IOCB plus a chain of outbound address lists (OAL) that
2609 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2610 * will used to point to an OAL when more ALP entries are required.
2611 * The IOCB is always the top of the chain followed by one or more
2612 * OALs (when necessary).
2613 */
2614 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2615 {
2616 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2617 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2618 struct ql_tx_buf_cb *tx_cb;
2619 u32 tot_len = skb->len;
2620 struct ob_mac_iocb_req *mac_iocb_ptr;
2621
2622 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2623 return NETDEV_TX_BUSY;
2624 }
2625
2626 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2627 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2628 (skb_shinfo(skb)->nr_frags))) == -1) {
2629 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2630 return NETDEV_TX_OK;
2631 }
2632
2633 mac_iocb_ptr = tx_cb->queue_entry;
2634 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2635 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2636 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2637 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2638 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2639 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2640 tx_cb->skb = skb;
2641 if (qdev->device_id == QL3032_DEVICE_ID &&
2642 skb->ip_summed == CHECKSUM_PARTIAL)
2643 ql_hw_csum_setup(skb, mac_iocb_ptr);
2644
2645 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2646 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2647 return NETDEV_TX_BUSY;
2648 }
2649
2650 wmb();
2651 qdev->req_producer_index++;
2652 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2653 qdev->req_producer_index = 0;
2654 wmb();
2655 ql_write_common_reg_l(qdev,
2656 &port_regs->CommonRegs.reqQProducerIndex,
2657 qdev->req_producer_index);
2658
2659 ndev->trans_start = jiffies;
2660 if (netif_msg_tx_queued(qdev))
2661 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2662 ndev->name, qdev->req_producer_index, skb->len);
2663
2664 atomic_dec(&qdev->tx_count);
2665 return NETDEV_TX_OK;
2666 }
2667
2668 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2669 {
2670 qdev->req_q_size =
2671 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2672
2673 qdev->req_q_virt_addr =
2674 pci_alloc_consistent(qdev->pdev,
2675 (size_t) qdev->req_q_size,
2676 &qdev->req_q_phy_addr);
2677
2678 if ((qdev->req_q_virt_addr == NULL) ||
2679 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2680 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2681 qdev->ndev->name);
2682 return -ENOMEM;
2683 }
2684
2685 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2686
2687 qdev->rsp_q_virt_addr =
2688 pci_alloc_consistent(qdev->pdev,
2689 (size_t) qdev->rsp_q_size,
2690 &qdev->rsp_q_phy_addr);
2691
2692 if ((qdev->rsp_q_virt_addr == NULL) ||
2693 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2694 printk(KERN_ERR PFX
2695 "%s: rspQ allocation failed\n",
2696 qdev->ndev->name);
2697 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2698 qdev->req_q_virt_addr,
2699 qdev->req_q_phy_addr);
2700 return -ENOMEM;
2701 }
2702
2703 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2704
2705 return 0;
2706 }
2707
2708 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2709 {
2710 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2711 printk(KERN_INFO PFX
2712 "%s: Already done.\n", qdev->ndev->name);
2713 return;
2714 }
2715
2716 pci_free_consistent(qdev->pdev,
2717 qdev->req_q_size,
2718 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2719
2720 qdev->req_q_virt_addr = NULL;
2721
2722 pci_free_consistent(qdev->pdev,
2723 qdev->rsp_q_size,
2724 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2725
2726 qdev->rsp_q_virt_addr = NULL;
2727
2728 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2729 }
2730
2731 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2732 {
2733 /* Create Large Buffer Queue */
2734 qdev->lrg_buf_q_size =
2735 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2736 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2737 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2738 else
2739 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2740
2741 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2742 if (qdev->lrg_buf == NULL) {
2743 printk(KERN_ERR PFX
2744 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2745 return -ENOMEM;
2746 }
2747
2748 qdev->lrg_buf_q_alloc_virt_addr =
2749 pci_alloc_consistent(qdev->pdev,
2750 qdev->lrg_buf_q_alloc_size,
2751 &qdev->lrg_buf_q_alloc_phy_addr);
2752
2753 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2754 printk(KERN_ERR PFX
2755 "%s: lBufQ failed\n", qdev->ndev->name);
2756 return -ENOMEM;
2757 }
2758 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2759 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2760
2761 /* Create Small Buffer Queue */
2762 qdev->small_buf_q_size =
2763 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2764 if (qdev->small_buf_q_size < PAGE_SIZE)
2765 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2766 else
2767 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2768
2769 qdev->small_buf_q_alloc_virt_addr =
2770 pci_alloc_consistent(qdev->pdev,
2771 qdev->small_buf_q_alloc_size,
2772 &qdev->small_buf_q_alloc_phy_addr);
2773
2774 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2775 printk(KERN_ERR PFX
2776 "%s: Small Buffer Queue allocation failed.\n",
2777 qdev->ndev->name);
2778 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2779 qdev->lrg_buf_q_alloc_virt_addr,
2780 qdev->lrg_buf_q_alloc_phy_addr);
2781 return -ENOMEM;
2782 }
2783
2784 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2785 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2786 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2787 return 0;
2788 }
2789
2790 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2791 {
2792 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2793 printk(KERN_INFO PFX
2794 "%s: Already done.\n", qdev->ndev->name);
2795 return;
2796 }
2797 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2798 pci_free_consistent(qdev->pdev,
2799 qdev->lrg_buf_q_alloc_size,
2800 qdev->lrg_buf_q_alloc_virt_addr,
2801 qdev->lrg_buf_q_alloc_phy_addr);
2802
2803 qdev->lrg_buf_q_virt_addr = NULL;
2804
2805 pci_free_consistent(qdev->pdev,
2806 qdev->small_buf_q_alloc_size,
2807 qdev->small_buf_q_alloc_virt_addr,
2808 qdev->small_buf_q_alloc_phy_addr);
2809
2810 qdev->small_buf_q_virt_addr = NULL;
2811
2812 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2813 }
2814
2815 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2816 {
2817 int i;
2818 struct bufq_addr_element *small_buf_q_entry;
2819
2820 /* Currently we allocate on one of memory and use it for smallbuffers */
2821 qdev->small_buf_total_size =
2822 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2823 QL_SMALL_BUFFER_SIZE);
2824
2825 qdev->small_buf_virt_addr =
2826 pci_alloc_consistent(qdev->pdev,
2827 qdev->small_buf_total_size,
2828 &qdev->small_buf_phy_addr);
2829
2830 if (qdev->small_buf_virt_addr == NULL) {
2831 printk(KERN_ERR PFX
2832 "%s: Failed to get small buffer memory.\n",
2833 qdev->ndev->name);
2834 return -ENOMEM;
2835 }
2836
2837 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2838 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2839
2840 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2841
2842 /* Initialize the small buffer queue. */
2843 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2844 small_buf_q_entry->addr_high =
2845 cpu_to_le32(qdev->small_buf_phy_addr_high);
2846 small_buf_q_entry->addr_low =
2847 cpu_to_le32(qdev->small_buf_phy_addr_low +
2848 (i * QL_SMALL_BUFFER_SIZE));
2849 small_buf_q_entry++;
2850 }
2851 qdev->small_buf_index = 0;
2852 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2853 return 0;
2854 }
2855
2856 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2857 {
2858 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2859 printk(KERN_INFO PFX
2860 "%s: Already done.\n", qdev->ndev->name);
2861 return;
2862 }
2863 if (qdev->small_buf_virt_addr != NULL) {
2864 pci_free_consistent(qdev->pdev,
2865 qdev->small_buf_total_size,
2866 qdev->small_buf_virt_addr,
2867 qdev->small_buf_phy_addr);
2868
2869 qdev->small_buf_virt_addr = NULL;
2870 }
2871 }
2872
2873 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2874 {
2875 int i = 0;
2876 struct ql_rcv_buf_cb *lrg_buf_cb;
2877
2878 for (i = 0; i < qdev->num_large_buffers; i++) {
2879 lrg_buf_cb = &qdev->lrg_buf[i];
2880 if (lrg_buf_cb->skb) {
2881 dev_kfree_skb(lrg_buf_cb->skb);
2882 pci_unmap_single(qdev->pdev,
2883 pci_unmap_addr(lrg_buf_cb, mapaddr),
2884 pci_unmap_len(lrg_buf_cb, maplen),
2885 PCI_DMA_FROMDEVICE);
2886 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2887 } else {
2888 break;
2889 }
2890 }
2891 }
2892
2893 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2894 {
2895 int i;
2896 struct ql_rcv_buf_cb *lrg_buf_cb;
2897 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2898
2899 for (i = 0; i < qdev->num_large_buffers; i++) {
2900 lrg_buf_cb = &qdev->lrg_buf[i];
2901 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2902 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2903 buf_addr_ele++;
2904 }
2905 qdev->lrg_buf_index = 0;
2906 qdev->lrg_buf_skb_check = 0;
2907 }
2908
2909 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2910 {
2911 int i;
2912 struct ql_rcv_buf_cb *lrg_buf_cb;
2913 struct sk_buff *skb;
2914 dma_addr_t map;
2915 int err;
2916
2917 for (i = 0; i < qdev->num_large_buffers; i++) {
2918 skb = netdev_alloc_skb(qdev->ndev,
2919 qdev->lrg_buffer_len);
2920 if (unlikely(!skb)) {
2921 /* Better luck next round */
2922 printk(KERN_ERR PFX
2923 "%s: large buff alloc failed, "
2924 "for %d bytes at index %d.\n",
2925 qdev->ndev->name,
2926 qdev->lrg_buffer_len * 2, i);
2927 ql_free_large_buffers(qdev);
2928 return -ENOMEM;
2929 } else {
2930
2931 lrg_buf_cb = &qdev->lrg_buf[i];
2932 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2933 lrg_buf_cb->index = i;
2934 lrg_buf_cb->skb = skb;
2935 /*
2936 * We save some space to copy the ethhdr from first
2937 * buffer
2938 */
2939 skb_reserve(skb, QL_HEADER_SPACE);
2940 map = pci_map_single(qdev->pdev,
2941 skb->data,
2942 qdev->lrg_buffer_len -
2943 QL_HEADER_SPACE,
2944 PCI_DMA_FROMDEVICE);
2945
2946 err = pci_dma_mapping_error(map);
2947 if(err) {
2948 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2949 qdev->ndev->name, err);
2950 ql_free_large_buffers(qdev);
2951 return -ENOMEM;
2952 }
2953
2954 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2955 pci_unmap_len_set(lrg_buf_cb, maplen,
2956 qdev->lrg_buffer_len -
2957 QL_HEADER_SPACE);
2958 lrg_buf_cb->buf_phy_addr_low =
2959 cpu_to_le32(LS_64BITS(map));
2960 lrg_buf_cb->buf_phy_addr_high =
2961 cpu_to_le32(MS_64BITS(map));
2962 }
2963 }
2964 return 0;
2965 }
2966
2967 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2968 {
2969 struct ql_tx_buf_cb *tx_cb;
2970 int i;
2971
2972 tx_cb = &qdev->tx_buf[0];
2973 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2974 if (tx_cb->oal) {
2975 kfree(tx_cb->oal);
2976 tx_cb->oal = NULL;
2977 }
2978 tx_cb++;
2979 }
2980 }
2981
2982 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2983 {
2984 struct ql_tx_buf_cb *tx_cb;
2985 int i;
2986 struct ob_mac_iocb_req *req_q_curr =
2987 qdev->req_q_virt_addr;
2988
2989 /* Create free list of transmit buffers */
2990 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2991
2992 tx_cb = &qdev->tx_buf[i];
2993 tx_cb->skb = NULL;
2994 tx_cb->queue_entry = req_q_curr;
2995 req_q_curr++;
2996 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2997 if (tx_cb->oal == NULL)
2998 return -1;
2999 }
3000 return 0;
3001 }
3002
3003 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
3004 {
3005 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
3006 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
3007 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
3008 }
3009 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
3010 /*
3011 * Bigger buffers, so less of them.
3012 */
3013 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
3014 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
3015 } else {
3016 printk(KERN_ERR PFX
3017 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
3018 qdev->ndev->name);
3019 return -ENOMEM;
3020 }
3021 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
3022 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
3023 qdev->max_frame_size =
3024 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
3025
3026 /*
3027 * First allocate a page of shared memory and use it for shadow
3028 * locations of Network Request Queue Consumer Address Register and
3029 * Network Completion Queue Producer Index Register
3030 */
3031 qdev->shadow_reg_virt_addr =
3032 pci_alloc_consistent(qdev->pdev,
3033 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3034
3035 if (qdev->shadow_reg_virt_addr != NULL) {
3036 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3037 qdev->req_consumer_index_phy_addr_high =
3038 MS_64BITS(qdev->shadow_reg_phy_addr);
3039 qdev->req_consumer_index_phy_addr_low =
3040 LS_64BITS(qdev->shadow_reg_phy_addr);
3041
3042 qdev->prsp_producer_index =
3043 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3044 qdev->rsp_producer_index_phy_addr_high =
3045 qdev->req_consumer_index_phy_addr_high;
3046 qdev->rsp_producer_index_phy_addr_low =
3047 qdev->req_consumer_index_phy_addr_low + 8;
3048 } else {
3049 printk(KERN_ERR PFX
3050 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3051 return -ENOMEM;
3052 }
3053
3054 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3055 printk(KERN_ERR PFX
3056 "%s: ql_alloc_net_req_rsp_queues failed.\n",
3057 qdev->ndev->name);
3058 goto err_req_rsp;
3059 }
3060
3061 if (ql_alloc_buffer_queues(qdev) != 0) {
3062 printk(KERN_ERR PFX
3063 "%s: ql_alloc_buffer_queues failed.\n",
3064 qdev->ndev->name);
3065 goto err_buffer_queues;
3066 }
3067
3068 if (ql_alloc_small_buffers(qdev) != 0) {
3069 printk(KERN_ERR PFX
3070 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3071 goto err_small_buffers;
3072 }
3073
3074 if (ql_alloc_large_buffers(qdev) != 0) {
3075 printk(KERN_ERR PFX
3076 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3077 goto err_small_buffers;
3078 }
3079
3080 /* Initialize the large buffer queue. */
3081 ql_init_large_buffers(qdev);
3082 if (ql_create_send_free_list(qdev))
3083 goto err_free_list;
3084
3085 qdev->rsp_current = qdev->rsp_q_virt_addr;
3086
3087 return 0;
3088 err_free_list:
3089 ql_free_send_free_list(qdev);
3090 err_small_buffers:
3091 ql_free_buffer_queues(qdev);
3092 err_buffer_queues:
3093 ql_free_net_req_rsp_queues(qdev);
3094 err_req_rsp:
3095 pci_free_consistent(qdev->pdev,
3096 PAGE_SIZE,
3097 qdev->shadow_reg_virt_addr,
3098 qdev->shadow_reg_phy_addr);
3099
3100 return -ENOMEM;
3101 }
3102
3103 static void ql_free_mem_resources(struct ql3_adapter *qdev)
3104 {
3105 ql_free_send_free_list(qdev);
3106 ql_free_large_buffers(qdev);
3107 ql_free_small_buffers(qdev);
3108 ql_free_buffer_queues(qdev);
3109 ql_free_net_req_rsp_queues(qdev);
3110 if (qdev->shadow_reg_virt_addr != NULL) {
3111 pci_free_consistent(qdev->pdev,
3112 PAGE_SIZE,
3113 qdev->shadow_reg_virt_addr,
3114 qdev->shadow_reg_phy_addr);
3115 qdev->shadow_reg_virt_addr = NULL;
3116 }
3117 }
3118
3119 static int ql_init_misc_registers(struct ql3_adapter *qdev)
3120 {
3121 struct ql3xxx_local_ram_registers __iomem *local_ram =
3122 (void __iomem *)qdev->mem_map_registers;
3123
3124 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3125 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3126 2) << 4))
3127 return -1;
3128
3129 ql_write_page2_reg(qdev,
3130 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3131
3132 ql_write_page2_reg(qdev,
3133 &local_ram->maxBufletCount,
3134 qdev->nvram_data.bufletCount);
3135
3136 ql_write_page2_reg(qdev,
3137 &local_ram->freeBufletThresholdLow,
3138 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3139 (qdev->nvram_data.tcpWindowThreshold0));
3140
3141 ql_write_page2_reg(qdev,
3142 &local_ram->freeBufletThresholdHigh,
3143 qdev->nvram_data.tcpWindowThreshold50);
3144
3145 ql_write_page2_reg(qdev,
3146 &local_ram->ipHashTableBase,
3147 (qdev->nvram_data.ipHashTableBaseHi << 16) |
3148 qdev->nvram_data.ipHashTableBaseLo);
3149 ql_write_page2_reg(qdev,
3150 &local_ram->ipHashTableCount,
3151 qdev->nvram_data.ipHashTableSize);
3152 ql_write_page2_reg(qdev,
3153 &local_ram->tcpHashTableBase,
3154 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3155 qdev->nvram_data.tcpHashTableBaseLo);
3156 ql_write_page2_reg(qdev,
3157 &local_ram->tcpHashTableCount,
3158 qdev->nvram_data.tcpHashTableSize);
3159 ql_write_page2_reg(qdev,
3160 &local_ram->ncbBase,
3161 (qdev->nvram_data.ncbTableBaseHi << 16) |
3162 qdev->nvram_data.ncbTableBaseLo);
3163 ql_write_page2_reg(qdev,
3164 &local_ram->maxNcbCount,
3165 qdev->nvram_data.ncbTableSize);
3166 ql_write_page2_reg(qdev,
3167 &local_ram->drbBase,
3168 (qdev->nvram_data.drbTableBaseHi << 16) |
3169 qdev->nvram_data.drbTableBaseLo);
3170 ql_write_page2_reg(qdev,
3171 &local_ram->maxDrbCount,
3172 qdev->nvram_data.drbTableSize);
3173 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3174 return 0;
3175 }
3176
3177 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3178 {
3179 u32 value;
3180 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3181 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3182 (void __iomem *)port_regs;
3183 u32 delay = 10;
3184 int status = 0;
3185
3186 if(ql_mii_setup(qdev))
3187 return -1;
3188
3189 /* Bring out PHY out of reset */
3190 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3191 (ISP_SERIAL_PORT_IF_WE |
3192 (ISP_SERIAL_PORT_IF_WE << 16)));
3193
3194 qdev->port_link_state = LS_DOWN;
3195 netif_carrier_off(qdev->ndev);
3196
3197 /* V2 chip fix for ARS-39168. */
3198 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3199 (ISP_SERIAL_PORT_IF_SDE |
3200 (ISP_SERIAL_PORT_IF_SDE << 16)));
3201
3202 /* Request Queue Registers */
3203 *((u32 *) (qdev->preq_consumer_index)) = 0;
3204 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3205 qdev->req_producer_index = 0;
3206
3207 ql_write_page1_reg(qdev,
3208 &hmem_regs->reqConsumerIndexAddrHigh,
3209 qdev->req_consumer_index_phy_addr_high);
3210 ql_write_page1_reg(qdev,
3211 &hmem_regs->reqConsumerIndexAddrLow,
3212 qdev->req_consumer_index_phy_addr_low);
3213
3214 ql_write_page1_reg(qdev,
3215 &hmem_regs->reqBaseAddrHigh,
3216 MS_64BITS(qdev->req_q_phy_addr));
3217 ql_write_page1_reg(qdev,
3218 &hmem_regs->reqBaseAddrLow,
3219 LS_64BITS(qdev->req_q_phy_addr));
3220 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3221
3222 /* Response Queue Registers */
3223 *((u16 *) (qdev->prsp_producer_index)) = 0;
3224 qdev->rsp_consumer_index = 0;
3225 qdev->rsp_current = qdev->rsp_q_virt_addr;
3226
3227 ql_write_page1_reg(qdev,
3228 &hmem_regs->rspProducerIndexAddrHigh,
3229 qdev->rsp_producer_index_phy_addr_high);
3230
3231 ql_write_page1_reg(qdev,
3232 &hmem_regs->rspProducerIndexAddrLow,
3233 qdev->rsp_producer_index_phy_addr_low);
3234
3235 ql_write_page1_reg(qdev,
3236 &hmem_regs->rspBaseAddrHigh,
3237 MS_64BITS(qdev->rsp_q_phy_addr));
3238
3239 ql_write_page1_reg(qdev,
3240 &hmem_regs->rspBaseAddrLow,
3241 LS_64BITS(qdev->rsp_q_phy_addr));
3242
3243 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3244
3245 /* Large Buffer Queue */
3246 ql_write_page1_reg(qdev,
3247 &hmem_regs->rxLargeQBaseAddrHigh,
3248 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3249
3250 ql_write_page1_reg(qdev,
3251 &hmem_regs->rxLargeQBaseAddrLow,
3252 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3253
3254 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3255
3256 ql_write_page1_reg(qdev,
3257 &hmem_regs->rxLargeBufferLength,
3258 qdev->lrg_buffer_len);
3259
3260 /* Small Buffer Queue */
3261 ql_write_page1_reg(qdev,
3262 &hmem_regs->rxSmallQBaseAddrHigh,
3263 MS_64BITS(qdev->small_buf_q_phy_addr));
3264
3265 ql_write_page1_reg(qdev,
3266 &hmem_regs->rxSmallQBaseAddrLow,
3267 LS_64BITS(qdev->small_buf_q_phy_addr));
3268
3269 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3270 ql_write_page1_reg(qdev,
3271 &hmem_regs->rxSmallBufferLength,
3272 QL_SMALL_BUFFER_SIZE);
3273
3274 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3275 qdev->small_buf_release_cnt = 8;
3276 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3277 qdev->lrg_buf_release_cnt = 8;
3278 qdev->lrg_buf_next_free =
3279 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3280 qdev->small_buf_index = 0;
3281 qdev->lrg_buf_index = 0;
3282 qdev->lrg_buf_free_count = 0;
3283 qdev->lrg_buf_free_head = NULL;
3284 qdev->lrg_buf_free_tail = NULL;
3285
3286 ql_write_common_reg(qdev,
3287 &port_regs->CommonRegs.
3288 rxSmallQProducerIndex,
3289 qdev->small_buf_q_producer_index);
3290 ql_write_common_reg(qdev,
3291 &port_regs->CommonRegs.
3292 rxLargeQProducerIndex,
3293 qdev->lrg_buf_q_producer_index);
3294
3295 /*
3296 * Find out if the chip has already been initialized. If it has, then
3297 * we skip some of the initialization.
3298 */
3299 clear_bit(QL_LINK_MASTER, &qdev->flags);
3300 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3301 if ((value & PORT_STATUS_IC) == 0) {
3302
3303 /* Chip has not been configured yet, so let it rip. */
3304 if(ql_init_misc_registers(qdev)) {
3305 status = -1;
3306 goto out;
3307 }
3308
3309 value = qdev->nvram_data.tcpMaxWindowSize;
3310 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3311
3312 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3313
3314 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3315 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3316 * 2) << 13)) {
3317 status = -1;
3318 goto out;
3319 }
3320 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3321 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3322 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3323 16) | (INTERNAL_CHIP_SD |
3324 INTERNAL_CHIP_WE)));
3325 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3326 }
3327
3328 if (qdev->mac_index)
3329 ql_write_page0_reg(qdev,
3330 &port_regs->mac1MaxFrameLengthReg,
3331 qdev->max_frame_size);
3332 else
3333 ql_write_page0_reg(qdev,
3334 &port_regs->mac0MaxFrameLengthReg,
3335 qdev->max_frame_size);
3336
3337 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3338 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3339 2) << 7)) {
3340 status = -1;
3341 goto out;
3342 }
3343
3344 PHY_Setup(qdev);
3345 ql_init_scan_mode(qdev);
3346 ql_get_phy_owner(qdev);
3347
3348 /* Load the MAC Configuration */
3349
3350 /* Program lower 32 bits of the MAC address */
3351 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3352 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3353 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3354 ((qdev->ndev->dev_addr[2] << 24)
3355 | (qdev->ndev->dev_addr[3] << 16)
3356 | (qdev->ndev->dev_addr[4] << 8)
3357 | qdev->ndev->dev_addr[5]));
3358
3359 /* Program top 16 bits of the MAC address */
3360 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3361 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3362 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3363 ((qdev->ndev->dev_addr[0] << 8)
3364 | qdev->ndev->dev_addr[1]));
3365
3366 /* Enable Primary MAC */
3367 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3368 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3369 MAC_ADDR_INDIRECT_PTR_REG_PE));
3370
3371 /* Clear Primary and Secondary IP addresses */
3372 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3373 ((IP_ADDR_INDEX_REG_MASK << 16) |
3374 (qdev->mac_index << 2)));
3375 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3376
3377 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3378 ((IP_ADDR_INDEX_REG_MASK << 16) |
3379 ((qdev->mac_index << 2) + 1)));
3380 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3381
3382 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3383
3384 /* Indicate Configuration Complete */
3385 ql_write_page0_reg(qdev,
3386 &port_regs->portControl,
3387 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3388
3389 do {
3390 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3391 if (value & PORT_STATUS_IC)
3392 break;
3393 msleep(500);
3394 } while (--delay);
3395
3396 if (delay == 0) {
3397 printk(KERN_ERR PFX
3398 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3399 status = -1;
3400 goto out;
3401 }
3402
3403 /* Enable Ethernet Function */
3404 if (qdev->device_id == QL3032_DEVICE_ID) {
3405 value =
3406 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3407 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3408 QL3032_PORT_CONTROL_ET);
3409 ql_write_page0_reg(qdev, &port_regs->functionControl,
3410 ((value << 16) | value));
3411 } else {
3412 value =
3413 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3414 PORT_CONTROL_HH);
3415 ql_write_page0_reg(qdev, &port_regs->portControl,
3416 ((value << 16) | value));
3417 }
3418
3419
3420 out:
3421 return status;
3422 }
3423
3424 /*
3425 * Caller holds hw_lock.
3426 */
3427 static int ql_adapter_reset(struct ql3_adapter *qdev)
3428 {
3429 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3430 int status = 0;
3431 u16 value;
3432 int max_wait_time;
3433
3434 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3435 clear_bit(QL_RESET_DONE, &qdev->flags);
3436
3437 /*
3438 * Issue soft reset to chip.
3439 */
3440 printk(KERN_DEBUG PFX
3441 "%s: Issue soft reset to chip.\n",
3442 qdev->ndev->name);
3443 ql_write_common_reg(qdev,
3444 &port_regs->CommonRegs.ispControlStatus,
3445 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3446
3447 /* Wait 3 seconds for reset to complete. */
3448 printk(KERN_DEBUG PFX
3449 "%s: Wait 10 milliseconds for reset to complete.\n",
3450 qdev->ndev->name);
3451
3452 /* Wait until the firmware tells us the Soft Reset is done */
3453 max_wait_time = 5;
3454 do {
3455 value =
3456 ql_read_common_reg(qdev,
3457 &port_regs->CommonRegs.ispControlStatus);
3458 if ((value & ISP_CONTROL_SR) == 0)
3459 break;
3460
3461 ssleep(1);
3462 } while ((--max_wait_time));
3463
3464 /*
3465 * Also, make sure that the Network Reset Interrupt bit has been
3466 * cleared after the soft reset has taken place.
3467 */
3468 value =
3469 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3470 if (value & ISP_CONTROL_RI) {
3471 printk(KERN_DEBUG PFX
3472 "ql_adapter_reset: clearing RI after reset.\n");
3473 ql_write_common_reg(qdev,
3474 &port_regs->CommonRegs.
3475 ispControlStatus,
3476 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3477 }
3478
3479 if (max_wait_time == 0) {
3480 /* Issue Force Soft Reset */
3481 ql_write_common_reg(qdev,
3482 &port_regs->CommonRegs.
3483 ispControlStatus,
3484 ((ISP_CONTROL_FSR << 16) |
3485 ISP_CONTROL_FSR));
3486 /*
3487 * Wait until the firmware tells us the Force Soft Reset is
3488 * done
3489 */
3490 max_wait_time = 5;
3491 do {
3492 value =
3493 ql_read_common_reg(qdev,
3494 &port_regs->CommonRegs.
3495 ispControlStatus);
3496 if ((value & ISP_CONTROL_FSR) == 0) {
3497 break;
3498 }
3499 ssleep(1);
3500 } while ((--max_wait_time));
3501 }
3502 if (max_wait_time == 0)
3503 status = 1;
3504
3505 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3506 set_bit(QL_RESET_DONE, &qdev->flags);
3507 return status;
3508 }
3509
3510 static void ql_set_mac_info(struct ql3_adapter *qdev)
3511 {
3512 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3513 u32 value, port_status;
3514 u8 func_number;
3515
3516 /* Get the function number */
3517 value =
3518 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3519 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3520 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3521 switch (value & ISP_CONTROL_FN_MASK) {
3522 case ISP_CONTROL_FN0_NET:
3523 qdev->mac_index = 0;
3524 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3525 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3526 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3527 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3528 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3529 if (port_status & PORT_STATUS_SM0)
3530 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3531 else
3532 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3533 break;
3534
3535 case ISP_CONTROL_FN1_NET:
3536 qdev->mac_index = 1;
3537 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3538 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3539 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3540 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3541 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3542 if (port_status & PORT_STATUS_SM1)
3543 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3544 else
3545 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3546 break;
3547
3548 case ISP_CONTROL_FN0_SCSI:
3549 case ISP_CONTROL_FN1_SCSI:
3550 default:
3551 printk(KERN_DEBUG PFX
3552 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3553 qdev->ndev->name,value);
3554 break;
3555 }
3556 qdev->numPorts = qdev->nvram_data.numPorts;
3557 }
3558
3559 static void ql_display_dev_info(struct net_device *ndev)
3560 {
3561 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3562 struct pci_dev *pdev = qdev->pdev;
3563 DECLARE_MAC_BUF(mac);
3564
3565 printk(KERN_INFO PFX
3566 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3567 DRV_NAME, qdev->index, qdev->chip_rev_id,
3568 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3569 qdev->pci_slot);
3570 printk(KERN_INFO PFX
3571 "%s Interface.\n",
3572 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3573
3574 /*
3575 * Print PCI bus width/type.
3576 */
3577 printk(KERN_INFO PFX
3578 "Bus interface is %s %s.\n",
3579 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3580 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3581
3582 printk(KERN_INFO PFX
3583 "mem IO base address adjusted = 0x%p\n",
3584 qdev->mem_map_registers);
3585 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3586
3587 if (netif_msg_probe(qdev))
3588 printk(KERN_INFO PFX
3589 "%s: MAC address %s\n",
3590 ndev->name, print_mac(mac, ndev->dev_addr));
3591 }
3592
3593 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3594 {
3595 struct net_device *ndev = qdev->ndev;
3596 int retval = 0;
3597
3598 netif_stop_queue(ndev);
3599 netif_carrier_off(ndev);
3600
3601 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3602 clear_bit(QL_LINK_MASTER,&qdev->flags);
3603
3604 ql_disable_interrupts(qdev);
3605
3606 free_irq(qdev->pdev->irq, ndev);
3607
3608 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3609 printk(KERN_INFO PFX
3610 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3611 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3612 pci_disable_msi(qdev->pdev);
3613 }
3614
3615 del_timer_sync(&qdev->adapter_timer);
3616
3617 napi_disable(&qdev->napi);
3618
3619 if (do_reset) {
3620 int soft_reset;
3621 unsigned long hw_flags;
3622
3623 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3624 if (ql_wait_for_drvr_lock(qdev)) {
3625 if ((soft_reset = ql_adapter_reset(qdev))) {
3626 printk(KERN_ERR PFX
3627 "%s: ql_adapter_reset(%d) FAILED!\n",
3628 ndev->name, qdev->index);
3629 }
3630 printk(KERN_ERR PFX
3631 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3632 } else {
3633 printk(KERN_ERR PFX
3634 "%s: Could not acquire driver lock to do "
3635 "reset!\n", ndev->name);
3636 retval = -1;
3637 }
3638 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3639 }
3640 ql_free_mem_resources(qdev);
3641 return retval;
3642 }
3643
3644 static int ql_adapter_up(struct ql3_adapter *qdev)
3645 {
3646 struct net_device *ndev = qdev->ndev;
3647 int err;
3648 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3649 unsigned long hw_flags;
3650
3651 if (ql_alloc_mem_resources(qdev)) {
3652 printk(KERN_ERR PFX
3653 "%s Unable to allocate buffers.\n", ndev->name);
3654 return -ENOMEM;
3655 }
3656
3657 if (qdev->msi) {
3658 if (pci_enable_msi(qdev->pdev)) {
3659 printk(KERN_ERR PFX
3660 "%s: User requested MSI, but MSI failed to "
3661 "initialize. Continuing without MSI.\n",
3662 qdev->ndev->name);
3663 qdev->msi = 0;
3664 } else {
3665 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3666 set_bit(QL_MSI_ENABLED,&qdev->flags);
3667 irq_flags &= ~IRQF_SHARED;
3668 }
3669 }
3670
3671 if ((err = request_irq(qdev->pdev->irq,
3672 ql3xxx_isr,
3673 irq_flags, ndev->name, ndev))) {
3674 printk(KERN_ERR PFX
3675 "%s: Failed to reserve interrupt %d already in use.\n",
3676 ndev->name, qdev->pdev->irq);
3677 goto err_irq;
3678 }
3679
3680 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3681
3682 if ((err = ql_wait_for_drvr_lock(qdev))) {
3683 if ((err = ql_adapter_initialize(qdev))) {
3684 printk(KERN_ERR PFX
3685 "%s: Unable to initialize adapter.\n",
3686 ndev->name);
3687 goto err_init;
3688 }
3689 printk(KERN_ERR PFX
3690 "%s: Releaseing driver lock.\n",ndev->name);
3691 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3692 } else {
3693 printk(KERN_ERR PFX
3694 "%s: Could not aquire driver lock.\n",
3695 ndev->name);
3696 goto err_lock;
3697 }
3698
3699 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3700
3701 set_bit(QL_ADAPTER_UP,&qdev->flags);
3702
3703 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3704
3705 napi_enable(&qdev->napi);
3706 ql_enable_interrupts(qdev);
3707 return 0;
3708
3709 err_init:
3710 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3711 err_lock:
3712 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3713 free_irq(qdev->pdev->irq, ndev);
3714 err_irq:
3715 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3716 printk(KERN_INFO PFX
3717 "%s: calling pci_disable_msi().\n",
3718 qdev->ndev->name);
3719 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3720 pci_disable_msi(qdev->pdev);
3721 }
3722 return err;
3723 }
3724
3725 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3726 {
3727 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3728 printk(KERN_ERR PFX
3729 "%s: Driver up/down cycle failed, "
3730 "closing device\n",qdev->ndev->name);
3731 dev_close(qdev->ndev);
3732 return -1;
3733 }
3734 return 0;
3735 }
3736
3737 static int ql3xxx_close(struct net_device *ndev)
3738 {
3739 struct ql3_adapter *qdev = netdev_priv(ndev);
3740
3741 /*
3742 * Wait for device to recover from a reset.
3743 * (Rarely happens, but possible.)
3744 */
3745 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3746 msleep(50);
3747
3748 ql_adapter_down(qdev,QL_DO_RESET);
3749 return 0;
3750 }
3751
3752 static int ql3xxx_open(struct net_device *ndev)
3753 {
3754 struct ql3_adapter *qdev = netdev_priv(ndev);
3755 return (ql_adapter_up(qdev));
3756 }
3757
3758 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3759 {
3760 /*
3761 * We are manually parsing the list in the net_device structure.
3762 */
3763 return;
3764 }
3765
3766 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3767 {
3768 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3769 struct ql3xxx_port_registers __iomem *port_regs =
3770 qdev->mem_map_registers;
3771 struct sockaddr *addr = p;
3772 unsigned long hw_flags;
3773
3774 if (netif_running(ndev))
3775 return -EBUSY;
3776
3777 if (!is_valid_ether_addr(addr->sa_data))
3778 return -EADDRNOTAVAIL;
3779
3780 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3781
3782 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3783 /* Program lower 32 bits of the MAC address */
3784 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3785 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3786 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3787 ((ndev->dev_addr[2] << 24) | (ndev->
3788 dev_addr[3] << 16) |
3789 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3790
3791 /* Program top 16 bits of the MAC address */
3792 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3793 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3794 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3795 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3796 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3797
3798 return 0;
3799 }
3800
3801 static void ql3xxx_tx_timeout(struct net_device *ndev)
3802 {
3803 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3804
3805 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3806 /*
3807 * Stop the queues, we've got a problem.
3808 */
3809 netif_stop_queue(ndev);
3810
3811 /*
3812 * Wake up the worker to process this event.
3813 */
3814 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3815 }
3816
3817 static void ql_reset_work(struct work_struct *work)
3818 {
3819 struct ql3_adapter *qdev =
3820 container_of(work, struct ql3_adapter, reset_work.work);
3821 struct net_device *ndev = qdev->ndev;
3822 u32 value;
3823 struct ql_tx_buf_cb *tx_cb;
3824 int max_wait_time, i;
3825 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3826 unsigned long hw_flags;
3827
3828 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3829 clear_bit(QL_LINK_MASTER,&qdev->flags);
3830
3831 /*
3832 * Loop through the active list and return the skb.
3833 */
3834 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3835 int j;
3836 tx_cb = &qdev->tx_buf[i];
3837 if (tx_cb->skb) {
3838 printk(KERN_DEBUG PFX
3839 "%s: Freeing lost SKB.\n",
3840 qdev->ndev->name);
3841 pci_unmap_single(qdev->pdev,
3842 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3843 pci_unmap_len(&tx_cb->map[0], maplen),
3844 PCI_DMA_TODEVICE);
3845 for(j=1;j<tx_cb->seg_count;j++) {
3846 pci_unmap_page(qdev->pdev,
3847 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3848 pci_unmap_len(&tx_cb->map[j],maplen),
3849 PCI_DMA_TODEVICE);
3850 }
3851 dev_kfree_skb(tx_cb->skb);
3852 tx_cb->skb = NULL;
3853 }
3854 }
3855
3856 printk(KERN_ERR PFX
3857 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3858 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3859 ql_write_common_reg(qdev,
3860 &port_regs->CommonRegs.
3861 ispControlStatus,
3862 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3863 /*
3864 * Wait the for Soft Reset to Complete.
3865 */
3866 max_wait_time = 10;
3867 do {
3868 value = ql_read_common_reg(qdev,
3869 &port_regs->CommonRegs.
3870
3871 ispControlStatus);
3872 if ((value & ISP_CONTROL_SR) == 0) {
3873 printk(KERN_DEBUG PFX
3874 "%s: reset completed.\n",
3875 qdev->ndev->name);
3876 break;
3877 }
3878
3879 if (value & ISP_CONTROL_RI) {
3880 printk(KERN_DEBUG PFX
3881 "%s: clearing NRI after reset.\n",
3882 qdev->ndev->name);
3883 ql_write_common_reg(qdev,
3884 &port_regs->
3885 CommonRegs.
3886 ispControlStatus,
3887 ((ISP_CONTROL_RI <<
3888 16) | ISP_CONTROL_RI));
3889 }
3890
3891 ssleep(1);
3892 } while (--max_wait_time);
3893 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3894
3895 if (value & ISP_CONTROL_SR) {
3896
3897 /*
3898 * Set the reset flags and clear the board again.
3899 * Nothing else to do...
3900 */
3901 printk(KERN_ERR PFX
3902 "%s: Timed out waiting for reset to "
3903 "complete.\n", ndev->name);
3904 printk(KERN_ERR PFX
3905 "%s: Do a reset.\n", ndev->name);
3906 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3907 clear_bit(QL_RESET_START,&qdev->flags);
3908 ql_cycle_adapter(qdev,QL_DO_RESET);
3909 return;
3910 }
3911
3912 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3913 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3914 clear_bit(QL_RESET_START,&qdev->flags);
3915 ql_cycle_adapter(qdev,QL_NO_RESET);
3916 }
3917 }
3918
3919 static void ql_tx_timeout_work(struct work_struct *work)
3920 {
3921 struct ql3_adapter *qdev =
3922 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3923
3924 ql_cycle_adapter(qdev, QL_DO_RESET);
3925 }
3926
3927 static void ql_get_board_info(struct ql3_adapter *qdev)
3928 {
3929 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3930 u32 value;
3931
3932 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3933
3934 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3935 if (value & PORT_STATUS_64)
3936 qdev->pci_width = 64;
3937 else
3938 qdev->pci_width = 32;
3939 if (value & PORT_STATUS_X)
3940 qdev->pci_x = 1;
3941 else
3942 qdev->pci_x = 0;
3943 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3944 }
3945
3946 static void ql3xxx_timer(unsigned long ptr)
3947 {
3948 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3949 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3950 }
3951
3952 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3953 const struct pci_device_id *pci_entry)
3954 {
3955 struct net_device *ndev = NULL;
3956 struct ql3_adapter *qdev = NULL;
3957 static int cards_found = 0;
3958 int pci_using_dac, err;
3959
3960 err = pci_enable_device(pdev);
3961 if (err) {
3962 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3963 pci_name(pdev));
3964 goto err_out;
3965 }
3966
3967 err = pci_request_regions(pdev, DRV_NAME);
3968 if (err) {
3969 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3970 pci_name(pdev));
3971 goto err_out_disable_pdev;
3972 }
3973
3974 pci_set_master(pdev);
3975
3976 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3977 pci_using_dac = 1;
3978 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3979 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3980 pci_using_dac = 0;
3981 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3982 }
3983
3984 if (err) {
3985 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3986 pci_name(pdev));
3987 goto err_out_free_regions;
3988 }
3989
3990 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3991 if (!ndev) {
3992 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3993 pci_name(pdev));
3994 err = -ENOMEM;
3995 goto err_out_free_regions;
3996 }
3997
3998 SET_NETDEV_DEV(ndev, &pdev->dev);
3999
4000 pci_set_drvdata(pdev, ndev);
4001
4002 qdev = netdev_priv(ndev);
4003 qdev->index = cards_found;
4004 qdev->ndev = ndev;
4005 qdev->pdev = pdev;
4006 qdev->device_id = pci_entry->device;
4007 qdev->port_link_state = LS_DOWN;
4008 if (msi)
4009 qdev->msi = 1;
4010
4011 qdev->msg_enable = netif_msg_init(debug, default_msg);
4012
4013 if (pci_using_dac)
4014 ndev->features |= NETIF_F_HIGHDMA;
4015 if (qdev->device_id == QL3032_DEVICE_ID)
4016 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4017
4018 qdev->mem_map_registers =
4019 ioremap_nocache(pci_resource_start(pdev, 1),
4020 pci_resource_len(qdev->pdev, 1));
4021 if (!qdev->mem_map_registers) {
4022 printk(KERN_ERR PFX "%s: cannot map device registers\n",
4023 pci_name(pdev));
4024 err = -EIO;
4025 goto err_out_free_ndev;
4026 }
4027
4028 spin_lock_init(&qdev->adapter_lock);
4029 spin_lock_init(&qdev->hw_lock);
4030
4031 /* Set driver entry points */
4032 ndev->open = ql3xxx_open;
4033 ndev->hard_start_xmit = ql3xxx_send;
4034 ndev->stop = ql3xxx_close;
4035 ndev->set_multicast_list = ql3xxx_set_multicast_list;
4036 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4037 ndev->set_mac_address = ql3xxx_set_mac_address;
4038 ndev->tx_timeout = ql3xxx_tx_timeout;
4039 ndev->watchdog_timeo = 5 * HZ;
4040
4041 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
4042
4043 ndev->irq = pdev->irq;
4044
4045 /* make sure the EEPROM is good */
4046 if (ql_get_nvram_params(qdev)) {
4047 printk(KERN_ALERT PFX
4048 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4049 qdev->index);
4050 err = -EIO;
4051 goto err_out_iounmap;
4052 }
4053
4054 ql_set_mac_info(qdev);
4055
4056 /* Validate and set parameters */
4057 if (qdev->mac_index) {
4058 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
4059 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
4060 ETH_ALEN);
4061 } else {
4062 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
4063 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
4064 ETH_ALEN);
4065 }
4066 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4067
4068 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4069
4070 /* Turn off support for multicasting */
4071 ndev->flags &= ~IFF_MULTICAST;
4072
4073 /* Record PCI bus information. */
4074 ql_get_board_info(qdev);
4075
4076 /*
4077 * Set the Maximum Memory Read Byte Count value. We do this to handle
4078 * jumbo frames.
4079 */
4080 if (qdev->pci_x) {
4081 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4082 }
4083
4084 err = register_netdev(ndev);
4085 if (err) {
4086 printk(KERN_ERR PFX "%s: cannot register net device\n",
4087 pci_name(pdev));
4088 goto err_out_iounmap;
4089 }
4090
4091 /* we're going to reset, so assume we have no link for now */
4092
4093 netif_carrier_off(ndev);
4094 netif_stop_queue(ndev);
4095
4096 qdev->workqueue = create_singlethread_workqueue(ndev->name);
4097 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4098 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
4099 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
4100
4101 init_timer(&qdev->adapter_timer);
4102 qdev->adapter_timer.function = ql3xxx_timer;
4103 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4104 qdev->adapter_timer.data = (unsigned long)qdev;
4105
4106 if(!cards_found) {
4107 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4108 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4109 DRV_NAME, DRV_VERSION);
4110 }
4111 ql_display_dev_info(ndev);
4112
4113 cards_found++;
4114 return 0;
4115
4116 err_out_iounmap:
4117 iounmap(qdev->mem_map_registers);
4118 err_out_free_ndev:
4119 free_netdev(ndev);
4120 err_out_free_regions:
4121 pci_release_regions(pdev);
4122 err_out_disable_pdev:
4123 pci_disable_device(pdev);
4124 pci_set_drvdata(pdev, NULL);
4125 err_out:
4126 return err;
4127 }
4128
4129 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4130 {
4131 struct net_device *ndev = pci_get_drvdata(pdev);
4132 struct ql3_adapter *qdev = netdev_priv(ndev);
4133
4134 unregister_netdev(ndev);
4135 qdev = netdev_priv(ndev);
4136
4137 ql_disable_interrupts(qdev);
4138
4139 if (qdev->workqueue) {
4140 cancel_delayed_work(&qdev->reset_work);
4141 cancel_delayed_work(&qdev->tx_timeout_work);
4142 destroy_workqueue(qdev->workqueue);
4143 qdev->workqueue = NULL;
4144 }
4145
4146 iounmap(qdev->mem_map_registers);
4147 pci_release_regions(pdev);
4148 pci_set_drvdata(pdev, NULL);
4149 free_netdev(ndev);
4150 }
4151
4152 static struct pci_driver ql3xxx_driver = {
4153
4154 .name = DRV_NAME,
4155 .id_table = ql3xxx_pci_tbl,
4156 .probe = ql3xxx_probe,
4157 .remove = __devexit_p(ql3xxx_remove),
4158 };
4159
4160 static int __init ql3xxx_init_module(void)
4161 {
4162 return pci_register_driver(&ql3xxx_driver);
4163 }
4164
4165 static void __exit ql3xxx_exit(void)
4166 {
4167 pci_unregister_driver(&ql3xxx_driver);
4168 }
4169
4170 module_init(ql3xxx_init_module);
4171 module_exit(ql3xxx_exit);
CJK support for tty framebuffer vt