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mISDN: Rework of LED status display for HFC-4S/8S/E1 cards.
[linux-2.6/cjktty.git] / drivers / isdn / hardware / mISDN / hfcmulti.c
blob876f7d0db26ff8912ca3b4c3c598aecb47cb7035
1 /*
2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
3 *
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
7 *
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *
28 * Thanks to Cologne Chip AG for this great controller!
29 */
30
31 /*
32 * module parameters:
33 * type:
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
41 * Bit 10 = spare
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
44 * Bit 13 = spare
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
49 * Bit 18 = spare
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
53 * bus (PCM master)
54 *
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
64 *
65 * HFC-E1 only bits:
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
73 * mode instead.
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
77 * (E1 only)
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
79 * for default.
80 * (all other bits are reserved and shall be 0)
81 *
82 * debug:
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
85 *
86 * poll:
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
92 *
93 * pcm:
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
105 *
106 * dslot:
107 * NOTE: only one dslot value must be given for every card.
108 * Also this value must be given for non-E1 cards. If omitted, the E1
109 * card has D-channel on time slot 16, which is default.
110 * If 1..15 or 17..31, an alternate time slot is used for D-channel.
111 * In this case, the application must be able to handle this.
112 * If -1 is given, the D-channel is disabled and all 31 slots can be used
113 * for B-channel. (only for specific applications)
114 * If you don't know how to use it, you don't need it!
115 *
116 * iomode:
117 * NOTE: only one mode value must be given for every card.
118 * -> See hfc_multi.h for HFC_IO_MODE_* values
119 * By default, the IO mode is pci memory IO (MEMIO).
120 * Some cards require specific IO mode, so it cannot be changed.
121 * It may be useful to set IO mode to register io (REGIO) to solve
122 * PCI bridge problems.
123 * If unsure, don't give this parameter.
124 *
125 * clockdelay_nt:
126 * NOTE: only one clockdelay_nt value must be given once for all cards.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
128 * of the S/T interfaces in NT mode.
129 * This register is needed for the TBR3 certification, so don't change it.
130 *
131 * clockdelay_te:
132 * NOTE: only one clockdelay_te value must be given once
133 * Give the value of the clock control register (A_ST_CLK_DLY)
134 * of the S/T interfaces in TE mode.
135 * This register is needed for the TBR3 certification, so don't change it.
136 *
137 * clock:
138 * NOTE: only one clock value must be given once
139 * Selects interface with clock source for mISDN and applications.
140 * Set to card number starting with 1. Set to -1 to disable.
141 * By default, the first card is used as clock source.
142 *
143 * hwid:
144 * NOTE: only one hwid value must be given once
145 * Enable special embedded devices with XHFC controllers.
146 */
147
148 /*
149 * debug register access (never use this, it will flood your system log)
150 * #define HFC_REGISTER_DEBUG
151 */
152
153 #define HFC_MULTI_VERSION "2.03"
154
155 #include <linux/interrupt.h>
156 #include <linux/module.h>
157 #include <linux/slab.h>
158 #include <linux/pci.h>
159 #include <linux/delay.h>
160 #include <linux/mISDNhw.h>
161 #include <linux/mISDNdsp.h>
162
163 /*
164 #define IRQCOUNT_DEBUG
165 #define IRQ_DEBUG
166 */
167
168 #include "hfc_multi.h"
169 #ifdef ECHOPREP
170 #include "gaintab.h"
171 #endif
172
173 #define MAX_CARDS 8
174 #define MAX_PORTS (8 * MAX_CARDS)
175
176 static LIST_HEAD(HFClist);
177 static spinlock_t HFClock; /* global hfc list lock */
178
179 static void ph_state_change(struct dchannel *);
180
181 static struct hfc_multi *syncmaster;
182 static int plxsd_master; /* if we have a master card (yet) */
183 static spinlock_t plx_lock; /* may not acquire other lock inside */
184
185 #define TYP_E1 1
186 #define TYP_4S 4
187 #define TYP_8S 8
188
189 static int poll_timer = 6; /* default = 128 samples = 16ms */
190 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
191 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
192 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
193 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
194 (0x60 MUST be included!) */
195
196 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
197 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
198 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
199
200 /*
201 * module stuff
202 */
203
204 static uint type[MAX_CARDS];
205 static int pcm[MAX_CARDS];
206 static int dslot[MAX_CARDS];
207 static uint iomode[MAX_CARDS];
208 static uint port[MAX_PORTS];
209 static uint debug;
210 static uint poll;
211 static int clock;
212 static uint timer;
213 static uint clockdelay_te = CLKDEL_TE;
214 static uint clockdelay_nt = CLKDEL_NT;
215 #define HWID_NONE 0
216 #define HWID_MINIP4 1
217 #define HWID_MINIP8 2
218 #define HWID_MINIP16 3
219 static uint hwid = HWID_NONE;
220
221 static int HFC_cnt, Port_cnt, PCM_cnt = 99;
222
223 MODULE_AUTHOR("Andreas Eversberg");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(HFC_MULTI_VERSION);
226 module_param(debug, uint, S_IRUGO | S_IWUSR);
227 module_param(poll, uint, S_IRUGO | S_IWUSR);
228 module_param(clock, int, S_IRUGO | S_IWUSR);
229 module_param(timer, uint, S_IRUGO | S_IWUSR);
230 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
231 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
232 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
233 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
234 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
235 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
236 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
237 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
238
239 #ifdef HFC_REGISTER_DEBUG
240 #define HFC_outb(hc, reg, val) \
241 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
242 #define HFC_outb_nodebug(hc, reg, val) \
243 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
244 #define HFC_inb(hc, reg) \
245 (hc->HFC_inb(hc, reg, __func__, __LINE__))
246 #define HFC_inb_nodebug(hc, reg) \
247 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
248 #define HFC_inw(hc, reg) \
249 (hc->HFC_inw(hc, reg, __func__, __LINE__))
250 #define HFC_inw_nodebug(hc, reg) \
251 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
252 #define HFC_wait(hc) \
253 (hc->HFC_wait(hc, __func__, __LINE__))
254 #define HFC_wait_nodebug(hc) \
255 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
256 #else
257 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
258 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
259 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
260 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
261 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
262 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
263 #define HFC_wait(hc) (hc->HFC_wait(hc))
264 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
265 #endif
266
267 #ifdef CONFIG_MISDN_HFCMULTI_8xx
268 #include "hfc_multi_8xx.h"
269 #endif
270
271 /* HFC_IO_MODE_PCIMEM */
272 static void
273 #ifdef HFC_REGISTER_DEBUG
274 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
275 const char *function, int line)
276 #else
277 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
278 #endif
279 {
280 writeb(val, hc->pci_membase + reg);
281 }
282 static u_char
283 #ifdef HFC_REGISTER_DEBUG
284 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
285 #else
286 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
287 #endif
288 {
289 return readb(hc->pci_membase + reg);
290 }
291 static u_short
292 #ifdef HFC_REGISTER_DEBUG
293 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
294 #else
295 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
296 #endif
297 {
298 return readw(hc->pci_membase + reg);
299 }
300 static void
301 #ifdef HFC_REGISTER_DEBUG
302 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
303 #else
304 HFC_wait_pcimem(struct hfc_multi *hc)
305 #endif
306 {
307 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
308 cpu_relax();
309 }
310
311 /* HFC_IO_MODE_REGIO */
312 static void
313 #ifdef HFC_REGISTER_DEBUG
314 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
315 const char *function, int line)
316 #else
317 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
318 #endif
319 {
320 outb(reg, hc->pci_iobase + 4);
321 outb(val, hc->pci_iobase);
322 }
323 static u_char
324 #ifdef HFC_REGISTER_DEBUG
325 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
326 #else
327 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
328 #endif
329 {
330 outb(reg, hc->pci_iobase + 4);
331 return inb(hc->pci_iobase);
332 }
333 static u_short
334 #ifdef HFC_REGISTER_DEBUG
335 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
336 #else
337 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
338 #endif
339 {
340 outb(reg, hc->pci_iobase + 4);
341 return inw(hc->pci_iobase);
342 }
343 static void
344 #ifdef HFC_REGISTER_DEBUG
345 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
346 #else
347 HFC_wait_regio(struct hfc_multi *hc)
348 #endif
349 {
350 outb(R_STATUS, hc->pci_iobase + 4);
351 while (inb(hc->pci_iobase) & V_BUSY)
352 cpu_relax();
353 }
354
355 #ifdef HFC_REGISTER_DEBUG
356 static void
357 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
358 const char *function, int line)
359 {
360 char regname[256] = "", bits[9] = "xxxxxxxx";
361 int i;
362
363 i = -1;
364 while (hfc_register_names[++i].name) {
365 if (hfc_register_names[i].reg == reg)
366 strcat(regname, hfc_register_names[i].name);
367 }
368 if (regname[0] == '\0')
369 strcpy(regname, "register");
370
371 bits[7] = '0' + (!!(val & 1));
372 bits[6] = '0' + (!!(val & 2));
373 bits[5] = '0' + (!!(val & 4));
374 bits[4] = '0' + (!!(val & 8));
375 bits[3] = '0' + (!!(val & 16));
376 bits[2] = '0' + (!!(val & 32));
377 bits[1] = '0' + (!!(val & 64));
378 bits[0] = '0' + (!!(val & 128));
379 printk(KERN_DEBUG
380 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
381 hc->id, reg, regname, val, bits, function, line);
382 HFC_outb_nodebug(hc, reg, val);
383 }
384 static u_char
385 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
386 {
387 char regname[256] = "", bits[9] = "xxxxxxxx";
388 u_char val = HFC_inb_nodebug(hc, reg);
389 int i;
390
391 i = 0;
392 while (hfc_register_names[i++].name)
393 ;
394 while (hfc_register_names[++i].name) {
395 if (hfc_register_names[i].reg == reg)
396 strcat(regname, hfc_register_names[i].name);
397 }
398 if (regname[0] == '\0')
399 strcpy(regname, "register");
400
401 bits[7] = '0' + (!!(val & 1));
402 bits[6] = '0' + (!!(val & 2));
403 bits[5] = '0' + (!!(val & 4));
404 bits[4] = '0' + (!!(val & 8));
405 bits[3] = '0' + (!!(val & 16));
406 bits[2] = '0' + (!!(val & 32));
407 bits[1] = '0' + (!!(val & 64));
408 bits[0] = '0' + (!!(val & 128));
409 printk(KERN_DEBUG
410 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
411 hc->id, reg, regname, val, bits, function, line);
412 return val;
413 }
414 static u_short
415 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
416 {
417 char regname[256] = "";
418 u_short val = HFC_inw_nodebug(hc, reg);
419 int i;
420
421 i = 0;
422 while (hfc_register_names[i++].name)
423 ;
424 while (hfc_register_names[++i].name) {
425 if (hfc_register_names[i].reg == reg)
426 strcat(regname, hfc_register_names[i].name);
427 }
428 if (regname[0] == '\0')
429 strcpy(regname, "register");
430
431 printk(KERN_DEBUG
432 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
433 hc->id, reg, regname, val, function, line);
434 return val;
435 }
436 static void
437 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
438 {
439 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
440 hc->id, function, line);
441 HFC_wait_nodebug(hc);
442 }
443 #endif
444
445 /* write fifo data (REGIO) */
446 static void
447 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
448 {
449 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
450 while (len >> 2) {
451 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
452 data += 4;
453 len -= 4;
454 }
455 while (len >> 1) {
456 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
457 data += 2;
458 len -= 2;
459 }
460 while (len) {
461 outb(*data, hc->pci_iobase);
462 data++;
463 len--;
464 }
465 }
466 /* write fifo data (PCIMEM) */
467 static void
468 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
469 {
470 while (len >> 2) {
471 writel(cpu_to_le32(*(u32 *)data),
472 hc->pci_membase + A_FIFO_DATA0);
473 data += 4;
474 len -= 4;
475 }
476 while (len >> 1) {
477 writew(cpu_to_le16(*(u16 *)data),
478 hc->pci_membase + A_FIFO_DATA0);
479 data += 2;
480 len -= 2;
481 }
482 while (len) {
483 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
484 data++;
485 len--;
486 }
487 }
488
489 /* read fifo data (REGIO) */
490 static void
491 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
492 {
493 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
494 while (len >> 2) {
495 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
496 data += 4;
497 len -= 4;
498 }
499 while (len >> 1) {
500 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
501 data += 2;
502 len -= 2;
503 }
504 while (len) {
505 *data = inb(hc->pci_iobase);
506 data++;
507 len--;
508 }
509 }
510
511 /* read fifo data (PCIMEM) */
512 static void
513 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
514 {
515 while (len >> 2) {
516 *(u32 *)data =
517 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
518 data += 4;
519 len -= 4;
520 }
521 while (len >> 1) {
522 *(u16 *)data =
523 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
524 data += 2;
525 len -= 2;
526 }
527 while (len) {
528 *data = readb(hc->pci_membase + A_FIFO_DATA0);
529 data++;
530 len--;
531 }
532 }
533
534 static void
535 enable_hwirq(struct hfc_multi *hc)
536 {
537 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
538 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
539 }
540
541 static void
542 disable_hwirq(struct hfc_multi *hc)
543 {
544 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
545 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
546 }
547
548 #define NUM_EC 2
549 #define MAX_TDM_CHAN 32
550
551
552 inline void
553 enablepcibridge(struct hfc_multi *c)
554 {
555 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
556 }
557
558 inline void
559 disablepcibridge(struct hfc_multi *c)
560 {
561 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
562 }
563
564 inline unsigned char
565 readpcibridge(struct hfc_multi *hc, unsigned char address)
566 {
567 unsigned short cipv;
568 unsigned char data;
569
570 if (!hc->pci_iobase)
571 return 0;
572
573 /* slow down a PCI read access by 1 PCI clock cycle */
574 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
575
576 if (address == 0)
577 cipv = 0x4000;
578 else
579 cipv = 0x5800;
580
581 /* select local bridge port address by writing to CIP port */
582 /* data = HFC_inb(c, cipv); * was _io before */
583 outw(cipv, hc->pci_iobase + 4);
584 data = inb(hc->pci_iobase);
585
586 /* restore R_CTRL for normal PCI read cycle speed */
587 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
588
589 return data;
590 }
591
592 inline void
593 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
594 {
595 unsigned short cipv;
596 unsigned int datav;
597
598 if (!hc->pci_iobase)
599 return;
600
601 if (address == 0)
602 cipv = 0x4000;
603 else
604 cipv = 0x5800;
605
606 /* select local bridge port address by writing to CIP port */
607 outw(cipv, hc->pci_iobase + 4);
608 /* define a 32 bit dword with 4 identical bytes for write sequence */
609 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
610 ((__u32) data << 24);
611
612 /*
613 * write this 32 bit dword to the bridge data port
614 * this will initiate a write sequence of up to 4 writes to the same
615 * address on the local bus interface the number of write accesses
616 * is undefined but >=1 and depends on the next PCI transaction
617 * during write sequence on the local bus
618 */
619 outl(datav, hc->pci_iobase);
620 }
621
622 inline void
623 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
624 {
625 /* Do data pin read low byte */
626 HFC_outb(hc, R_GPIO_OUT1, reg);
627 }
628
629 inline void
630 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
631 {
632 cpld_set_reg(hc, reg);
633
634 enablepcibridge(hc);
635 writepcibridge(hc, 1, val);
636 disablepcibridge(hc);
637
638 return;
639 }
640
641 inline unsigned char
642 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
643 {
644 unsigned char bytein;
645
646 cpld_set_reg(hc, reg);
647
648 /* Do data pin read low byte */
649 HFC_outb(hc, R_GPIO_OUT1, reg);
650
651 enablepcibridge(hc);
652 bytein = readpcibridge(hc, 1);
653 disablepcibridge(hc);
654
655 return bytein;
656 }
657
658 inline void
659 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
660 {
661 cpld_write_reg(hc, 0, 0xff & addr);
662 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
663 }
664
665 inline unsigned short
666 vpm_read_address(struct hfc_multi *c)
667 {
668 unsigned short addr;
669 unsigned short highbit;
670
671 addr = cpld_read_reg(c, 0);
672 highbit = cpld_read_reg(c, 1);
673
674 addr = addr | (highbit << 8);
675
676 return addr & 0x1ff;
677 }
678
679 inline unsigned char
680 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
681 {
682 unsigned char res;
683
684 vpm_write_address(c, addr);
685
686 if (!which)
687 cpld_set_reg(c, 2);
688 else
689 cpld_set_reg(c, 3);
690
691 enablepcibridge(c);
692 res = readpcibridge(c, 1);
693 disablepcibridge(c);
694
695 cpld_set_reg(c, 0);
696
697 return res;
698 }
699
700 inline void
701 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
702 unsigned char data)
703 {
704 vpm_write_address(c, addr);
705
706 enablepcibridge(c);
707
708 if (!which)
709 cpld_set_reg(c, 2);
710 else
711 cpld_set_reg(c, 3);
712
713 writepcibridge(c, 1, data);
714
715 cpld_set_reg(c, 0);
716
717 disablepcibridge(c);
718
719 {
720 unsigned char regin;
721 regin = vpm_in(c, which, addr);
722 if (regin != data)
723 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
724 "0x%x\n", data, addr, regin);
725 }
726
727 }
728
729
730 static void
731 vpm_init(struct hfc_multi *wc)
732 {
733 unsigned char reg;
734 unsigned int mask;
735 unsigned int i, x, y;
736 unsigned int ver;
737
738 for (x = 0; x < NUM_EC; x++) {
739 /* Setup GPIO's */
740 if (!x) {
741 ver = vpm_in(wc, x, 0x1a0);
742 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
743 }
744
745 for (y = 0; y < 4; y++) {
746 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
747 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
748 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
749 }
750
751 /* Setup TDM path - sets fsync and tdm_clk as inputs */
752 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
753 vpm_out(wc, x, 0x1a3, reg & ~2);
754
755 /* Setup Echo length (256 taps) */
756 vpm_out(wc, x, 0x022, 1);
757 vpm_out(wc, x, 0x023, 0xff);
758
759 /* Setup timeslots */
760 vpm_out(wc, x, 0x02f, 0x00);
761 mask = 0x02020202 << (x * 4);
762
763 /* Setup the tdm channel masks for all chips */
764 for (i = 0; i < 4; i++)
765 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
766
767 /* Setup convergence rate */
768 printk(KERN_DEBUG "VPM: A-law mode\n");
769 reg = 0x00 | 0x10 | 0x01;
770 vpm_out(wc, x, 0x20, reg);
771 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
772 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
773
774 vpm_out(wc, x, 0x24, 0x02);
775 reg = vpm_in(wc, x, 0x24);
776 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
777
778 /* Initialize echo cans */
779 for (i = 0; i < MAX_TDM_CHAN; i++) {
780 if (mask & (0x00000001 << i))
781 vpm_out(wc, x, i, 0x00);
782 }
783
784 /*
785 * ARM arch at least disallows a udelay of
786 * more than 2ms... it gives a fake "__bad_udelay"
787 * reference at link-time.
788 * long delays in kernel code are pretty sucky anyway
789 * for now work around it using 5 x 2ms instead of 1 x 10ms
790 */
791
792 udelay(2000);
793 udelay(2000);
794 udelay(2000);
795 udelay(2000);
796 udelay(2000);
797
798 /* Put in bypass mode */
799 for (i = 0; i < MAX_TDM_CHAN; i++) {
800 if (mask & (0x00000001 << i))
801 vpm_out(wc, x, i, 0x01);
802 }
803
804 /* Enable bypass */
805 for (i = 0; i < MAX_TDM_CHAN; i++) {
806 if (mask & (0x00000001 << i))
807 vpm_out(wc, x, 0x78 + i, 0x01);
808 }
809
810 }
811 }
812
813 #ifdef UNUSED
814 static void
815 vpm_check(struct hfc_multi *hctmp)
816 {
817 unsigned char gpi2;
818
819 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
820
821 if ((gpi2 & 0x3) != 0x3)
822 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
823 }
824 #endif /* UNUSED */
825
826
827 /*
828 * Interface to enable/disable the HW Echocan
829 *
830 * these functions are called within a spin_lock_irqsave on
831 * the channel instance lock, so we are not disturbed by irqs
832 *
833 * we can later easily change the interface to make other
834 * things configurable, for now we configure the taps
835 *
836 */
837
838 static void
839 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
840 {
841 unsigned int timeslot;
842 unsigned int unit;
843 struct bchannel *bch = hc->chan[ch].bch;
844 #ifdef TXADJ
845 int txadj = -4;
846 struct sk_buff *skb;
847 #endif
848 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
849 return;
850
851 if (!bch)
852 return;
853
854 #ifdef TXADJ
855 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
856 sizeof(int), &txadj, GFP_ATOMIC);
857 if (skb)
858 recv_Bchannel_skb(bch, skb);
859 #endif
860
861 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
862 unit = ch % 4;
863
864 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
865 taps, timeslot);
866
867 vpm_out(hc, unit, timeslot, 0x7e);
868 }
869
870 static void
871 vpm_echocan_off(struct hfc_multi *hc, int ch)
872 {
873 unsigned int timeslot;
874 unsigned int unit;
875 struct bchannel *bch = hc->chan[ch].bch;
876 #ifdef TXADJ
877 int txadj = 0;
878 struct sk_buff *skb;
879 #endif
880
881 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
882 return;
883
884 if (!bch)
885 return;
886
887 #ifdef TXADJ
888 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
889 sizeof(int), &txadj, GFP_ATOMIC);
890 if (skb)
891 recv_Bchannel_skb(bch, skb);
892 #endif
893
894 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
895 unit = ch % 4;
896
897 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
898 timeslot);
899 /* FILLME */
900 vpm_out(hc, unit, timeslot, 0x01);
901 }
902
903
904 /*
905 * Speech Design resync feature
906 * NOTE: This is called sometimes outside interrupt handler.
907 * We must lock irqsave, so no other interrupt (other card) will occur!
908 * Also multiple interrupts may nest, so must lock each access (lists, card)!
909 */
910 static inline void
911 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
912 {
913 struct hfc_multi *hc, *next, *pcmmaster = NULL;
914 void __iomem *plx_acc_32;
915 u_int pv;
916 u_long flags;
917
918 spin_lock_irqsave(&HFClock, flags);
919 spin_lock(&plx_lock); /* must be locked inside other locks */
920
921 if (debug & DEBUG_HFCMULTI_PLXSD)
922 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
923 __func__, syncmaster);
924
925 /* select new master */
926 if (newmaster) {
927 if (debug & DEBUG_HFCMULTI_PLXSD)
928 printk(KERN_DEBUG "using provided controller\n");
929 } else {
930 list_for_each_entry_safe(hc, next, &HFClist, list) {
931 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
932 if (hc->syncronized) {
933 newmaster = hc;
934 break;
935 }
936 }
937 }
938 }
939
940 /* Disable sync of all cards */
941 list_for_each_entry_safe(hc, next, &HFClist, list) {
942 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
943 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
944 pv = readl(plx_acc_32);
945 pv &= ~PLX_SYNC_O_EN;
946 writel(pv, plx_acc_32);
947 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
948 pcmmaster = hc;
949 if (hc->ctype == HFC_TYPE_E1) {
950 if (debug & DEBUG_HFCMULTI_PLXSD)
951 printk(KERN_DEBUG
952 "Schedule SYNC_I\n");
953 hc->e1_resync |= 1; /* get SYNC_I */
954 }
955 }
956 }
957 }
958
959 if (newmaster) {
960 hc = newmaster;
961 if (debug & DEBUG_HFCMULTI_PLXSD)
962 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
963 "interface.\n", hc->id, hc);
964 /* Enable new sync master */
965 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
966 pv = readl(plx_acc_32);
967 pv |= PLX_SYNC_O_EN;
968 writel(pv, plx_acc_32);
969 /* switch to jatt PLL, if not disabled by RX_SYNC */
970 if (hc->ctype == HFC_TYPE_E1
971 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
972 if (debug & DEBUG_HFCMULTI_PLXSD)
973 printk(KERN_DEBUG "Schedule jatt PLL\n");
974 hc->e1_resync |= 2; /* switch to jatt */
975 }
976 } else {
977 if (pcmmaster) {
978 hc = pcmmaster;
979 if (debug & DEBUG_HFCMULTI_PLXSD)
980 printk(KERN_DEBUG
981 "id=%d (0x%p) = PCM master syncronized "
982 "with QUARTZ\n", hc->id, hc);
983 if (hc->ctype == HFC_TYPE_E1) {
984 /* Use the crystal clock for the PCM
985 master card */
986 if (debug & DEBUG_HFCMULTI_PLXSD)
987 printk(KERN_DEBUG
988 "Schedule QUARTZ for HFC-E1\n");
989 hc->e1_resync |= 4; /* switch quartz */
990 } else {
991 if (debug & DEBUG_HFCMULTI_PLXSD)
992 printk(KERN_DEBUG
993 "QUARTZ is automatically "
994 "enabled by HFC-%dS\n", hc->ctype);
995 }
996 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
997 pv = readl(plx_acc_32);
998 pv |= PLX_SYNC_O_EN;
999 writel(pv, plx_acc_32);
1000 } else
1001 if (!rm)
1002 printk(KERN_ERR "%s no pcm master, this MUST "
1003 "not happen!\n", __func__);
1004 }
1005 syncmaster = newmaster;
1006
1007 spin_unlock(&plx_lock);
1008 spin_unlock_irqrestore(&HFClock, flags);
1009 }
1010
1011 /* This must be called AND hc must be locked irqsave!!! */
1012 inline void
1013 plxsd_checksync(struct hfc_multi *hc, int rm)
1014 {
1015 if (hc->syncronized) {
1016 if (syncmaster == NULL) {
1017 if (debug & DEBUG_HFCMULTI_PLXSD)
1018 printk(KERN_DEBUG "%s: GOT sync on card %d"
1019 " (id=%d)\n", __func__, hc->id + 1,
1020 hc->id);
1021 hfcmulti_resync(hc, hc, rm);
1022 }
1023 } else {
1024 if (syncmaster == hc) {
1025 if (debug & DEBUG_HFCMULTI_PLXSD)
1026 printk(KERN_DEBUG "%s: LOST sync on card %d"
1027 " (id=%d)\n", __func__, hc->id + 1,
1028 hc->id);
1029 hfcmulti_resync(hc, NULL, rm);
1030 }
1031 }
1032 }
1033
1034
1035 /*
1036 * free hardware resources used by driver
1037 */
1038 static void
1039 release_io_hfcmulti(struct hfc_multi *hc)
1040 {
1041 void __iomem *plx_acc_32;
1042 u_int pv;
1043 u_long plx_flags;
1044
1045 if (debug & DEBUG_HFCMULTI_INIT)
1046 printk(KERN_DEBUG "%s: entered\n", __func__);
1047
1048 /* soft reset also masks all interrupts */
1049 hc->hw.r_cirm |= V_SRES;
1050 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1051 udelay(1000);
1052 hc->hw.r_cirm &= ~V_SRES;
1053 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1054 udelay(1000); /* instead of 'wait' that may cause locking */
1055
1056 /* release Speech Design card, if PLX was initialized */
1057 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1058 if (debug & DEBUG_HFCMULTI_PLXSD)
1059 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1060 __func__, hc->id + 1);
1061 spin_lock_irqsave(&plx_lock, plx_flags);
1062 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1063 writel(PLX_GPIOC_INIT, plx_acc_32);
1064 pv = readl(plx_acc_32);
1065 /* Termination off */
1066 pv &= ~PLX_TERM_ON;
1067 /* Disconnect the PCM */
1068 pv |= PLX_SLAVE_EN_N;
1069 pv &= ~PLX_MASTER_EN;
1070 pv &= ~PLX_SYNC_O_EN;
1071 /* Put the DSP in Reset */
1072 pv &= ~PLX_DSP_RES_N;
1073 writel(pv, plx_acc_32);
1074 if (debug & DEBUG_HFCMULTI_INIT)
1075 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1076 __func__, pv);
1077 spin_unlock_irqrestore(&plx_lock, plx_flags);
1078 }
1079
1080 /* disable memory mapped ports / io ports */
1081 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1082 if (hc->pci_dev)
1083 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1084 if (hc->pci_membase)
1085 iounmap(hc->pci_membase);
1086 if (hc->plx_membase)
1087 iounmap(hc->plx_membase);
1088 if (hc->pci_iobase)
1089 release_region(hc->pci_iobase, 8);
1090 if (hc->xhfc_membase)
1091 iounmap((void *)hc->xhfc_membase);
1092
1093 if (hc->pci_dev) {
1094 pci_disable_device(hc->pci_dev);
1095 pci_set_drvdata(hc->pci_dev, NULL);
1096 }
1097 if (debug & DEBUG_HFCMULTI_INIT)
1098 printk(KERN_DEBUG "%s: done\n", __func__);
1099 }
1100
1101 /*
1102 * function called to reset the HFC chip. A complete software reset of chip
1103 * and fifos is done. All configuration of the chip is done.
1104 */
1105
1106 static int
1107 init_chip(struct hfc_multi *hc)
1108 {
1109 u_long flags, val, val2 = 0, rev;
1110 int i, err = 0;
1111 u_char r_conf_en, rval;
1112 void __iomem *plx_acc_32;
1113 u_int pv;
1114 u_long plx_flags, hfc_flags;
1115 int plx_count;
1116 struct hfc_multi *pos, *next, *plx_last_hc;
1117
1118 spin_lock_irqsave(&hc->lock, flags);
1119 /* reset all registers */
1120 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1121
1122 /* revision check */
1123 if (debug & DEBUG_HFCMULTI_INIT)
1124 printk(KERN_DEBUG "%s: entered\n", __func__);
1125 val = HFC_inb(hc, R_CHIP_ID);
1126 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1127 (val >> 1) != 0x31) {
1128 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1129 err = -EIO;
1130 goto out;
1131 }
1132 rev = HFC_inb(hc, R_CHIP_RV);
1133 printk(KERN_INFO
1134 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1135 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1136 " (old FIFO handling)" : "");
1137 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1138 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1139 printk(KERN_WARNING
1140 "HFC_multi: NOTE: Your chip is revision 0, "
1141 "ask Cologne Chip for update. Newer chips "
1142 "have a better FIFO handling. Old chips "
1143 "still work but may have slightly lower "
1144 "HDLC transmit performance.\n");
1145 }
1146 if (rev > 1) {
1147 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1148 "consider chip revision = %ld. The chip / "
1149 "bridge may not work.\n", rev);
1150 }
1151
1152 /* set s-ram size */
1153 hc->Flen = 0x10;
1154 hc->Zmin = 0x80;
1155 hc->Zlen = 384;
1156 hc->DTMFbase = 0x1000;
1157 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1158 if (debug & DEBUG_HFCMULTI_INIT)
1159 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1160 __func__);
1161 hc->hw.r_ctrl |= V_EXT_RAM;
1162 hc->hw.r_ram_sz = 1;
1163 hc->Flen = 0x20;
1164 hc->Zmin = 0xc0;
1165 hc->Zlen = 1856;
1166 hc->DTMFbase = 0x2000;
1167 }
1168 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1169 if (debug & DEBUG_HFCMULTI_INIT)
1170 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1171 __func__);
1172 hc->hw.r_ctrl |= V_EXT_RAM;
1173 hc->hw.r_ram_sz = 2;
1174 hc->Flen = 0x20;
1175 hc->Zmin = 0xc0;
1176 hc->Zlen = 8000;
1177 hc->DTMFbase = 0x2000;
1178 }
1179 if (hc->ctype == HFC_TYPE_XHFC) {
1180 hc->Flen = 0x8;
1181 hc->Zmin = 0x0;
1182 hc->Zlen = 64;
1183 hc->DTMFbase = 0x0;
1184 }
1185 hc->max_trans = poll << 1;
1186 if (hc->max_trans > hc->Zlen)
1187 hc->max_trans = hc->Zlen;
1188
1189 /* Speech Design PLX bridge */
1190 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1191 if (debug & DEBUG_HFCMULTI_PLXSD)
1192 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1193 __func__, hc->id + 1);
1194 spin_lock_irqsave(&plx_lock, plx_flags);
1195 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1196 writel(PLX_GPIOC_INIT, plx_acc_32);
1197 pv = readl(plx_acc_32);
1198 /* The first and the last cards are terminating the PCM bus */
1199 pv |= PLX_TERM_ON; /* hc is currently the last */
1200 /* Disconnect the PCM */
1201 pv |= PLX_SLAVE_EN_N;
1202 pv &= ~PLX_MASTER_EN;
1203 pv &= ~PLX_SYNC_O_EN;
1204 /* Put the DSP in Reset */
1205 pv &= ~PLX_DSP_RES_N;
1206 writel(pv, plx_acc_32);
1207 spin_unlock_irqrestore(&plx_lock, plx_flags);
1208 if (debug & DEBUG_HFCMULTI_INIT)
1209 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1210 __func__, pv);
1211 /*
1212 * If we are the 3rd PLXSD card or higher, we must turn
1213 * termination of last PLXSD card off.
1214 */
1215 spin_lock_irqsave(&HFClock, hfc_flags);
1216 plx_count = 0;
1217 plx_last_hc = NULL;
1218 list_for_each_entry_safe(pos, next, &HFClist, list) {
1219 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1220 plx_count++;
1221 if (pos != hc)
1222 plx_last_hc = pos;
1223 }
1224 }
1225 if (plx_count >= 3) {
1226 if (debug & DEBUG_HFCMULTI_PLXSD)
1227 printk(KERN_DEBUG "%s: card %d is between, so "
1228 "we disable termination\n",
1229 __func__, plx_last_hc->id + 1);
1230 spin_lock_irqsave(&plx_lock, plx_flags);
1231 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1232 pv = readl(plx_acc_32);
1233 pv &= ~PLX_TERM_ON;
1234 writel(pv, plx_acc_32);
1235 spin_unlock_irqrestore(&plx_lock, plx_flags);
1236 if (debug & DEBUG_HFCMULTI_INIT)
1237 printk(KERN_DEBUG
1238 "%s: term off: PLX_GPIO=%x\n",
1239 __func__, pv);
1240 }
1241 spin_unlock_irqrestore(&HFClock, hfc_flags);
1242 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1243 }
1244
1245 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1246 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1247
1248 /* we only want the real Z2 read-pointer for revision > 0 */
1249 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1250 hc->hw.r_ram_sz |= V_FZ_MD;
1251
1252 /* select pcm mode */
1253 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1254 if (debug & DEBUG_HFCMULTI_INIT)
1255 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1256 __func__);
1257 } else
1258 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1259 if (debug & DEBUG_HFCMULTI_INIT)
1260 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1261 __func__);
1262 hc->hw.r_pcm_md0 |= V_PCM_MD;
1263 } else {
1264 if (debug & DEBUG_HFCMULTI_INIT)
1265 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1266 __func__);
1267 }
1268
1269 /* soft reset */
1270 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1271 if (hc->ctype == HFC_TYPE_XHFC)
1272 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1273 0x11 /* 16 Bytes TX/RX */);
1274 else
1275 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1276 HFC_outb(hc, R_FIFO_MD, 0);
1277 if (hc->ctype == HFC_TYPE_XHFC)
1278 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1279 else
1280 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1281 | V_RLD_EPR;
1282 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1283 udelay(100);
1284 hc->hw.r_cirm = 0;
1285 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1286 udelay(100);
1287 if (hc->ctype != HFC_TYPE_XHFC)
1288 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1289
1290 /* Speech Design PLX bridge pcm and sync mode */
1291 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1292 spin_lock_irqsave(&plx_lock, plx_flags);
1293 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1294 pv = readl(plx_acc_32);
1295 /* Connect PCM */
1296 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1297 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1298 pv |= PLX_SYNC_O_EN;
1299 if (debug & DEBUG_HFCMULTI_INIT)
1300 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1301 __func__, pv);
1302 } else {
1303 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1304 pv &= ~PLX_SYNC_O_EN;
1305 if (debug & DEBUG_HFCMULTI_INIT)
1306 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1307 __func__, pv);
1308 }
1309 writel(pv, plx_acc_32);
1310 spin_unlock_irqrestore(&plx_lock, plx_flags);
1311 }
1312
1313 /* PCM setup */
1314 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1315 if (hc->slots == 32)
1316 HFC_outb(hc, R_PCM_MD1, 0x00);
1317 if (hc->slots == 64)
1318 HFC_outb(hc, R_PCM_MD1, 0x10);
1319 if (hc->slots == 128)
1320 HFC_outb(hc, R_PCM_MD1, 0x20);
1321 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1322 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1323 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1324 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1325 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1326 else
1327 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1328 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1329 for (i = 0; i < 256; i++) {
1330 HFC_outb_nodebug(hc, R_SLOT, i);
1331 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1332 if (hc->ctype != HFC_TYPE_XHFC)
1333 HFC_outb_nodebug(hc, A_CONF, 0);
1334 hc->slot_owner[i] = -1;
1335 }
1336
1337 /* set clock speed */
1338 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1339 if (debug & DEBUG_HFCMULTI_INIT)
1340 printk(KERN_DEBUG
1341 "%s: setting double clock\n", __func__);
1342 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1343 }
1344
1345 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1346 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1347
1348 /* B410P GPIO */
1349 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1350 printk(KERN_NOTICE "Setting GPIOs\n");
1351 HFC_outb(hc, R_GPIO_SEL, 0x30);
1352 HFC_outb(hc, R_GPIO_EN1, 0x3);
1353 udelay(1000);
1354 printk(KERN_NOTICE "calling vpm_init\n");
1355 vpm_init(hc);
1356 }
1357
1358 /* check if R_F0_CNT counts (8 kHz frame count) */
1359 val = HFC_inb(hc, R_F0_CNTL);
1360 val += HFC_inb(hc, R_F0_CNTH) << 8;
1361 if (debug & DEBUG_HFCMULTI_INIT)
1362 printk(KERN_DEBUG
1363 "HFC_multi F0_CNT %ld after reset\n", val);
1364 spin_unlock_irqrestore(&hc->lock, flags);
1365 set_current_state(TASK_UNINTERRUPTIBLE);
1366 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1367 spin_lock_irqsave(&hc->lock, flags);
1368 val2 = HFC_inb(hc, R_F0_CNTL);
1369 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1370 if (debug & DEBUG_HFCMULTI_INIT)
1371 printk(KERN_DEBUG
1372 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1373 val2);
1374 if (val2 >= val + 8) { /* 1 ms */
1375 /* it counts, so we keep the pcm mode */
1376 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1377 printk(KERN_INFO "controller is PCM bus MASTER\n");
1378 else
1379 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1380 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1381 else {
1382 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1383 printk(KERN_INFO "controller is PCM bus SLAVE "
1384 "(auto detected)\n");
1385 }
1386 } else {
1387 /* does not count */
1388 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1389 controller_fail:
1390 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1391 "pulse. Seems that controller fails.\n");
1392 err = -EIO;
1393 goto out;
1394 }
1395 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1396 printk(KERN_INFO "controller is PCM bus SLAVE "
1397 "(ignoring missing PCM clock)\n");
1398 } else {
1399 /* only one pcm master */
1400 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1401 && plxsd_master) {
1402 printk(KERN_ERR "HFC_multi ERROR, no clock "
1403 "on another Speech Design card found. "
1404 "Please be sure to connect PCM cable.\n");
1405 err = -EIO;
1406 goto out;
1407 }
1408 /* retry with master clock */
1409 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1410 spin_lock_irqsave(&plx_lock, plx_flags);
1411 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1412 pv = readl(plx_acc_32);
1413 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1414 pv |= PLX_SYNC_O_EN;
1415 writel(pv, plx_acc_32);
1416 spin_unlock_irqrestore(&plx_lock, plx_flags);
1417 if (debug & DEBUG_HFCMULTI_INIT)
1418 printk(KERN_DEBUG "%s: master: "
1419 "PLX_GPIO=%x\n", __func__, pv);
1420 }
1421 hc->hw.r_pcm_md0 |= V_PCM_MD;
1422 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1423 spin_unlock_irqrestore(&hc->lock, flags);
1424 set_current_state(TASK_UNINTERRUPTIBLE);
1425 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1426 spin_lock_irqsave(&hc->lock, flags);
1427 val2 = HFC_inb(hc, R_F0_CNTL);
1428 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1429 if (debug & DEBUG_HFCMULTI_INIT)
1430 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1431 "10 ms (2nd try)\n", val2);
1432 if (val2 >= val + 8) { /* 1 ms */
1433 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1434 &hc->chip);
1435 printk(KERN_INFO "controller is PCM bus MASTER "
1436 "(auto detected)\n");
1437 } else
1438 goto controller_fail;
1439 }
1440 }
1441
1442 /* Release the DSP Reset */
1443 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1444 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1445 plxsd_master = 1;
1446 spin_lock_irqsave(&plx_lock, plx_flags);
1447 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1448 pv = readl(plx_acc_32);
1449 pv |= PLX_DSP_RES_N;
1450 writel(pv, plx_acc_32);
1451 spin_unlock_irqrestore(&plx_lock, plx_flags);
1452 if (debug & DEBUG_HFCMULTI_INIT)
1453 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1454 __func__, pv);
1455 }
1456
1457 /* pcm id */
1458 if (hc->pcm)
1459 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1460 hc->pcm);
1461 else {
1462 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1463 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1464 PCM_cnt++; /* SD has proprietary bridging */
1465 }
1466 hc->pcm = PCM_cnt;
1467 printk(KERN_INFO "controller has PCM BUS ID %d "
1468 "(auto selected)\n", hc->pcm);
1469 }
1470
1471 /* set up timer */
1472 HFC_outb(hc, R_TI_WD, poll_timer);
1473 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1474
1475 /* set E1 state machine IRQ */
1476 if (hc->ctype == HFC_TYPE_E1)
1477 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1478
1479 /* set DTMF detection */
1480 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1481 if (debug & DEBUG_HFCMULTI_INIT)
1482 printk(KERN_DEBUG "%s: enabling DTMF detection "
1483 "for all B-channel\n", __func__);
1484 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1485 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1486 hc->hw.r_dtmf |= V_ULAW_SEL;
1487 HFC_outb(hc, R_DTMF_N, 102 - 1);
1488 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1489 }
1490
1491 /* conference engine */
1492 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1493 r_conf_en = V_CONF_EN | V_ULAW;
1494 else
1495 r_conf_en = V_CONF_EN;
1496 if (hc->ctype != HFC_TYPE_XHFC)
1497 HFC_outb(hc, R_CONF_EN, r_conf_en);
1498
1499 /* setting leds */
1500 switch (hc->leds) {
1501 case 1: /* HFC-E1 OEM */
1502 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1503 HFC_outb(hc, R_GPIO_SEL, 0x32);
1504 else
1505 HFC_outb(hc, R_GPIO_SEL, 0x30);
1506
1507 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1508 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1509
1510 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1511 break;
1512
1513 case 2: /* HFC-4S OEM */
1514 case 3:
1515 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1516 HFC_outb(hc, R_GPIO_EN1, 0xff);
1517 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1518 break;
1519 }
1520
1521 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1522 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1523 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1524 }
1525
1526 /* set master clock */
1527 if (hc->masterclk >= 0) {
1528 if (debug & DEBUG_HFCMULTI_INIT)
1529 printk(KERN_DEBUG "%s: setting ST master clock "
1530 "to port %d (0..%d)\n",
1531 __func__, hc->masterclk, hc->ports - 1);
1532 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1533 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1534 }
1535
1536
1537
1538 /* setting misc irq */
1539 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1540 if (debug & DEBUG_HFCMULTI_INIT)
1541 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1542 hc->hw.r_irqmsk_misc);
1543
1544 /* RAM access test */
1545 HFC_outb(hc, R_RAM_ADDR0, 0);
1546 HFC_outb(hc, R_RAM_ADDR1, 0);
1547 HFC_outb(hc, R_RAM_ADDR2, 0);
1548 for (i = 0; i < 256; i++) {
1549 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1550 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1551 }
1552 for (i = 0; i < 256; i++) {
1553 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1554 HFC_inb_nodebug(hc, R_RAM_DATA);
1555 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1556 if (rval != ((i * 3) & 0xff)) {
1557 printk(KERN_DEBUG
1558 "addr:%x val:%x should:%x\n", i, rval,
1559 (i * 3) & 0xff);
1560 err++;
1561 }
1562 }
1563 if (err) {
1564 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1565 err = -EIO;
1566 goto out;
1567 }
1568
1569 if (debug & DEBUG_HFCMULTI_INIT)
1570 printk(KERN_DEBUG "%s: done\n", __func__);
1571 out:
1572 spin_unlock_irqrestore(&hc->lock, flags);
1573 return err;
1574 }
1575
1576
1577 /*
1578 * control the watchdog
1579 */
1580 static void
1581 hfcmulti_watchdog(struct hfc_multi *hc)
1582 {
1583 hc->wdcount++;
1584
1585 if (hc->wdcount > 10) {
1586 hc->wdcount = 0;
1587 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1588 V_GPIO_OUT3 : V_GPIO_OUT2;
1589
1590 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1591 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1592 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1593 }
1594 }
1595
1596
1597
1598 /*
1599 * output leds
1600 */
1601 static void
1602 hfcmulti_leds(struct hfc_multi *hc)
1603 {
1604 unsigned long lled;
1605 unsigned long leddw;
1606 int i, state, active, leds;
1607 struct dchannel *dch;
1608 int led[4];
1609
1610 switch (hc->leds) {
1611 case 1: /* HFC-E1 OEM */
1612 /* 2 red steady: LOS
1613 * 1 red steady: L1 not active
1614 * 2 green steady: L1 active
1615 * 1st green flashing: activity on TX
1616 * 2nd green flashing: activity on RX
1617 */
1618 led[0] = 0;
1619 led[1] = 0;
1620 led[2] = 0;
1621 led[3] = 0;
1622 dch = hc->chan[hc->dslot].dch;
1623 if (dch) {
1624 if (hc->chan[hc->dslot].los)
1625 led[1] = 1;
1626 if (hc->e1_state != 1) {
1627 led[0] = 1;
1628 hc->flash[2] = 0;
1629 hc->flash[3] = 0;
1630 } else {
1631 led[2] = 1;
1632 led[3] = 1;
1633 if (!hc->flash[2] && hc->activity_tx)
1634 hc->flash[2] = poll;
1635 if (!hc->flash[3] && hc->activity_rx)
1636 hc->flash[3] = poll;
1637 if (hc->flash[2] && hc->flash[2] < 1024)
1638 led[2] = 0;
1639 if (hc->flash[3] && hc->flash[3] < 1024)
1640 led[3] = 0;
1641 if (hc->flash[2] >= 2048)
1642 hc->flash[2] = 0;
1643 if (hc->flash[3] >= 2048)
1644 hc->flash[3] = 0;
1645 if (hc->flash[2])
1646 hc->flash[2] += poll;
1647 if (hc->flash[3])
1648 hc->flash[3] += poll;
1649 }
1650 }
1651 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1652 /* leds are inverted */
1653 if (leds != (int)hc->ledstate) {
1654 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1655 hc->ledstate = leds;
1656 }
1657 break;
1658
1659 case 2: /* HFC-4S OEM */
1660 /* red steady: PH_DEACTIVATE
1661 * green steady: PH_ACTIVATE
1662 * green flashing: activity on TX
1663 */
1664 for (i = 0; i < 4; i++) {
1665 state = 0;
1666 active = -1;
1667 dch = hc->chan[(i << 2) | 2].dch;
1668 if (dch) {
1669 state = dch->state;
1670 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1671 active = 3;
1672 else
1673 active = 7;
1674 }
1675 if (state) {
1676 if (state == active) {
1677 led[i] = 1; /* led green */
1678 hc->activity_tx |= hc->activity_rx;
1679 if (!hc->flash[i] &&
1680 (hc->activity_tx & (1 << i)))
1681 hc->flash[i] = poll;
1682 if (hc->flash[i] && hc->flash[i] < 1024)
1683 led[i] = 0; /* led off */
1684 if (hc->flash[i] >= 2048)
1685 hc->flash[i] = 0;
1686 if (hc->flash[i])
1687 hc->flash[i] += poll;
1688 } else {
1689 led[i] = 2; /* led red */
1690 hc->flash[i] = 0;
1691 }
1692 } else
1693 led[i] = 0; /* led off */
1694 }
1695 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1696 leds = 0;
1697 for (i = 0; i < 4; i++) {
1698 if (led[i] == 1) {
1699 /*green*/
1700 leds |= (0x2 << (i * 2));
1701 } else if (led[i] == 2) {
1702 /*red*/
1703 leds |= (0x1 << (i * 2));
1704 }
1705 }
1706 if (leds != (int)hc->ledstate) {
1707 vpm_out(hc, 0, 0x1a8 + 3, leds);
1708 hc->ledstate = leds;
1709 }
1710 } else {
1711 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1712 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1713 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1714 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1715 if (leds != (int)hc->ledstate) {
1716 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1717 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1718 hc->ledstate = leds;
1719 }
1720 }
1721 break;
1722
1723 case 3: /* HFC 1S/2S Beronet */
1724 /* red steady: PH_DEACTIVATE
1725 * green steady: PH_ACTIVATE
1726 * green flashing: activity on TX
1727 */
1728 for (i = 0; i < 2; i++) {
1729 state = 0;
1730 active = -1;
1731 dch = hc->chan[(i << 2) | 2].dch;
1732 if (dch) {
1733 state = dch->state;
1734 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1735 active = 3;
1736 else
1737 active = 7;
1738 }
1739 if (state) {
1740 if (state == active) {
1741 led[i] = 1; /* led green */
1742 hc->activity_tx |= hc->activity_rx;
1743 if (!hc->flash[i] &&
1744 (hc->activity_tx & (1 << i)))
1745 hc->flash[i] = poll;
1746 if (hc->flash[i] < 1024)
1747 led[i] = 0; /* led off */
1748 if (hc->flash[i] >= 2048)
1749 hc->flash[i] = 0;
1750 if (hc->flash[i])
1751 hc->flash[i] += poll;
1752 } else {
1753 led[i] = 2; /* led red */
1754 hc->flash[i] = 0;
1755 }
1756 } else
1757 led[i] = 0; /* led off */
1758 }
1759 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1760 | ((led[1]&1) << 3);
1761 if (leds != (int)hc->ledstate) {
1762 HFC_outb_nodebug(hc, R_GPIO_EN1,
1763 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1764 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1765 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1766 hc->ledstate = leds;
1767 }
1768 break;
1769 case 8: /* HFC 8S+ Beronet */
1770 /* off: PH_DEACTIVATE
1771 * steady: PH_ACTIVATE
1772 * flashing: activity on TX
1773 */
1774 lled = 0xff; /* leds off */
1775 for (i = 0; i < 8; i++) {
1776 state = 0;
1777 active = -1;
1778 dch = hc->chan[(i << 2) | 2].dch;
1779 if (dch) {
1780 state = dch->state;
1781 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1782 active = 3;
1783 else
1784 active = 7;
1785 }
1786 if (state) {
1787 if (state == active) {
1788 lled &= ~(1 << i); /* led on */
1789 hc->activity_tx |= hc->activity_rx;
1790 if (!hc->flash[i] &&
1791 (hc->activity_tx & (1 << i)))
1792 hc->flash[i] = poll;
1793 if (hc->flash[i] < 1024)
1794 lled |= 1 << i; /* led off */
1795 if (hc->flash[i] >= 2048)
1796 hc->flash[i] = 0;
1797 if (hc->flash[i])
1798 hc->flash[i] += poll;
1799 } else
1800 hc->flash[i] = 0;
1801 }
1802 }
1803 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1804 if (leddw != hc->ledstate) {
1805 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1806 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1807 /* was _io before */
1808 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1809 outw(0x4000, hc->pci_iobase + 4);
1810 outl(leddw, hc->pci_iobase);
1811 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1812 hc->ledstate = leddw;
1813 }
1814 break;
1815 }
1816 hc->activity_tx = 0;
1817 hc->activity_rx = 0;
1818 }
1819 /*
1820 * read dtmf coefficients
1821 */
1822
1823 static void
1824 hfcmulti_dtmf(struct hfc_multi *hc)
1825 {
1826 s32 *coeff;
1827 u_int mantissa;
1828 int co, ch;
1829 struct bchannel *bch = NULL;
1830 u8 exponent;
1831 int dtmf = 0;
1832 int addr;
1833 u16 w_float;
1834 struct sk_buff *skb;
1835 struct mISDNhead *hh;
1836
1837 if (debug & DEBUG_HFCMULTI_DTMF)
1838 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1839 for (ch = 0; ch <= 31; ch++) {
1840 /* only process enabled B-channels */
1841 bch = hc->chan[ch].bch;
1842 if (!bch)
1843 continue;
1844 if (!hc->created[hc->chan[ch].port])
1845 continue;
1846 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1847 continue;
1848 if (debug & DEBUG_HFCMULTI_DTMF)
1849 printk(KERN_DEBUG "%s: dtmf channel %d:",
1850 __func__, ch);
1851 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1852 dtmf = 1;
1853 for (co = 0; co < 8; co++) {
1854 /* read W(n-1) coefficient */
1855 addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1856 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1857 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1858 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1859 | V_ADDR_INC);
1860 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1861 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1862 if (debug & DEBUG_HFCMULTI_DTMF)
1863 printk(" %04x", w_float);
1864
1865 /* decode float (see chip doc) */
1866 mantissa = w_float & 0x0fff;
1867 if (w_float & 0x8000)
1868 mantissa |= 0xfffff000;
1869 exponent = (w_float >> 12) & 0x7;
1870 if (exponent) {
1871 mantissa ^= 0x1000;
1872 mantissa <<= (exponent - 1);
1873 }
1874
1875 /* store coefficient */
1876 coeff[co << 1] = mantissa;
1877
1878 /* read W(n) coefficient */
1879 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1880 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1881 if (debug & DEBUG_HFCMULTI_DTMF)
1882 printk(" %04x", w_float);
1883
1884 /* decode float (see chip doc) */
1885 mantissa = w_float & 0x0fff;
1886 if (w_float & 0x8000)
1887 mantissa |= 0xfffff000;
1888 exponent = (w_float >> 12) & 0x7;
1889 if (exponent) {
1890 mantissa ^= 0x1000;
1891 mantissa <<= (exponent - 1);
1892 }
1893
1894 /* store coefficient */
1895 coeff[(co << 1) | 1] = mantissa;
1896 }
1897 if (debug & DEBUG_HFCMULTI_DTMF)
1898 printk(" DTMF ready %08x %08x %08x %08x "
1899 "%08x %08x %08x %08x\n",
1900 coeff[0], coeff[1], coeff[2], coeff[3],
1901 coeff[4], coeff[5], coeff[6], coeff[7]);
1902 hc->chan[ch].coeff_count++;
1903 if (hc->chan[ch].coeff_count == 8) {
1904 hc->chan[ch].coeff_count = 0;
1905 skb = mI_alloc_skb(512, GFP_ATOMIC);
1906 if (!skb) {
1907 printk(KERN_DEBUG "%s: No memory for skb\n",
1908 __func__);
1909 continue;
1910 }
1911 hh = mISDN_HEAD_P(skb);
1912 hh->prim = PH_CONTROL_IND;
1913 hh->id = DTMF_HFC_COEF;
1914 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1915 recv_Bchannel_skb(bch, skb);
1916 }
1917 }
1918
1919 /* restart DTMF processing */
1920 hc->dtmf = dtmf;
1921 if (dtmf)
1922 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1923 }
1924
1925
1926 /*
1927 * fill fifo as much as possible
1928 */
1929
1930 static void
1931 hfcmulti_tx(struct hfc_multi *hc, int ch)
1932 {
1933 int i, ii, temp, len = 0;
1934 int Zspace, z1, z2; /* must be int for calculation */
1935 int Fspace, f1, f2;
1936 u_char *d;
1937 int *txpending, slot_tx;
1938 struct bchannel *bch;
1939 struct dchannel *dch;
1940 struct sk_buff **sp = NULL;
1941 int *idxp;
1942
1943 bch = hc->chan[ch].bch;
1944 dch = hc->chan[ch].dch;
1945 if ((!dch) && (!bch))
1946 return;
1947
1948 txpending = &hc->chan[ch].txpending;
1949 slot_tx = hc->chan[ch].slot_tx;
1950 if (dch) {
1951 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1952 return;
1953 sp = &dch->tx_skb;
1954 idxp = &dch->tx_idx;
1955 } else {
1956 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1957 return;
1958 sp = &bch->tx_skb;
1959 idxp = &bch->tx_idx;
1960 }
1961 if (*sp)
1962 len = (*sp)->len;
1963
1964 if ((!len) && *txpending != 1)
1965 return; /* no data */
1966
1967 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1968 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1969 (hc->chan[ch].slot_rx < 0) &&
1970 (hc->chan[ch].slot_tx < 0))
1971 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1972 else
1973 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1974 HFC_wait_nodebug(hc);
1975
1976 if (*txpending == 2) {
1977 /* reset fifo */
1978 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1979 HFC_wait_nodebug(hc);
1980 HFC_outb(hc, A_SUBCH_CFG, 0);
1981 *txpending = 1;
1982 }
1983 next_frame:
1984 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1985 f1 = HFC_inb_nodebug(hc, A_F1);
1986 f2 = HFC_inb_nodebug(hc, A_F2);
1987 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1988 if (debug & DEBUG_HFCMULTI_FIFO)
1989 printk(KERN_DEBUG
1990 "%s(card %d): reread f2 because %d!=%d\n",
1991 __func__, hc->id + 1, temp, f2);
1992 f2 = temp; /* repeat until F2 is equal */
1993 }
1994 Fspace = f2 - f1 - 1;
1995 if (Fspace < 0)
1996 Fspace += hc->Flen;
1997 /*
1998 * Old FIFO handling doesn't give us the current Z2 read
1999 * pointer, so we cannot send the next frame before the fifo
2000 * is empty. It makes no difference except for a slightly
2001 * lower performance.
2002 */
2003 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
2004 if (f1 != f2)
2005 Fspace = 0;
2006 else
2007 Fspace = 1;
2008 }
2009 /* one frame only for ST D-channels, to allow resending */
2010 if (hc->ctype != HFC_TYPE_E1 && dch) {
2011 if (f1 != f2)
2012 Fspace = 0;
2013 }
2014 /* F-counter full condition */
2015 if (Fspace == 0)
2016 return;
2017 }
2018 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2019 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2020 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2021 if (debug & DEBUG_HFCMULTI_FIFO)
2022 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2023 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2024 z2 = temp; /* repeat unti Z2 is equal */
2025 }
2026 hc->chan[ch].Zfill = z1 - z2;
2027 if (hc->chan[ch].Zfill < 0)
2028 hc->chan[ch].Zfill += hc->Zlen;
2029 Zspace = z2 - z1;
2030 if (Zspace <= 0)
2031 Zspace += hc->Zlen;
2032 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2033 /* fill transparent data only to maxinum transparent load (minus 4) */
2034 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2035 Zspace = Zspace - hc->Zlen + hc->max_trans;
2036 if (Zspace <= 0) /* no space of 4 bytes */
2037 return;
2038
2039 /* if no data */
2040 if (!len) {
2041 if (z1 == z2) { /* empty */
2042 /* if done with FIFO audio data during PCM connection */
2043 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2044 *txpending && slot_tx >= 0) {
2045 if (debug & DEBUG_HFCMULTI_MODE)
2046 printk(KERN_DEBUG
2047 "%s: reconnecting PCM due to no "
2048 "more FIFO data: channel %d "
2049 "slot_tx %d\n",
2050 __func__, ch, slot_tx);
2051 /* connect slot */
2052 if (hc->ctype == HFC_TYPE_XHFC)
2053 HFC_outb(hc, A_CON_HDLC, 0xc0
2054 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2055 /* Enable FIFO, no interrupt */
2056 else
2057 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2058 V_HDLC_TRP | V_IFF);
2059 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2060 HFC_wait_nodebug(hc);
2061 if (hc->ctype == HFC_TYPE_XHFC)
2062 HFC_outb(hc, A_CON_HDLC, 0xc0
2063 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2064 /* Enable FIFO, no interrupt */
2065 else
2066 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2067 V_HDLC_TRP | V_IFF);
2068 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2069 HFC_wait_nodebug(hc);
2070 }
2071 *txpending = 0;
2072 }
2073 return; /* no data */
2074 }
2075
2076 /* "fill fifo if empty" feature */
2077 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2078 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2079 if (debug & DEBUG_HFCMULTI_FILL)
2080 printk(KERN_DEBUG "%s: buffer empty, so we have "
2081 "underrun\n", __func__);
2082 /* fill buffer, to prevent future underrun */
2083 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2084 Zspace -= (poll >> 1);
2085 }
2086
2087 /* if audio data and connected slot */
2088 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2089 && slot_tx >= 0) {
2090 if (debug & DEBUG_HFCMULTI_MODE)
2091 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2092 "FIFO data: channel %d slot_tx %d\n",
2093 __func__, ch, slot_tx);
2094 /* disconnect slot */
2095 if (hc->ctype == HFC_TYPE_XHFC)
2096 HFC_outb(hc, A_CON_HDLC, 0x80
2097 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2098 /* Enable FIFO, no interrupt */
2099 else
2100 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2101 V_HDLC_TRP | V_IFF);
2102 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2103 HFC_wait_nodebug(hc);
2104 if (hc->ctype == HFC_TYPE_XHFC)
2105 HFC_outb(hc, A_CON_HDLC, 0x80
2106 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2107 /* Enable FIFO, no interrupt */
2108 else
2109 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2110 V_HDLC_TRP | V_IFF);
2111 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2112 HFC_wait_nodebug(hc);
2113 }
2114 *txpending = 1;
2115
2116 /* show activity */
2117 if (dch)
2118 hc->activity_tx |= 1 << hc->chan[ch].port;
2119
2120 /* fill fifo to what we have left */
2121 ii = len;
2122 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2123 temp = 1;
2124 else
2125 temp = 0;
2126 i = *idxp;
2127 d = (*sp)->data + i;
2128 if (ii - i > Zspace)
2129 ii = Zspace + i;
2130 if (debug & DEBUG_HFCMULTI_FIFO)
2131 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2132 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2133 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2134 temp ? "HDLC" : "TRANS");
2135
2136 /* Have to prep the audio data */
2137 hc->write_fifo(hc, d, ii - i);
2138 hc->chan[ch].Zfill += ii - i;
2139 *idxp = ii;
2140
2141 /* if not all data has been written */
2142 if (ii != len) {
2143 /* NOTE: fifo is started by the calling function */
2144 return;
2145 }
2146
2147 /* if all data has been written, terminate frame */
2148 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2149 /* increment f-counter */
2150 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2151 HFC_wait_nodebug(hc);
2152 }
2153
2154 /* send confirm, since get_net_bframe will not do it with trans */
2155 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2156 confirm_Bsend(bch);
2157
2158 /* check for next frame */
2159 dev_kfree_skb(*sp);
2160 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2161 len = (*sp)->len;
2162 goto next_frame;
2163 }
2164 if (dch && get_next_dframe(dch)) {
2165 len = (*sp)->len;
2166 goto next_frame;
2167 }
2168
2169 /*
2170 * now we have no more data, so in case of transparent,
2171 * we set the last byte in fifo to 'silence' in case we will get
2172 * no more data at all. this prevents sending an undefined value.
2173 */
2174 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2175 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2176 }
2177
2178
2179 /* NOTE: only called if E1 card is in active state */
2180 static void
2181 hfcmulti_rx(struct hfc_multi *hc, int ch)
2182 {
2183 int temp;
2184 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2185 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2186 int again = 0;
2187 struct bchannel *bch;
2188 struct dchannel *dch;
2189 struct sk_buff *skb, **sp = NULL;
2190 int maxlen;
2191
2192 bch = hc->chan[ch].bch;
2193 dch = hc->chan[ch].dch;
2194 if ((!dch) && (!bch))
2195 return;
2196 if (dch) {
2197 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2198 return;
2199 sp = &dch->rx_skb;
2200 maxlen = dch->maxlen;
2201 } else {
2202 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2203 return;
2204 sp = &bch->rx_skb;
2205 maxlen = bch->maxlen;
2206 }
2207 next_frame:
2208 /* on first AND before getting next valid frame, R_FIFO must be written
2209 to. */
2210 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2211 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2212 (hc->chan[ch].slot_rx < 0) &&
2213 (hc->chan[ch].slot_tx < 0))
2214 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2215 else
2216 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2217 HFC_wait_nodebug(hc);
2218
2219 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2220 if (hc->chan[ch].rx_off)
2221 return;
2222
2223 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2224 f1 = HFC_inb_nodebug(hc, A_F1);
2225 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2226 if (debug & DEBUG_HFCMULTI_FIFO)
2227 printk(KERN_DEBUG
2228 "%s(card %d): reread f1 because %d!=%d\n",
2229 __func__, hc->id + 1, temp, f1);
2230 f1 = temp; /* repeat until F1 is equal */
2231 }
2232 f2 = HFC_inb_nodebug(hc, A_F2);
2233 }
2234 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2235 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2236 if (debug & DEBUG_HFCMULTI_FIFO)
2237 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2238 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2239 z1 = temp; /* repeat until Z1 is equal */
2240 }
2241 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2242 Zsize = z1 - z2;
2243 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2244 /* complete hdlc frame */
2245 Zsize++;
2246 if (Zsize < 0)
2247 Zsize += hc->Zlen;
2248 /* if buffer is empty */
2249 if (Zsize <= 0)
2250 return;
2251
2252 if (*sp == NULL) {
2253 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2254 if (*sp == NULL) {
2255 printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2256 __func__);
2257 return;
2258 }
2259 }
2260 /* show activity */
2261 if (dch)
2262 hc->activity_rx |= 1 << hc->chan[ch].port;
2263
2264 /* empty fifo with what we have */
2265 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2266 if (debug & DEBUG_HFCMULTI_FIFO)
2267 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2268 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2269 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2270 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2271 f1, f2, Zsize + (*sp)->len, again);
2272 /* HDLC */
2273 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2274 if (debug & DEBUG_HFCMULTI_FIFO)
2275 printk(KERN_DEBUG
2276 "%s(card %d): hdlc-frame too large.\n",
2277 __func__, hc->id + 1);
2278 skb_trim(*sp, 0);
2279 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2280 HFC_wait_nodebug(hc);
2281 return;
2282 }
2283
2284 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2285
2286 if (f1 != f2) {
2287 /* increment Z2,F2-counter */
2288 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2289 HFC_wait_nodebug(hc);
2290 /* check size */
2291 if ((*sp)->len < 4) {
2292 if (debug & DEBUG_HFCMULTI_FIFO)
2293 printk(KERN_DEBUG
2294 "%s(card %d): Frame below minimum "
2295 "size\n", __func__, hc->id + 1);
2296 skb_trim(*sp, 0);
2297 goto next_frame;
2298 }
2299 /* there is at least one complete frame, check crc */
2300 if ((*sp)->data[(*sp)->len - 1]) {
2301 if (debug & DEBUG_HFCMULTI_CRC)
2302 printk(KERN_DEBUG
2303 "%s: CRC-error\n", __func__);
2304 skb_trim(*sp, 0);
2305 goto next_frame;
2306 }
2307 skb_trim(*sp, (*sp)->len - 3);
2308 if ((*sp)->len < MISDN_COPY_SIZE) {
2309 skb = *sp;
2310 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2311 if (*sp) {
2312 memcpy(skb_put(*sp, skb->len),
2313 skb->data, skb->len);
2314 skb_trim(skb, 0);
2315 } else {
2316 printk(KERN_DEBUG "%s: No mem\n",
2317 __func__);
2318 *sp = skb;
2319 skb = NULL;
2320 }
2321 } else {
2322 skb = NULL;
2323 }
2324 if (debug & DEBUG_HFCMULTI_FIFO) {
2325 printk(KERN_DEBUG "%s(card %d):",
2326 __func__, hc->id + 1);
2327 temp = 0;
2328 while (temp < (*sp)->len)
2329 printk(" %02x", (*sp)->data[temp++]);
2330 printk("\n");
2331 }
2332 if (dch)
2333 recv_Dchannel(dch);
2334 else
2335 recv_Bchannel(bch, MISDN_ID_ANY);
2336 *sp = skb;
2337 again++;
2338 goto next_frame;
2339 }
2340 /* there is an incomplete frame */
2341 } else {
2342 /* transparent */
2343 if (Zsize > skb_tailroom(*sp))
2344 Zsize = skb_tailroom(*sp);
2345 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2346 if (((*sp)->len) < MISDN_COPY_SIZE) {
2347 skb = *sp;
2348 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2349 if (*sp) {
2350 memcpy(skb_put(*sp, skb->len),
2351 skb->data, skb->len);
2352 skb_trim(skb, 0);
2353 } else {
2354 printk(KERN_DEBUG "%s: No mem\n", __func__);
2355 *sp = skb;
2356 skb = NULL;
2357 }
2358 } else {
2359 skb = NULL;
2360 }
2361 if (debug & DEBUG_HFCMULTI_FIFO)
2362 printk(KERN_DEBUG
2363 "%s(card %d): fifo(%d) reading %d bytes "
2364 "(z1=%04x, z2=%04x) TRANS\n",
2365 __func__, hc->id + 1, ch, Zsize, z1, z2);
2366 /* only bch is transparent */
2367 recv_Bchannel(bch, hc->chan[ch].Zfill);
2368 *sp = skb;
2369 }
2370 }
2371
2372
2373 /*
2374 * Interrupt handler
2375 */
2376 static void
2377 signal_state_up(struct dchannel *dch, int info, char *msg)
2378 {
2379 struct sk_buff *skb;
2380 int id, data = info;
2381
2382 if (debug & DEBUG_HFCMULTI_STATE)
2383 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2384
2385 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2386
2387 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2388 GFP_ATOMIC);
2389 if (!skb)
2390 return;
2391 recv_Dchannel_skb(dch, skb);
2392 }
2393
2394 static inline void
2395 handle_timer_irq(struct hfc_multi *hc)
2396 {
2397 int ch, temp;
2398 struct dchannel *dch;
2399 u_long flags;
2400
2401 /* process queued resync jobs */
2402 if (hc->e1_resync) {
2403 /* lock, so e1_resync gets not changed */
2404 spin_lock_irqsave(&HFClock, flags);
2405 if (hc->e1_resync & 1) {
2406 if (debug & DEBUG_HFCMULTI_PLXSD)
2407 printk(KERN_DEBUG "Enable SYNC_I\n");
2408 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2409 /* disable JATT, if RX_SYNC is set */
2410 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2411 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2412 }
2413 if (hc->e1_resync & 2) {
2414 if (debug & DEBUG_HFCMULTI_PLXSD)
2415 printk(KERN_DEBUG "Enable jatt PLL\n");
2416 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2417 }
2418 if (hc->e1_resync & 4) {
2419 if (debug & DEBUG_HFCMULTI_PLXSD)
2420 printk(KERN_DEBUG
2421 "Enable QUARTZ for HFC-E1\n");
2422 /* set jatt to quartz */
2423 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2424 | V_JATT_OFF);
2425 /* switch to JATT, in case it is not already */
2426 HFC_outb(hc, R_SYNC_OUT, 0);
2427 }
2428 hc->e1_resync = 0;
2429 spin_unlock_irqrestore(&HFClock, flags);
2430 }
2431
2432 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2433 for (ch = 0; ch <= 31; ch++) {
2434 if (hc->created[hc->chan[ch].port]) {
2435 hfcmulti_tx(hc, ch);
2436 /* fifo is started when switching to rx-fifo */
2437 hfcmulti_rx(hc, ch);
2438 if (hc->chan[ch].dch &&
2439 hc->chan[ch].nt_timer > -1) {
2440 dch = hc->chan[ch].dch;
2441 if (!(--hc->chan[ch].nt_timer)) {
2442 schedule_event(dch,
2443 FLG_PHCHANGE);
2444 if (debug &
2445 DEBUG_HFCMULTI_STATE)
2446 printk(KERN_DEBUG
2447 "%s: nt_timer at "
2448 "state %x\n",
2449 __func__,
2450 dch->state);
2451 }
2452 }
2453 }
2454 }
2455 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2456 dch = hc->chan[hc->dslot].dch;
2457 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2458 /* LOS */
2459 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2460 if (!temp && hc->chan[hc->dslot].los)
2461 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2462 "LOS detected");
2463 if (temp && !hc->chan[hc->dslot].los)
2464 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2465 "LOS gone");
2466 hc->chan[hc->dslot].los = temp;
2467 }
2468 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2469 /* AIS */
2470 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2471 if (!temp && hc->chan[hc->dslot].ais)
2472 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2473 "AIS detected");
2474 if (temp && !hc->chan[hc->dslot].ais)
2475 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2476 "AIS gone");
2477 hc->chan[hc->dslot].ais = temp;
2478 }
2479 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2480 /* SLIP */
2481 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2482 if (!temp && hc->chan[hc->dslot].slip_rx)
2483 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2484 " bit SLIP detected RX");
2485 hc->chan[hc->dslot].slip_rx = temp;
2486 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2487 if (!temp && hc->chan[hc->dslot].slip_tx)
2488 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2489 " bit SLIP detected TX");
2490 hc->chan[hc->dslot].slip_tx = temp;
2491 }
2492 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2493 /* RDI */
2494 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2495 if (!temp && hc->chan[hc->dslot].rdi)
2496 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2497 "RDI detected");
2498 if (temp && !hc->chan[hc->dslot].rdi)
2499 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2500 "RDI gone");
2501 hc->chan[hc->dslot].rdi = temp;
2502 }
2503 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2504 switch (hc->chan[hc->dslot].sync) {
2505 case 0:
2506 if ((temp & 0x60) == 0x60) {
2507 if (debug & DEBUG_HFCMULTI_SYNC)
2508 printk(KERN_DEBUG
2509 "%s: (id=%d) E1 now "
2510 "in clock sync\n",
2511 __func__, hc->id);
2512 HFC_outb(hc, R_RX_OFF,
2513 hc->chan[hc->dslot].jitter | V_RX_INIT);
2514 HFC_outb(hc, R_TX_OFF,
2515 hc->chan[hc->dslot].jitter | V_RX_INIT);
2516 hc->chan[hc->dslot].sync = 1;
2517 goto check_framesync;
2518 }
2519 break;
2520 case 1:
2521 if ((temp & 0x60) != 0x60) {
2522 if (debug & DEBUG_HFCMULTI_SYNC)
2523 printk(KERN_DEBUG
2524 "%s: (id=%d) E1 "
2525 "lost clock sync\n",
2526 __func__, hc->id);
2527 hc->chan[hc->dslot].sync = 0;
2528 break;
2529 }
2530 check_framesync:
2531 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2532 if (temp == 0x27) {
2533 if (debug & DEBUG_HFCMULTI_SYNC)
2534 printk(KERN_DEBUG
2535 "%s: (id=%d) E1 "
2536 "now in frame sync\n",
2537 __func__, hc->id);
2538 hc->chan[hc->dslot].sync = 2;
2539 }
2540 break;
2541 case 2:
2542 if ((temp & 0x60) != 0x60) {
2543 if (debug & DEBUG_HFCMULTI_SYNC)
2544 printk(KERN_DEBUG
2545 "%s: (id=%d) E1 lost "
2546 "clock & frame sync\n",
2547 __func__, hc->id);
2548 hc->chan[hc->dslot].sync = 0;
2549 break;
2550 }
2551 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2552 if (temp != 0x27) {
2553 if (debug & DEBUG_HFCMULTI_SYNC)
2554 printk(KERN_DEBUG
2555 "%s: (id=%d) E1 "
2556 "lost frame sync\n",
2557 __func__, hc->id);
2558 hc->chan[hc->dslot].sync = 1;
2559 }
2560 break;
2561 }
2562 }
2563
2564 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2565 hfcmulti_watchdog(hc);
2566
2567 if (hc->leds)
2568 hfcmulti_leds(hc);
2569 }
2570
2571 static void
2572 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2573 {
2574 struct dchannel *dch;
2575 int ch;
2576 int active;
2577 u_char st_status, temp;
2578
2579 /* state machine */
2580 for (ch = 0; ch <= 31; ch++) {
2581 if (hc->chan[ch].dch) {
2582 dch = hc->chan[ch].dch;
2583 if (r_irq_statech & 1) {
2584 HFC_outb_nodebug(hc, R_ST_SEL,
2585 hc->chan[ch].port);
2586 /* undocumented: delay after R_ST_SEL */
2587 udelay(1);
2588 /* undocumented: status changes during read */
2589 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2590 while (st_status != (temp =
2591 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2592 if (debug & DEBUG_HFCMULTI_STATE)
2593 printk(KERN_DEBUG "%s: reread "
2594 "STATE because %d!=%d\n",
2595 __func__, temp,
2596 st_status);
2597 st_status = temp; /* repeat */
2598 }
2599
2600 /* Speech Design TE-sync indication */
2601 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2602 dch->dev.D.protocol == ISDN_P_TE_S0) {
2603 if (st_status & V_FR_SYNC_ST)
2604 hc->syncronized |=
2605 (1 << hc->chan[ch].port);
2606 else
2607 hc->syncronized &=
2608 ~(1 << hc->chan[ch].port);
2609 }
2610 dch->state = st_status & 0x0f;
2611 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2612 active = 3;
2613 else
2614 active = 7;
2615 if (dch->state == active) {
2616 HFC_outb_nodebug(hc, R_FIFO,
2617 (ch << 1) | 1);
2618 HFC_wait_nodebug(hc);
2619 HFC_outb_nodebug(hc,
2620 R_INC_RES_FIFO, V_RES_F);
2621 HFC_wait_nodebug(hc);
2622 dch->tx_idx = 0;
2623 }
2624 schedule_event(dch, FLG_PHCHANGE);
2625 if (debug & DEBUG_HFCMULTI_STATE)
2626 printk(KERN_DEBUG
2627 "%s: S/T newstate %x port %d\n",
2628 __func__, dch->state,
2629 hc->chan[ch].port);
2630 }
2631 r_irq_statech >>= 1;
2632 }
2633 }
2634 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2635 plxsd_checksync(hc, 0);
2636 }
2637
2638 static void
2639 fifo_irq(struct hfc_multi *hc, int block)
2640 {
2641 int ch, j;
2642 struct dchannel *dch;
2643 struct bchannel *bch;
2644 u_char r_irq_fifo_bl;
2645
2646 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2647 j = 0;
2648 while (j < 8) {
2649 ch = (block << 2) + (j >> 1);
2650 dch = hc->chan[ch].dch;
2651 bch = hc->chan[ch].bch;
2652 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2653 j += 2;
2654 continue;
2655 }
2656 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2657 test_bit(FLG_ACTIVE, &dch->Flags)) {
2658 hfcmulti_tx(hc, ch);
2659 /* start fifo */
2660 HFC_outb_nodebug(hc, R_FIFO, 0);
2661 HFC_wait_nodebug(hc);
2662 }
2663 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2664 test_bit(FLG_ACTIVE, &bch->Flags)) {
2665 hfcmulti_tx(hc, ch);
2666 /* start fifo */
2667 HFC_outb_nodebug(hc, R_FIFO, 0);
2668 HFC_wait_nodebug(hc);
2669 }
2670 j++;
2671 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2672 test_bit(FLG_ACTIVE, &dch->Flags)) {
2673 hfcmulti_rx(hc, ch);
2674 }
2675 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2676 test_bit(FLG_ACTIVE, &bch->Flags)) {
2677 hfcmulti_rx(hc, ch);
2678 }
2679 j++;
2680 }
2681 }
2682
2683 #ifdef IRQ_DEBUG
2684 int irqsem;
2685 #endif
2686 static irqreturn_t
2687 hfcmulti_interrupt(int intno, void *dev_id)
2688 {
2689 #ifdef IRQCOUNT_DEBUG
2690 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2691 iq5 = 0, iq6 = 0, iqcnt = 0;
2692 #endif
2693 struct hfc_multi *hc = dev_id;
2694 struct dchannel *dch;
2695 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2696 int i;
2697 void __iomem *plx_acc;
2698 u_short wval;
2699 u_char e1_syncsta, temp;
2700 u_long flags;
2701
2702 if (!hc) {
2703 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2704 return IRQ_NONE;
2705 }
2706
2707 spin_lock(&hc->lock);
2708
2709 #ifdef IRQ_DEBUG
2710 if (irqsem)
2711 printk(KERN_ERR "irq for card %d during irq from "
2712 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2713 irqsem = hc->id + 1;
2714 #endif
2715 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2716 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2717 goto irq_notforus;
2718 #endif
2719 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2720 spin_lock_irqsave(&plx_lock, flags);
2721 plx_acc = hc->plx_membase + PLX_INTCSR;
2722 wval = readw(plx_acc);
2723 spin_unlock_irqrestore(&plx_lock, flags);
2724 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2725 goto irq_notforus;
2726 }
2727
2728 status = HFC_inb_nodebug(hc, R_STATUS);
2729 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2730 #ifdef IRQCOUNT_DEBUG
2731 if (r_irq_statech)
2732 iq1++;
2733 if (status & V_DTMF_STA)
2734 iq2++;
2735 if (status & V_LOST_STA)
2736 iq3++;
2737 if (status & V_EXT_IRQSTA)
2738 iq4++;
2739 if (status & V_MISC_IRQSTA)
2740 iq5++;
2741 if (status & V_FR_IRQSTA)
2742 iq6++;
2743 if (iqcnt++ > 5000) {
2744 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2745 iq1, iq2, iq3, iq4, iq5, iq6);
2746 iqcnt = 0;
2747 }
2748 #endif
2749
2750 if (!r_irq_statech &&
2751 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2752 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2753 /* irq is not for us */
2754 goto irq_notforus;
2755 }
2756 hc->irqcnt++;
2757 if (r_irq_statech) {
2758 if (hc->ctype != HFC_TYPE_E1)
2759 ph_state_irq(hc, r_irq_statech);
2760 }
2761 if (status & V_EXT_IRQSTA)
2762 ; /* external IRQ */
2763 if (status & V_LOST_STA) {
2764 /* LOST IRQ */
2765 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2766 }
2767 if (status & V_MISC_IRQSTA) {
2768 /* misc IRQ */
2769 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2770 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2771 if (r_irq_misc & V_STA_IRQ) {
2772 if (hc->ctype == HFC_TYPE_E1) {
2773 /* state machine */
2774 dch = hc->chan[hc->dslot].dch;
2775 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2776 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2777 && hc->e1_getclock) {
2778 if (e1_syncsta & V_FR_SYNC_E1)
2779 hc->syncronized = 1;
2780 else
2781 hc->syncronized = 0;
2782 }
2783 /* undocumented: status changes during read */
2784 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2785 while (dch->state != (temp =
2786 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2787 if (debug & DEBUG_HFCMULTI_STATE)
2788 printk(KERN_DEBUG "%s: reread "
2789 "STATE because %d!=%d\n",
2790 __func__, temp,
2791 dch->state);
2792 dch->state = temp; /* repeat */
2793 }
2794 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2795 & 0x7;
2796 schedule_event(dch, FLG_PHCHANGE);
2797 if (debug & DEBUG_HFCMULTI_STATE)
2798 printk(KERN_DEBUG
2799 "%s: E1 (id=%d) newstate %x\n",
2800 __func__, hc->id, dch->state);
2801 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2802 plxsd_checksync(hc, 0);
2803 }
2804 }
2805 if (r_irq_misc & V_TI_IRQ) {
2806 if (hc->iclock_on)
2807 mISDN_clock_update(hc->iclock, poll, NULL);
2808 handle_timer_irq(hc);
2809 }
2810
2811 if (r_irq_misc & V_DTMF_IRQ)
2812 hfcmulti_dtmf(hc);
2813
2814 if (r_irq_misc & V_IRQ_PROC) {
2815 static int irq_proc_cnt;
2816 if (!irq_proc_cnt++)
2817 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2818 " this should not happen\n", __func__);
2819 }
2820
2821 }
2822 if (status & V_FR_IRQSTA) {
2823 /* FIFO IRQ */
2824 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2825 for (i = 0; i < 8; i++) {
2826 if (r_irq_oview & (1 << i))
2827 fifo_irq(hc, i);
2828 }
2829 }
2830
2831 #ifdef IRQ_DEBUG
2832 irqsem = 0;
2833 #endif
2834 spin_unlock(&hc->lock);
2835 return IRQ_HANDLED;
2836
2837 irq_notforus:
2838 #ifdef IRQ_DEBUG
2839 irqsem = 0;
2840 #endif
2841 spin_unlock(&hc->lock);
2842 return IRQ_NONE;
2843 }
2844
2845
2846 /*
2847 * timer callback for D-chan busy resolution. Currently no function
2848 */
2849
2850 static void
2851 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2852 {
2853 }
2854
2855
2856 /*
2857 * activate/deactivate hardware for selected channels and mode
2858 *
2859 * configure B-channel with the given protocol
2860 * ch eqals to the HFC-channel (0-31)
2861 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2862 * for S/T, 1-31 for E1)
2863 * the hdlc interrupts will be set/unset
2864 */
2865 static int
2866 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2867 int bank_tx, int slot_rx, int bank_rx)
2868 {
2869 int flow_tx = 0, flow_rx = 0, routing = 0;
2870 int oslot_tx, oslot_rx;
2871 int conf;
2872
2873 if (ch < 0 || ch > 31)
2874 return -EINVAL;
2875 oslot_tx = hc->chan[ch].slot_tx;
2876 oslot_rx = hc->chan[ch].slot_rx;
2877 conf = hc->chan[ch].conf;
2878
2879 if (debug & DEBUG_HFCMULTI_MODE)
2880 printk(KERN_DEBUG
2881 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2882 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2883 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2884 bank_tx, oslot_rx, slot_rx, bank_rx);
2885
2886 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2887 /* remove from slot */
2888 if (debug & DEBUG_HFCMULTI_MODE)
2889 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2890 __func__, oslot_tx);
2891 if (hc->slot_owner[oslot_tx << 1] == ch) {
2892 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2893 HFC_outb(hc, A_SL_CFG, 0);
2894 if (hc->ctype != HFC_TYPE_XHFC)
2895 HFC_outb(hc, A_CONF, 0);
2896 hc->slot_owner[oslot_tx << 1] = -1;
2897 } else {
2898 if (debug & DEBUG_HFCMULTI_MODE)
2899 printk(KERN_DEBUG
2900 "%s: we are not owner of this tx slot "
2901 "anymore, channel %d is.\n",
2902 __func__, hc->slot_owner[oslot_tx << 1]);
2903 }
2904 }
2905
2906 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2907 /* remove from slot */
2908 if (debug & DEBUG_HFCMULTI_MODE)
2909 printk(KERN_DEBUG
2910 "%s: remove from slot %d (RX)\n",
2911 __func__, oslot_rx);
2912 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2913 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2914 HFC_outb(hc, A_SL_CFG, 0);
2915 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2916 } else {
2917 if (debug & DEBUG_HFCMULTI_MODE)
2918 printk(KERN_DEBUG
2919 "%s: we are not owner of this rx slot "
2920 "anymore, channel %d is.\n",
2921 __func__,
2922 hc->slot_owner[(oslot_rx << 1) | 1]);
2923 }
2924 }
2925
2926 if (slot_tx < 0) {
2927 flow_tx = 0x80; /* FIFO->ST */
2928 /* disable pcm slot */
2929 hc->chan[ch].slot_tx = -1;
2930 hc->chan[ch].bank_tx = 0;
2931 } else {
2932 /* set pcm slot */
2933 if (hc->chan[ch].txpending)
2934 flow_tx = 0x80; /* FIFO->ST */
2935 else
2936 flow_tx = 0xc0; /* PCM->ST */
2937 /* put on slot */
2938 routing = bank_tx ? 0xc0 : 0x80;
2939 if (conf >= 0 || bank_tx > 1)
2940 routing = 0x40; /* loop */
2941 if (debug & DEBUG_HFCMULTI_MODE)
2942 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2943 " %d flow %02x routing %02x conf %d (TX)\n",
2944 __func__, ch, slot_tx, bank_tx,
2945 flow_tx, routing, conf);
2946 HFC_outb(hc, R_SLOT, slot_tx << 1);
2947 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2948 if (hc->ctype != HFC_TYPE_XHFC)
2949 HFC_outb(hc, A_CONF,
2950 (conf < 0) ? 0 : (conf | V_CONF_SL));
2951 hc->slot_owner[slot_tx << 1] = ch;
2952 hc->chan[ch].slot_tx = slot_tx;
2953 hc->chan[ch].bank_tx = bank_tx;
2954 }
2955 if (slot_rx < 0) {
2956 /* disable pcm slot */
2957 flow_rx = 0x80; /* ST->FIFO */
2958 hc->chan[ch].slot_rx = -1;
2959 hc->chan[ch].bank_rx = 0;
2960 } else {
2961 /* set pcm slot */
2962 if (hc->chan[ch].txpending)
2963 flow_rx = 0x80; /* ST->FIFO */
2964 else
2965 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2966 /* put on slot */
2967 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2968 if (conf >= 0 || bank_rx > 1)
2969 routing = 0x40; /* loop */
2970 if (debug & DEBUG_HFCMULTI_MODE)
2971 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2972 " %d flow %02x routing %02x conf %d (RX)\n",
2973 __func__, ch, slot_rx, bank_rx,
2974 flow_rx, routing, conf);
2975 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2976 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2977 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2978 hc->chan[ch].slot_rx = slot_rx;
2979 hc->chan[ch].bank_rx = bank_rx;
2980 }
2981
2982 switch (protocol) {
2983 case (ISDN_P_NONE):
2984 /* disable TX fifo */
2985 HFC_outb(hc, R_FIFO, ch << 1);
2986 HFC_wait(hc);
2987 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2988 HFC_outb(hc, A_SUBCH_CFG, 0);
2989 HFC_outb(hc, A_IRQ_MSK, 0);
2990 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2991 HFC_wait(hc);
2992 /* disable RX fifo */
2993 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2994 HFC_wait(hc);
2995 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2996 HFC_outb(hc, A_SUBCH_CFG, 0);
2997 HFC_outb(hc, A_IRQ_MSK, 0);
2998 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2999 HFC_wait(hc);
3000 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
3001 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
3002 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
3003 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3004 /* undocumented: delay after R_ST_SEL */
3005 udelay(1);
3006 HFC_outb(hc, A_ST_CTRL0,
3007 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3008 }
3009 if (hc->chan[ch].bch) {
3010 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3011 test_and_clear_bit(FLG_TRANSPARENT,
3012 &hc->chan[ch].bch->Flags);
3013 }
3014 break;
3015 case (ISDN_P_B_RAW): /* B-channel */
3016
3017 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
3018 (hc->chan[ch].slot_rx < 0) &&
3019 (hc->chan[ch].slot_tx < 0)) {
3020
3021 printk(KERN_DEBUG
3022 "Setting B-channel %d to echo cancelable "
3023 "state on PCM slot %d\n", ch,
3024 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3025 printk(KERN_DEBUG
3026 "Enabling pass through for channel\n");
3027 vpm_out(hc, ch, ((ch / 4) * 8) +
3028 ((ch % 4) * 4) + 1, 0x01);
3029 /* rx path */
3030 /* S/T -> PCM */
3031 HFC_outb(hc, R_FIFO, (ch << 1));
3032 HFC_wait(hc);
3033 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3034 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3035 ((ch % 4) * 4) + 1) << 1);
3036 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3037
3038 /* PCM -> FIFO */
3039 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3040 HFC_wait(hc);
3041 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3042 HFC_outb(hc, A_SUBCH_CFG, 0);
3043 HFC_outb(hc, A_IRQ_MSK, 0);
3044 if (hc->chan[ch].protocol != protocol) {
3045 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3046 HFC_wait(hc);
3047 }
3048 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3049 ((ch % 4) * 4) + 1) << 1) | 1);
3050 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3051
3052 /* tx path */
3053 /* PCM -> S/T */
3054 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3055 HFC_wait(hc);
3056 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3057 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3058 ((ch % 4) * 4)) << 1) | 1);
3059 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3060
3061 /* FIFO -> PCM */
3062 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3063 HFC_wait(hc);
3064 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3065 HFC_outb(hc, A_SUBCH_CFG, 0);
3066 HFC_outb(hc, A_IRQ_MSK, 0);
3067 if (hc->chan[ch].protocol != protocol) {
3068 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3069 HFC_wait(hc);
3070 }
3071 /* tx silence */
3072 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3073 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3074 ((ch % 4) * 4)) << 1);
3075 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3076 } else {
3077 /* enable TX fifo */
3078 HFC_outb(hc, R_FIFO, ch << 1);
3079 HFC_wait(hc);
3080 if (hc->ctype == HFC_TYPE_XHFC)
3081 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3082 V_HDLC_TRP | V_IFF);
3083 /* Enable FIFO, no interrupt */
3084 else
3085 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3086 V_HDLC_TRP | V_IFF);
3087 HFC_outb(hc, A_SUBCH_CFG, 0);
3088 HFC_outb(hc, A_IRQ_MSK, 0);
3089 if (hc->chan[ch].protocol != protocol) {
3090 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3091 HFC_wait(hc);
3092 }
3093 /* tx silence */
3094 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3095 /* enable RX fifo */
3096 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3097 HFC_wait(hc);
3098 if (hc->ctype == HFC_TYPE_XHFC)
3099 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3100 V_HDLC_TRP);
3101 /* Enable FIFO, no interrupt*/
3102 else
3103 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3104 V_HDLC_TRP);
3105 HFC_outb(hc, A_SUBCH_CFG, 0);
3106 HFC_outb(hc, A_IRQ_MSK, 0);
3107 if (hc->chan[ch].protocol != protocol) {
3108 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3109 HFC_wait(hc);
3110 }
3111 }
3112 if (hc->ctype != HFC_TYPE_E1) {
3113 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3114 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3115 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3116 /* undocumented: delay after R_ST_SEL */
3117 udelay(1);
3118 HFC_outb(hc, A_ST_CTRL0,
3119 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3120 }
3121 if (hc->chan[ch].bch)
3122 test_and_set_bit(FLG_TRANSPARENT,
3123 &hc->chan[ch].bch->Flags);
3124 break;
3125 case (ISDN_P_B_HDLC): /* B-channel */
3126 case (ISDN_P_TE_S0): /* D-channel */
3127 case (ISDN_P_NT_S0):
3128 case (ISDN_P_TE_E1):
3129 case (ISDN_P_NT_E1):
3130 /* enable TX fifo */
3131 HFC_outb(hc, R_FIFO, ch << 1);
3132 HFC_wait(hc);
3133 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3134 /* E1 or B-channel */
3135 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3136 HFC_outb(hc, A_SUBCH_CFG, 0);
3137 } else {
3138 /* D-Channel without HDLC fill flags */
3139 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3140 HFC_outb(hc, A_SUBCH_CFG, 2);
3141 }
3142 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3143 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3144 HFC_wait(hc);
3145 /* enable RX fifo */
3146 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3147 HFC_wait(hc);
3148 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3149 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3150 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3151 else
3152 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3153 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3154 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3155 HFC_wait(hc);
3156 if (hc->chan[ch].bch) {
3157 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3158 if (hc->ctype != HFC_TYPE_E1) {
3159 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3160 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3161 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3162 /* undocumented: delay after R_ST_SEL */
3163 udelay(1);
3164 HFC_outb(hc, A_ST_CTRL0,
3165 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3166 }
3167 }
3168 break;
3169 default:
3170 printk(KERN_DEBUG "%s: protocol not known %x\n",
3171 __func__, protocol);
3172 hc->chan[ch].protocol = ISDN_P_NONE;
3173 return -ENOPROTOOPT;
3174 }
3175 hc->chan[ch].protocol = protocol;
3176 return 0;
3177 }
3178
3179
3180 /*
3181 * connect/disconnect PCM
3182 */
3183
3184 static void
3185 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3186 int slot_rx, int bank_rx)
3187 {
3188 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3189 /* disable PCM */
3190 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3191 return;
3192 }
3193
3194 /* enable pcm */
3195 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3196 slot_rx, bank_rx);
3197 }
3198
3199 /*
3200 * set/disable conference
3201 */
3202
3203 static void
3204 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3205 {
3206 if (num >= 0 && num <= 7)
3207 hc->chan[ch].conf = num;
3208 else
3209 hc->chan[ch].conf = -1;
3210 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3211 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3212 hc->chan[ch].bank_rx);
3213 }
3214
3215
3216 /*
3217 * set/disable sample loop
3218 */
3219
3220 /* NOTE: this function is experimental and therefore disabled */
3221
3222 /*
3223 * Layer 1 callback function
3224 */
3225 static int
3226 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3227 {
3228 struct hfc_multi *hc = dch->hw;
3229 u_long flags;
3230
3231 switch (cmd) {
3232 case INFO3_P8:
3233 case INFO3_P10:
3234 break;
3235 case HW_RESET_REQ:
3236 /* start activation */
3237 spin_lock_irqsave(&hc->lock, flags);
3238 if (hc->ctype == HFC_TYPE_E1) {
3239 if (debug & DEBUG_HFCMULTI_MSG)
3240 printk(KERN_DEBUG
3241 "%s: HW_RESET_REQ no BRI\n",
3242 __func__);
3243 } else {
3244 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3245 /* undocumented: delay after R_ST_SEL */
3246 udelay(1);
3247 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3248 udelay(6); /* wait at least 5,21us */
3249 HFC_outb(hc, A_ST_WR_STATE, 3);
3250 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3251 /* activate */
3252 }
3253 spin_unlock_irqrestore(&hc->lock, flags);
3254 l1_event(dch->l1, HW_POWERUP_IND);
3255 break;
3256 case HW_DEACT_REQ:
3257 /* start deactivation */
3258 spin_lock_irqsave(&hc->lock, flags);
3259 if (hc->ctype == HFC_TYPE_E1) {
3260 if (debug & DEBUG_HFCMULTI_MSG)
3261 printk(KERN_DEBUG
3262 "%s: HW_DEACT_REQ no BRI\n",
3263 __func__);
3264 } else {
3265 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3266 /* undocumented: delay after R_ST_SEL */
3267 udelay(1);
3268 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3269 /* deactivate */
3270 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3271 hc->syncronized &=
3272 ~(1 << hc->chan[dch->slot].port);
3273 plxsd_checksync(hc, 0);
3274 }
3275 }
3276 skb_queue_purge(&dch->squeue);
3277 if (dch->tx_skb) {
3278 dev_kfree_skb(dch->tx_skb);
3279 dch->tx_skb = NULL;
3280 }
3281 dch->tx_idx = 0;
3282 if (dch->rx_skb) {
3283 dev_kfree_skb(dch->rx_skb);
3284 dch->rx_skb = NULL;
3285 }
3286 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3287 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3288 del_timer(&dch->timer);
3289 spin_unlock_irqrestore(&hc->lock, flags);
3290 break;
3291 case HW_POWERUP_REQ:
3292 spin_lock_irqsave(&hc->lock, flags);
3293 if (hc->ctype == HFC_TYPE_E1) {
3294 if (debug & DEBUG_HFCMULTI_MSG)
3295 printk(KERN_DEBUG
3296 "%s: HW_POWERUP_REQ no BRI\n",
3297 __func__);
3298 } else {
3299 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3300 /* undocumented: delay after R_ST_SEL */
3301 udelay(1);
3302 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3303 udelay(6); /* wait at least 5,21us */
3304 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3305 }
3306 spin_unlock_irqrestore(&hc->lock, flags);
3307 break;
3308 case PH_ACTIVATE_IND:
3309 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3310 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3311 GFP_ATOMIC);
3312 break;
3313 case PH_DEACTIVATE_IND:
3314 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3315 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3316 GFP_ATOMIC);
3317 break;
3318 default:
3319 if (dch->debug & DEBUG_HW)
3320 printk(KERN_DEBUG "%s: unknown command %x\n",
3321 __func__, cmd);
3322 return -1;
3323 }
3324 return 0;
3325 }
3326
3327 /*
3328 * Layer2 -> Layer 1 Transfer
3329 */
3330
3331 static int
3332 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3333 {
3334 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3335 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3336 struct hfc_multi *hc = dch->hw;
3337 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3338 int ret = -EINVAL;
3339 unsigned int id;
3340 u_long flags;
3341
3342 switch (hh->prim) {
3343 case PH_DATA_REQ:
3344 if (skb->len < 1)
3345 break;
3346 spin_lock_irqsave(&hc->lock, flags);
3347 ret = dchannel_senddata(dch, skb);
3348 if (ret > 0) { /* direct TX */
3349 id = hh->id; /* skb can be freed */
3350 hfcmulti_tx(hc, dch->slot);
3351 ret = 0;
3352 /* start fifo */
3353 HFC_outb(hc, R_FIFO, 0);
3354 HFC_wait(hc);
3355 spin_unlock_irqrestore(&hc->lock, flags);
3356 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3357 } else
3358 spin_unlock_irqrestore(&hc->lock, flags);
3359 return ret;
3360 case PH_ACTIVATE_REQ:
3361 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3362 spin_lock_irqsave(&hc->lock, flags);
3363 ret = 0;
3364 if (debug & DEBUG_HFCMULTI_MSG)
3365 printk(KERN_DEBUG
3366 "%s: PH_ACTIVATE port %d (0..%d)\n",
3367 __func__, hc->chan[dch->slot].port,
3368 hc->ports - 1);
3369 /* start activation */
3370 if (hc->ctype == HFC_TYPE_E1) {
3371 ph_state_change(dch);
3372 if (debug & DEBUG_HFCMULTI_STATE)
3373 printk(KERN_DEBUG
3374 "%s: E1 report state %x \n",
3375 __func__, dch->state);
3376 } else {
3377 HFC_outb(hc, R_ST_SEL,
3378 hc->chan[dch->slot].port);
3379 /* undocumented: delay after R_ST_SEL */
3380 udelay(1);
3381 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3382 /* G1 */
3383 udelay(6); /* wait at least 5,21us */
3384 HFC_outb(hc, A_ST_WR_STATE, 1);
3385 HFC_outb(hc, A_ST_WR_STATE, 1 |
3386 (V_ST_ACT * 3)); /* activate */
3387 dch->state = 1;
3388 }
3389 spin_unlock_irqrestore(&hc->lock, flags);
3390 } else
3391 ret = l1_event(dch->l1, hh->prim);
3392 break;
3393 case PH_DEACTIVATE_REQ:
3394 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3395 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3396 spin_lock_irqsave(&hc->lock, flags);
3397 if (debug & DEBUG_HFCMULTI_MSG)
3398 printk(KERN_DEBUG
3399 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3400 __func__, hc->chan[dch->slot].port,
3401 hc->ports - 1);
3402 /* start deactivation */
3403 if (hc->ctype == HFC_TYPE_E1) {
3404 if (debug & DEBUG_HFCMULTI_MSG)
3405 printk(KERN_DEBUG
3406 "%s: PH_DEACTIVATE no BRI\n",
3407 __func__);
3408 } else {
3409 HFC_outb(hc, R_ST_SEL,
3410 hc->chan[dch->slot].port);
3411 /* undocumented: delay after R_ST_SEL */
3412 udelay(1);
3413 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3414 /* deactivate */
3415 dch->state = 1;
3416 }
3417 skb_queue_purge(&dch->squeue);
3418 if (dch->tx_skb) {
3419 dev_kfree_skb(dch->tx_skb);
3420 dch->tx_skb = NULL;
3421 }
3422 dch->tx_idx = 0;
3423 if (dch->rx_skb) {
3424 dev_kfree_skb(dch->rx_skb);
3425 dch->rx_skb = NULL;
3426 }
3427 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3428 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3429 del_timer(&dch->timer);
3430 #ifdef FIXME
3431 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3432 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3433 #endif
3434 ret = 0;
3435 spin_unlock_irqrestore(&hc->lock, flags);
3436 } else
3437 ret = l1_event(dch->l1, hh->prim);
3438 break;
3439 }
3440 if (!ret)
3441 dev_kfree_skb(skb);
3442 return ret;
3443 }
3444
3445 static void
3446 deactivate_bchannel(struct bchannel *bch)
3447 {
3448 struct hfc_multi *hc = bch->hw;
3449 u_long flags;
3450
3451 spin_lock_irqsave(&hc->lock, flags);
3452 mISDN_clear_bchannel(bch);
3453 hc->chan[bch->slot].coeff_count = 0;
3454 hc->chan[bch->slot].rx_off = 0;
3455 hc->chan[bch->slot].conf = -1;
3456 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3457 spin_unlock_irqrestore(&hc->lock, flags);
3458 }
3459
3460 static int
3461 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3462 {
3463 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3464 struct hfc_multi *hc = bch->hw;
3465 int ret = -EINVAL;
3466 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3467 unsigned int id;
3468 u_long flags;
3469
3470 switch (hh->prim) {
3471 case PH_DATA_REQ:
3472 if (!skb->len)
3473 break;
3474 spin_lock_irqsave(&hc->lock, flags);
3475 ret = bchannel_senddata(bch, skb);
3476 if (ret > 0) { /* direct TX */
3477 id = hh->id; /* skb can be freed */
3478 hfcmulti_tx(hc, bch->slot);
3479 ret = 0;
3480 /* start fifo */
3481 HFC_outb_nodebug(hc, R_FIFO, 0);
3482 HFC_wait_nodebug(hc);
3483 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3484 spin_unlock_irqrestore(&hc->lock, flags);
3485 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3486 } else
3487 spin_unlock_irqrestore(&hc->lock, flags);
3488 } else
3489 spin_unlock_irqrestore(&hc->lock, flags);
3490 return ret;
3491 case PH_ACTIVATE_REQ:
3492 if (debug & DEBUG_HFCMULTI_MSG)
3493 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3494 __func__, bch->slot);
3495 spin_lock_irqsave(&hc->lock, flags);
3496 /* activate B-channel if not already activated */
3497 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3498 hc->chan[bch->slot].txpending = 0;
3499 ret = mode_hfcmulti(hc, bch->slot,
3500 ch->protocol,
3501 hc->chan[bch->slot].slot_tx,
3502 hc->chan[bch->slot].bank_tx,
3503 hc->chan[bch->slot].slot_rx,
3504 hc->chan[bch->slot].bank_rx);
3505 if (!ret) {
3506 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3507 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3508 /* start decoder */
3509 hc->dtmf = 1;
3510 if (debug & DEBUG_HFCMULTI_DTMF)
3511 printk(KERN_DEBUG
3512 "%s: start dtmf decoder\n",
3513 __func__);
3514 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3515 V_RST_DTMF);
3516 }
3517 }
3518 } else
3519 ret = 0;
3520 spin_unlock_irqrestore(&hc->lock, flags);
3521 if (!ret)
3522 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3523 GFP_KERNEL);
3524 break;
3525 case PH_CONTROL_REQ:
3526 spin_lock_irqsave(&hc->lock, flags);
3527 switch (hh->id) {
3528 case HFC_SPL_LOOP_ON: /* set sample loop */
3529 if (debug & DEBUG_HFCMULTI_MSG)
3530 printk(KERN_DEBUG
3531 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3532 __func__, skb->len);
3533 ret = 0;
3534 break;
3535 case HFC_SPL_LOOP_OFF: /* set silence */
3536 if (debug & DEBUG_HFCMULTI_MSG)
3537 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3538 __func__);
3539 ret = 0;
3540 break;
3541 default:
3542 printk(KERN_ERR
3543 "%s: unknown PH_CONTROL_REQ info %x\n",
3544 __func__, hh->id);
3545 ret = -EINVAL;
3546 }
3547 spin_unlock_irqrestore(&hc->lock, flags);
3548 break;
3549 case PH_DEACTIVATE_REQ:
3550 deactivate_bchannel(bch); /* locked there */
3551 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3552 GFP_KERNEL);
3553 ret = 0;
3554 break;
3555 }
3556 if (!ret)
3557 dev_kfree_skb(skb);
3558 return ret;
3559 }
3560
3561 /*
3562 * bchannel control function
3563 */
3564 static int
3565 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3566 {
3567 int ret = 0;
3568 struct dsp_features *features =
3569 (struct dsp_features *)(*((u_long *)&cq->p1));
3570 struct hfc_multi *hc = bch->hw;
3571 int slot_tx;
3572 int bank_tx;
3573 int slot_rx;
3574 int bank_rx;
3575 int num;
3576
3577 switch (cq->op) {
3578 case MISDN_CTRL_GETOP:
3579 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3580 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3581 break;
3582 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3583 hc->chan[bch->slot].rx_off = !!cq->p1;
3584 if (!hc->chan[bch->slot].rx_off) {
3585 /* reset fifo on rx on */
3586 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3587 HFC_wait_nodebug(hc);
3588 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3589 HFC_wait_nodebug(hc);
3590 }
3591 if (debug & DEBUG_HFCMULTI_MSG)
3592 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3593 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3594 break;
3595 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3596 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3597 if (debug & DEBUG_HFCMULTI_MSG)
3598 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3599 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3600 break;
3601 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3602 if (debug & DEBUG_HFCMULTI_MSG)
3603 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3604 __func__);
3605 /* create confirm */
3606 features->hfc_id = hc->id;
3607 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3608 features->hfc_dtmf = 1;
3609 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3610 features->hfc_conf = 1;
3611 features->hfc_loops = 0;
3612 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3613 features->hfc_echocanhw = 1;
3614 } else {
3615 features->pcm_id = hc->pcm;
3616 features->pcm_slots = hc->slots;
3617 features->pcm_banks = 2;
3618 }
3619 break;
3620 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3621 slot_tx = cq->p1 & 0xff;
3622 bank_tx = cq->p1 >> 8;
3623 slot_rx = cq->p2 & 0xff;
3624 bank_rx = cq->p2 >> 8;
3625 if (debug & DEBUG_HFCMULTI_MSG)
3626 printk(KERN_DEBUG
3627 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3628 "slot %d bank %d (RX)\n",
3629 __func__, slot_tx, bank_tx,
3630 slot_rx, bank_rx);
3631 if (slot_tx < hc->slots && bank_tx <= 2 &&
3632 slot_rx < hc->slots && bank_rx <= 2)
3633 hfcmulti_pcm(hc, bch->slot,
3634 slot_tx, bank_tx, slot_rx, bank_rx);
3635 else {
3636 printk(KERN_WARNING
3637 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3638 "slot %d bank %d (RX) out of range\n",
3639 __func__, slot_tx, bank_tx,
3640 slot_rx, bank_rx);
3641 ret = -EINVAL;
3642 }
3643 break;
3644 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3645 if (debug & DEBUG_HFCMULTI_MSG)
3646 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3647 __func__);
3648 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3649 break;
3650 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3651 num = cq->p1 & 0xff;
3652 if (debug & DEBUG_HFCMULTI_MSG)
3653 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3654 __func__, num);
3655 if (num <= 7)
3656 hfcmulti_conf(hc, bch->slot, num);
3657 else {
3658 printk(KERN_WARNING
3659 "%s: HW_CONF_JOIN conf %d out of range\n",
3660 __func__, num);
3661 ret = -EINVAL;
3662 }
3663 break;
3664 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3665 if (debug & DEBUG_HFCMULTI_MSG)
3666 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3667 hfcmulti_conf(hc, bch->slot, -1);
3668 break;
3669 case MISDN_CTRL_HFC_ECHOCAN_ON:
3670 if (debug & DEBUG_HFCMULTI_MSG)
3671 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3672 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3673 vpm_echocan_on(hc, bch->slot, cq->p1);
3674 else
3675 ret = -EINVAL;
3676 break;
3677
3678 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3679 if (debug & DEBUG_HFCMULTI_MSG)
3680 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3681 __func__);
3682 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3683 vpm_echocan_off(hc, bch->slot);
3684 else
3685 ret = -EINVAL;
3686 break;
3687 default:
3688 printk(KERN_WARNING "%s: unknown Op %x\n",
3689 __func__, cq->op);
3690 ret = -EINVAL;
3691 break;
3692 }
3693 return ret;
3694 }
3695
3696 static int
3697 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3698 {
3699 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3700 struct hfc_multi *hc = bch->hw;
3701 int err = -EINVAL;
3702 u_long flags;
3703
3704 if (bch->debug & DEBUG_HW)
3705 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3706 __func__, cmd, arg);
3707 switch (cmd) {
3708 case CLOSE_CHANNEL:
3709 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3710 if (test_bit(FLG_ACTIVE, &bch->Flags))
3711 deactivate_bchannel(bch); /* locked there */
3712 ch->protocol = ISDN_P_NONE;
3713 ch->peer = NULL;
3714 module_put(THIS_MODULE);
3715 err = 0;
3716 break;
3717 case CONTROL_CHANNEL:
3718 spin_lock_irqsave(&hc->lock, flags);
3719 err = channel_bctrl(bch, arg);
3720 spin_unlock_irqrestore(&hc->lock, flags);
3721 break;
3722 default:
3723 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3724 __func__, cmd);
3725 }
3726 return err;
3727 }
3728
3729 /*
3730 * handle D-channel events
3731 *
3732 * handle state change event
3733 */
3734 static void
3735 ph_state_change(struct dchannel *dch)
3736 {
3737 struct hfc_multi *hc;
3738 int ch, i;
3739
3740 if (!dch) {
3741 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3742 return;
3743 }
3744 hc = dch->hw;
3745 ch = dch->slot;
3746
3747 if (hc->ctype == HFC_TYPE_E1) {
3748 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3749 if (debug & DEBUG_HFCMULTI_STATE)
3750 printk(KERN_DEBUG
3751 "%s: E1 TE (id=%d) newstate %x\n",
3752 __func__, hc->id, dch->state);
3753 } else {
3754 if (debug & DEBUG_HFCMULTI_STATE)
3755 printk(KERN_DEBUG
3756 "%s: E1 NT (id=%d) newstate %x\n",
3757 __func__, hc->id, dch->state);
3758 }
3759 switch (dch->state) {
3760 case (1):
3761 if (hc->e1_state != 1) {
3762 for (i = 1; i <= 31; i++) {
3763 /* reset fifos on e1 activation */
3764 HFC_outb_nodebug(hc, R_FIFO,
3765 (i << 1) | 1);
3766 HFC_wait_nodebug(hc);
3767 HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3768 V_RES_F);
3769 HFC_wait_nodebug(hc);
3770 }
3771 }
3772 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3773 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3774 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3775 break;
3776
3777 default:
3778 if (hc->e1_state != 1)
3779 return;
3780 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3781 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3782 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3783 }
3784 hc->e1_state = dch->state;
3785 } else {
3786 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3787 if (debug & DEBUG_HFCMULTI_STATE)
3788 printk(KERN_DEBUG
3789 "%s: S/T TE newstate %x\n",
3790 __func__, dch->state);
3791 switch (dch->state) {
3792 case (0):
3793 l1_event(dch->l1, HW_RESET_IND);
3794 break;
3795 case (3):
3796 l1_event(dch->l1, HW_DEACT_IND);
3797 break;
3798 case (5):
3799 case (8):
3800 l1_event(dch->l1, ANYSIGNAL);
3801 break;
3802 case (6):
3803 l1_event(dch->l1, INFO2);
3804 break;
3805 case (7):
3806 l1_event(dch->l1, INFO4_P8);
3807 break;
3808 }
3809 } else {
3810 if (debug & DEBUG_HFCMULTI_STATE)
3811 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3812 __func__, dch->state);
3813 switch (dch->state) {
3814 case (2):
3815 if (hc->chan[ch].nt_timer == 0) {
3816 hc->chan[ch].nt_timer = -1;
3817 HFC_outb(hc, R_ST_SEL,
3818 hc->chan[ch].port);
3819 /* undocumented: delay after R_ST_SEL */
3820 udelay(1);
3821 HFC_outb(hc, A_ST_WR_STATE, 4 |
3822 V_ST_LD_STA); /* G4 */
3823 udelay(6); /* wait at least 5,21us */
3824 HFC_outb(hc, A_ST_WR_STATE, 4);
3825 dch->state = 4;
3826 } else {
3827 /* one extra count for the next event */
3828 hc->chan[ch].nt_timer =
3829 nt_t1_count[poll_timer] + 1;
3830 HFC_outb(hc, R_ST_SEL,
3831 hc->chan[ch].port);
3832 /* undocumented: delay after R_ST_SEL */
3833 udelay(1);
3834 /* allow G2 -> G3 transition */
3835 HFC_outb(hc, A_ST_WR_STATE, 2 |
3836 V_SET_G2_G3);
3837 }
3838 break;
3839 case (1):
3840 hc->chan[ch].nt_timer = -1;
3841 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3842 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3843 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3844 break;
3845 case (4):
3846 hc->chan[ch].nt_timer = -1;
3847 break;
3848 case (3):
3849 hc->chan[ch].nt_timer = -1;
3850 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3851 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3852 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3853 break;
3854 }
3855 }
3856 }
3857 }
3858
3859 /*
3860 * called for card mode init message
3861 */
3862
3863 static void
3864 hfcmulti_initmode(struct dchannel *dch)
3865 {
3866 struct hfc_multi *hc = dch->hw;
3867 u_char a_st_wr_state, r_e1_wr_sta;
3868 int i, pt;
3869
3870 if (debug & DEBUG_HFCMULTI_INIT)
3871 printk(KERN_DEBUG "%s: entered\n", __func__);
3872
3873 if (hc->ctype == HFC_TYPE_E1) {
3874 hc->chan[hc->dslot].slot_tx = -1;
3875 hc->chan[hc->dslot].slot_rx = -1;
3876 hc->chan[hc->dslot].conf = -1;
3877 if (hc->dslot) {
3878 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3879 -1, 0, -1, 0);
3880 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3881 dch->timer.data = (long) dch;
3882 init_timer(&dch->timer);
3883 }
3884 for (i = 1; i <= 31; i++) {
3885 if (i == hc->dslot)
3886 continue;
3887 hc->chan[i].slot_tx = -1;
3888 hc->chan[i].slot_rx = -1;
3889 hc->chan[i].conf = -1;
3890 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3891 }
3892 /* E1 */
3893 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3894 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3895 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3896 }
3897 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3898 HFC_outb(hc, R_RX0, 0);
3899 hc->hw.r_tx0 = 0 | V_OUT_EN;
3900 } else {
3901 HFC_outb(hc, R_RX0, 1);
3902 hc->hw.r_tx0 = 1 | V_OUT_EN;
3903 }
3904 hc->hw.r_tx1 = V_ATX | V_NTRI;
3905 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3906 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3907 HFC_outb(hc, R_TX_FR0, 0x00);
3908 HFC_outb(hc, R_TX_FR1, 0xf8);
3909
3910 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3911 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3912
3913 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3914
3915 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3916 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3917
3918 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3919 if (debug & DEBUG_HFCMULTI_INIT)
3920 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3921 __func__);
3922 r_e1_wr_sta = 0; /* G0 */
3923 hc->e1_getclock = 0;
3924 } else {
3925 if (debug & DEBUG_HFCMULTI_INIT)
3926 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3927 __func__);
3928 r_e1_wr_sta = 0; /* F0 */
3929 hc->e1_getclock = 1;
3930 }
3931 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3932 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3933 else
3934 HFC_outb(hc, R_SYNC_OUT, 0);
3935 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3936 hc->e1_getclock = 1;
3937 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3938 hc->e1_getclock = 0;
3939 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3940 /* SLAVE (clock master) */
3941 if (debug & DEBUG_HFCMULTI_INIT)
3942 printk(KERN_DEBUG
3943 "%s: E1 port is clock master "
3944 "(clock from PCM)\n", __func__);
3945 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3946 } else {
3947 if (hc->e1_getclock) {
3948 /* MASTER (clock slave) */
3949 if (debug & DEBUG_HFCMULTI_INIT)
3950 printk(KERN_DEBUG
3951 "%s: E1 port is clock slave "
3952 "(clock to PCM)\n", __func__);
3953 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3954 } else {
3955 /* MASTER (clock master) */
3956 if (debug & DEBUG_HFCMULTI_INIT)
3957 printk(KERN_DEBUG "%s: E1 port is "
3958 "clock master "
3959 "(clock from QUARTZ)\n",
3960 __func__);
3961 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3962 V_PCM_SYNC | V_JATT_OFF);
3963 HFC_outb(hc, R_SYNC_OUT, 0);
3964 }
3965 }
3966 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3967 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3968 HFC_outb(hc, R_PWM0, 0x50);
3969 HFC_outb(hc, R_PWM1, 0xff);
3970 /* state machine setup */
3971 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3972 udelay(6); /* wait at least 5,21us */
3973 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3974 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3975 hc->syncronized = 0;
3976 plxsd_checksync(hc, 0);
3977 }
3978 } else {
3979 i = dch->slot;
3980 hc->chan[i].slot_tx = -1;
3981 hc->chan[i].slot_rx = -1;
3982 hc->chan[i].conf = -1;
3983 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3984 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3985 dch->timer.data = (long) dch;
3986 init_timer(&dch->timer);
3987 hc->chan[i - 2].slot_tx = -1;
3988 hc->chan[i - 2].slot_rx = -1;
3989 hc->chan[i - 2].conf = -1;
3990 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3991 hc->chan[i - 1].slot_tx = -1;
3992 hc->chan[i - 1].slot_rx = -1;
3993 hc->chan[i - 1].conf = -1;
3994 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3995 /* ST */
3996 pt = hc->chan[i].port;
3997 /* select interface */
3998 HFC_outb(hc, R_ST_SEL, pt);
3999 /* undocumented: delay after R_ST_SEL */
4000 udelay(1);
4001 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
4002 if (debug & DEBUG_HFCMULTI_INIT)
4003 printk(KERN_DEBUG
4004 "%s: ST port %d is NT-mode\n",
4005 __func__, pt);
4006 /* clock delay */
4007 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
4008 a_st_wr_state = 1; /* G1 */
4009 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
4010 } else {
4011 if (debug & DEBUG_HFCMULTI_INIT)
4012 printk(KERN_DEBUG
4013 "%s: ST port %d is TE-mode\n",
4014 __func__, pt);
4015 /* clock delay */
4016 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
4017 a_st_wr_state = 2; /* F2 */
4018 hc->hw.a_st_ctrl0[pt] = 0;
4019 }
4020 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4021 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
4022 if (hc->ctype == HFC_TYPE_XHFC) {
4023 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4024 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4025 0x7c << 1 /* V_ST_PULSE */);
4026 }
4027 /* line setup */
4028 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
4029 /* disable E-channel */
4030 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4031 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4032 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4033 else
4034 HFC_outb(hc, A_ST_CTRL1, 0);
4035 /* enable B-channel receive */
4036 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
4037 /* state machine setup */
4038 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4039 udelay(6); /* wait at least 5,21us */
4040 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4041 hc->hw.r_sci_msk |= 1 << pt;
4042 /* state machine interrupts */
4043 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4044 /* unset sync on port */
4045 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4046 hc->syncronized &=
4047 ~(1 << hc->chan[dch->slot].port);
4048 plxsd_checksync(hc, 0);
4049 }
4050 }
4051 if (debug & DEBUG_HFCMULTI_INIT)
4052 printk("%s: done\n", __func__);
4053 }
4054
4055
4056 static int
4057 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4058 struct channel_req *rq)
4059 {
4060 int err = 0;
4061 u_long flags;
4062
4063 if (debug & DEBUG_HW_OPEN)
4064 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4065 dch->dev.id, __builtin_return_address(0));
4066 if (rq->protocol == ISDN_P_NONE)
4067 return -EINVAL;
4068 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4069 (dch->dev.D.protocol != rq->protocol)) {
4070 if (debug & DEBUG_HFCMULTI_MODE)
4071 printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4072 __func__, dch->dev.D.protocol, rq->protocol);
4073 }
4074 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4075 (rq->protocol != ISDN_P_TE_S0))
4076 l1_event(dch->l1, CLOSE_CHANNEL);
4077 if (dch->dev.D.protocol != rq->protocol) {
4078 if (rq->protocol == ISDN_P_TE_S0) {
4079 err = create_l1(dch, hfcm_l1callback);
4080 if (err)
4081 return err;
4082 }
4083 dch->dev.D.protocol = rq->protocol;
4084 spin_lock_irqsave(&hc->lock, flags);
4085 hfcmulti_initmode(dch);
4086 spin_unlock_irqrestore(&hc->lock, flags);
4087 }
4088 if (test_bit(FLG_ACTIVE, &dch->Flags))
4089 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4090 0, NULL, GFP_KERNEL);
4091 rq->ch = &dch->dev.D;
4092 if (!try_module_get(THIS_MODULE))
4093 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4094 return 0;
4095 }
4096
4097 static int
4098 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4099 struct channel_req *rq)
4100 {
4101 struct bchannel *bch;
4102 int ch;
4103
4104 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4105 return -EINVAL;
4106 if (rq->protocol == ISDN_P_NONE)
4107 return -EINVAL;
4108 if (hc->ctype == HFC_TYPE_E1)
4109 ch = rq->adr.channel;
4110 else
4111 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4112 bch = hc->chan[ch].bch;
4113 if (!bch) {
4114 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4115 __func__, ch);
4116 return -EINVAL;
4117 }
4118 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4119 return -EBUSY; /* b-channel can be only open once */
4120 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
4121 bch->ch.protocol = rq->protocol;
4122 hc->chan[ch].rx_off = 0;
4123 rq->ch = &bch->ch;
4124 if (!try_module_get(THIS_MODULE))
4125 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4126 return 0;
4127 }
4128
4129 /*
4130 * device control function
4131 */
4132 static int
4133 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4134 {
4135 struct hfc_multi *hc = dch->hw;
4136 int ret = 0;
4137 int wd_mode, wd_cnt;
4138
4139 switch (cq->op) {
4140 case MISDN_CTRL_GETOP:
4141 cq->op = MISDN_CTRL_HFC_OP;
4142 break;
4143 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4144 wd_cnt = cq->p1 & 0xf;
4145 wd_mode = !!(cq->p1 >> 4);
4146 if (debug & DEBUG_HFCMULTI_MSG)
4147 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4148 ", counter 0x%x\n", __func__,
4149 wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4150 /* set the watchdog timer */
4151 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4152 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4153 if (hc->ctype == HFC_TYPE_XHFC)
4154 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4155 /* init the watchdog register and reset the counter */
4156 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4157 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4158 /* enable the watchdog output for Speech-Design */
4159 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4160 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4161 HFC_outb(hc, R_GPIO_OUT1, 0);
4162 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4163 }
4164 break;
4165 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4166 if (debug & DEBUG_HFCMULTI_MSG)
4167 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4168 __func__);
4169 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4170 break;
4171 default:
4172 printk(KERN_WARNING "%s: unknown Op %x\n",
4173 __func__, cq->op);
4174 ret = -EINVAL;
4175 break;
4176 }
4177 return ret;
4178 }
4179
4180 static int
4181 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4182 {
4183 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4184 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4185 struct hfc_multi *hc = dch->hw;
4186 struct channel_req *rq;
4187 int err = 0;
4188 u_long flags;
4189
4190 if (dch->debug & DEBUG_HW)
4191 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4192 __func__, cmd, arg);
4193 switch (cmd) {
4194 case OPEN_CHANNEL:
4195 rq = arg;
4196 switch (rq->protocol) {
4197 case ISDN_P_TE_S0:
4198 case ISDN_P_NT_S0:
4199 if (hc->ctype == HFC_TYPE_E1) {
4200 err = -EINVAL;
4201 break;
4202 }
4203 err = open_dchannel(hc, dch, rq); /* locked there */
4204 break;
4205 case ISDN_P_TE_E1:
4206 case ISDN_P_NT_E1:
4207 if (hc->ctype != HFC_TYPE_E1) {
4208 err = -EINVAL;
4209 break;
4210 }
4211 err = open_dchannel(hc, dch, rq); /* locked there */
4212 break;
4213 default:
4214 spin_lock_irqsave(&hc->lock, flags);
4215 err = open_bchannel(hc, dch, rq);
4216 spin_unlock_irqrestore(&hc->lock, flags);
4217 }
4218 break;
4219 case CLOSE_CHANNEL:
4220 if (debug & DEBUG_HW_OPEN)
4221 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4222 __func__, dch->dev.id,
4223 __builtin_return_address(0));
4224 module_put(THIS_MODULE);
4225 break;
4226 case CONTROL_CHANNEL:
4227 spin_lock_irqsave(&hc->lock, flags);
4228 err = channel_dctrl(dch, arg);
4229 spin_unlock_irqrestore(&hc->lock, flags);
4230 break;
4231 default:
4232 if (dch->debug & DEBUG_HW)
4233 printk(KERN_DEBUG "%s: unknown command %x\n",
4234 __func__, cmd);
4235 err = -EINVAL;
4236 }
4237 return err;
4238 }
4239
4240 static int
4241 clockctl(void *priv, int enable)
4242 {
4243 struct hfc_multi *hc = priv;
4244
4245 hc->iclock_on = enable;
4246 return 0;
4247 }
4248
4249 /*
4250 * initialize the card
4251 */
4252
4253 /*
4254 * start timer irq, wait some time and check if we have interrupts.
4255 * if not, reset chip and try again.
4256 */
4257 static int
4258 init_card(struct hfc_multi *hc)
4259 {
4260 int err = -EIO;
4261 u_long flags;
4262 void __iomem *plx_acc;
4263 u_long plx_flags;
4264
4265 if (debug & DEBUG_HFCMULTI_INIT)
4266 printk(KERN_DEBUG "%s: entered\n", __func__);
4267
4268 spin_lock_irqsave(&hc->lock, flags);
4269 /* set interrupts but leave global interrupt disabled */
4270 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4271 disable_hwirq(hc);
4272 spin_unlock_irqrestore(&hc->lock, flags);
4273
4274 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4275 "HFC-multi", hc)) {
4276 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4277 hc->irq);
4278 hc->irq = 0;
4279 return -EIO;
4280 }
4281
4282 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4283 spin_lock_irqsave(&plx_lock, plx_flags);
4284 plx_acc = hc->plx_membase + PLX_INTCSR;
4285 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4286 plx_acc); /* enable PCI & LINT1 irq */
4287 spin_unlock_irqrestore(&plx_lock, plx_flags);
4288 }
4289
4290 if (debug & DEBUG_HFCMULTI_INIT)
4291 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4292 __func__, hc->irq, hc->irqcnt);
4293 err = init_chip(hc);
4294 if (err)
4295 goto error;
4296 /*
4297 * Finally enable IRQ output
4298 * this is only allowed, if an IRQ routine is already
4299 * established for this HFC, so don't do that earlier
4300 */
4301 spin_lock_irqsave(&hc->lock, flags);
4302 enable_hwirq(hc);
4303 spin_unlock_irqrestore(&hc->lock, flags);
4304 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4305 set_current_state(TASK_UNINTERRUPTIBLE);
4306 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4307 /* turn IRQ off until chip is completely initialized */
4308 spin_lock_irqsave(&hc->lock, flags);
4309 disable_hwirq(hc);
4310 spin_unlock_irqrestore(&hc->lock, flags);
4311 if (debug & DEBUG_HFCMULTI_INIT)
4312 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4313 __func__, hc->irq, hc->irqcnt);
4314 if (hc->irqcnt) {
4315 if (debug & DEBUG_HFCMULTI_INIT)
4316 printk(KERN_DEBUG "%s: done\n", __func__);
4317
4318 return 0;
4319 }
4320 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4321 printk(KERN_INFO "ignoring missing interrupts\n");
4322 return 0;
4323 }
4324
4325 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4326 hc->irq);
4327
4328 err = -EIO;
4329
4330 error:
4331 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4332 spin_lock_irqsave(&plx_lock, plx_flags);
4333 plx_acc = hc->plx_membase + PLX_INTCSR;
4334 writew(0x00, plx_acc); /*disable IRQs*/
4335 spin_unlock_irqrestore(&plx_lock, plx_flags);
4336 }
4337
4338 if (debug & DEBUG_HFCMULTI_INIT)
4339 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4340 if (hc->irq) {
4341 free_irq(hc->irq, hc);
4342 hc->irq = 0;
4343 }
4344
4345 if (debug & DEBUG_HFCMULTI_INIT)
4346 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4347 return err;
4348 }
4349
4350 /*
4351 * find pci device and set it up
4352 */
4353
4354 static int
4355 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4356 const struct pci_device_id *ent)
4357 {
4358 struct hm_map *m = (struct hm_map *)ent->driver_data;
4359
4360 printk(KERN_INFO
4361 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4362 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4363
4364 hc->pci_dev = pdev;
4365 if (m->clock2)
4366 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4367
4368 if (ent->device == 0xB410) {
4369 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4370 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4371 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4372 hc->slots = 32;
4373 }
4374
4375 if (hc->pci_dev->irq <= 0) {
4376 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4377 return -EIO;
4378 }
4379 if (pci_enable_device(hc->pci_dev)) {
4380 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4381 return -EIO;
4382 }
4383 hc->leds = m->leds;
4384 hc->ledstate = 0xAFFEAFFE;
4385 hc->opticalsupport = m->opticalsupport;
4386
4387 hc->pci_iobase = 0;
4388 hc->pci_membase = NULL;
4389 hc->plx_membase = NULL;
4390
4391 /* set memory access methods */
4392 if (m->io_mode) /* use mode from card config */
4393 hc->io_mode = m->io_mode;
4394 switch (hc->io_mode) {
4395 case HFC_IO_MODE_PLXSD:
4396 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4397 hc->slots = 128; /* required */
4398 hc->HFC_outb = HFC_outb_pcimem;
4399 hc->HFC_inb = HFC_inb_pcimem;
4400 hc->HFC_inw = HFC_inw_pcimem;
4401 hc->HFC_wait = HFC_wait_pcimem;
4402 hc->read_fifo = read_fifo_pcimem;
4403 hc->write_fifo = write_fifo_pcimem;
4404 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4405 /* MEMBASE 1 is PLX PCI Bridge */
4406
4407 if (!hc->plx_origmembase) {
4408 printk(KERN_WARNING
4409 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4410 pci_disable_device(hc->pci_dev);
4411 return -EIO;
4412 }
4413
4414 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4415 if (!hc->plx_membase) {
4416 printk(KERN_WARNING
4417 "HFC-multi: failed to remap plx address space. "
4418 "(internal error)\n");
4419 pci_disable_device(hc->pci_dev);
4420 return -EIO;
4421 }
4422 printk(KERN_INFO
4423 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4424 (u_long)hc->plx_membase, hc->plx_origmembase);
4425
4426 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4427 /* MEMBASE 1 is PLX PCI Bridge */
4428 if (!hc->pci_origmembase) {
4429 printk(KERN_WARNING
4430 "HFC-multi: No IO-Memory for PCI card found\n");
4431 pci_disable_device(hc->pci_dev);
4432 return -EIO;
4433 }
4434
4435 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4436 if (!hc->pci_membase) {
4437 printk(KERN_WARNING "HFC-multi: failed to remap io "
4438 "address space. (internal error)\n");
4439 pci_disable_device(hc->pci_dev);
4440 return -EIO;
4441 }
4442
4443 printk(KERN_INFO
4444 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4445 "leds-type %d\n",
4446 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4447 hc->pci_dev->irq, HZ, hc->leds);
4448 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4449 break;
4450 case HFC_IO_MODE_PCIMEM:
4451 hc->HFC_outb = HFC_outb_pcimem;
4452 hc->HFC_inb = HFC_inb_pcimem;
4453 hc->HFC_inw = HFC_inw_pcimem;
4454 hc->HFC_wait = HFC_wait_pcimem;
4455 hc->read_fifo = read_fifo_pcimem;
4456 hc->write_fifo = write_fifo_pcimem;
4457 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4458 if (!hc->pci_origmembase) {
4459 printk(KERN_WARNING
4460 "HFC-multi: No IO-Memory for PCI card found\n");
4461 pci_disable_device(hc->pci_dev);
4462 return -EIO;
4463 }
4464
4465 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4466 if (!hc->pci_membase) {
4467 printk(KERN_WARNING
4468 "HFC-multi: failed to remap io address space. "
4469 "(internal error)\n");
4470 pci_disable_device(hc->pci_dev);
4471 return -EIO;
4472 }
4473 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4474 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4475 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4476 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4477 break;
4478 case HFC_IO_MODE_REGIO:
4479 hc->HFC_outb = HFC_outb_regio;
4480 hc->HFC_inb = HFC_inb_regio;
4481 hc->HFC_inw = HFC_inw_regio;
4482 hc->HFC_wait = HFC_wait_regio;
4483 hc->read_fifo = read_fifo_regio;
4484 hc->write_fifo = write_fifo_regio;
4485 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4486 if (!hc->pci_iobase) {
4487 printk(KERN_WARNING
4488 "HFC-multi: No IO for PCI card found\n");
4489 pci_disable_device(hc->pci_dev);
4490 return -EIO;
4491 }
4492
4493 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4494 printk(KERN_WARNING "HFC-multi: failed to request "
4495 "address space at 0x%08lx (internal error)\n",
4496 hc->pci_iobase);
4497 pci_disable_device(hc->pci_dev);
4498 return -EIO;
4499 }
4500
4501 printk(KERN_INFO
4502 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4503 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4504 hc->pci_dev->irq, HZ, hc->leds);
4505 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4506 break;
4507 default:
4508 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4509 pci_disable_device(hc->pci_dev);
4510 return -EIO;
4511 }
4512
4513 pci_set_drvdata(hc->pci_dev, hc);
4514
4515 /* At this point the needed PCI config is done */
4516 /* fifos are still not enabled */
4517 return 0;
4518 }
4519
4520
4521 /*
4522 * remove port
4523 */
4524
4525 static void
4526 release_port(struct hfc_multi *hc, struct dchannel *dch)
4527 {
4528 int pt, ci, i = 0;
4529 u_long flags;
4530 struct bchannel *pb;
4531
4532 ci = dch->slot;
4533 pt = hc->chan[ci].port;
4534
4535 if (debug & DEBUG_HFCMULTI_INIT)
4536 printk(KERN_DEBUG "%s: entered for port %d\n",
4537 __func__, pt + 1);
4538
4539 if (pt >= hc->ports) {
4540 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4541 __func__, pt + 1);
4542 return;
4543 }
4544
4545 if (debug & DEBUG_HFCMULTI_INIT)
4546 printk(KERN_DEBUG "%s: releasing port=%d\n",
4547 __func__, pt + 1);
4548
4549 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4550 l1_event(dch->l1, CLOSE_CHANNEL);
4551
4552 hc->chan[ci].dch = NULL;
4553
4554 if (hc->created[pt]) {
4555 hc->created[pt] = 0;
4556 mISDN_unregister_device(&dch->dev);
4557 }
4558
4559 spin_lock_irqsave(&hc->lock, flags);
4560
4561 if (dch->timer.function) {
4562 del_timer(&dch->timer);
4563 dch->timer.function = NULL;
4564 }
4565
4566 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4567 /* remove sync */
4568 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4569 hc->syncronized = 0;
4570 plxsd_checksync(hc, 1);
4571 }
4572 /* free channels */
4573 for (i = 0; i <= 31; i++) {
4574 if (hc->chan[i].bch) {
4575 if (debug & DEBUG_HFCMULTI_INIT)
4576 printk(KERN_DEBUG
4577 "%s: free port %d channel %d\n",
4578 __func__, hc->chan[i].port + 1, i);
4579 pb = hc->chan[i].bch;
4580 hc->chan[i].bch = NULL;
4581 spin_unlock_irqrestore(&hc->lock, flags);
4582 mISDN_freebchannel(pb);
4583 kfree(pb);
4584 kfree(hc->chan[i].coeff);
4585 spin_lock_irqsave(&hc->lock, flags);
4586 }
4587 }
4588 } else {
4589 /* remove sync */
4590 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4591 hc->syncronized &=
4592 ~(1 << hc->chan[ci].port);
4593 plxsd_checksync(hc, 1);
4594 }
4595 /* free channels */
4596 if (hc->chan[ci - 2].bch) {
4597 if (debug & DEBUG_HFCMULTI_INIT)
4598 printk(KERN_DEBUG
4599 "%s: free port %d channel %d\n",
4600 __func__, hc->chan[ci - 2].port + 1,
4601 ci - 2);
4602 pb = hc->chan[ci - 2].bch;
4603 hc->chan[ci - 2].bch = NULL;
4604 spin_unlock_irqrestore(&hc->lock, flags);
4605 mISDN_freebchannel(pb);
4606 kfree(pb);
4607 kfree(hc->chan[ci - 2].coeff);
4608 spin_lock_irqsave(&hc->lock, flags);
4609 }
4610 if (hc->chan[ci - 1].bch) {
4611 if (debug & DEBUG_HFCMULTI_INIT)
4612 printk(KERN_DEBUG
4613 "%s: free port %d channel %d\n",
4614 __func__, hc->chan[ci - 1].port + 1,
4615 ci - 1);
4616 pb = hc->chan[ci - 1].bch;
4617 hc->chan[ci - 1].bch = NULL;
4618 spin_unlock_irqrestore(&hc->lock, flags);
4619 mISDN_freebchannel(pb);
4620 kfree(pb);
4621 kfree(hc->chan[ci - 1].coeff);
4622 spin_lock_irqsave(&hc->lock, flags);
4623 }
4624 }
4625
4626 spin_unlock_irqrestore(&hc->lock, flags);
4627
4628 if (debug & DEBUG_HFCMULTI_INIT)
4629 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4630 mISDN_freedchannel(dch);
4631 kfree(dch);
4632
4633 if (debug & DEBUG_HFCMULTI_INIT)
4634 printk(KERN_DEBUG "%s: done!\n", __func__);
4635 }
4636
4637 static void
4638 release_card(struct hfc_multi *hc)
4639 {
4640 u_long flags;
4641 int ch;
4642
4643 if (debug & DEBUG_HFCMULTI_INIT)
4644 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4645 __func__, hc->id);
4646
4647 /* unregister clock source */
4648 if (hc->iclock)
4649 mISDN_unregister_clock(hc->iclock);
4650
4651 /* disable irq */
4652 spin_lock_irqsave(&hc->lock, flags);
4653 disable_hwirq(hc);
4654 spin_unlock_irqrestore(&hc->lock, flags);
4655 udelay(1000);
4656
4657 /* dimm leds */
4658 if (hc->leds)
4659 hfcmulti_leds(hc);
4660
4661 /* disable D-channels & B-channels */
4662 if (debug & DEBUG_HFCMULTI_INIT)
4663 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4664 __func__);
4665 for (ch = 0; ch <= 31; ch++) {
4666 if (hc->chan[ch].dch)
4667 release_port(hc, hc->chan[ch].dch);
4668 }
4669
4670 /* release hardware & irq */
4671 if (hc->irq) {
4672 if (debug & DEBUG_HFCMULTI_INIT)
4673 printk(KERN_DEBUG "%s: free irq %d\n",
4674 __func__, hc->irq);
4675 free_irq(hc->irq, hc);
4676 hc->irq = 0;
4677
4678 }
4679 release_io_hfcmulti(hc);
4680
4681 if (debug & DEBUG_HFCMULTI_INIT)
4682 printk(KERN_DEBUG "%s: remove instance from list\n",
4683 __func__);
4684 list_del(&hc->list);
4685
4686 if (debug & DEBUG_HFCMULTI_INIT)
4687 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4688 if (hc == syncmaster)
4689 syncmaster = NULL;
4690 kfree(hc);
4691 if (debug & DEBUG_HFCMULTI_INIT)
4692 printk(KERN_DEBUG "%s: card successfully removed\n",
4693 __func__);
4694 }
4695
4696 static int
4697 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4698 {
4699 struct dchannel *dch;
4700 struct bchannel *bch;
4701 int ch, ret = 0;
4702 char name[MISDN_MAX_IDLEN];
4703
4704 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4705 if (!dch)
4706 return -ENOMEM;
4707 dch->debug = debug;
4708 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4709 dch->hw = hc;
4710 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4711 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4712 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4713 dch->dev.D.send = handle_dmsg;
4714 dch->dev.D.ctrl = hfcm_dctrl;
4715 dch->dev.nrbchan = (hc->dslot) ? 30 : 31;
4716 dch->slot = hc->dslot;
4717 hc->chan[hc->dslot].dch = dch;
4718 hc->chan[hc->dslot].port = 0;
4719 hc->chan[hc->dslot].nt_timer = -1;
4720 for (ch = 1; ch <= 31; ch++) {
4721 if (ch == hc->dslot) /* skip dchannel */
4722 continue;
4723 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4724 if (!bch) {
4725 printk(KERN_ERR "%s: no memory for bchannel\n",
4726 __func__);
4727 ret = -ENOMEM;
4728 goto free_chan;
4729 }
4730 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4731 if (!hc->chan[ch].coeff) {
4732 printk(KERN_ERR "%s: no memory for coeffs\n",
4733 __func__);
4734 ret = -ENOMEM;
4735 kfree(bch);
4736 goto free_chan;
4737 }
4738 bch->nr = ch;
4739 bch->slot = ch;
4740 bch->debug = debug;
4741 mISDN_initbchannel(bch, MAX_DATA_MEM);
4742 bch->hw = hc;
4743 bch->ch.send = handle_bmsg;
4744 bch->ch.ctrl = hfcm_bctrl;
4745 bch->ch.nr = ch;
4746 list_add(&bch->ch.list, &dch->dev.bchannels);
4747 hc->chan[ch].bch = bch;
4748 hc->chan[ch].port = 0;
4749 set_channelmap(bch->nr, dch->dev.channelmap);
4750 }
4751 /* set optical line type */
4752 if (port[Port_cnt] & 0x001) {
4753 if (!m->opticalsupport) {
4754 printk(KERN_INFO
4755 "This board has no optical "
4756 "support\n");
4757 } else {
4758 if (debug & DEBUG_HFCMULTI_INIT)
4759 printk(KERN_DEBUG
4760 "%s: PORT set optical "
4761 "interfacs: card(%d) "
4762 "port(%d)\n",
4763 __func__,
4764 HFC_cnt + 1, 1);
4765 test_and_set_bit(HFC_CFG_OPTICAL,
4766 &hc->chan[hc->dslot].cfg);
4767 }
4768 }
4769 /* set LOS report */
4770 if (port[Port_cnt] & 0x004) {
4771 if (debug & DEBUG_HFCMULTI_INIT)
4772 printk(KERN_DEBUG "%s: PORT set "
4773 "LOS report: card(%d) port(%d)\n",
4774 __func__, HFC_cnt + 1, 1);
4775 test_and_set_bit(HFC_CFG_REPORT_LOS,
4776 &hc->chan[hc->dslot].cfg);
4777 }
4778 /* set AIS report */
4779 if (port[Port_cnt] & 0x008) {
4780 if (debug & DEBUG_HFCMULTI_INIT)
4781 printk(KERN_DEBUG "%s: PORT set "
4782 "AIS report: card(%d) port(%d)\n",
4783 __func__, HFC_cnt + 1, 1);
4784 test_and_set_bit(HFC_CFG_REPORT_AIS,
4785 &hc->chan[hc->dslot].cfg);
4786 }
4787 /* set SLIP report */
4788 if (port[Port_cnt] & 0x010) {
4789 if (debug & DEBUG_HFCMULTI_INIT)
4790 printk(KERN_DEBUG
4791 "%s: PORT set SLIP report: "
4792 "card(%d) port(%d)\n",
4793 __func__, HFC_cnt + 1, 1);
4794 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4795 &hc->chan[hc->dslot].cfg);
4796 }
4797 /* set RDI report */
4798 if (port[Port_cnt] & 0x020) {
4799 if (debug & DEBUG_HFCMULTI_INIT)
4800 printk(KERN_DEBUG
4801 "%s: PORT set RDI report: "
4802 "card(%d) port(%d)\n",
4803 __func__, HFC_cnt + 1, 1);
4804 test_and_set_bit(HFC_CFG_REPORT_RDI,
4805 &hc->chan[hc->dslot].cfg);
4806 }
4807 /* set CRC-4 Mode */
4808 if (!(port[Port_cnt] & 0x100)) {
4809 if (debug & DEBUG_HFCMULTI_INIT)
4810 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4811 " card(%d) port(%d)\n",
4812 __func__, HFC_cnt + 1, 1);
4813 test_and_set_bit(HFC_CFG_CRC4,
4814 &hc->chan[hc->dslot].cfg);
4815 } else {
4816 if (debug & DEBUG_HFCMULTI_INIT)
4817 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4818 " report: card(%d) port(%d)\n",
4819 __func__, HFC_cnt + 1, 1);
4820 }
4821 /* set forced clock */
4822 if (port[Port_cnt] & 0x0200) {
4823 if (debug & DEBUG_HFCMULTI_INIT)
4824 printk(KERN_DEBUG "%s: PORT force getting clock from "
4825 "E1: card(%d) port(%d)\n",
4826 __func__, HFC_cnt + 1, 1);
4827 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4828 } else
4829 if (port[Port_cnt] & 0x0400) {
4830 if (debug & DEBUG_HFCMULTI_INIT)
4831 printk(KERN_DEBUG "%s: PORT force putting clock to "
4832 "E1: card(%d) port(%d)\n",
4833 __func__, HFC_cnt + 1, 1);
4834 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4835 }
4836 /* set JATT PLL */
4837 if (port[Port_cnt] & 0x0800) {
4838 if (debug & DEBUG_HFCMULTI_INIT)
4839 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4840 "E1: card(%d) port(%d)\n",
4841 __func__, HFC_cnt + 1, 1);
4842 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4843 }
4844 /* set elastic jitter buffer */
4845 if (port[Port_cnt] & 0x3000) {
4846 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4847 if (debug & DEBUG_HFCMULTI_INIT)
4848 printk(KERN_DEBUG
4849 "%s: PORT set elastic "
4850 "buffer to %d: card(%d) port(%d)\n",
4851 __func__, hc->chan[hc->dslot].jitter,
4852 HFC_cnt + 1, 1);
4853 } else
4854 hc->chan[hc->dslot].jitter = 2; /* default */
4855 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4856 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4857 if (ret)
4858 goto free_chan;
4859 hc->created[0] = 1;
4860 return ret;
4861 free_chan:
4862 release_port(hc, dch);
4863 return ret;
4864 }
4865
4866 static int
4867 init_multi_port(struct hfc_multi *hc, int pt)
4868 {
4869 struct dchannel *dch;
4870 struct bchannel *bch;
4871 int ch, i, ret = 0;
4872 char name[MISDN_MAX_IDLEN];
4873
4874 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4875 if (!dch)
4876 return -ENOMEM;
4877 dch->debug = debug;
4878 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4879 dch->hw = hc;
4880 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4881 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4882 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4883 dch->dev.D.send = handle_dmsg;
4884 dch->dev.D.ctrl = hfcm_dctrl;
4885 dch->dev.nrbchan = 2;
4886 i = pt << 2;
4887 dch->slot = i + 2;
4888 hc->chan[i + 2].dch = dch;
4889 hc->chan[i + 2].port = pt;
4890 hc->chan[i + 2].nt_timer = -1;
4891 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4892 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4893 if (!bch) {
4894 printk(KERN_ERR "%s: no memory for bchannel\n",
4895 __func__);
4896 ret = -ENOMEM;
4897 goto free_chan;
4898 }
4899 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4900 if (!hc->chan[i + ch].coeff) {
4901 printk(KERN_ERR "%s: no memory for coeffs\n",
4902 __func__);
4903 ret = -ENOMEM;
4904 kfree(bch);
4905 goto free_chan;
4906 }
4907 bch->nr = ch + 1;
4908 bch->slot = i + ch;
4909 bch->debug = debug;
4910 mISDN_initbchannel(bch, MAX_DATA_MEM);
4911 bch->hw = hc;
4912 bch->ch.send = handle_bmsg;
4913 bch->ch.ctrl = hfcm_bctrl;
4914 bch->ch.nr = ch + 1;
4915 list_add(&bch->ch.list, &dch->dev.bchannels);
4916 hc->chan[i + ch].bch = bch;
4917 hc->chan[i + ch].port = pt;
4918 set_channelmap(bch->nr, dch->dev.channelmap);
4919 }
4920 /* set master clock */
4921 if (port[Port_cnt] & 0x001) {
4922 if (debug & DEBUG_HFCMULTI_INIT)
4923 printk(KERN_DEBUG
4924 "%s: PROTOCOL set master clock: "
4925 "card(%d) port(%d)\n",
4926 __func__, HFC_cnt + 1, pt + 1);
4927 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4928 printk(KERN_ERR "Error: Master clock "
4929 "for port(%d) of card(%d) is only"
4930 " possible with TE-mode\n",
4931 pt + 1, HFC_cnt + 1);
4932 ret = -EINVAL;
4933 goto free_chan;
4934 }
4935 if (hc->masterclk >= 0) {
4936 printk(KERN_ERR "Error: Master clock "
4937 "for port(%d) of card(%d) already "
4938 "defined for port(%d)\n",
4939 pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4940 ret = -EINVAL;
4941 goto free_chan;
4942 }
4943 hc->masterclk = pt;
4944 }
4945 /* set transmitter line to non capacitive */
4946 if (port[Port_cnt] & 0x002) {
4947 if (debug & DEBUG_HFCMULTI_INIT)
4948 printk(KERN_DEBUG
4949 "%s: PROTOCOL set non capacitive "
4950 "transmitter: card(%d) port(%d)\n",
4951 __func__, HFC_cnt + 1, pt + 1);
4952 test_and_set_bit(HFC_CFG_NONCAP_TX,
4953 &hc->chan[i + 2].cfg);
4954 }
4955 /* disable E-channel */
4956 if (port[Port_cnt] & 0x004) {
4957 if (debug & DEBUG_HFCMULTI_INIT)
4958 printk(KERN_DEBUG
4959 "%s: PROTOCOL disable E-channel: "
4960 "card(%d) port(%d)\n",
4961 __func__, HFC_cnt + 1, pt + 1);
4962 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4963 &hc->chan[i + 2].cfg);
4964 }
4965 if (hc->ctype == HFC_TYPE_XHFC) {
4966 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4967 HFC_cnt + 1, pt + 1);
4968 ret = mISDN_register_device(&dch->dev, NULL, name);
4969 } else {
4970 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4971 hc->ctype, HFC_cnt + 1, pt + 1);
4972 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4973 }
4974 if (ret)
4975 goto free_chan;
4976 hc->created[pt] = 1;
4977 return ret;
4978 free_chan:
4979 release_port(hc, dch);
4980 return ret;
4981 }
4982
4983 static int
4984 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4985 const struct pci_device_id *ent)
4986 {
4987 int ret_err = 0;
4988 int pt;
4989 struct hfc_multi *hc;
4990 u_long flags;
4991 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4992 int i;
4993
4994 if (HFC_cnt >= MAX_CARDS) {
4995 printk(KERN_ERR "too many cards (max=%d).\n",
4996 MAX_CARDS);
4997 return -EINVAL;
4998 }
4999 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
5000 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
5001 "type[%d] %d was supplied as module parameter\n",
5002 m->vendor_name, m->card_name, m->type, HFC_cnt,
5003 type[HFC_cnt] & 0xff);
5004 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
5005 "first, to see cards and their types.");
5006 return -EINVAL;
5007 }
5008 if (debug & DEBUG_HFCMULTI_INIT)
5009 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
5010 __func__, m->vendor_name, m->card_name, m->type,
5011 type[HFC_cnt]);
5012
5013 /* allocate card+fifo structure */
5014 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5015 if (!hc) {
5016 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5017 return -ENOMEM;
5018 }
5019 spin_lock_init(&hc->lock);
5020 hc->mtyp = m;
5021 hc->ctype = m->type;
5022 hc->ports = m->ports;
5023 hc->id = HFC_cnt;
5024 hc->pcm = pcm[HFC_cnt];
5025 hc->io_mode = iomode[HFC_cnt];
5026 if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
5027 hc->dslot = 0;
5028 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
5029 "31 B-channels\n");
5030 }
5031 if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
5032 && hc->ctype == HFC_TYPE_E1) {
5033 hc->dslot = dslot[HFC_cnt];
5034 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
5035 "time slot %d\n", dslot[HFC_cnt]);
5036 } else
5037 hc->dslot = 16;
5038
5039 /* set chip specific features */
5040 hc->masterclk = -1;
5041 if (type[HFC_cnt] & 0x100) {
5042 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5043 hc->silence = 0xff; /* ulaw silence */
5044 } else
5045 hc->silence = 0x2a; /* alaw silence */
5046 if ((poll >> 1) > sizeof(hc->silence_data)) {
5047 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5048 "please fix\n");
5049 return -EINVAL;
5050 }
5051 for (i = 0; i < (poll >> 1); i++)
5052 hc->silence_data[i] = hc->silence;
5053
5054 if (hc->ctype != HFC_TYPE_XHFC) {
5055 if (!(type[HFC_cnt] & 0x200))
5056 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5057 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5058 }
5059
5060 if (type[HFC_cnt] & 0x800)
5061 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5062 if (type[HFC_cnt] & 0x1000) {
5063 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5064 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5065 }
5066 if (type[HFC_cnt] & 0x4000)
5067 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5068 if (type[HFC_cnt] & 0x8000)
5069 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5070 hc->slots = 32;
5071 if (type[HFC_cnt] & 0x10000)
5072 hc->slots = 64;
5073 if (type[HFC_cnt] & 0x20000)
5074 hc->slots = 128;
5075 if (type[HFC_cnt] & 0x80000) {
5076 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5077 hc->wdcount = 0;
5078 hc->wdbyte = V_GPIO_OUT2;
5079 printk(KERN_NOTICE "Watchdog enabled\n");
5080 }
5081
5082 if (pdev && ent)
5083 /* setup pci, hc->slots may change due to PLXSD */
5084 ret_err = setup_pci(hc, pdev, ent);
5085 else
5086 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5087 ret_err = setup_embedded(hc, m);
5088 #else
5089 {
5090 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5091 ret_err = -EIO;
5092 }
5093 #endif
5094 if (ret_err) {
5095 if (hc == syncmaster)
5096 syncmaster = NULL;
5097 kfree(hc);
5098 return ret_err;
5099 }
5100
5101 hc->HFC_outb_nodebug = hc->HFC_outb;
5102 hc->HFC_inb_nodebug = hc->HFC_inb;
5103 hc->HFC_inw_nodebug = hc->HFC_inw;
5104 hc->HFC_wait_nodebug = hc->HFC_wait;
5105 #ifdef HFC_REGISTER_DEBUG
5106 hc->HFC_outb = HFC_outb_debug;
5107 hc->HFC_inb = HFC_inb_debug;
5108 hc->HFC_inw = HFC_inw_debug;
5109 hc->HFC_wait = HFC_wait_debug;
5110 #endif
5111 /* create channels */
5112 for (pt = 0; pt < hc->ports; pt++) {
5113 if (Port_cnt >= MAX_PORTS) {
5114 printk(KERN_ERR "too many ports (max=%d).\n",
5115 MAX_PORTS);
5116 ret_err = -EINVAL;
5117 goto free_card;
5118 }
5119 if (hc->ctype == HFC_TYPE_E1)
5120 ret_err = init_e1_port(hc, m);
5121 else
5122 ret_err = init_multi_port(hc, pt);
5123 if (debug & DEBUG_HFCMULTI_INIT)
5124 printk(KERN_DEBUG
5125 "%s: Registering D-channel, card(%d) port(%d)"
5126 "result %d\n",
5127 __func__, HFC_cnt + 1, pt, ret_err);
5128
5129 if (ret_err) {
5130 while (pt) { /* release already registered ports */
5131 pt--;
5132 release_port(hc, hc->chan[(pt << 2) + 2].dch);
5133 }
5134 goto free_card;
5135 }
5136 Port_cnt++;
5137 }
5138
5139 /* disp switches */
5140 switch (m->dip_type) {
5141 case DIP_4S:
5142 /*
5143 * Get DIP setting for beroNet 1S/2S/4S cards
5144 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5145 * GPI 19/23 (R_GPI_IN2))
5146 */
5147 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5148 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5149 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5150
5151 /* Port mode (TE/NT) jumpers */
5152 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5153
5154 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5155 pmj = ~pmj & 0xf;
5156
5157 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5158 m->vendor_name, m->card_name, dips, pmj);
5159 break;
5160 case DIP_8S:
5161 /*
5162 * Get DIP Setting for beroNet 8S0+ cards
5163 * Enable PCI auxbridge function
5164 */
5165 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5166 /* prepare access to auxport */
5167 outw(0x4000, hc->pci_iobase + 4);
5168 /*
5169 * some dummy reads are required to
5170 * read valid DIP switch data
5171 */
5172 dips = inb(hc->pci_iobase);
5173 dips = inb(hc->pci_iobase);
5174 dips = inb(hc->pci_iobase);
5175 dips = ~inb(hc->pci_iobase) & 0x3F;
5176 outw(0x0, hc->pci_iobase + 4);
5177 /* disable PCI auxbridge function */
5178 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5179 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5180 m->vendor_name, m->card_name, dips);
5181 break;
5182 case DIP_E1:
5183 /*
5184 * get DIP Setting for beroNet E1 cards
5185 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5186 */
5187 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5188 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5189 m->vendor_name, m->card_name, dips);
5190 break;
5191 }
5192
5193 /* add to list */
5194 spin_lock_irqsave(&HFClock, flags);
5195 list_add_tail(&hc->list, &HFClist);
5196 spin_unlock_irqrestore(&HFClock, flags);
5197
5198 /* use as clock source */
5199 if (clock == HFC_cnt + 1)
5200 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5201
5202 /* initialize hardware */
5203 hc->irq = (m->irq) ? : hc->pci_dev->irq;
5204 ret_err = init_card(hc);
5205 if (ret_err) {
5206 printk(KERN_ERR "init card returns %d\n", ret_err);
5207 release_card(hc);
5208 return ret_err;
5209 }
5210
5211 /* start IRQ and return */
5212 spin_lock_irqsave(&hc->lock, flags);
5213 enable_hwirq(hc);
5214 spin_unlock_irqrestore(&hc->lock, flags);
5215 return 0;
5216
5217 free_card:
5218 release_io_hfcmulti(hc);
5219 if (hc == syncmaster)
5220 syncmaster = NULL;
5221 kfree(hc);
5222 return ret_err;
5223 }
5224
5225 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5226 {
5227 struct hfc_multi *card = pci_get_drvdata(pdev);
5228 u_long flags;
5229
5230 if (debug)
5231 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5232 "device:%x subvendor:%x subdevice:%x\n",
5233 pdev->vendor, pdev->device,
5234 pdev->subsystem_vendor, pdev->subsystem_device);
5235
5236 if (card) {
5237 spin_lock_irqsave(&HFClock, flags);
5238 release_card(card);
5239 spin_unlock_irqrestore(&HFClock, flags);
5240 } else {
5241 if (debug)
5242 printk(KERN_DEBUG "%s: drvdata already removed\n",
5243 __func__);
5244 }
5245 }
5246
5247 #define VENDOR_CCD "Cologne Chip AG"
5248 #define VENDOR_BN "beroNet GmbH"
5249 #define VENDOR_DIG "Digium Inc."
5250 #define VENDOR_JH "Junghanns.NET GmbH"
5251 #define VENDOR_PRIM "PrimuX"
5252
5253 static const struct hm_map hfcm_map[] = {
5254 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5255 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5256 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5257 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5258 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5259 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5260 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5261 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5262 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5263 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5264 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5265 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5266
5267 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5268 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5269 HFC_IO_MODE_REGIO, 0},
5270 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5271 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5272
5273 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5274 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5275 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5276
5277 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5278 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5279 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5280 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5281
5282 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5283 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5284 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5285
5286 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5287 HFC_IO_MODE_PLXSD, 0},
5288 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5289 HFC_IO_MODE_PLXSD, 0},
5290 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5291 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5292 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5293 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5294 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5295 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5296 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5297 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5298 };
5299
5300 #undef H
5301 #define H(x) ((unsigned long)&hfcm_map[x])
5302 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5303
5304 /* Cards with HFC-4S Chip */
5305 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5306 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5307 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5308 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5309 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5310 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5311 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5312 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5313 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5314 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5315 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5316 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5317 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5318 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5319 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5320 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5321 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5322 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5323 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5324 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5325 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5326 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5327 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5328 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5329 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5330 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5331 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5332 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5333 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5334 0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5335 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5336 0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5337
5338 /* Cards with HFC-8S Chip */
5339 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5340 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5341 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5342 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5343 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5344 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5345 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5346 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5347 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5348 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5349 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5350 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5351 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5352 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5353 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5354 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5355 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5356 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
5357
5358
5359 /* Cards with HFC-E1 Chip */
5360 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5361 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5362 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5363 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5364 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5365 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5366 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5367 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5368
5369 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5370 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5371 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5372 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5373 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5374 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5375
5376 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5377 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5379 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5380
5381 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5382 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5383
5384 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5385 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5386 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5387 {0, }
5388 };
5389 #undef H
5390
5391 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5392
5393 static int
5394 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5395 {
5396 struct hm_map *m = (struct hm_map *)ent->driver_data;
5397 int ret;
5398
5399 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5400 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5401 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5402 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5403 printk(KERN_ERR
5404 "Unknown HFC multiport controller (vendor:%04x device:%04x "
5405 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5406 pdev->device, pdev->subsystem_vendor,
5407 pdev->subsystem_device);
5408 printk(KERN_ERR
5409 "Please contact the driver maintainer for support.\n");
5410 return -ENODEV;
5411 }
5412 ret = hfcmulti_init(m, pdev, ent);
5413 if (ret)
5414 return ret;
5415 HFC_cnt++;
5416 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5417 return 0;
5418 }
5419
5420 static struct pci_driver hfcmultipci_driver = {
5421 .name = "hfc_multi",
5422 .probe = hfcmulti_probe,
5423 .remove = __devexit_p(hfc_remove_pci),
5424 .id_table = hfmultipci_ids,
5425 };
5426
5427 static void __exit
5428 HFCmulti_cleanup(void)
5429 {
5430 struct hfc_multi *card, *next;
5431
5432 /* get rid of all devices of this driver */
5433 list_for_each_entry_safe(card, next, &HFClist, list)
5434 release_card(card);
5435 pci_unregister_driver(&hfcmultipci_driver);
5436 }
5437
5438 static int __init
5439 HFCmulti_init(void)
5440 {
5441 int err;
5442 int i, xhfc = 0;
5443 struct hm_map m;
5444
5445 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5446
5447 #ifdef IRQ_DEBUG
5448 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5449 #endif
5450
5451 spin_lock_init(&HFClock);
5452 spin_lock_init(&plx_lock);
5453
5454 if (debug & DEBUG_HFCMULTI_INIT)
5455 printk(KERN_DEBUG "%s: init entered\n", __func__);
5456
5457 switch (poll) {
5458 case 0:
5459 poll_timer = 6;
5460 poll = 128;
5461 break;
5462 case 8:
5463 poll_timer = 2;
5464 break;
5465 case 16:
5466 poll_timer = 3;
5467 break;
5468 case 32:
5469 poll_timer = 4;
5470 break;
5471 case 64:
5472 poll_timer = 5;
5473 break;
5474 case 128:
5475 poll_timer = 6;
5476 break;
5477 case 256:
5478 poll_timer = 7;
5479 break;
5480 default:
5481 printk(KERN_ERR
5482 "%s: Wrong poll value (%d).\n", __func__, poll);
5483 err = -EINVAL;
5484 return err;
5485
5486 }
5487
5488 if (!clock)
5489 clock = 1;
5490
5491 /* Register the embedded devices.
5492 * This should be done before the PCI cards registration */
5493 switch (hwid) {
5494 case HWID_MINIP4:
5495 xhfc = 1;
5496 m = hfcm_map[31];
5497 break;
5498 case HWID_MINIP8:
5499 xhfc = 2;
5500 m = hfcm_map[31];
5501 break;
5502 case HWID_MINIP16:
5503 xhfc = 4;
5504 m = hfcm_map[31];
5505 break;
5506 default:
5507 xhfc = 0;
5508 }
5509
5510 for (i = 0; i < xhfc; ++i) {
5511 err = hfcmulti_init(&m, NULL, NULL);
5512 if (err) {
5513 printk(KERN_ERR "error registering embedded driver: "
5514 "%x\n", err);
5515 return err;
5516 }
5517 HFC_cnt++;
5518 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5519 }
5520
5521 /* Register the PCI cards */
5522 err = pci_register_driver(&hfcmultipci_driver);
5523 if (err < 0) {
5524 printk(KERN_ERR "error registering pci driver: %x\n", err);
5525 return err;
5526 }
5527
5528 return 0;
5529 }
5530
5531
5532 module_init(HFCmulti_init);
5533 module_exit(HFCmulti_cleanup);
CJK support for tty framebuffer vt