?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MN10300: Fix misaligned index-register addressing handling
[linux-2.6/cjktty.git] / arch / mn10300 / mm / misalignment.c
bloba59836804bc6f480cb053f9b5f41b91d562867b9
1 /* MN10300 Misalignment fixup handler
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/timer.h>
18 #include <linux/mm.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <asm/processor.h>
27 #include <asm/system.h>
28 #include <asm/uaccess.h>
29 #include <asm/io.h>
30 #include <asm/atomic.h>
31 #include <asm/smp.h>
32 #include <asm/pgalloc.h>
33 #include <asm/cpu-regs.h>
34 #include <asm/busctl-regs.h>
35 #include <asm/fpu.h>
36 #include <asm/gdb-stub.h>
37 #include <asm/asm-offsets.h>
38
39 #if 0
40 #define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
41 #else
42 #define kdebug(FMT, ...) do {} while (0)
43 #endif
44
45 static int misalignment_addr(unsigned long *registers, unsigned params,
46 unsigned opcode, unsigned long disp,
47 void **_address, unsigned long **_postinc,
48 unsigned long *_inc);
49
50 static int misalignment_reg(unsigned long *registers, unsigned params,
51 unsigned opcode, unsigned long disp,
52 unsigned long **_register);
53
54 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
55
56 static const unsigned Dreg_index[] = {
57 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
58 };
59
60 static const unsigned Areg_index[] = {
61 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
62 };
63
64 static const unsigned Rreg_index[] = {
65 REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
66 REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
67 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
68 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
69 };
70
71 enum format_id {
72 FMT_S0,
73 FMT_S1,
74 FMT_S2,
75 FMT_S4,
76 FMT_D0,
77 FMT_D1,
78 FMT_D2,
79 FMT_D4,
80 FMT_D6,
81 FMT_D7,
82 FMT_D8,
83 FMT_D9,
84 FMT_D10,
85 };
86
87 static const struct {
88 u_int8_t opsz, dispsz;
89 } format_tbl[16] = {
90 [FMT_S0] = { 8, 0 },
91 [FMT_S1] = { 8, 8 },
92 [FMT_S2] = { 8, 16 },
93 [FMT_S4] = { 8, 32 },
94 [FMT_D0] = { 16, 0 },
95 [FMT_D1] = { 16, 8 },
96 [FMT_D2] = { 16, 16 },
97 [FMT_D4] = { 16, 32 },
98 [FMT_D6] = { 24, 0 },
99 [FMT_D7] = { 24, 8 },
100 [FMT_D8] = { 24, 24 },
101 [FMT_D9] = { 24, 32 },
102 [FMT_D10] = { 32, 0 },
103 };
104
105 enum value_id {
106 DM0, /* data reg in opcode in bits 0-1 */
107 DM1, /* data reg in opcode in bits 2-3 */
108 DM2, /* data reg in opcode in bits 4-5 */
109 AM0, /* addr reg in opcode in bits 0-1 */
110 AM1, /* addr reg in opcode in bits 2-3 */
111 AM2, /* addr reg in opcode in bits 4-5 */
112 RM0, /* reg in opcode in bits 0-3 */
113 RM1, /* reg in opcode in bits 2-5 */
114 RM2, /* reg in opcode in bits 4-7 */
115 RM4, /* reg in opcode in bits 8-11 */
116 RM6, /* reg in opcode in bits 12-15 */
117
118 RD0, /* reg in displacement in bits 0-3 */
119 RD2, /* reg in displacement in bits 4-7 */
120
121 SP, /* stack pointer */
122
123 SD8, /* 8-bit signed displacement */
124 SD16, /* 16-bit signed displacement */
125 SD24, /* 24-bit signed displacement */
126 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
127 SIMM8, /* 8-bit signed immediate */
128 IMM8, /* 8-bit unsigned immediate */
129 IMM16, /* 16-bit unsigned immediate */
130 IMM24, /* 24-bit unsigned immediate */
131 IMM32, /* 32-bit unsigned immediate */
132 IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */
133
134 IMM32_MEM, /* 32-bit unsigned displacement */
135 IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */
136
137 DN0 = DM0,
138 DN1 = DM1,
139 DN2 = DM2,
140 AN0 = AM0,
141 AN1 = AM1,
142 AN2 = AM2,
143 RN0 = RM0,
144 RN1 = RM1,
145 RN2 = RM2,
146 RN4 = RM4,
147 RN6 = RM6,
148 DI = DM1,
149 RI = RM2,
150
151 };
152
153 struct mn10300_opcode {
154 const char name[8];
155 u_int32_t opcode;
156 u_int32_t opmask;
157 unsigned exclusion;
158
159 enum format_id format;
160
161 unsigned cpu_mask;
162 #define AM33 330
163
164 unsigned params[2];
165 #define MEM(ADDR) (0x80000000 | (ADDR))
166 #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
167 #define MEMINC(ADDR) (0x81000000 | (ADDR))
168 #define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
169 };
170
171 /* LIBOPCODES EXCERPT
172 Assemble Matsushita MN10300 instructions.
173 Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
174
175 This program is free software; you can redistribute it and/or modify
176 it under the terms of the GNU General Public Licence as published by
177 the Free Software Foundation; either version 2 of the Licence, or
178 (at your option) any later version.
179
180 This program is distributed in the hope that it will be useful,
181 but WITHOUT ANY WARRANTY; without even the implied warranty of
182 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
183 GNU General Public Licence for more details.
184
185 You should have received a copy of the GNU General Public Licence
186 along with this program; if not, write to the Free Software
187 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
188 */
189 static const struct mn10300_opcode mn10300_opcodes[] = {
190 { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
191 { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
192 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
193 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
194 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
195 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
196 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
197 { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
198 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
199 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
200 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
201 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
202 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
203 { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
204 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
205 { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
206 { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
207 { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
208 { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
209 { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
210 { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
211 { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
212 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
213 { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
214 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
215 { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
216 { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
217 { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
218 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
219 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
220 { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
221 { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
222 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
223 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
224 { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
225 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
226 { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
227 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
228 { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
229 { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
230 { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
231 { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
232 { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
233 { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
234 { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
235 { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
236 { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
237 { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
238 { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
239 { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
240 { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
241 { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
242 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
243 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
244 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
245 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
246 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
247 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
248 { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
249 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
250 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
251 { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
252 { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
253 { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
254 { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
255 { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
256
257 { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
258 { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
259 { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
260 { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
261 { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
262 { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
263 { "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
264 { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
265 { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
266 { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
267 { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
268 { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
269 { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
270 { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
271 { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
272 { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
273 { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
274 { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
275 { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
276 { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
277 { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
278 { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
279 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
280 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
281 { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
282 { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
283 { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
284 { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
285 { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
286 { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
287 { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
288 { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
289 { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
290 { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
291 { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
292 { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
293 { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
294 { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
295 { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
296 { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
297 { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
298 { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
299 { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
300 { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
301
302 { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
303 { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
304 { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
305 { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
306 { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
307 { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
308 { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
309 { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
310 { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
311 { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
312 { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
313
314 { "", 0, 0, 0, 0, 0, {0}},
315 };
316
317 /*
318 * fix up misalignment problems where possible
319 */
320 asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
321 {
322 const struct exception_table_entry *fixup;
323 const struct mn10300_opcode *pop;
324 unsigned long *registers = (unsigned long *) regs;
325 unsigned long data, *store, *postinc, disp, inc;
326 mm_segment_t seg;
327 siginfo_t info;
328 uint32_t opcode, noc, xo, xm;
329 uint8_t *pc, byte, datasz;
330 void *address;
331 unsigned tmp, npop, dispsz, loop;
332
333 kdebug("==>misalignment({pc=%lx})", regs->pc);
334
335 if (regs->epsw & EPSW_IE)
336 asm volatile("or %0,epsw" : : "i"(EPSW_IE));
337
338 seg = get_fs();
339 set_fs(KERNEL_DS);
340
341 fixup = search_exception_tables(regs->pc);
342
343 /* first thing to do is to match the opcode */
344 pc = (u_int8_t *) regs->pc;
345
346 if (__get_user(byte, pc) != 0)
347 goto fetch_error;
348 opcode = byte;
349 noc = 8;
350
351 for (pop = mn10300_opcodes; pop->name[0]; pop++) {
352 npop = ilog2(pop->opcode | pop->opmask);
353 if (npop <= 0 || npop > 31)
354 continue;
355 npop = (npop + 8) & ~7;
356
357 got_more_bits:
358 if (npop == noc) {
359 if ((opcode & pop->opmask) == pop->opcode)
360 goto found_opcode;
361 } else if (npop > noc) {
362 xo = pop->opcode >> (npop - noc);
363 xm = pop->opmask >> (npop - noc);
364
365 if ((opcode & xm) != xo)
366 continue;
367
368 /* we've got a partial match (an exact match on the
369 * first N bytes), so we need to get some more data */
370 pc++;
371 if (__get_user(byte, pc) != 0)
372 goto fetch_error;
373 opcode = opcode << 8 | byte;
374 noc += 8;
375 goto got_more_bits;
376 } else {
377 /* there's already been a partial match as long as the
378 * complete match we're now considering, so this one
379 * should't match */
380 continue;
381 }
382 }
383
384 /* didn't manage to find a fixup */
385 if (!user_mode(regs))
386 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
387 regs->pc, opcode);
388
389 failed:
390 set_fs(seg);
391 if (die_if_no_fixup("misalignment error", regs, code))
392 return;
393
394 info.si_signo = SIGBUS;
395 info.si_errno = 0;
396 info.si_code = BUS_ADRALN;
397 info.si_addr = (void *) regs->pc;
398 force_sig_info(SIGBUS, &info, current);
399 return;
400
401 /* error reading opcodes */
402 fetch_error:
403 if (!user_mode(regs))
404 printk(KERN_CRIT
405 "MISALIGN: %p: fault whilst reading instruction data\n",
406 pc);
407 goto failed;
408
409 bad_addr_mode:
410 if (!user_mode(regs))
411 printk(KERN_CRIT
412 "MISALIGN: %lx: unsupported addressing mode %x\n",
413 regs->pc, opcode);
414 goto failed;
415
416 bad_reg_mode:
417 if (!user_mode(regs))
418 printk(KERN_CRIT
419 "MISALIGN: %lx: unsupported register mode %x\n",
420 regs->pc, opcode);
421 goto failed;
422
423 unsupported_instruction:
424 if (!user_mode(regs))
425 printk(KERN_CRIT
426 "MISALIGN: %lx: unsupported instruction %x (%s)\n",
427 regs->pc, opcode, pop->name);
428 goto failed;
429
430 transfer_failed:
431 set_fs(seg);
432 if (fixup) {
433 regs->pc = fixup->fixup;
434 return;
435 }
436 if (die_if_no_fixup("misalignment fixup", regs, code))
437 return;
438
439 info.si_signo = SIGSEGV;
440 info.si_errno = 0;
441 info.si_code = 0;
442 info.si_addr = (void *) regs->pc;
443 force_sig_info(SIGSEGV, &info, current);
444 return;
445
446 /* we matched the opcode */
447 found_opcode:
448 kdebug("%lx: %x==%x { %x, %x }",
449 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
450
451 tmp = format_tbl[pop->format].opsz;
452 if (tmp > noc)
453 BUG(); /* match was less complete than it ought to have been */
454
455 if (tmp < noc) {
456 tmp = noc - tmp;
457 opcode >>= tmp;
458 pc -= tmp >> 3;
459 }
460
461 /* grab the extra displacement (note it's LSB first) */
462 disp = 0;
463 dispsz = format_tbl[pop->format].dispsz;
464 for (loop = 0; loop < dispsz; loop += 8) {
465 pc++;
466 if (__get_user(byte, pc) != 0)
467 goto fetch_error;
468 disp |= byte << loop;
469 kdebug("{%p} disp[%02x]=%02x", pc, loop, byte);
470 }
471
472 kdebug("disp=%lx", disp);
473
474 set_fs(KERNEL_XDS);
475 if (fixup || regs->epsw & EPSW_nSL)
476 set_fs(seg);
477
478 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
479 if (!tmp) {
480 if (!user_mode(regs))
481 printk(KERN_CRIT
482 "MISALIGN: %lx:"
483 " insn not move to/from memory %x\n",
484 regs->pc, opcode);
485 goto failed;
486 }
487
488 /* determine the data transfer size of the move */
489 if (pop->name[3] == 0 || /* "mov" */
490 pop->name[4] == 'l') /* mov_lcc */
491 inc = datasz = 4;
492 else if (pop->name[3] == 'h') /* movhu */
493 inc = datasz = 2;
494 else
495 goto unsupported_instruction;
496
497 if (pop->params[0] & 0x80000000) {
498 /* move memory to register */
499 if (!misalignment_addr(registers, pop->params[0], opcode, disp,
500 &address, &postinc, &inc))
501 goto bad_addr_mode;
502
503 if (!misalignment_reg(registers, pop->params[1], opcode, disp,
504 &store))
505 goto bad_reg_mode;
506
507 kdebug("mov%u (%p),DARn", datasz, address);
508 if (copy_from_user(&data, (void *) address, datasz) != 0)
509 goto transfer_failed;
510 if (pop->params[0] & 0x1000000) {
511 kdebug("inc=%lx", inc);
512 *postinc += inc;
513 }
514
515 *store = data;
516 kdebug("loaded %lx", data);
517 } else {
518 /* move register to memory */
519 if (!misalignment_reg(registers, pop->params[0], opcode, disp,
520 &store))
521 goto bad_reg_mode;
522
523 if (!misalignment_addr(registers, pop->params[1], opcode, disp,
524 &address, &postinc, &inc))
525 goto bad_addr_mode;
526
527 data = *store;
528
529 kdebug("mov%u %lx,(%p)", datasz, data, address);
530 if (copy_to_user((void *) address, &data, datasz) != 0)
531 goto transfer_failed;
532 if (pop->params[1] & 0x1000000)
533 *postinc += inc;
534 }
535
536 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
537 regs->pc += tmp >> 3;
538
539 /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
540 * access memory */
541 if (pop->format == FMT_D10)
542 misalignment_MOV_Lcc(regs, opcode);
543
544 set_fs(seg);
545 return;
546 }
547
548 /*
549 * determine the address that was being accessed
550 */
551 static int misalignment_addr(unsigned long *registers, unsigned params,
552 unsigned opcode, unsigned long disp,
553 void **_address, unsigned long **_postinc,
554 unsigned long *_inc)
555 {
556 unsigned long *postinc = NULL, address = 0, tmp;
557
558 if (!(params & 0x1000000)) {
559 kdebug("noinc");
560 *_inc = 0;
561 _inc = NULL;
562 }
563
564 params &= 0x00ffffff;
565
566 do {
567 switch (params & 0xff) {
568 case DM0:
569 postinc = &registers[Dreg_index[opcode & 0x03]];
570 address += *postinc;
571 break;
572 case DM1:
573 postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
574 address += *postinc;
575 break;
576 case DM2:
577 postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
578 address += *postinc;
579 break;
580 case AM0:
581 postinc = &registers[Areg_index[opcode & 0x03]];
582 address += *postinc;
583 break;
584 case AM1:
585 postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
586 address += *postinc;
587 break;
588 case AM2:
589 postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
590 address += *postinc;
591 break;
592 case RM0:
593 postinc = &registers[Rreg_index[opcode & 0x0f]];
594 address += *postinc;
595 break;
596 case RM1:
597 postinc = &registers[Rreg_index[opcode >> 2 & 0x0f]];
598 address += *postinc;
599 break;
600 case RM2:
601 postinc = &registers[Rreg_index[opcode >> 4 & 0x0f]];
602 address += *postinc;
603 break;
604 case RM4:
605 postinc = &registers[Rreg_index[opcode >> 8 & 0x0f]];
606 address += *postinc;
607 break;
608 case RM6:
609 postinc = &registers[Rreg_index[opcode >> 12 & 0x0f]];
610 address += *postinc;
611 break;
612 case RD0:
613 postinc = &registers[Rreg_index[disp & 0x0f]];
614 address += *postinc;
615 break;
616 case RD2:
617 postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
618 address += *postinc;
619 break;
620 case SP:
621 address += registers[REG_SP >> 2];
622 break;
623
624 /* displacements are either to be added to the address
625 * before use, or, in the case of post-inc addressing,
626 * to be added into the base register after use */
627 case SD8:
628 case SIMM8:
629 disp = (long) (int8_t) (disp & 0xff);
630 goto displace_or_inc;
631 case SD16:
632 disp = (long) (int16_t) (disp & 0xffff);
633 goto displace_or_inc;
634 case SD24:
635 tmp = disp << 8;
636 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
637 disp = (long) tmp;
638 goto displace_or_inc;
639 case SIMM4_2:
640 tmp = opcode >> 4 & 0x0f;
641 tmp <<= 28;
642 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
643 disp = (long) tmp;
644 goto displace_or_inc;
645 case IMM24:
646 disp &= 0x00ffffff;
647 goto displace_or_inc;
648 case IMM32:
649 case IMM32_MEM:
650 case IMM32_HIGH8:
651 case IMM32_HIGH8_MEM:
652 displace_or_inc:
653 kdebug("%s %lx", _inc ? "incr" : "disp", disp);
654 if (!_inc)
655 address += disp;
656 else
657 *_inc = disp;
658 break;
659 default:
660 BUG();
661 return 0;
662 }
663 } while ((params >>= 8));
664
665 *_address = (void *) address;
666 *_postinc = postinc;
667 return 1;
668 }
669
670 /*
671 * determine the register that is acting as source/dest
672 */
673 static int misalignment_reg(unsigned long *registers, unsigned params,
674 unsigned opcode, unsigned long disp,
675 unsigned long **_register)
676 {
677 params &= 0x7fffffff;
678
679 if (params & 0xffffff00)
680 return 0;
681
682 switch (params & 0xff) {
683 case DM0:
684 *_register = &registers[Dreg_index[opcode & 0x03]];
685 break;
686 case DM1:
687 *_register = &registers[Dreg_index[opcode >> 2 & 0x03]];
688 break;
689 case DM2:
690 *_register = &registers[Dreg_index[opcode >> 4 & 0x03]];
691 break;
692 case AM0:
693 *_register = &registers[Areg_index[opcode & 0x03]];
694 break;
695 case AM1:
696 *_register = &registers[Areg_index[opcode >> 2 & 0x03]];
697 break;
698 case AM2:
699 *_register = &registers[Areg_index[opcode >> 4 & 0x03]];
700 break;
701 case RM0:
702 *_register = &registers[Rreg_index[opcode & 0x0f]];
703 break;
704 case RM1:
705 *_register = &registers[Rreg_index[opcode >> 2 & 0x0f]];
706 break;
707 case RM2:
708 *_register = &registers[Rreg_index[opcode >> 4 & 0x0f]];
709 break;
710 case RM4:
711 *_register = &registers[Rreg_index[opcode >> 8 & 0x0f]];
712 break;
713 case RM6:
714 *_register = &registers[Rreg_index[opcode >> 12 & 0x0f]];
715 break;
716 case RD0:
717 *_register = &registers[Rreg_index[disp & 0x0f]];
718 break;
719 case RD2:
720 *_register = &registers[Rreg_index[disp >> 4 & 0x0f]];
721 break;
722 case SP:
723 *_register = &registers[REG_SP >> 2];
724 break;
725
726 default:
727 BUG();
728 return 0;
729 }
730
731 return 1;
732 }
733
734 /*
735 * handle the conditional loop part of the move-and-loop instructions
736 */
737 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
738 {
739 unsigned long epsw = regs->epsw;
740 unsigned long NxorV;
741
742 kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
743
744 /* calculate N^V and shift onto the same bit position as Z */
745 NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
746
747 switch (opcode & 0xf) {
748 case 0x0: /* MOV_LLT: N^V */
749 if (NxorV)
750 goto take_the_loop;
751 return;
752 case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
753 if (!((epsw & EPSW_FLAG_Z) | NxorV))
754 goto take_the_loop;
755 return;
756 case 0x2: /* MOV_LGE: ~(N^V) */
757 if (!NxorV)
758 goto take_the_loop;
759 return;
760 case 0x3: /* MOV_LLE: Z or (N^V) */
761 if ((epsw & EPSW_FLAG_Z) | NxorV)
762 goto take_the_loop;
763 return;
764
765 case 0x4: /* MOV_LCS: C */
766 if (epsw & EPSW_FLAG_C)
767 goto take_the_loop;
768 return;
769 case 0x5: /* MOV_LHI: ~(C or Z) */
770 if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
771 goto take_the_loop;
772 return;
773 case 0x6: /* MOV_LCC: ~C */
774 if (!(epsw & EPSW_FLAG_C))
775 goto take_the_loop;
776 return;
777 case 0x7: /* MOV_LLS: C or Z */
778 if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
779 goto take_the_loop;
780 return;
781
782 case 0x8: /* MOV_LEQ: Z */
783 if (epsw & EPSW_FLAG_Z)
784 goto take_the_loop;
785 return;
786 case 0x9: /* MOV_LNE: ~Z */
787 if (!(epsw & EPSW_FLAG_Z))
788 goto take_the_loop;
789 return;
790 case 0xa: /* MOV_LRA: always */
791 goto take_the_loop;
792
793 default:
794 BUG();
795 }
796
797 take_the_loop:
798 /* wind the PC back to just after the SETLB insn */
799 kdebug("loop LAR=%lx", regs->lar);
800 regs->pc = regs->lar - 4;
801 }
802
803 /*
804 * misalignment handler tests
805 */
806 #ifdef CONFIG_TEST_MISALIGNMENT_HANDLER
807 static u8 __initdata testbuf[512] __attribute__((aligned(16))) = {
808 [257] = 0x11,
809 [258] = 0x22,
810 [259] = 0x33,
811 [260] = 0x44,
812 };
813
814 #define ASSERTCMP(X, OP, Y) \
815 do { \
816 if (unlikely(!((X) OP (Y)))) { \
817 printk(KERN_ERR "\n"); \
818 printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \
819 __LINE__); \
820 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
821 (unsigned long)(X), (unsigned long)(Y)); \
822 BUG(); \
823 } \
824 } while(0)
825
826 static int __init test_misalignment(void)
827 {
828 register void *r asm("e0");
829 register u32 y asm("e1");
830 void *p = testbuf, *q;
831 u32 tmp, tmp2, x;
832
833 printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p);
834 p++;
835
836 printk(KERN_NOTICE "___ MOV (Am),Dn ___\n");
837 q = p + 256;
838 asm volatile("mov (%0),%1" : "+a"(q), "=d"(x));
839 ASSERTCMP(q, ==, p + 256);
840 ASSERTCMP(x, ==, 0x44332211);
841
842 printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n");
843 q = p;
844 asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x));
845 ASSERTCMP(q, ==, p);
846 ASSERTCMP(x, ==, 0x44332211);
847
848 printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n");
849 tmp = 256;
850 q = p;
851 asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp));
852 ASSERTCMP(q, ==, p);
853 ASSERTCMP(x, ==, 0x44332211);
854 ASSERTCMP(tmp, ==, 256);
855
856 printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n");
857 r = p;
858 asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y));
859 ASSERTCMP(r, ==, p);
860 ASSERTCMP(y, ==, 0x44332211);
861
862 printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n");
863 r = p + 256;
864 asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y));
865 ASSERTCMP(r, ==, p + 256 + 4);
866 ASSERTCMP(y, ==, 0x44332211);
867
868 printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n");
869 r = p + 256;
870 asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y));
871 ASSERTCMP(r, ==, p + 256 + 8);
872 ASSERTCMP(y, ==, 0x44332211);
873
874 printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n");
875 asm volatile(
876 "add -16,sp \n"
877 "mov +0x11,%0 \n"
878 "movbu %0,(7,sp) \n"
879 "mov +0x22,%0 \n"
880 "movbu %0,(8,sp) \n"
881 "mov +0x33,%0 \n"
882 "movbu %0,(9,sp) \n"
883 "mov +0x44,%0 \n"
884 "movbu %0,(10,sp) \n"
885 "mov (7,sp),%1 \n"
886 "add +16,sp \n"
887 : "+a"(q), "=d"(x));
888 ASSERTCMP(x, ==, 0x44332211);
889
890 printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n");
891 asm volatile(
892 "add -264,sp \n"
893 "mov +0x11,%0 \n"
894 "movbu %0,(259,sp) \n"
895 "mov +0x22,%0 \n"
896 "movbu %0,(260,sp) \n"
897 "mov +0x33,%0 \n"
898 "movbu %0,(261,sp) \n"
899 "mov +0x55,%0 \n"
900 "movbu %0,(262,sp) \n"
901 "mov (259,sp),%1 \n"
902 "add +264,sp \n"
903 : "+d"(tmp), "=d"(x));
904 ASSERTCMP(x, ==, 0x55332211);
905
906 printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n");
907 asm volatile(
908 "add -264,sp \n"
909 "mov +0x11,%0 \n"
910 "movbu %0,(260,sp) \n"
911 "mov +0x22,%0 \n"
912 "movbu %0,(261,sp) \n"
913 "mov +0x33,%0 \n"
914 "movbu %0,(262,sp) \n"
915 "mov +0x55,%0 \n"
916 "movbu %0,(263,sp) \n"
917 "mov (260,sp),%1 \n"
918 "add +264,sp \n"
919 : "+d"(tmp), "=d"(x));
920 ASSERTCMP(x, ==, 0x55332211);
921
922
923 printk(KERN_NOTICE "___ MOV_LNE ___\n");
924 tmp = 1;
925 tmp2 = 2;
926 q = p + 256;
927 asm volatile(
928 "setlb \n"
929 "mov %2,%3 \n"
930 "mov %1,%2 \n"
931 "cmp +0,%1 \n"
932 "mov_lne (%0+,4),%1"
933 : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
934 :
935 : "cc");
936 ASSERTCMP(q, ==, p + 256 + 12);
937 ASSERTCMP(x, ==, 0x44332211);
938
939 printk(KERN_NOTICE "___ MOV in SETLB ___\n");
940 tmp = 1;
941 tmp2 = 2;
942 q = p + 256;
943 asm volatile(
944 "setlb \n"
945 "mov %1,%3 \n"
946 "mov (%0+),%1 \n"
947 "cmp +0,%1 \n"
948 "lne "
949 : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
950 :
951 : "cc");
952
953 ASSERTCMP(q, ==, p + 256 + 8);
954 ASSERTCMP(x, ==, 0x44332211);
955
956 printk(KERN_NOTICE "<==test_misalignment()\n");
957 return 0;
958 }
959
960 arch_initcall(test_misalignment);
961
962 #endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */
CJK support for tty framebuffer vt