2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit
= 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) readl (ioaddr + (reg))
94 RTL_GIGA_MAC_NONE
= 0x00,
95 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
96 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27
= 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask
; /* Clears the bits supported by this chip */
131 } rtl_chip_info
[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device
*);
169 static void rtl_hw_start_8168(struct net_device
*);
170 static void rtl_hw_start_8101(struct net_device
*);
172 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
181 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
182 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
184 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
188 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
190 static int rx_buf_sz
= 16383;
197 MAC0
= 0, /* Ethernet hardware address. */
199 MAR0
= 8, /* Multicast filter. */
200 CounterAddrLow
= 0x10,
201 CounterAddrHigh
= 0x14,
202 TxDescStartAddrLow
= 0x20,
203 TxDescStartAddrHigh
= 0x24,
204 TxHDescStartAddrLow
= 0x28,
205 TxHDescStartAddrHigh
= 0x2c,
228 RxDescAddrLow
= 0xe4,
229 RxDescAddrHigh
= 0xe8,
232 FuncEventMask
= 0xf4,
233 FuncPresetState
= 0xf8,
234 FuncForceEvent
= 0xfc,
237 enum rtl8110_registers
{
243 enum rtl8168_8101_registers
{
246 #define CSIAR_FLAG 0x80000000
247 #define CSIAR_WRITE_CMD 0x80000000
248 #define CSIAR_BYTE_ENABLE 0x0f
249 #define CSIAR_BYTE_ENABLE_SHIFT 12
250 #define CSIAR_ADDR_MASK 0x0fff
253 #define EPHYAR_FLAG 0x80000000
254 #define EPHYAR_WRITE_CMD 0x80000000
255 #define EPHYAR_REG_MASK 0x1f
256 #define EPHYAR_REG_SHIFT 16
257 #define EPHYAR_DATA_MASK 0xffff
259 #define FIX_NAK_1 (1 << 4)
260 #define FIX_NAK_2 (1 << 3)
262 #define EFUSEAR_FLAG 0x80000000
263 #define EFUSEAR_WRITE_CMD 0x80000000
264 #define EFUSEAR_READ_CMD 0x00000000
265 #define EFUSEAR_REG_MASK 0x03ff
266 #define EFUSEAR_REG_SHIFT 8
267 #define EFUSEAR_DATA_MASK 0xff
270 enum rtl_register_content
{
271 /* InterruptStatusBits */
275 TxDescUnavail
= 0x0080,
297 /* TXPoll register p.5 */
298 HPQ
= 0x80, /* Poll cmd on the high prio queue */
299 NPQ
= 0x40, /* Poll cmd on the low prio queue */
300 FSWInt
= 0x01, /* Forced software interrupt */
304 Cfg9346_Unlock
= 0xc0,
309 AcceptBroadcast
= 0x08,
310 AcceptMulticast
= 0x04,
312 AcceptAllPhys
= 0x01,
319 TxInterFrameGapShift
= 24,
320 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
322 /* Config1 register p.24 */
325 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
326 Speed_down
= (1 << 4),
330 PMEnable
= (1 << 0), /* Power Management Enable */
332 /* Config2 register p. 25 */
333 PCI_Clock_66MHz
= 0x01,
334 PCI_Clock_33MHz
= 0x00,
336 /* Config3 register p.25 */
337 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
338 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
339 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
341 /* Config5 register p.27 */
342 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
344 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake
= (1 << 1), /* LanWake enable/disable */
346 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
349 TBIReset
= 0x80000000,
350 TBILoopback
= 0x40000000,
351 TBINwEnable
= 0x20000000,
352 TBINwRestart
= 0x10000000,
353 TBILinkOk
= 0x02000000,
354 TBINwComplete
= 0x01000000,
357 EnableBist
= (1 << 15), // 8168 8101
358 Mac_dbgo_oe
= (1 << 14), // 8168 8101
359 Normal_mode
= (1 << 13), // unused
360 Force_half_dup
= (1 << 12), // 8168 8101
361 Force_rxflow_en
= (1 << 11), // 8168 8101
362 Force_txflow_en
= (1 << 10), // 8168 8101
363 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
364 ASF
= (1 << 8), // 8168 8101
365 PktCntrDisable
= (1 << 7), // 8168 8101
366 Mac_dbgo_sel
= 0x001c, // 8168
371 INTT_0
= 0x0000, // 8168
372 INTT_1
= 0x0001, // 8168
373 INTT_2
= 0x0002, // 8168
374 INTT_3
= 0x0003, // 8168
376 /* rtl8169_PHYstatus */
387 TBILinkOK
= 0x02000000,
389 /* DumpCounterCommand */
393 enum desc_status_bit
{
394 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
395 RingEnd
= (1 << 30), /* End of descriptor ring */
396 FirstFrag
= (1 << 29), /* First segment of a packet */
397 LastFrag
= (1 << 28), /* Final segment of a packet */
400 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
401 MSSShift
= 16, /* MSS value position */
402 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
403 IPCS
= (1 << 18), /* Calculate IP checksum */
404 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
405 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
406 TxVlanTag
= (1 << 17), /* Add VLAN tag */
409 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
410 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
412 #define RxProtoUDP (PID1)
413 #define RxProtoTCP (PID0)
414 #define RxProtoIP (PID1 | PID0)
415 #define RxProtoMask RxProtoIP
417 IPFail
= (1 << 16), /* IP checksum failed */
418 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
419 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
420 RxVlanTag
= (1 << 16), /* VLAN tag available */
423 #define RsvdMask 0x3fffc000
440 u8 __pad
[sizeof(void *) - sizeof(u32
)];
444 RTL_FEATURE_WOL
= (1 << 0),
445 RTL_FEATURE_MSI
= (1 << 1),
446 RTL_FEATURE_GMII
= (1 << 2),
449 struct rtl8169_counters
{
456 __le32 tx_one_collision
;
457 __le32 tx_multi_collision
;
465 struct rtl8169_private
{
466 void __iomem
*mmio_addr
; /* memory map physical address */
467 struct pci_dev
*pci_dev
; /* Index of PCI device */
468 struct net_device
*dev
;
469 struct napi_struct napi
;
470 spinlock_t lock
; /* spin lock flag */
474 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
475 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
478 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
479 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
480 dma_addr_t TxPhyAddr
;
481 dma_addr_t RxPhyAddr
;
482 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
483 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
484 struct timer_list timer
;
489 int phy_1000_ctrl_reg
;
490 #ifdef CONFIG_R8169_VLAN
491 struct vlan_group
*vlgrp
;
493 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
494 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
495 void (*phy_reset_enable
)(void __iomem
*);
496 void (*hw_start
)(struct net_device
*);
497 unsigned int (*phy_reset_pending
)(void __iomem
*);
498 unsigned int (*link_ok
)(void __iomem
*);
499 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
501 struct delayed_work task
;
504 struct mii_if_info mii
;
505 struct rtl8169_counters counters
;
509 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
510 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
511 module_param(use_dac
, int, 0);
512 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
513 module_param_named(debug
, debug
.msg_enable
, int, 0);
514 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
515 MODULE_LICENSE("GPL");
516 MODULE_VERSION(RTL8169_VERSION
);
518 static int rtl8169_open(struct net_device
*dev
);
519 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
520 struct net_device
*dev
);
521 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
522 static int rtl8169_init_ring(struct net_device
*dev
);
523 static void rtl_hw_start(struct net_device
*dev
);
524 static int rtl8169_close(struct net_device
*dev
);
525 static void rtl_set_rx_mode(struct net_device
*dev
);
526 static void rtl8169_tx_timeout(struct net_device
*dev
);
527 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
528 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
529 void __iomem
*, u32 budget
);
530 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
531 static void rtl8169_down(struct net_device
*dev
);
532 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
533 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
535 static const unsigned int rtl8169_rx_config
=
536 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
538 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
542 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
544 for (i
= 20; i
> 0; i
--) {
546 * Check if the RTL8169 has completed writing to the specified
549 if (!(RTL_R32(PHYAR
) & 0x80000000))
554 * According to hardware specs a 20us delay is required after write
555 * complete indication, but before sending next command.
560 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
564 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
566 for (i
= 20; i
> 0; i
--) {
568 * Check if the RTL8169 has completed retrieving data from
569 * the specified MII register.
571 if (RTL_R32(PHYAR
) & 0x80000000) {
572 value
= RTL_R32(PHYAR
) & 0xffff;
578 * According to hardware specs a 20us delay is required after read
579 * complete indication, but before sending next command.
586 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
588 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
591 static void mdio_plus_minus(void __iomem
*ioaddr
, int reg_addr
, int p
, int m
)
595 val
= mdio_read(ioaddr
, reg_addr
);
596 mdio_write(ioaddr
, reg_addr
, (val
| p
) & ~m
);
599 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
602 struct rtl8169_private
*tp
= netdev_priv(dev
);
603 void __iomem
*ioaddr
= tp
->mmio_addr
;
605 mdio_write(ioaddr
, location
, val
);
608 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
610 struct rtl8169_private
*tp
= netdev_priv(dev
);
611 void __iomem
*ioaddr
= tp
->mmio_addr
;
613 return mdio_read(ioaddr
, location
);
616 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
620 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
621 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
623 for (i
= 0; i
< 100; i
++) {
624 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
630 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
635 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
637 for (i
= 0; i
< 100; i
++) {
638 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
639 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
648 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
652 RTL_W32(CSIDR
, value
);
653 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
654 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
656 for (i
= 0; i
< 100; i
++) {
657 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
663 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
668 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
669 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
671 for (i
= 0; i
< 100; i
++) {
672 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
673 value
= RTL_R32(CSIDR
);
682 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
687 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
689 for (i
= 0; i
< 300; i
++) {
690 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
691 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
700 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
702 RTL_W16(IntrMask
, 0x0000);
704 RTL_W16(IntrStatus
, 0xffff);
707 static void rtl8169_asic_down(void __iomem
*ioaddr
)
709 RTL_W8(ChipCmd
, 0x00);
710 rtl8169_irq_mask_and_ack(ioaddr
);
714 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
716 return RTL_R32(TBICSR
) & TBIReset
;
719 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
721 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
724 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
726 return RTL_R32(TBICSR
) & TBILinkOk
;
729 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
731 return RTL_R8(PHYstatus
) & LinkStatus
;
734 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
736 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
739 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
743 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
744 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
747 static void rtl8169_check_link_status(struct net_device
*dev
,
748 struct rtl8169_private
*tp
,
749 void __iomem
*ioaddr
)
753 spin_lock_irqsave(&tp
->lock
, flags
);
754 if (tp
->link_ok(ioaddr
)) {
755 /* This is to cancel a scheduled suspend if there's one. */
756 pm_request_resume(&tp
->pci_dev
->dev
);
757 netif_carrier_on(dev
);
758 netif_info(tp
, ifup
, dev
, "link up\n");
760 netif_carrier_off(dev
);
761 netif_info(tp
, ifdown
, dev
, "link down\n");
762 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
764 spin_unlock_irqrestore(&tp
->lock
, flags
);
767 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
769 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
771 void __iomem
*ioaddr
= tp
->mmio_addr
;
775 options
= RTL_R8(Config1
);
776 if (!(options
& PMEnable
))
779 options
= RTL_R8(Config3
);
780 if (options
& LinkUp
)
782 if (options
& MagicPacket
)
783 wolopts
|= WAKE_MAGIC
;
785 options
= RTL_R8(Config5
);
787 wolopts
|= WAKE_UCAST
;
789 wolopts
|= WAKE_BCAST
;
791 wolopts
|= WAKE_MCAST
;
796 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
798 struct rtl8169_private
*tp
= netdev_priv(dev
);
800 spin_lock_irq(&tp
->lock
);
802 wol
->supported
= WAKE_ANY
;
803 wol
->wolopts
= __rtl8169_get_wol(tp
);
805 spin_unlock_irq(&tp
->lock
);
808 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
810 void __iomem
*ioaddr
= tp
->mmio_addr
;
812 static const struct {
817 { WAKE_ANY
, Config1
, PMEnable
},
818 { WAKE_PHY
, Config3
, LinkUp
},
819 { WAKE_MAGIC
, Config3
, MagicPacket
},
820 { WAKE_UCAST
, Config5
, UWF
},
821 { WAKE_BCAST
, Config5
, BWF
},
822 { WAKE_MCAST
, Config5
, MWF
},
823 { WAKE_ANY
, Config5
, LanWake
}
826 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
828 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
829 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
830 if (wolopts
& cfg
[i
].opt
)
831 options
|= cfg
[i
].mask
;
832 RTL_W8(cfg
[i
].reg
, options
);
835 RTL_W8(Cfg9346
, Cfg9346_Lock
);
838 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
840 struct rtl8169_private
*tp
= netdev_priv(dev
);
842 spin_lock_irq(&tp
->lock
);
845 tp
->features
|= RTL_FEATURE_WOL
;
847 tp
->features
&= ~RTL_FEATURE_WOL
;
848 __rtl8169_set_wol(tp
, wol
->wolopts
);
849 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
851 spin_unlock_irq(&tp
->lock
);
856 static void rtl8169_get_drvinfo(struct net_device
*dev
,
857 struct ethtool_drvinfo
*info
)
859 struct rtl8169_private
*tp
= netdev_priv(dev
);
861 strcpy(info
->driver
, MODULENAME
);
862 strcpy(info
->version
, RTL8169_VERSION
);
863 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
866 static int rtl8169_get_regs_len(struct net_device
*dev
)
868 return R8169_REGS_SIZE
;
871 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
872 u8 autoneg
, u16 speed
, u8 duplex
)
874 struct rtl8169_private
*tp
= netdev_priv(dev
);
875 void __iomem
*ioaddr
= tp
->mmio_addr
;
879 reg
= RTL_R32(TBICSR
);
880 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
881 (duplex
== DUPLEX_FULL
)) {
882 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
883 } else if (autoneg
== AUTONEG_ENABLE
)
884 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
886 netif_warn(tp
, link
, dev
,
887 "incorrect speed setting refused in TBI mode\n");
894 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
895 u8 autoneg
, u16 speed
, u8 duplex
)
897 struct rtl8169_private
*tp
= netdev_priv(dev
);
898 void __iomem
*ioaddr
= tp
->mmio_addr
;
901 if (autoneg
== AUTONEG_ENABLE
) {
904 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
905 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
906 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
907 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
909 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
910 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
912 /* The 8100e/8101e/8102e do Fast Ethernet only. */
913 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
914 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
915 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
916 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
917 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
918 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
919 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
920 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
921 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
923 netif_info(tp
, link
, dev
,
924 "PHY does not support 1000Mbps\n");
927 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
929 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
930 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
931 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
934 * Vendor specific (0x1f) and reserved (0x0e) MII
937 mdio_write(ioaddr
, 0x1f, 0x0000);
938 mdio_write(ioaddr
, 0x0e, 0x0000);
941 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
942 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
946 if (speed
== SPEED_10
)
948 else if (speed
== SPEED_100
)
949 bmcr
= BMCR_SPEED100
;
953 if (duplex
== DUPLEX_FULL
)
954 bmcr
|= BMCR_FULLDPLX
;
956 mdio_write(ioaddr
, 0x1f, 0x0000);
959 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
961 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
963 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
964 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
965 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
966 mdio_write(ioaddr
, 0x17, 0x2138);
967 mdio_write(ioaddr
, 0x0e, 0x0260);
969 mdio_write(ioaddr
, 0x17, 0x2108);
970 mdio_write(ioaddr
, 0x0e, 0x0000);
977 static int rtl8169_set_speed(struct net_device
*dev
,
978 u8 autoneg
, u16 speed
, u8 duplex
)
980 struct rtl8169_private
*tp
= netdev_priv(dev
);
983 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
985 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
986 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
991 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
993 struct rtl8169_private
*tp
= netdev_priv(dev
);
997 spin_lock_irqsave(&tp
->lock
, flags
);
998 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
999 spin_unlock_irqrestore(&tp
->lock
, flags
);
1004 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
1006 struct rtl8169_private
*tp
= netdev_priv(dev
);
1008 return tp
->cp_cmd
& RxChkSum
;
1011 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1013 struct rtl8169_private
*tp
= netdev_priv(dev
);
1014 void __iomem
*ioaddr
= tp
->mmio_addr
;
1015 unsigned long flags
;
1017 spin_lock_irqsave(&tp
->lock
, flags
);
1020 tp
->cp_cmd
|= RxChkSum
;
1022 tp
->cp_cmd
&= ~RxChkSum
;
1024 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1027 spin_unlock_irqrestore(&tp
->lock
, flags
);
1032 #ifdef CONFIG_R8169_VLAN
1034 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1035 struct sk_buff
*skb
)
1037 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
1038 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1041 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1042 struct vlan_group
*grp
)
1044 struct rtl8169_private
*tp
= netdev_priv(dev
);
1045 void __iomem
*ioaddr
= tp
->mmio_addr
;
1046 unsigned long flags
;
1048 spin_lock_irqsave(&tp
->lock
, flags
);
1051 * Do not disable RxVlan on 8110SCd.
1053 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1054 tp
->cp_cmd
|= RxVlan
;
1056 tp
->cp_cmd
&= ~RxVlan
;
1057 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1059 spin_unlock_irqrestore(&tp
->lock
, flags
);
1062 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1063 struct sk_buff
*skb
, int polling
)
1065 u32 opts2
= le32_to_cpu(desc
->opts2
);
1066 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1069 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1070 u16 vtag
= swab16(opts2
& 0xffff);
1072 if (likely(polling
))
1073 vlan_gro_receive(&tp
->napi
, vlgrp
, vtag
, skb
);
1075 __vlan_hwaccel_rx(skb
, vlgrp
, vtag
, polling
);
1083 #else /* !CONFIG_R8169_VLAN */
1085 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1086 struct sk_buff
*skb
)
1091 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1092 struct sk_buff
*skb
, int polling
)
1099 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1101 struct rtl8169_private
*tp
= netdev_priv(dev
);
1102 void __iomem
*ioaddr
= tp
->mmio_addr
;
1106 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1107 cmd
->port
= PORT_FIBRE
;
1108 cmd
->transceiver
= XCVR_INTERNAL
;
1110 status
= RTL_R32(TBICSR
);
1111 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1112 cmd
->autoneg
= !!(status
& TBINwEnable
);
1114 cmd
->speed
= SPEED_1000
;
1115 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1120 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1122 struct rtl8169_private
*tp
= netdev_priv(dev
);
1124 return mii_ethtool_gset(&tp
->mii
, cmd
);
1127 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1129 struct rtl8169_private
*tp
= netdev_priv(dev
);
1130 unsigned long flags
;
1133 spin_lock_irqsave(&tp
->lock
, flags
);
1135 rc
= tp
->get_settings(dev
, cmd
);
1137 spin_unlock_irqrestore(&tp
->lock
, flags
);
1141 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1144 struct rtl8169_private
*tp
= netdev_priv(dev
);
1145 unsigned long flags
;
1147 if (regs
->len
> R8169_REGS_SIZE
)
1148 regs
->len
= R8169_REGS_SIZE
;
1150 spin_lock_irqsave(&tp
->lock
, flags
);
1151 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1152 spin_unlock_irqrestore(&tp
->lock
, flags
);
1155 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1157 struct rtl8169_private
*tp
= netdev_priv(dev
);
1159 return tp
->msg_enable
;
1162 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1164 struct rtl8169_private
*tp
= netdev_priv(dev
);
1166 tp
->msg_enable
= value
;
1169 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1176 "tx_single_collisions",
1177 "tx_multi_collisions",
1185 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1189 return ARRAY_SIZE(rtl8169_gstrings
);
1195 static void rtl8169_update_counters(struct net_device
*dev
)
1197 struct rtl8169_private
*tp
= netdev_priv(dev
);
1198 void __iomem
*ioaddr
= tp
->mmio_addr
;
1199 struct rtl8169_counters
*counters
;
1205 * Some chips are unable to dump tally counters when the receiver
1208 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1211 counters
= dma_alloc_coherent(&tp
->pci_dev
->dev
, sizeof(*counters
),
1212 &paddr
, GFP_KERNEL
);
1216 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1217 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1218 RTL_W32(CounterAddrLow
, cmd
);
1219 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1222 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1223 /* copy updated counters */
1224 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1230 RTL_W32(CounterAddrLow
, 0);
1231 RTL_W32(CounterAddrHigh
, 0);
1233 dma_free_coherent(&tp
->pci_dev
->dev
, sizeof(*counters
), counters
,
1237 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1238 struct ethtool_stats
*stats
, u64
*data
)
1240 struct rtl8169_private
*tp
= netdev_priv(dev
);
1244 rtl8169_update_counters(dev
);
1246 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1247 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1248 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1249 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1250 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1251 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1252 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1253 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1254 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1255 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1256 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1257 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1258 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1261 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1265 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1270 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1271 .get_drvinfo
= rtl8169_get_drvinfo
,
1272 .get_regs_len
= rtl8169_get_regs_len
,
1273 .get_link
= ethtool_op_get_link
,
1274 .get_settings
= rtl8169_get_settings
,
1275 .set_settings
= rtl8169_set_settings
,
1276 .get_msglevel
= rtl8169_get_msglevel
,
1277 .set_msglevel
= rtl8169_set_msglevel
,
1278 .get_rx_csum
= rtl8169_get_rx_csum
,
1279 .set_rx_csum
= rtl8169_set_rx_csum
,
1280 .set_tx_csum
= ethtool_op_set_tx_csum
,
1281 .set_sg
= ethtool_op_set_sg
,
1282 .set_tso
= ethtool_op_set_tso
,
1283 .get_regs
= rtl8169_get_regs
,
1284 .get_wol
= rtl8169_get_wol
,
1285 .set_wol
= rtl8169_set_wol
,
1286 .get_strings
= rtl8169_get_strings
,
1287 .get_sset_count
= rtl8169_get_sset_count
,
1288 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1291 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1292 void __iomem
*ioaddr
)
1295 * The driver currently handles the 8168Bf and the 8168Be identically
1296 * but they can be identified more specifically through the test below
1299 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1301 * Same thing for the 8101Eb and the 8101Ec:
1303 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1305 static const struct {
1311 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1312 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1313 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1314 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1317 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1318 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1319 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1320 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1321 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1322 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1323 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1324 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1325 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1328 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1329 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1330 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1331 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1334 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1335 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1336 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1337 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1338 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1339 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1340 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1341 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1342 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1343 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1344 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1345 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1346 /* FIXME: where did these entries come from ? -- FR */
1347 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1348 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1351 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1352 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1353 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1354 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1355 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1356 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1359 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1363 reg
= RTL_R32(TxConfig
);
1364 while ((reg
& p
->mask
) != p
->val
)
1366 tp
->mac_version
= p
->mac_version
;
1369 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1371 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1379 static void rtl_phy_write(void __iomem
*ioaddr
, const struct phy_reg
*regs
, int len
)
1382 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1387 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1389 static const struct phy_reg phy_reg_init
[] = {
1451 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1454 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1456 static const struct phy_reg phy_reg_init
[] = {
1462 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1465 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1466 void __iomem
*ioaddr
)
1468 struct pci_dev
*pdev
= tp
->pci_dev
;
1469 u16 vendor_id
, device_id
;
1471 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1472 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1474 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1477 mdio_write(ioaddr
, 0x1f, 0x0001);
1478 mdio_write(ioaddr
, 0x10, 0xf01b);
1479 mdio_write(ioaddr
, 0x1f, 0x0000);
1482 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1483 void __iomem
*ioaddr
)
1485 static const struct phy_reg phy_reg_init
[] = {
1525 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1527 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1530 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1532 static const struct phy_reg phy_reg_init
[] = {
1580 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1583 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1585 static const struct phy_reg phy_reg_init
[] = {
1590 mdio_write(ioaddr
, 0x1f, 0x0001);
1591 mdio_patch(ioaddr
, 0x16, 1 << 0);
1593 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1596 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1598 static const struct phy_reg phy_reg_init
[] = {
1604 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1607 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1609 static const struct phy_reg phy_reg_init
[] = {
1617 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1620 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1622 static const struct phy_reg phy_reg_init
[] = {
1628 mdio_write(ioaddr
, 0x1f, 0x0000);
1629 mdio_patch(ioaddr
, 0x14, 1 << 5);
1630 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1632 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1635 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1637 static const struct phy_reg phy_reg_init
[] = {
1657 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1659 mdio_patch(ioaddr
, 0x14, 1 << 5);
1660 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1661 mdio_write(ioaddr
, 0x1f, 0x0000);
1664 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1666 static const struct phy_reg phy_reg_init
[] = {
1684 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1686 mdio_patch(ioaddr
, 0x16, 1 << 0);
1687 mdio_patch(ioaddr
, 0x14, 1 << 5);
1688 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1689 mdio_write(ioaddr
, 0x1f, 0x0000);
1692 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1694 static const struct phy_reg phy_reg_init
[] = {
1706 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1708 mdio_patch(ioaddr
, 0x16, 1 << 0);
1709 mdio_patch(ioaddr
, 0x14, 1 << 5);
1710 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1711 mdio_write(ioaddr
, 0x1f, 0x0000);
1714 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1716 rtl8168c_3_hw_phy_config(ioaddr
);
1719 static void rtl8168d_1_hw_phy_config(void __iomem
*ioaddr
)
1721 static const struct phy_reg phy_reg_init_0
[] = {
1740 static const struct phy_reg phy_reg_init_1
[] = {
1747 static const struct phy_reg phy_reg_init_2
[] = {
2103 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2105 mdio_write(ioaddr
, 0x1f, 0x0002);
2106 mdio_plus_minus(ioaddr
, 0x0b, 0x0010, 0x00ef);
2107 mdio_plus_minus(ioaddr
, 0x0c, 0xa200, 0x5d00);
2109 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2111 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2112 static const struct phy_reg phy_reg_init
[] = {
2122 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2124 val
= mdio_read(ioaddr
, 0x0d);
2126 if ((val
& 0x00ff) != 0x006c) {
2127 static const u32 set
[] = {
2128 0x0065, 0x0066, 0x0067, 0x0068,
2129 0x0069, 0x006a, 0x006b, 0x006c
2133 mdio_write(ioaddr
, 0x1f, 0x0002);
2136 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2137 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2140 static const struct phy_reg phy_reg_init
[] = {
2148 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2151 mdio_write(ioaddr
, 0x1f, 0x0002);
2152 mdio_patch(ioaddr
, 0x0d, 0x0300);
2153 mdio_patch(ioaddr
, 0x0f, 0x0010);
2155 mdio_write(ioaddr
, 0x1f, 0x0002);
2156 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2157 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2159 rtl_phy_write(ioaddr
, phy_reg_init_2
, ARRAY_SIZE(phy_reg_init_2
));
2162 static void rtl8168d_2_hw_phy_config(void __iomem
*ioaddr
)
2164 static const struct phy_reg phy_reg_init_0
[] = {
2189 static const struct phy_reg phy_reg_init_1
[] = {
2502 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2504 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2505 static const struct phy_reg phy_reg_init
[] = {
2516 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2518 val
= mdio_read(ioaddr
, 0x0d);
2519 if ((val
& 0x00ff) != 0x006c) {
2521 0x0065, 0x0066, 0x0067, 0x0068,
2522 0x0069, 0x006a, 0x006b, 0x006c
2526 mdio_write(ioaddr
, 0x1f, 0x0002);
2529 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2530 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2533 static const struct phy_reg phy_reg_init
[] = {
2541 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2544 mdio_write(ioaddr
, 0x1f, 0x0002);
2545 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2546 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2548 mdio_write(ioaddr
, 0x1f, 0x0001);
2549 mdio_write(ioaddr
, 0x17, 0x0cc0);
2551 mdio_write(ioaddr
, 0x1f, 0x0002);
2552 mdio_patch(ioaddr
, 0x0f, 0x0017);
2554 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2557 static void rtl8168d_3_hw_phy_config(void __iomem
*ioaddr
)
2559 static const struct phy_reg phy_reg_init
[] = {
2615 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2618 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
2620 static const struct phy_reg phy_reg_init
[] = {
2627 mdio_write(ioaddr
, 0x1f, 0x0000);
2628 mdio_patch(ioaddr
, 0x11, 1 << 12);
2629 mdio_patch(ioaddr
, 0x19, 1 << 13);
2630 mdio_patch(ioaddr
, 0x10, 1 << 15);
2632 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2635 static void rtl_hw_phy_config(struct net_device
*dev
)
2637 struct rtl8169_private
*tp
= netdev_priv(dev
);
2638 void __iomem
*ioaddr
= tp
->mmio_addr
;
2640 rtl8169_print_mac_version(tp
);
2642 switch (tp
->mac_version
) {
2643 case RTL_GIGA_MAC_VER_01
:
2645 case RTL_GIGA_MAC_VER_02
:
2646 case RTL_GIGA_MAC_VER_03
:
2647 rtl8169s_hw_phy_config(ioaddr
);
2649 case RTL_GIGA_MAC_VER_04
:
2650 rtl8169sb_hw_phy_config(ioaddr
);
2652 case RTL_GIGA_MAC_VER_05
:
2653 rtl8169scd_hw_phy_config(tp
, ioaddr
);
2655 case RTL_GIGA_MAC_VER_06
:
2656 rtl8169sce_hw_phy_config(ioaddr
);
2658 case RTL_GIGA_MAC_VER_07
:
2659 case RTL_GIGA_MAC_VER_08
:
2660 case RTL_GIGA_MAC_VER_09
:
2661 rtl8102e_hw_phy_config(ioaddr
);
2663 case RTL_GIGA_MAC_VER_11
:
2664 rtl8168bb_hw_phy_config(ioaddr
);
2666 case RTL_GIGA_MAC_VER_12
:
2667 rtl8168bef_hw_phy_config(ioaddr
);
2669 case RTL_GIGA_MAC_VER_17
:
2670 rtl8168bef_hw_phy_config(ioaddr
);
2672 case RTL_GIGA_MAC_VER_18
:
2673 rtl8168cp_1_hw_phy_config(ioaddr
);
2675 case RTL_GIGA_MAC_VER_19
:
2676 rtl8168c_1_hw_phy_config(ioaddr
);
2678 case RTL_GIGA_MAC_VER_20
:
2679 rtl8168c_2_hw_phy_config(ioaddr
);
2681 case RTL_GIGA_MAC_VER_21
:
2682 rtl8168c_3_hw_phy_config(ioaddr
);
2684 case RTL_GIGA_MAC_VER_22
:
2685 rtl8168c_4_hw_phy_config(ioaddr
);
2687 case RTL_GIGA_MAC_VER_23
:
2688 case RTL_GIGA_MAC_VER_24
:
2689 rtl8168cp_2_hw_phy_config(ioaddr
);
2691 case RTL_GIGA_MAC_VER_25
:
2692 rtl8168d_1_hw_phy_config(ioaddr
);
2694 case RTL_GIGA_MAC_VER_26
:
2695 rtl8168d_2_hw_phy_config(ioaddr
);
2697 case RTL_GIGA_MAC_VER_27
:
2698 rtl8168d_3_hw_phy_config(ioaddr
);
2706 static void rtl8169_phy_timer(unsigned long __opaque
)
2708 struct net_device
*dev
= (struct net_device
*)__opaque
;
2709 struct rtl8169_private
*tp
= netdev_priv(dev
);
2710 struct timer_list
*timer
= &tp
->timer
;
2711 void __iomem
*ioaddr
= tp
->mmio_addr
;
2712 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2714 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2716 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2719 spin_lock_irq(&tp
->lock
);
2721 if (tp
->phy_reset_pending(ioaddr
)) {
2723 * A busy loop could burn quite a few cycles on nowadays CPU.
2724 * Let's delay the execution of the timer for a few ticks.
2730 if (tp
->link_ok(ioaddr
))
2733 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2735 tp
->phy_reset_enable(ioaddr
);
2738 mod_timer(timer
, jiffies
+ timeout
);
2740 spin_unlock_irq(&tp
->lock
);
2743 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2745 struct rtl8169_private
*tp
= netdev_priv(dev
);
2746 struct timer_list
*timer
= &tp
->timer
;
2748 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2751 del_timer_sync(timer
);
2754 static inline void rtl8169_request_timer(struct net_device
*dev
)
2756 struct rtl8169_private
*tp
= netdev_priv(dev
);
2757 struct timer_list
*timer
= &tp
->timer
;
2759 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2762 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2765 #ifdef CONFIG_NET_POLL_CONTROLLER
2767 * Polling 'interrupt' - used by things like netconsole to send skbs
2768 * without having to re-enable interrupts. It's not called while
2769 * the interrupt routine is executing.
2771 static void rtl8169_netpoll(struct net_device
*dev
)
2773 struct rtl8169_private
*tp
= netdev_priv(dev
);
2774 struct pci_dev
*pdev
= tp
->pci_dev
;
2776 disable_irq(pdev
->irq
);
2777 rtl8169_interrupt(pdev
->irq
, dev
);
2778 enable_irq(pdev
->irq
);
2782 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2783 void __iomem
*ioaddr
)
2786 pci_release_regions(pdev
);
2787 pci_clear_mwi(pdev
);
2788 pci_disable_device(pdev
);
2792 static void rtl8169_phy_reset(struct net_device
*dev
,
2793 struct rtl8169_private
*tp
)
2795 void __iomem
*ioaddr
= tp
->mmio_addr
;
2798 tp
->phy_reset_enable(ioaddr
);
2799 for (i
= 0; i
< 100; i
++) {
2800 if (!tp
->phy_reset_pending(ioaddr
))
2804 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2807 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2809 void __iomem
*ioaddr
= tp
->mmio_addr
;
2811 rtl_hw_phy_config(dev
);
2813 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2814 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2818 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2820 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2821 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2823 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2824 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2826 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2827 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
2830 rtl8169_phy_reset(dev
, tp
);
2833 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2834 * only 8101. Don't panic.
2836 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2838 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2839 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2842 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2844 void __iomem
*ioaddr
= tp
->mmio_addr
;
2848 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2849 high
= addr
[4] | (addr
[5] << 8);
2851 spin_lock_irq(&tp
->lock
);
2853 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2855 RTL_W32(MAC4
, high
);
2861 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2863 spin_unlock_irq(&tp
->lock
);
2866 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2868 struct rtl8169_private
*tp
= netdev_priv(dev
);
2869 struct sockaddr
*addr
= p
;
2871 if (!is_valid_ether_addr(addr
->sa_data
))
2872 return -EADDRNOTAVAIL
;
2874 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2876 rtl_rar_set(tp
, dev
->dev_addr
);
2881 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2883 struct rtl8169_private
*tp
= netdev_priv(dev
);
2884 struct mii_ioctl_data
*data
= if_mii(ifr
);
2886 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2889 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2893 data
->phy_id
= 32; /* Internal PHY */
2897 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
2901 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2907 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2912 static const struct rtl_cfg_info
{
2913 void (*hw_start
)(struct net_device
*);
2914 unsigned int region
;
2920 } rtl_cfg_infos
[] = {
2922 .hw_start
= rtl_hw_start_8169
,
2925 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2926 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2927 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2928 .features
= RTL_FEATURE_GMII
,
2929 .default_ver
= RTL_GIGA_MAC_VER_01
,
2932 .hw_start
= rtl_hw_start_8168
,
2935 .intr_event
= SYSErr
| RxFIFOOver
| LinkChg
| RxOverflow
|
2936 TxErr
| TxOK
| RxOK
| RxErr
,
2937 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2938 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2939 .default_ver
= RTL_GIGA_MAC_VER_11
,
2942 .hw_start
= rtl_hw_start_8101
,
2945 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2946 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2947 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2948 .features
= RTL_FEATURE_MSI
,
2949 .default_ver
= RTL_GIGA_MAC_VER_13
,
2953 /* Cfg9346_Unlock assumed. */
2954 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2955 const struct rtl_cfg_info
*cfg
)
2960 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2961 if (cfg
->features
& RTL_FEATURE_MSI
) {
2962 if (pci_enable_msi(pdev
)) {
2963 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2966 msi
= RTL_FEATURE_MSI
;
2969 RTL_W8(Config2
, cfg2
);
2973 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2975 if (tp
->features
& RTL_FEATURE_MSI
) {
2976 pci_disable_msi(pdev
);
2977 tp
->features
&= ~RTL_FEATURE_MSI
;
2981 static const struct net_device_ops rtl8169_netdev_ops
= {
2982 .ndo_open
= rtl8169_open
,
2983 .ndo_stop
= rtl8169_close
,
2984 .ndo_get_stats
= rtl8169_get_stats
,
2985 .ndo_start_xmit
= rtl8169_start_xmit
,
2986 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2987 .ndo_validate_addr
= eth_validate_addr
,
2988 .ndo_change_mtu
= rtl8169_change_mtu
,
2989 .ndo_set_mac_address
= rtl_set_mac_address
,
2990 .ndo_do_ioctl
= rtl8169_ioctl
,
2991 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2992 #ifdef CONFIG_R8169_VLAN
2993 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2995 #ifdef CONFIG_NET_POLL_CONTROLLER
2996 .ndo_poll_controller
= rtl8169_netpoll
,
3001 static int __devinit
3002 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3004 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3005 const unsigned int region
= cfg
->region
;
3006 struct rtl8169_private
*tp
;
3007 struct mii_if_info
*mii
;
3008 struct net_device
*dev
;
3009 void __iomem
*ioaddr
;
3013 if (netif_msg_drv(&debug
)) {
3014 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3015 MODULENAME
, RTL8169_VERSION
);
3018 dev
= alloc_etherdev(sizeof (*tp
));
3020 if (netif_msg_drv(&debug
))
3021 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3026 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3027 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3028 tp
= netdev_priv(dev
);
3031 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3035 mii
->mdio_read
= rtl_mdio_read
;
3036 mii
->mdio_write
= rtl_mdio_write
;
3037 mii
->phy_id_mask
= 0x1f;
3038 mii
->reg_num_mask
= 0x1f;
3039 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3041 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3042 rc
= pci_enable_device(pdev
);
3044 netif_err(tp
, probe
, dev
, "enable failure\n");
3045 goto err_out_free_dev_1
;
3048 if (pci_set_mwi(pdev
) < 0)
3049 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3051 /* make sure PCI base addr 1 is MMIO */
3052 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3053 netif_err(tp
, probe
, dev
,
3054 "region #%d not an MMIO resource, aborting\n",
3060 /* check for weird/broken PCI region reporting */
3061 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3062 netif_err(tp
, probe
, dev
,
3063 "Invalid PCI region size(s), aborting\n");
3068 rc
= pci_request_regions(pdev
, MODULENAME
);
3070 netif_err(tp
, probe
, dev
, "could not request regions\n");
3074 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3076 if ((sizeof(dma_addr_t
) > 4) &&
3077 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3078 tp
->cp_cmd
|= PCIDAC
;
3079 dev
->features
|= NETIF_F_HIGHDMA
;
3081 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3083 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3084 goto err_out_free_res_3
;
3088 /* ioremap MMIO region */
3089 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3091 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3093 goto err_out_free_res_3
;
3096 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3098 netif_info(tp
, probe
, dev
, "no PCI Express capability\n");
3100 RTL_W16(IntrMask
, 0x0000);
3102 /* Soft reset the chip. */
3103 RTL_W8(ChipCmd
, CmdReset
);
3105 /* Check that the chip has finished the reset. */
3106 for (i
= 0; i
< 100; i
++) {
3107 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3109 msleep_interruptible(1);
3112 RTL_W16(IntrStatus
, 0xffff);
3114 pci_set_master(pdev
);
3116 /* Identify chip attached to board */
3117 rtl8169_get_mac_version(tp
, ioaddr
);
3119 /* Use appropriate default if unknown */
3120 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3121 netif_notice(tp
, probe
, dev
,
3122 "unknown MAC, using family default\n");
3123 tp
->mac_version
= cfg
->default_ver
;
3126 rtl8169_print_mac_version(tp
);
3128 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3129 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3132 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3134 "driver bug, MAC version not found in rtl_chip_info\n");
3139 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3140 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3141 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3142 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3143 tp
->features
|= RTL_FEATURE_WOL
;
3144 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3145 tp
->features
|= RTL_FEATURE_WOL
;
3146 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3147 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3149 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3150 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3151 tp
->set_speed
= rtl8169_set_speed_tbi
;
3152 tp
->get_settings
= rtl8169_gset_tbi
;
3153 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3154 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3155 tp
->link_ok
= rtl8169_tbi_link_ok
;
3156 tp
->do_ioctl
= rtl_tbi_ioctl
;
3158 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3160 tp
->set_speed
= rtl8169_set_speed_xmii
;
3161 tp
->get_settings
= rtl8169_gset_xmii
;
3162 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3163 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3164 tp
->link_ok
= rtl8169_xmii_link_ok
;
3165 tp
->do_ioctl
= rtl_xmii_ioctl
;
3168 spin_lock_init(&tp
->lock
);
3170 tp
->mmio_addr
= ioaddr
;
3172 /* Get MAC address */
3173 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3174 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3175 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3177 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3178 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3179 dev
->irq
= pdev
->irq
;
3180 dev
->base_addr
= (unsigned long) ioaddr
;
3182 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3184 #ifdef CONFIG_R8169_VLAN
3185 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3187 dev
->features
|= NETIF_F_GRO
;
3189 tp
->intr_mask
= 0xffff;
3190 tp
->hw_start
= cfg
->hw_start
;
3191 tp
->intr_event
= cfg
->intr_event
;
3192 tp
->napi_event
= cfg
->napi_event
;
3194 init_timer(&tp
->timer
);
3195 tp
->timer
.data
= (unsigned long) dev
;
3196 tp
->timer
.function
= rtl8169_phy_timer
;
3198 rc
= register_netdev(dev
);
3202 pci_set_drvdata(pdev
, dev
);
3204 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3205 rtl_chip_info
[tp
->chipset
].name
,
3206 dev
->base_addr
, dev
->dev_addr
,
3207 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3209 rtl8169_init_phy(dev
, tp
);
3212 * Pretend we are using VLANs; This bypasses a nasty bug where
3213 * Interrupts stop flowing on high load on 8110SCd controllers.
3215 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3216 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3218 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3220 if (pci_dev_run_wake(pdev
))
3221 pm_runtime_put_noidle(&pdev
->dev
);
3227 rtl_disable_msi(pdev
, tp
);
3230 pci_release_regions(pdev
);
3232 pci_clear_mwi(pdev
);
3233 pci_disable_device(pdev
);
3239 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3241 struct net_device
*dev
= pci_get_drvdata(pdev
);
3242 struct rtl8169_private
*tp
= netdev_priv(dev
);
3244 flush_scheduled_work();
3246 unregister_netdev(dev
);
3248 if (pci_dev_run_wake(pdev
))
3249 pm_runtime_get_noresume(&pdev
->dev
);
3251 /* restore original MAC address */
3252 rtl_rar_set(tp
, dev
->perm_addr
);
3254 rtl_disable_msi(pdev
, tp
);
3255 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3256 pci_set_drvdata(pdev
, NULL
);
3259 static int rtl8169_open(struct net_device
*dev
)
3261 struct rtl8169_private
*tp
= netdev_priv(dev
);
3262 struct pci_dev
*pdev
= tp
->pci_dev
;
3263 int retval
= -ENOMEM
;
3265 pm_runtime_get_sync(&pdev
->dev
);
3268 * Rx and Tx desscriptors needs 256 bytes alignment.
3269 * dma_alloc_coherent provides more.
3271 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3272 &tp
->TxPhyAddr
, GFP_KERNEL
);
3273 if (!tp
->TxDescArray
)
3274 goto err_pm_runtime_put
;
3276 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3277 &tp
->RxPhyAddr
, GFP_KERNEL
);
3278 if (!tp
->RxDescArray
)
3281 retval
= rtl8169_init_ring(dev
);
3285 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3289 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3290 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3293 goto err_release_ring_2
;
3295 napi_enable(&tp
->napi
);
3299 rtl8169_request_timer(dev
);
3301 tp
->saved_wolopts
= 0;
3302 pm_runtime_put_noidle(&pdev
->dev
);
3304 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3309 rtl8169_rx_clear(tp
);
3311 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3313 tp
->RxDescArray
= NULL
;
3315 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3317 tp
->TxDescArray
= NULL
;
3319 pm_runtime_put_noidle(&pdev
->dev
);
3323 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
3325 /* Disable interrupts */
3326 rtl8169_irq_mask_and_ack(ioaddr
);
3328 /* Reset the chipset */
3329 RTL_W8(ChipCmd
, CmdReset
);
3335 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3337 void __iomem
*ioaddr
= tp
->mmio_addr
;
3338 u32 cfg
= rtl8169_rx_config
;
3340 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3341 RTL_W32(RxConfig
, cfg
);
3343 /* Set DMA burst size and Interframe Gap Time */
3344 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3345 (InterFrameGap
<< TxInterFrameGapShift
));
3348 static void rtl_hw_start(struct net_device
*dev
)
3350 struct rtl8169_private
*tp
= netdev_priv(dev
);
3351 void __iomem
*ioaddr
= tp
->mmio_addr
;
3354 /* Soft reset the chip. */
3355 RTL_W8(ChipCmd
, CmdReset
);
3357 /* Check that the chip has finished the reset. */
3358 for (i
= 0; i
< 100; i
++) {
3359 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3361 msleep_interruptible(1);
3366 netif_start_queue(dev
);
3370 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3371 void __iomem
*ioaddr
)
3374 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3375 * register to be written before TxDescAddrLow to work.
3376 * Switching from MMIO to I/O access fixes the issue as well.
3378 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3379 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3380 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3381 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3384 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3388 cmd
= RTL_R16(CPlusCmd
);
3389 RTL_W16(CPlusCmd
, cmd
);
3393 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3395 /* Low hurts. Let's disable the filtering. */
3396 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3399 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3401 static const struct {
3406 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3407 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3408 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3409 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3414 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3415 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3416 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3417 RTL_W32(0x7c, p
->val
);
3423 static void rtl_hw_start_8169(struct net_device
*dev
)
3425 struct rtl8169_private
*tp
= netdev_priv(dev
);
3426 void __iomem
*ioaddr
= tp
->mmio_addr
;
3427 struct pci_dev
*pdev
= tp
->pci_dev
;
3429 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3430 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3431 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3434 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3435 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3436 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3437 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3438 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3439 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3441 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3443 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3445 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3446 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3447 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3448 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3449 rtl_set_rx_tx_config_registers(tp
);
3451 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3453 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3454 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3455 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3456 "Bit-3 and bit-14 MUST be 1\n");
3457 tp
->cp_cmd
|= (1 << 14);
3460 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3462 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3465 * Undocumented corner. Supposedly:
3466 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3468 RTL_W16(IntrMitigate
, 0x0000);
3470 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3472 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3473 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3474 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3475 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3476 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3477 rtl_set_rx_tx_config_registers(tp
);
3480 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3482 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3485 RTL_W32(RxMissed
, 0);
3487 rtl_set_rx_mode(dev
);
3489 /* no early-rx interrupts */
3490 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3492 /* Enable all known interrupts by setting the interrupt mask. */
3493 RTL_W16(IntrMask
, tp
->intr_event
);
3496 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3498 struct net_device
*dev
= pci_get_drvdata(pdev
);
3499 struct rtl8169_private
*tp
= netdev_priv(dev
);
3500 int cap
= tp
->pcie_cap
;
3505 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3506 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3507 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3511 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
3515 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3516 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
3520 unsigned int offset
;
3525 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3530 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3531 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3536 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3538 struct net_device
*dev
= pci_get_drvdata(pdev
);
3539 struct rtl8169_private
*tp
= netdev_priv(dev
);
3540 int cap
= tp
->pcie_cap
;
3545 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3546 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3547 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3551 #define R8168_CPCMD_QUIRK_MASK (\
3562 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3564 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3566 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3568 rtl_tx_performance_tweak(pdev
,
3569 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3572 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3574 rtl_hw_start_8168bb(ioaddr
, pdev
);
3576 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3578 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3581 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3583 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3585 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3587 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3589 rtl_disable_clock_request(pdev
);
3591 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3594 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3596 static const struct ephy_info e_info_8168cp
[] = {
3597 { 0x01, 0, 0x0001 },
3598 { 0x02, 0x0800, 0x1000 },
3599 { 0x03, 0, 0x0042 },
3600 { 0x06, 0x0080, 0x0000 },
3604 rtl_csi_access_enable(ioaddr
);
3606 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3608 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3611 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3613 rtl_csi_access_enable(ioaddr
);
3615 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3617 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3619 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3622 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3624 rtl_csi_access_enable(ioaddr
);
3626 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3629 RTL_W8(DBG_REG
, 0x20);
3631 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3633 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3635 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3638 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3640 static const struct ephy_info e_info_8168c_1
[] = {
3641 { 0x02, 0x0800, 0x1000 },
3642 { 0x03, 0, 0x0002 },
3643 { 0x06, 0x0080, 0x0000 }
3646 rtl_csi_access_enable(ioaddr
);
3648 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3650 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3652 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3655 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3657 static const struct ephy_info e_info_8168c_2
[] = {
3658 { 0x01, 0, 0x0001 },
3659 { 0x03, 0x0400, 0x0220 }
3662 rtl_csi_access_enable(ioaddr
);
3664 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3666 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3669 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3671 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3674 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3676 rtl_csi_access_enable(ioaddr
);
3678 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3681 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3683 rtl_csi_access_enable(ioaddr
);
3685 rtl_disable_clock_request(pdev
);
3687 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3689 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3691 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3694 static void rtl_hw_start_8168(struct net_device
*dev
)
3696 struct rtl8169_private
*tp
= netdev_priv(dev
);
3697 void __iomem
*ioaddr
= tp
->mmio_addr
;
3698 struct pci_dev
*pdev
= tp
->pci_dev
;
3700 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3702 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3704 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3706 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3708 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3710 RTL_W16(IntrMitigate
, 0x5151);
3712 /* Work around for RxFIFO overflow. */
3713 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
3714 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3715 tp
->intr_event
&= ~RxOverflow
;
3718 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3720 rtl_set_rx_mode(dev
);
3722 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3723 (InterFrameGap
<< TxInterFrameGapShift
));
3727 switch (tp
->mac_version
) {
3728 case RTL_GIGA_MAC_VER_11
:
3729 rtl_hw_start_8168bb(ioaddr
, pdev
);
3732 case RTL_GIGA_MAC_VER_12
:
3733 case RTL_GIGA_MAC_VER_17
:
3734 rtl_hw_start_8168bef(ioaddr
, pdev
);
3737 case RTL_GIGA_MAC_VER_18
:
3738 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3741 case RTL_GIGA_MAC_VER_19
:
3742 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3745 case RTL_GIGA_MAC_VER_20
:
3746 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3749 case RTL_GIGA_MAC_VER_21
:
3750 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3753 case RTL_GIGA_MAC_VER_22
:
3754 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3757 case RTL_GIGA_MAC_VER_23
:
3758 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3761 case RTL_GIGA_MAC_VER_24
:
3762 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3765 case RTL_GIGA_MAC_VER_25
:
3766 case RTL_GIGA_MAC_VER_26
:
3767 case RTL_GIGA_MAC_VER_27
:
3768 rtl_hw_start_8168d(ioaddr
, pdev
);
3772 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3773 dev
->name
, tp
->mac_version
);
3777 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3779 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3781 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3783 RTL_W16(IntrMask
, tp
->intr_event
);
3786 #define R810X_CPCMD_QUIRK_MASK (\
3798 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3800 static const struct ephy_info e_info_8102e_1
[] = {
3801 { 0x01, 0, 0x6e65 },
3802 { 0x02, 0, 0x091f },
3803 { 0x03, 0, 0xc2f9 },
3804 { 0x06, 0, 0xafb5 },
3805 { 0x07, 0, 0x0e00 },
3806 { 0x19, 0, 0xec80 },
3807 { 0x01, 0, 0x2e65 },
3812 rtl_csi_access_enable(ioaddr
);
3814 RTL_W8(DBG_REG
, FIX_NAK_1
);
3816 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3819 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3820 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3822 cfg1
= RTL_R8(Config1
);
3823 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3824 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3826 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3828 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3831 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3833 rtl_csi_access_enable(ioaddr
);
3835 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3837 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3838 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3840 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3843 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3845 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3847 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3850 static void rtl_hw_start_8101(struct net_device
*dev
)
3852 struct rtl8169_private
*tp
= netdev_priv(dev
);
3853 void __iomem
*ioaddr
= tp
->mmio_addr
;
3854 struct pci_dev
*pdev
= tp
->pci_dev
;
3856 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3857 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3858 int cap
= tp
->pcie_cap
;
3861 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3862 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3866 switch (tp
->mac_version
) {
3867 case RTL_GIGA_MAC_VER_07
:
3868 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3871 case RTL_GIGA_MAC_VER_08
:
3872 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3875 case RTL_GIGA_MAC_VER_09
:
3876 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3880 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3882 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3884 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3886 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3888 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3890 RTL_W16(IntrMitigate
, 0x0000);
3892 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3894 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3895 rtl_set_rx_tx_config_registers(tp
);
3897 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3901 rtl_set_rx_mode(dev
);
3903 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3905 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3907 RTL_W16(IntrMask
, tp
->intr_event
);
3910 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3912 struct rtl8169_private
*tp
= netdev_priv(dev
);
3915 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3920 if (!netif_running(dev
))
3925 ret
= rtl8169_init_ring(dev
);
3929 napi_enable(&tp
->napi
);
3933 rtl8169_request_timer(dev
);
3939 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3941 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3942 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3945 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
3946 void **data_buff
, struct RxDesc
*desc
)
3948 struct pci_dev
*pdev
= tp
->pci_dev
;
3950 dma_unmap_single(&pdev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
3951 PCI_DMA_FROMDEVICE
);
3954 rtl8169_make_unusable_by_asic(desc
);
3957 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3959 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3961 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3964 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3967 desc
->addr
= cpu_to_le64(mapping
);
3969 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
3972 static inline void *rtl8169_align(void *data
)
3974 return (void *)ALIGN((long)data
, 16);
3977 static struct sk_buff
*rtl8169_alloc_rx_data(struct pci_dev
*pdev
,
3978 struct net_device
*dev
,
3979 struct RxDesc
*desc
)
3983 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
3985 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
3989 if (rtl8169_align(data
) != data
) {
3991 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
3995 mapping
= dma_map_single(&pdev
->dev
, rtl8169_align(data
), rx_buf_sz
,
3996 PCI_DMA_FROMDEVICE
);
3998 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4002 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4006 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4007 if (tp
->Rx_databuff
[i
]) {
4008 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4009 tp
->RxDescArray
+ i
);
4014 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
4015 u32 start
, u32 end
, gfp_t gfp
)
4019 for (cur
= start
; end
- cur
!= 0; cur
++) {
4021 unsigned int i
= cur
% NUM_RX_DESC
;
4023 WARN_ON((s32
)(end
- cur
) < 0);
4025 if (tp
->Rx_databuff
[i
])
4028 data
= rtl8169_alloc_rx_data(tp
->pci_dev
, dev
,
4029 tp
->RxDescArray
+ i
);
4031 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4034 tp
->Rx_databuff
[i
] = data
;
4039 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4041 desc
->opts1
|= cpu_to_le32(RingEnd
);
4044 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4046 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4049 static int rtl8169_init_ring(struct net_device
*dev
)
4051 struct rtl8169_private
*tp
= netdev_priv(dev
);
4053 rtl8169_init_ring_indexes(tp
);
4055 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4056 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4058 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
, GFP_KERNEL
) != NUM_RX_DESC
)
4061 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4066 rtl8169_rx_clear(tp
);
4070 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
4071 struct TxDesc
*desc
)
4073 unsigned int len
= tx_skb
->len
;
4075 dma_unmap_single(&pdev
->dev
, le64_to_cpu(desc
->addr
), len
,
4083 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4087 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
4088 unsigned int entry
= i
% NUM_TX_DESC
;
4089 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4090 unsigned int len
= tx_skb
->len
;
4093 struct sk_buff
*skb
= tx_skb
->skb
;
4095 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
4096 tp
->TxDescArray
+ entry
);
4101 tp
->dev
->stats
.tx_dropped
++;
4104 tp
->cur_tx
= tp
->dirty_tx
= 0;
4107 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4109 struct rtl8169_private
*tp
= netdev_priv(dev
);
4111 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4112 schedule_delayed_work(&tp
->task
, 4);
4115 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4117 struct rtl8169_private
*tp
= netdev_priv(dev
);
4118 void __iomem
*ioaddr
= tp
->mmio_addr
;
4120 synchronize_irq(dev
->irq
);
4122 /* Wait for any pending NAPI task to complete */
4123 napi_disable(&tp
->napi
);
4125 rtl8169_irq_mask_and_ack(ioaddr
);
4127 tp
->intr_mask
= 0xffff;
4128 RTL_W16(IntrMask
, tp
->intr_event
);
4129 napi_enable(&tp
->napi
);
4132 static void rtl8169_reinit_task(struct work_struct
*work
)
4134 struct rtl8169_private
*tp
=
4135 container_of(work
, struct rtl8169_private
, task
.work
);
4136 struct net_device
*dev
= tp
->dev
;
4141 if (!netif_running(dev
))
4144 rtl8169_wait_for_quiescence(dev
);
4147 ret
= rtl8169_open(dev
);
4148 if (unlikely(ret
< 0)) {
4149 if (net_ratelimit())
4150 netif_err(tp
, drv
, dev
,
4151 "reinit failure (status = %d). Rescheduling\n",
4153 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4160 static void rtl8169_reset_task(struct work_struct
*work
)
4162 struct rtl8169_private
*tp
=
4163 container_of(work
, struct rtl8169_private
, task
.work
);
4164 struct net_device
*dev
= tp
->dev
;
4168 if (!netif_running(dev
))
4171 rtl8169_wait_for_quiescence(dev
);
4173 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4174 rtl8169_tx_clear(tp
);
4176 if (tp
->dirty_rx
== tp
->cur_rx
) {
4177 rtl8169_init_ring_indexes(tp
);
4179 netif_wake_queue(dev
);
4180 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4182 if (net_ratelimit())
4183 netif_emerg(tp
, intr
, dev
, "Rx buffers shortage\n");
4184 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4191 static void rtl8169_tx_timeout(struct net_device
*dev
)
4193 struct rtl8169_private
*tp
= netdev_priv(dev
);
4195 rtl8169_hw_reset(tp
->mmio_addr
);
4197 /* Let's wait a bit while any (async) irq lands on */
4198 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4201 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4204 struct skb_shared_info
*info
= skb_shinfo(skb
);
4205 unsigned int cur_frag
, entry
;
4206 struct TxDesc
* uninitialized_var(txd
);
4209 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4210 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4215 entry
= (entry
+ 1) % NUM_TX_DESC
;
4217 txd
= tp
->TxDescArray
+ entry
;
4219 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4220 mapping
= dma_map_single(&tp
->pci_dev
->dev
, addr
, len
,
4223 /* anti gcc 2.95.3 bugware (sic) */
4224 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4226 txd
->opts1
= cpu_to_le32(status
);
4227 txd
->addr
= cpu_to_le64(mapping
);
4229 tp
->tx_skb
[entry
].len
= len
;
4233 tp
->tx_skb
[entry
].skb
= skb
;
4234 txd
->opts1
|= cpu_to_le32(LastFrag
);
4240 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4242 if (dev
->features
& NETIF_F_TSO
) {
4243 u32 mss
= skb_shinfo(skb
)->gso_size
;
4246 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4248 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4249 const struct iphdr
*ip
= ip_hdr(skb
);
4251 if (ip
->protocol
== IPPROTO_TCP
)
4252 return IPCS
| TCPCS
;
4253 else if (ip
->protocol
== IPPROTO_UDP
)
4254 return IPCS
| UDPCS
;
4255 WARN_ON(1); /* we need a WARN() */
4260 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4261 struct net_device
*dev
)
4263 struct rtl8169_private
*tp
= netdev_priv(dev
);
4264 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
4265 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4266 void __iomem
*ioaddr
= tp
->mmio_addr
;
4271 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4272 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4276 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4279 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4281 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4283 len
= skb_headlen(skb
);
4287 opts1
|= FirstFrag
| LastFrag
;
4288 tp
->tx_skb
[entry
].skb
= skb
;
4291 mapping
= dma_map_single(&tp
->pci_dev
->dev
, skb
->data
, len
,
4294 tp
->tx_skb
[entry
].len
= len
;
4295 txd
->addr
= cpu_to_le64(mapping
);
4296 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4300 /* anti gcc 2.95.3 bugware (sic) */
4301 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4302 txd
->opts1
= cpu_to_le32(status
);
4304 tp
->cur_tx
+= frags
+ 1;
4308 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4310 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4311 netif_stop_queue(dev
);
4313 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4314 netif_wake_queue(dev
);
4317 return NETDEV_TX_OK
;
4320 netif_stop_queue(dev
);
4321 dev
->stats
.tx_dropped
++;
4322 return NETDEV_TX_BUSY
;
4325 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4327 struct rtl8169_private
*tp
= netdev_priv(dev
);
4328 struct pci_dev
*pdev
= tp
->pci_dev
;
4329 void __iomem
*ioaddr
= tp
->mmio_addr
;
4330 u16 pci_status
, pci_cmd
;
4332 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4333 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4335 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4336 pci_cmd
, pci_status
);
4339 * The recovery sequence below admits a very elaborated explanation:
4340 * - it seems to work;
4341 * - I did not see what else could be done;
4342 * - it makes iop3xx happy.
4344 * Feel free to adjust to your needs.
4346 if (pdev
->broken_parity_status
)
4347 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4349 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4351 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4353 pci_write_config_word(pdev
, PCI_STATUS
,
4354 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4355 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4356 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4358 /* The infamous DAC f*ckup only happens at boot time */
4359 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4360 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4361 tp
->cp_cmd
&= ~PCIDAC
;
4362 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4363 dev
->features
&= ~NETIF_F_HIGHDMA
;
4366 rtl8169_hw_reset(ioaddr
);
4368 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4371 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4372 struct rtl8169_private
*tp
,
4373 void __iomem
*ioaddr
)
4375 unsigned int dirty_tx
, tx_left
;
4377 dirty_tx
= tp
->dirty_tx
;
4379 tx_left
= tp
->cur_tx
- dirty_tx
;
4381 while (tx_left
> 0) {
4382 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4383 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4384 u32 len
= tx_skb
->len
;
4388 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4389 if (status
& DescOwn
)
4392 dev
->stats
.tx_bytes
+= len
;
4393 dev
->stats
.tx_packets
++;
4395 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
4397 if (status
& LastFrag
) {
4398 dev_kfree_skb(tx_skb
->skb
);
4405 if (tp
->dirty_tx
!= dirty_tx
) {
4406 tp
->dirty_tx
= dirty_tx
;
4408 if (netif_queue_stopped(dev
) &&
4409 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4410 netif_wake_queue(dev
);
4413 * 8168 hack: TxPoll requests are lost when the Tx packets are
4414 * too close. Let's kick an extra TxPoll request when a burst
4415 * of start_xmit activity is detected (if it is not detected,
4416 * it is slow enough). -- FR
4419 if (tp
->cur_tx
!= dirty_tx
)
4420 RTL_W8(TxPoll
, NPQ
);
4424 static inline int rtl8169_fragmented_frame(u32 status
)
4426 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4429 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4431 u32 status
= opts1
& RxProtoMask
;
4433 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4434 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
4435 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
4436 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4438 skb_checksum_none_assert(skb
);
4441 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
4442 struct rtl8169_private
*tp
,
4446 struct sk_buff
*skb
;
4448 data
= rtl8169_align(data
);
4449 dma_sync_single_for_cpu(&tp
->pci_dev
->dev
, addr
, pkt_size
,
4450 PCI_DMA_FROMDEVICE
);
4452 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4454 memcpy(skb
->data
, data
, pkt_size
);
4455 dma_sync_single_for_device(&tp
->pci_dev
->dev
, addr
, pkt_size
,
4456 PCI_DMA_FROMDEVICE
);
4461 * Warning : rtl8169_rx_interrupt() might be called :
4462 * 1) from NAPI (softirq) context
4463 * (polling = 1 : we should call netif_receive_skb())
4464 * 2) from process context (rtl8169_reset_task())
4465 * (polling = 0 : we must call netif_rx() instead)
4467 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4468 struct rtl8169_private
*tp
,
4469 void __iomem
*ioaddr
, u32 budget
)
4471 unsigned int cur_rx
, rx_left
;
4473 int polling
= (budget
!= ~(u32
)0) ? 1 : 0;
4475 cur_rx
= tp
->cur_rx
;
4476 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4477 rx_left
= min(rx_left
, budget
);
4479 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4480 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4481 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4485 status
= le32_to_cpu(desc
->opts1
);
4487 if (status
& DescOwn
)
4489 if (unlikely(status
& RxRES
)) {
4490 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
4492 dev
->stats
.rx_errors
++;
4493 if (status
& (RxRWT
| RxRUNT
))
4494 dev
->stats
.rx_length_errors
++;
4496 dev
->stats
.rx_crc_errors
++;
4497 if (status
& RxFOVF
) {
4498 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4499 dev
->stats
.rx_fifo_errors
++;
4501 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4503 struct sk_buff
*skb
;
4504 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4505 int pkt_size
= (status
& 0x00001FFF) - 4;
4508 * The driver does not support incoming fragmented
4509 * frames. They are seen as a symptom of over-mtu
4512 if (unlikely(rtl8169_fragmented_frame(status
))) {
4513 dev
->stats
.rx_dropped
++;
4514 dev
->stats
.rx_length_errors
++;
4515 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4519 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
4520 tp
, pkt_size
, addr
);
4521 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4523 dev
->stats
.rx_dropped
++;
4527 rtl8169_rx_csum(skb
, status
);
4528 skb_put(skb
, pkt_size
);
4529 skb
->protocol
= eth_type_trans(skb
, dev
);
4531 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
, polling
) < 0) {
4532 if (likely(polling
))
4533 napi_gro_receive(&tp
->napi
, skb
);
4538 dev
->stats
.rx_bytes
+= pkt_size
;
4539 dev
->stats
.rx_packets
++;
4542 /* Work around for AMD plateform. */
4543 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4544 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4550 count
= cur_rx
- tp
->cur_rx
;
4551 tp
->cur_rx
= cur_rx
;
4553 tp
->dirty_rx
+= count
;
4558 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4560 struct net_device
*dev
= dev_instance
;
4561 struct rtl8169_private
*tp
= netdev_priv(dev
);
4562 void __iomem
*ioaddr
= tp
->mmio_addr
;
4566 /* loop handling interrupts until we have no new ones or
4567 * we hit a invalid/hotplug case.
4569 status
= RTL_R16(IntrStatus
);
4570 while (status
&& status
!= 0xffff) {
4573 /* Handle all of the error cases first. These will reset
4574 * the chip, so just exit the loop.
4576 if (unlikely(!netif_running(dev
))) {
4577 rtl8169_asic_down(ioaddr
);
4581 /* Work around for rx fifo overflow */
4582 if (unlikely(status
& RxFIFOOver
)) {
4583 netif_stop_queue(dev
);
4584 rtl8169_tx_timeout(dev
);
4588 if (unlikely(status
& SYSErr
)) {
4589 rtl8169_pcierr_interrupt(dev
);
4593 if (status
& LinkChg
)
4594 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4596 /* We need to see the lastest version of tp->intr_mask to
4597 * avoid ignoring an MSI interrupt and having to wait for
4598 * another event which may never come.
4601 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4602 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4603 tp
->intr_mask
= ~tp
->napi_event
;
4605 if (likely(napi_schedule_prep(&tp
->napi
)))
4606 __napi_schedule(&tp
->napi
);
4608 netif_info(tp
, intr
, dev
,
4609 "interrupt %04x in poll\n", status
);
4612 /* We only get a new MSI interrupt when all active irq
4613 * sources on the chip have been acknowledged. So, ack
4614 * everything we've seen and check if new sources have become
4615 * active to avoid blocking all interrupts from the chip.
4618 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4619 status
= RTL_R16(IntrStatus
);
4622 return IRQ_RETVAL(handled
);
4625 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4627 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4628 struct net_device
*dev
= tp
->dev
;
4629 void __iomem
*ioaddr
= tp
->mmio_addr
;
4632 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4633 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4635 if (work_done
< budget
) {
4636 napi_complete(napi
);
4638 /* We need for force the visibility of tp->intr_mask
4639 * for other CPUs, as we can loose an MSI interrupt
4640 * and potentially wait for a retransmit timeout if we don't.
4641 * The posted write to IntrMask is safe, as it will
4642 * eventually make it to the chip and we won't loose anything
4645 tp
->intr_mask
= 0xffff;
4647 RTL_W16(IntrMask
, tp
->intr_event
);
4653 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4655 struct rtl8169_private
*tp
= netdev_priv(dev
);
4657 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4660 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4661 RTL_W32(RxMissed
, 0);
4664 static void rtl8169_down(struct net_device
*dev
)
4666 struct rtl8169_private
*tp
= netdev_priv(dev
);
4667 void __iomem
*ioaddr
= tp
->mmio_addr
;
4668 unsigned int intrmask
;
4670 rtl8169_delete_timer(dev
);
4672 netif_stop_queue(dev
);
4674 napi_disable(&tp
->napi
);
4677 spin_lock_irq(&tp
->lock
);
4679 rtl8169_asic_down(ioaddr
);
4681 rtl8169_rx_missed(dev
, ioaddr
);
4683 spin_unlock_irq(&tp
->lock
);
4685 synchronize_irq(dev
->irq
);
4687 /* Give a racing hard_start_xmit a few cycles to complete. */
4688 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4691 * And now for the 50k$ question: are IRQ disabled or not ?
4693 * Two paths lead here:
4695 * -> netif_running() is available to sync the current code and the
4696 * IRQ handler. See rtl8169_interrupt for details.
4697 * 2) dev->change_mtu
4698 * -> rtl8169_poll can not be issued again and re-enable the
4699 * interruptions. Let's simply issue the IRQ down sequence again.
4701 * No loop if hotpluged or major error (0xffff).
4703 intrmask
= RTL_R16(IntrMask
);
4704 if (intrmask
&& (intrmask
!= 0xffff))
4707 rtl8169_tx_clear(tp
);
4709 rtl8169_rx_clear(tp
);
4712 static int rtl8169_close(struct net_device
*dev
)
4714 struct rtl8169_private
*tp
= netdev_priv(dev
);
4715 struct pci_dev
*pdev
= tp
->pci_dev
;
4717 pm_runtime_get_sync(&pdev
->dev
);
4719 /* update counters before going down */
4720 rtl8169_update_counters(dev
);
4724 free_irq(dev
->irq
, dev
);
4726 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4728 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4730 tp
->TxDescArray
= NULL
;
4731 tp
->RxDescArray
= NULL
;
4733 pm_runtime_put_sync(&pdev
->dev
);
4738 static void rtl_set_rx_mode(struct net_device
*dev
)
4740 struct rtl8169_private
*tp
= netdev_priv(dev
);
4741 void __iomem
*ioaddr
= tp
->mmio_addr
;
4742 unsigned long flags
;
4743 u32 mc_filter
[2]; /* Multicast hash filter */
4747 if (dev
->flags
& IFF_PROMISC
) {
4748 /* Unconditionally log net taps. */
4749 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4751 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4753 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4754 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4755 (dev
->flags
& IFF_ALLMULTI
)) {
4756 /* Too many to filter perfectly -- accept all multicasts. */
4757 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4758 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4760 struct netdev_hw_addr
*ha
;
4762 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4763 mc_filter
[1] = mc_filter
[0] = 0;
4764 netdev_for_each_mc_addr(ha
, dev
) {
4765 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4766 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4767 rx_mode
|= AcceptMulticast
;
4771 spin_lock_irqsave(&tp
->lock
, flags
);
4773 tmp
= rtl8169_rx_config
| rx_mode
|
4774 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4776 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4777 u32 data
= mc_filter
[0];
4779 mc_filter
[0] = swab32(mc_filter
[1]);
4780 mc_filter
[1] = swab32(data
);
4783 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4784 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4786 RTL_W32(RxConfig
, tmp
);
4788 spin_unlock_irqrestore(&tp
->lock
, flags
);
4792 * rtl8169_get_stats - Get rtl8169 read/write statistics
4793 * @dev: The Ethernet Device to get statistics for
4795 * Get TX/RX statistics for rtl8169
4797 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4799 struct rtl8169_private
*tp
= netdev_priv(dev
);
4800 void __iomem
*ioaddr
= tp
->mmio_addr
;
4801 unsigned long flags
;
4803 if (netif_running(dev
)) {
4804 spin_lock_irqsave(&tp
->lock
, flags
);
4805 rtl8169_rx_missed(dev
, ioaddr
);
4806 spin_unlock_irqrestore(&tp
->lock
, flags
);
4812 static void rtl8169_net_suspend(struct net_device
*dev
)
4814 if (!netif_running(dev
))
4817 netif_device_detach(dev
);
4818 netif_stop_queue(dev
);
4823 static int rtl8169_suspend(struct device
*device
)
4825 struct pci_dev
*pdev
= to_pci_dev(device
);
4826 struct net_device
*dev
= pci_get_drvdata(pdev
);
4828 rtl8169_net_suspend(dev
);
4833 static void __rtl8169_resume(struct net_device
*dev
)
4835 netif_device_attach(dev
);
4836 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4839 static int rtl8169_resume(struct device
*device
)
4841 struct pci_dev
*pdev
= to_pci_dev(device
);
4842 struct net_device
*dev
= pci_get_drvdata(pdev
);
4844 if (netif_running(dev
))
4845 __rtl8169_resume(dev
);
4850 static int rtl8169_runtime_suspend(struct device
*device
)
4852 struct pci_dev
*pdev
= to_pci_dev(device
);
4853 struct net_device
*dev
= pci_get_drvdata(pdev
);
4854 struct rtl8169_private
*tp
= netdev_priv(dev
);
4856 if (!tp
->TxDescArray
)
4859 spin_lock_irq(&tp
->lock
);
4860 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
4861 __rtl8169_set_wol(tp
, WAKE_ANY
);
4862 spin_unlock_irq(&tp
->lock
);
4864 rtl8169_net_suspend(dev
);
4869 static int rtl8169_runtime_resume(struct device
*device
)
4871 struct pci_dev
*pdev
= to_pci_dev(device
);
4872 struct net_device
*dev
= pci_get_drvdata(pdev
);
4873 struct rtl8169_private
*tp
= netdev_priv(dev
);
4875 if (!tp
->TxDescArray
)
4878 spin_lock_irq(&tp
->lock
);
4879 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
4880 tp
->saved_wolopts
= 0;
4881 spin_unlock_irq(&tp
->lock
);
4883 __rtl8169_resume(dev
);
4888 static int rtl8169_runtime_idle(struct device
*device
)
4890 struct pci_dev
*pdev
= to_pci_dev(device
);
4891 struct net_device
*dev
= pci_get_drvdata(pdev
);
4892 struct rtl8169_private
*tp
= netdev_priv(dev
);
4894 if (!tp
->TxDescArray
)
4897 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4901 static const struct dev_pm_ops rtl8169_pm_ops
= {
4902 .suspend
= rtl8169_suspend
,
4903 .resume
= rtl8169_resume
,
4904 .freeze
= rtl8169_suspend
,
4905 .thaw
= rtl8169_resume
,
4906 .poweroff
= rtl8169_suspend
,
4907 .restore
= rtl8169_resume
,
4908 .runtime_suspend
= rtl8169_runtime_suspend
,
4909 .runtime_resume
= rtl8169_runtime_resume
,
4910 .runtime_idle
= rtl8169_runtime_idle
,
4913 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4915 #else /* !CONFIG_PM */
4917 #define RTL8169_PM_OPS NULL
4919 #endif /* !CONFIG_PM */
4921 static void rtl_shutdown(struct pci_dev
*pdev
)
4923 struct net_device
*dev
= pci_get_drvdata(pdev
);
4924 struct rtl8169_private
*tp
= netdev_priv(dev
);
4925 void __iomem
*ioaddr
= tp
->mmio_addr
;
4927 rtl8169_net_suspend(dev
);
4929 /* restore original MAC address */
4930 rtl_rar_set(tp
, dev
->perm_addr
);
4932 spin_lock_irq(&tp
->lock
);
4934 rtl8169_asic_down(ioaddr
);
4936 spin_unlock_irq(&tp
->lock
);
4938 if (system_state
== SYSTEM_POWER_OFF
) {
4939 /* WoL fails with some 8168 when the receiver is disabled. */
4940 if (tp
->features
& RTL_FEATURE_WOL
) {
4941 pci_clear_master(pdev
);
4943 RTL_W8(ChipCmd
, CmdRxEnb
);
4948 pci_wake_from_d3(pdev
, true);
4949 pci_set_power_state(pdev
, PCI_D3hot
);
4953 static struct pci_driver rtl8169_pci_driver
= {
4955 .id_table
= rtl8169_pci_tbl
,
4956 .probe
= rtl8169_init_one
,
4957 .remove
= __devexit_p(rtl8169_remove_one
),
4958 .shutdown
= rtl_shutdown
,
4959 .driver
.pm
= RTL8169_PM_OPS
,
4962 static int __init
rtl8169_init_module(void)
4964 return pci_register_driver(&rtl8169_pci_driver
);
4967 static void __exit
rtl8169_cleanup_module(void)
4969 pci_unregister_driver(&rtl8169_pci_driver
);
4972 module_init(rtl8169_init_module
);
4973 module_exit(rtl8169_cleanup_module
);