2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/sysdev.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 #include <linux/module.h>
29 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
35 #include <asm/pmac_feature.h>
41 * XXX this should be in xmon.h, but putting it there means xmon.h
42 * has to include <linux/interrupt.h> (to get irqreturn_t), which
43 * causes all sorts of problems. -- paulus
45 extern irqreturn_t
xmon_irq(int, void *, struct pt_regs
*);
55 /* Default addresses */
56 static volatile struct pmac_irq_hw __iomem
*pmac_irq_hw
[4];
58 #define GC_LEVEL_MASK 0x3ff00000
59 #define OHARE_LEVEL_MASK 0x1ff00000
60 #define HEATHROW_LEVEL_MASK 0x1ff00000
63 static int max_real_irqs
;
64 static u32 level_mask
[4];
66 static DEFINE_SPINLOCK(pmac_pic_lock
);
68 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
69 static unsigned long ppc_lost_interrupts
[NR_MASK_WORDS
];
70 static unsigned long ppc_cached_irq_mask
[NR_MASK_WORDS
];
71 static int pmac_irq_cascade
= -1;
72 static struct irq_host
*pmac_pic_host
;
74 static void __pmac_retrigger(unsigned int irq_nr
)
76 if (irq_nr
>= max_real_irqs
&& pmac_irq_cascade
> 0) {
77 __set_bit(irq_nr
, ppc_lost_interrupts
);
78 irq_nr
= pmac_irq_cascade
;
81 if (!__test_and_set_bit(irq_nr
, ppc_lost_interrupts
)) {
82 atomic_inc(&ppc_n_lost_interrupts
);
87 static void pmac_mask_and_ack_irq(unsigned int virq
)
89 unsigned int src
= irq_map
[virq
].hwirq
;
90 unsigned long bit
= 1UL << (src
& 0x1f);
94 spin_lock_irqsave(&pmac_pic_lock
, flags
);
95 __clear_bit(src
, ppc_cached_irq_mask
);
96 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
97 atomic_dec(&ppc_n_lost_interrupts
);
98 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
99 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
101 /* make sure ack gets to controller before we enable
104 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
105 != (ppc_cached_irq_mask
[i
] & bit
));
106 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
109 static void pmac_ack_irq(unsigned int virq
)
111 unsigned int src
= irq_map
[virq
].hwirq
;
112 unsigned long bit
= 1UL << (src
& 0x1f);
116 spin_lock_irqsave(&pmac_pic_lock
, flags
);
117 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
118 atomic_dec(&ppc_n_lost_interrupts
);
119 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
120 (void)in_le32(&pmac_irq_hw
[i
]->ack
);
121 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
124 static void __pmac_set_irq_mask(unsigned int irq_nr
, int nokicklost
)
126 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
129 if ((unsigned)irq_nr
>= max_irqs
)
132 /* enable unmasked interrupts */
133 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
136 /* make sure mask gets to controller before we
139 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
140 != (ppc_cached_irq_mask
[i
] & bit
));
143 * Unfortunately, setting the bit in the enable register
144 * when the device interrupt is already on *doesn't* set
145 * the bit in the flag register or request another interrupt.
147 if (bit
& ppc_cached_irq_mask
[i
] & in_le32(&pmac_irq_hw
[i
]->level
))
148 __pmac_retrigger(irq_nr
);
151 /* When an irq gets requested for the first client, if it's an
152 * edge interrupt, we clear any previous one on the controller
154 static unsigned int pmac_startup_irq(unsigned int virq
)
157 unsigned int src
= irq_map
[virq
].hwirq
;
158 unsigned long bit
= 1UL << (src
& 0x1f);
161 spin_lock_irqsave(&pmac_pic_lock
, flags
);
162 if ((irq_desc
[virq
].status
& IRQ_LEVEL
) == 0)
163 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
164 __set_bit(src
, ppc_cached_irq_mask
);
165 __pmac_set_irq_mask(src
, 0);
166 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
171 static void pmac_mask_irq(unsigned int virq
)
174 unsigned int src
= irq_map
[virq
].hwirq
;
176 spin_lock_irqsave(&pmac_pic_lock
, flags
);
177 __clear_bit(src
, ppc_cached_irq_mask
);
178 __pmac_set_irq_mask(src
, 1);
179 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
182 static void pmac_unmask_irq(unsigned int virq
)
185 unsigned int src
= irq_map
[virq
].hwirq
;
187 spin_lock_irqsave(&pmac_pic_lock
, flags
);
188 __set_bit(src
, ppc_cached_irq_mask
);
189 __pmac_set_irq_mask(src
, 0);
190 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
193 static int pmac_retrigger(unsigned int virq
)
197 spin_lock_irqsave(&pmac_pic_lock
, flags
);
198 __pmac_retrigger(irq_map
[virq
].hwirq
);
199 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
203 static struct irq_chip pmac_pic
= {
204 .typename
= " PMAC-PIC ",
205 .startup
= pmac_startup_irq
,
206 .mask
= pmac_mask_irq
,
208 .mask_ack
= pmac_mask_and_ack_irq
,
209 .unmask
= pmac_unmask_irq
,
210 .retrigger
= pmac_retrigger
,
213 static irqreturn_t
gatwick_action(int cpl
, void *dev_id
, struct pt_regs
*regs
)
219 spin_lock_irqsave(&pmac_pic_lock
, flags
);
220 for (irq
= max_irqs
; (irq
-= 32) >= max_real_irqs
; ) {
222 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
223 /* We must read level interrupts from the level register */
224 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
225 bits
&= ppc_cached_irq_mask
[i
];
228 irq
+= __ilog2(bits
);
229 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
231 spin_lock_irqsave(&pmac_pic_lock
, flags
);
234 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
238 static unsigned int pmac_pic_get_irq(struct pt_regs
*regs
)
241 unsigned long bits
= 0;
245 void psurge_smp_message_recv(struct pt_regs
*);
247 /* IPI's are a hack on the powersurge -- Cort */
248 if ( smp_processor_id() != 0 ) {
249 psurge_smp_message_recv(regs
);
250 return NO_IRQ_IGNORE
; /* ignore, already handled */
252 #endif /* CONFIG_SMP */
253 spin_lock_irqsave(&pmac_pic_lock
, flags
);
254 for (irq
= max_real_irqs
; (irq
-= 32) >= 0; ) {
256 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
257 /* We must read level interrupts from the level register */
258 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
259 bits
&= ppc_cached_irq_mask
[i
];
262 irq
+= __ilog2(bits
);
265 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
266 if (unlikely(irq
< 0))
268 return irq_linear_revmap(pmac_pic_host
, irq
);
272 static struct irqaction xmon_action
= {
275 .mask
= CPU_MASK_NONE
,
280 static struct irqaction gatwick_cascade_action
= {
281 .handler
= gatwick_action
,
282 .flags
= IRQF_DISABLED
,
283 .mask
= CPU_MASK_NONE
,
287 static int pmac_pic_host_match(struct irq_host
*h
, struct device_node
*node
)
289 /* We match all, we don't always have a node anyway */
293 static int pmac_pic_host_map(struct irq_host
*h
, unsigned int virq
,
296 struct irq_desc
*desc
= get_irq_desc(virq
);
302 /* Mark level interrupts, set delayed disable for edge ones and set
305 level
= !!(level_mask
[hw
>> 5] & (1UL << (hw
& 0x1f)));
307 desc
->status
|= IRQ_LEVEL
;
309 desc
->status
|= IRQ_DELAYED_DISABLE
;
310 set_irq_chip_and_handler(virq
, &pmac_pic
, level
?
311 handle_level_irq
: handle_edge_irq
);
315 static int pmac_pic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
316 u32
*intspec
, unsigned int intsize
,
317 irq_hw_number_t
*out_hwirq
,
318 unsigned int *out_flags
)
321 *out_flags
= IRQ_TYPE_NONE
;
322 *out_hwirq
= *intspec
;
326 static struct irq_host_ops pmac_pic_host_ops
= {
327 .match
= pmac_pic_host_match
,
328 .map
= pmac_pic_host_map
,
329 .xlate
= pmac_pic_host_xlate
,
332 static void __init
pmac_pic_probe_oldstyle(void)
335 struct device_node
*master
= NULL
;
336 struct device_node
*slave
= NULL
;
340 /* Set our get_irq function */
341 ppc_md
.get_irq
= pmac_pic_get_irq
;
344 * Find the interrupt controller type & node
347 if ((master
= of_find_node_by_name(NULL
, "gc")) != NULL
) {
348 max_irqs
= max_real_irqs
= 32;
349 level_mask
[0] = GC_LEVEL_MASK
;
350 } else if ((master
= of_find_node_by_name(NULL
, "ohare")) != NULL
) {
351 max_irqs
= max_real_irqs
= 32;
352 level_mask
[0] = OHARE_LEVEL_MASK
;
354 /* We might have a second cascaded ohare */
355 slave
= of_find_node_by_name(NULL
, "pci106b,7");
358 level_mask
[1] = OHARE_LEVEL_MASK
;
360 } else if ((master
= of_find_node_by_name(NULL
, "mac-io")) != NULL
) {
361 max_irqs
= max_real_irqs
= 64;
362 level_mask
[0] = HEATHROW_LEVEL_MASK
;
365 /* We might have a second cascaded heathrow */
366 slave
= of_find_node_by_name(master
, "mac-io");
368 /* Check ordering of master & slave */
369 if (device_is_compatible(master
, "gatwick")) {
370 struct device_node
*tmp
;
371 BUG_ON(slave
== NULL
);
377 /* We found a slave */
380 level_mask
[2] = HEATHROW_LEVEL_MASK
;
384 BUG_ON(master
== NULL
);
387 * Allocate an irq host
389 pmac_pic_host
= irq_alloc_host(IRQ_HOST_MAP_LINEAR
, max_irqs
,
392 BUG_ON(pmac_pic_host
== NULL
);
393 irq_set_default_host(pmac_pic_host
);
395 /* Get addresses of first controller if we have a node for it */
396 BUG_ON(of_address_to_resource(master
, 0, &r
));
398 /* Map interrupts of primary controller */
399 addr
= (u8 __iomem
*) ioremap(r
.start
, 0x40);
401 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
403 if (max_real_irqs
> 32)
404 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
408 printk(KERN_INFO
"irq: Found primary Apple PIC %s for %d irqs\n",
409 master
->full_name
, max_real_irqs
);
411 /* Map interrupts of cascaded controller */
412 if (slave
&& !of_address_to_resource(slave
, 0, &r
)) {
413 addr
= (u8 __iomem
*)ioremap(r
.start
, 0x40);
414 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
418 (volatile struct pmac_irq_hw __iomem
*)
420 pmac_irq_cascade
= irq_of_parse_and_map(slave
, 0);
422 printk(KERN_INFO
"irq: Found slave Apple PIC %s for %d irqs"
423 " cascade: %d\n", slave
->full_name
,
424 max_irqs
- max_real_irqs
, pmac_irq_cascade
);
428 /* Disable all interrupts in all controllers */
429 for (i
= 0; i
* 32 < max_irqs
; ++i
)
430 out_le32(&pmac_irq_hw
[i
]->enable
, 0);
432 /* Hookup cascade irq */
433 if (slave
&& pmac_irq_cascade
!= NO_IRQ
)
434 setup_irq(pmac_irq_cascade
, &gatwick_cascade_action
);
436 printk(KERN_INFO
"irq: System has %d possible interrupts\n", max_irqs
);
438 setup_irq(irq_create_mapping(NULL
, 20), &xmon_action
);
441 #endif /* CONFIG_PPC32 */
443 static void pmac_u3_cascade(unsigned int irq
, struct irq_desc
*desc
)
445 struct mpic
*mpic
= desc
->handler_data
;
447 unsigned int cascade_irq
= mpic_get_one_irq(mpic
, get_irq_regs());
448 if (cascade_irq
!= NO_IRQ
)
449 generic_handle_irq(cascade_irq
);
450 desc
->chip
->eoi(irq
);
453 static void __init
pmac_pic_setup_mpic_nmi(struct mpic
*mpic
)
455 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
456 struct device_node
* pswitch
;
459 pswitch
= of_find_node_by_name(NULL
, "programmer-switch");
461 nmi_irq
= irq_of_parse_and_map(pswitch
, 0);
462 if (nmi_irq
!= NO_IRQ
) {
463 mpic_irq_set_priority(nmi_irq
, 9);
464 setup_irq(nmi_irq
, &xmon_action
);
466 of_node_put(pswitch
);
468 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
471 static struct mpic
* __init
pmac_setup_one_mpic(struct device_node
*np
,
474 const char *name
= master
? " MPIC 1 " : " MPIC 2 ";
477 unsigned int flags
= master
? MPIC_PRIMARY
: 0;
480 rc
= of_address_to_resource(np
, 0, &r
);
484 pmac_call_feature(PMAC_FTR_ENABLE_MPIC
, np
, 0, 0);
486 flags
|= MPIC_WANTS_RESET
;
487 if (get_property(np
, "big-endian", NULL
))
488 flags
|= MPIC_BIG_ENDIAN
;
490 /* Primary Big Endian means HT interrupts. This is quite dodgy
491 * but works until I find a better way
493 if (master
&& (flags
& MPIC_BIG_ENDIAN
))
494 flags
|= MPIC_BROKEN_U3
;
496 mpic
= mpic_alloc(np
, r
.start
, flags
, 0, 0, name
);
505 static int __init
pmac_pic_probe_mpic(void)
507 struct mpic
*mpic1
, *mpic2
;
508 struct device_node
*np
, *master
= NULL
, *slave
= NULL
;
509 unsigned int cascade
;
511 /* We can have up to 2 MPICs cascaded */
512 for (np
= NULL
; (np
= of_find_node_by_type(np
, "open-pic"))
514 if (master
== NULL
&&
515 get_property(np
, "interrupts", NULL
) == NULL
)
516 master
= of_node_get(np
);
517 else if (slave
== NULL
)
518 slave
= of_node_get(np
);
523 /* Check for bogus setups */
524 if (master
== NULL
&& slave
!= NULL
) {
529 /* Not found, default to good old pmac pic */
533 /* Set master handler */
534 ppc_md
.get_irq
= mpic_get_irq
;
537 mpic1
= pmac_setup_one_mpic(master
, 1);
538 BUG_ON(mpic1
== NULL
);
540 /* Install NMI if any */
541 pmac_pic_setup_mpic_nmi(mpic1
);
545 /* No slave, let's go out */
549 /* Get/Map slave interrupt */
550 cascade
= irq_of_parse_and_map(slave
, 0);
551 if (cascade
== NO_IRQ
) {
552 printk(KERN_ERR
"Failed to map cascade IRQ\n");
556 mpic2
= pmac_setup_one_mpic(slave
, 0);
558 printk(KERN_ERR
"Failed to setup slave MPIC\n");
562 set_irq_data(cascade
, mpic2
);
563 set_irq_chained_handler(cascade
, pmac_u3_cascade
);
570 void __init
pmac_pic_init(void)
572 unsigned int flags
= 0;
574 /* We configure the OF parsing based on our oldworld vs. newworld
575 * platform type and wether we were booted by BootX.
579 flags
|= OF_IMAP_OLDWORLD_MAC
;
580 if (get_property(of_chosen
, "linux,bootx", NULL
) != NULL
)
581 flags
|= OF_IMAP_NO_PHANDLE
;
582 #endif /* CONFIG_PPC_32 */
584 of_irq_map_init(flags
);
586 /* We first try to detect Apple's new Core99 chipset, since mac-io
587 * is quite different on those machines and contains an IBM MPIC2.
589 if (pmac_pic_probe_mpic() == 0)
593 pmac_pic_probe_oldstyle();
597 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
599 * These procedures are used in implementing sleep on the powerbooks.
600 * sleep_save_intrs() saves the states of all interrupt enables
601 * and disables all interrupts except for the nominated one.
602 * sleep_restore_intrs() restores the states of all interrupt enables.
604 unsigned long sleep_save_mask
[2];
606 /* This used to be passed by the PMU driver but that link got
607 * broken with the new driver model. We use this tweak for now...
608 * We really want to do things differently though...
610 static int pmacpic_find_viaint(void)
614 #ifdef CONFIG_ADB_PMU
615 struct device_node
*np
;
617 if (pmu_get_model() != PMU_OHARE_BASED
)
619 np
= of_find_node_by_name(NULL
, "via-pmu");
622 viaint
= irq_of_parse_and_map(np
, 0);;
623 #endif /* CONFIG_ADB_PMU */
629 static int pmacpic_suspend(struct sys_device
*sysdev
, pm_message_t state
)
631 int viaint
= pmacpic_find_viaint();
633 sleep_save_mask
[0] = ppc_cached_irq_mask
[0];
634 sleep_save_mask
[1] = ppc_cached_irq_mask
[1];
635 ppc_cached_irq_mask
[0] = 0;
636 ppc_cached_irq_mask
[1] = 0;
638 set_bit(viaint
, ppc_cached_irq_mask
);
639 out_le32(&pmac_irq_hw
[0]->enable
, ppc_cached_irq_mask
[0]);
640 if (max_real_irqs
> 32)
641 out_le32(&pmac_irq_hw
[1]->enable
, ppc_cached_irq_mask
[1]);
642 (void)in_le32(&pmac_irq_hw
[0]->event
);
643 /* make sure mask gets to controller before we return to caller */
645 (void)in_le32(&pmac_irq_hw
[0]->enable
);
650 static int pmacpic_resume(struct sys_device
*sysdev
)
654 out_le32(&pmac_irq_hw
[0]->enable
, 0);
655 if (max_real_irqs
> 32)
656 out_le32(&pmac_irq_hw
[1]->enable
, 0);
658 for (i
= 0; i
< max_real_irqs
; ++i
)
659 if (test_bit(i
, sleep_save_mask
))
665 #endif /* CONFIG_PM && CONFIG_PPC32 */
667 static struct sysdev_class pmacpic_sysclass
= {
668 set_kset_name("pmac_pic"),
671 static struct sys_device device_pmacpic
= {
673 .cls
= &pmacpic_sysclass
,
676 static struct sysdev_driver driver_pmacpic
= {
677 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
678 .suspend
= &pmacpic_suspend
,
679 .resume
= &pmacpic_resume
,
680 #endif /* CONFIG_PM && CONFIG_PPC32 */
683 static int __init
init_pmacpic_sysfs(void)
689 printk(KERN_DEBUG
"Registering pmac pic with sysfs...\n");
690 sysdev_class_register(&pmacpic_sysclass
);
691 sysdev_register(&device_pmacpic
);
692 sysdev_driver_register(&pmacpic_sysclass
, &driver_pmacpic
);
696 subsys_initcall(init_pmacpic_sysfs
);