2 * linux/drivers/ide/pci/siimage.c Version 1.17 Oct 18 2007
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 MontaVista Software, Inc.
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
9 * May be copied or modified under the terms of the GNU General Public License
11 * Documentation for CMD680:
12 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
14 * Documentation for SiI 3112:
15 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
17 * Errata and other documentation only available under NDA.
21 * If you are using Marvell SATA-IDE adapters with Maxtor drives
22 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
24 * If you are using WD drives with SATA bridges you must set the
25 * drive to "Single". "Master" will hang
27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS
31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
33 * This often causes drivers/ide/siimage to panic but is ok with the rather
34 * smarter code in libata.
41 #include <linux/types.h>
42 #include <linux/module.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/hdreg.h>
46 #include <linux/ide.h>
47 #include <linux/init.h>
52 * pdev_is_sata - check if device is SATA
53 * @pdev: PCI device to check
55 * Returns true if this is a SATA controller
58 static int pdev_is_sata(struct pci_dev
*pdev
)
62 case PCI_DEVICE_ID_SII_3112
:
63 case PCI_DEVICE_ID_SII_1210SA
:
65 case PCI_DEVICE_ID_SII_680
:
73 * is_sata - check if hwif is SATA
74 * @hwif: interface to check
76 * Returns true if this is a SATA controller
79 static inline int is_sata(ide_hwif_t
*hwif
)
81 return pdev_is_sata(hwif
->pci_dev
);
85 * siimage_selreg - return register base
89 * Turn a config register offset into the right address in either
90 * PCI space or MMIO space to access the control register in question
91 * Thankfully this is a configuration operation so isnt performance
95 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
97 unsigned long base
= (unsigned long)hwif
->hwif_data
;
100 base
+= (hwif
->channel
<< 6);
102 base
+= (hwif
->channel
<< 4);
107 * siimage_seldev - return register base
111 * Turn a config register offset into the right address in either
112 * PCI space or MMIO space to access the control register in question
113 * including accounting for the unit shift.
116 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
118 ide_hwif_t
*hwif
= HWIF(drive
);
119 unsigned long base
= (unsigned long)hwif
->hwif_data
;
122 base
+= (hwif
->channel
<< 6);
124 base
+= (hwif
->channel
<< 4);
125 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
130 * sil_udma_filter - compute UDMA mask
133 * Compute the available UDMA speeds for the device on the interface.
135 * For the CMD680 this depends on the clocking mode (scsc), for the
136 * SI3112 SATA controller life is a bit simpler.
139 static u8
sil_udma_filter(ide_drive_t
*drive
)
141 ide_hwif_t
*hwif
= drive
->hwif
;
142 unsigned long base
= (unsigned long) hwif
->hwif_data
;
143 u8 mask
= 0, scsc
= 0;
146 scsc
= hwif
->INB(base
+ 0x4A);
148 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
151 mask
= strstr(drive
->id
->model
, "Maxtor") ? 0x3f : 0x7f;
155 if ((scsc
& 0x30) == 0x10) /* 133 */
157 else if ((scsc
& 0x30) == 0x20) /* 2xPCI */
159 else if ((scsc
& 0x30) == 0x00) /* 100 */
161 else /* Disabled ? */
168 * sil_set_pio_mode - set host controller for PIO mode
170 * @pio: PIO mode number
172 * Load the timing settings for this device mode into the
173 * controller. If we are in PIO mode 3 or 4 turn on IORDY
174 * monitoring (bit 9). The TF timing is bits 31:16
177 static void sil_set_pio_mode(ide_drive_t
*drive
, u8 pio
)
179 const u16 tf_speed
[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
180 const u16 data_speed
[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
182 ide_hwif_t
*hwif
= HWIF(drive
);
183 ide_drive_t
*pair
= ide_get_paired_drive(drive
);
186 unsigned long addr
= siimage_seldev(drive
, 0x04);
187 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
188 unsigned long base
= (unsigned long)hwif
->hwif_data
;
190 u8 addr_mask
= hwif
->channel
? (hwif
->mmio
? 0xF4 : 0x84)
191 : (hwif
->mmio
? 0xB4 : 0x80);
193 u8 unit
= drive
->select
.b
.unit
;
195 /* trim *taskfile* PIO to the slowest of the master/slave */
197 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
199 if (pair_pio
< tf_pio
)
203 /* cheat for now and use the docs */
204 speedp
= data_speed
[pio
];
205 speedt
= tf_speed
[tf_pio
];
208 hwif
->OUTW(speedp
, addr
);
209 hwif
->OUTW(speedt
, tfaddr
);
210 /* Now set up IORDY */
212 hwif
->OUTW(hwif
->INW(tfaddr
-2)|0x200, tfaddr
-2);
214 hwif
->OUTW(hwif
->INW(tfaddr
-2)&~0x200, tfaddr
-2);
216 mode
= hwif
->INB(base
+ addr_mask
);
217 mode
&= ~(unit
? 0x30 : 0x03);
218 mode
|= (unit
? 0x10 : 0x01);
219 hwif
->OUTB(mode
, base
+ addr_mask
);
221 pci_write_config_word(hwif
->pci_dev
, addr
, speedp
);
222 pci_write_config_word(hwif
->pci_dev
, tfaddr
, speedt
);
223 pci_read_config_word(hwif
->pci_dev
, tfaddr
-2, &speedp
);
225 /* Set IORDY for mode 3 or 4 */
228 pci_write_config_word(hwif
->pci_dev
, tfaddr
-2, speedp
);
230 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
231 mode
&= ~(unit
? 0x30 : 0x03);
232 mode
|= (unit
? 0x10 : 0x01);
233 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
238 * sil_set_dma_mode - set host controller for DMA mode
242 * Tune the SiI chipset for the desired DMA mode.
245 static void sil_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
247 u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
248 u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
249 u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
251 ide_hwif_t
*hwif
= HWIF(drive
);
252 u16 ultra
= 0, multi
= 0;
253 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
254 unsigned long base
= (unsigned long)hwif
->hwif_data
;
255 u8 scsc
= 0, addr_mask
= ((hwif
->channel
) ?
256 ((hwif
->mmio
) ? 0xF4 : 0x84) :
257 ((hwif
->mmio
) ? 0xB4 : 0x80));
259 unsigned long ma
= siimage_seldev(drive
, 0x08);
260 unsigned long ua
= siimage_seldev(drive
, 0x0C);
263 scsc
= hwif
->INB(base
+ 0x4A);
264 mode
= hwif
->INB(base
+ addr_mask
);
265 multi
= hwif
->INW(ma
);
266 ultra
= hwif
->INW(ua
);
268 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
269 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
270 pci_read_config_word(hwif
->pci_dev
, ma
, &multi
);
271 pci_read_config_word(hwif
->pci_dev
, ua
, &ultra
);
274 mode
&= ~((unit
) ? 0x30 : 0x03);
276 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
278 scsc
= is_sata(hwif
) ? 1 : scsc
;
284 multi
= dma
[speed
- XFER_MW_DMA_0
];
285 mode
|= ((unit
) ? 0x20 : 0x02);
295 ultra
|= ((scsc
) ? (ultra6
[speed
- XFER_UDMA_0
]) :
296 (ultra5
[speed
- XFER_UDMA_0
]));
297 mode
|= ((unit
) ? 0x30 : 0x03);
304 hwif
->OUTB(mode
, base
+ addr_mask
);
305 hwif
->OUTW(multi
, ma
);
306 hwif
->OUTW(ultra
, ua
);
308 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
309 pci_write_config_word(hwif
->pci_dev
, ma
, multi
);
310 pci_write_config_word(hwif
->pci_dev
, ua
, ultra
);
314 /* returns 1 if dma irq issued, 0 otherwise */
315 static int siimage_io_ide_dma_test_irq (ide_drive_t
*drive
)
317 ide_hwif_t
*hwif
= HWIF(drive
);
319 unsigned long addr
= siimage_selreg(hwif
, 1);
321 /* return 1 if INTR asserted */
322 if ((hwif
->INB(hwif
->dma_status
) & 4) == 4)
325 /* return 1 if Device INTR asserted */
326 pci_read_config_byte(hwif
->pci_dev
, addr
, &dma_altstat
);
328 return 0; //return 1;
333 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
334 * @drive: drive we are testing
336 * Check if we caused an IDE DMA interrupt. We may also have caused
337 * SATA status interrupts, if so we clean them up and continue.
340 static int siimage_mmio_ide_dma_test_irq (ide_drive_t
*drive
)
342 ide_hwif_t
*hwif
= HWIF(drive
);
343 unsigned long base
= (unsigned long)hwif
->hwif_data
;
344 unsigned long addr
= siimage_selreg(hwif
, 0x1);
346 if (SATA_ERROR_REG
) {
347 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
349 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
350 u32 sata_error
= readl((void __iomem
*)SATA_ERROR_REG
);
351 writel(sata_error
, (void __iomem
*)SATA_ERROR_REG
);
352 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
353 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
354 "watchdog = %d, %s\n",
355 drive
->name
, sata_error
, watchdog
,
359 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
363 if (!(ext_stat
& 0x0404) && !watchdog
)
367 /* return 1 if INTR asserted */
368 if ((readb((void __iomem
*)hwif
->dma_status
) & 0x04) == 0x04)
371 /* return 1 if Device INTR asserted */
372 if ((readb((void __iomem
*)addr
) & 8) == 8)
373 return 0; //return 1;
379 * siimage_busproc - bus isolation ioctl
380 * @drive: drive to isolate/restore
381 * @state: bus state to set
383 * Used by the SII3112 to handle bus isolation. As this is a
384 * SATA controller the work required is quite limited, we
385 * just have to clean up the statistics
388 static int siimage_busproc (ide_drive_t
* drive
, int state
)
390 ide_hwif_t
*hwif
= HWIF(drive
);
392 unsigned long addr
= siimage_selreg(hwif
, 0);
395 stat_config
= readl((void __iomem
*)addr
);
397 pci_read_config_dword(hwif
->pci_dev
, addr
, &stat_config
);
401 hwif
->drives
[0].failures
= 0;
402 hwif
->drives
[1].failures
= 0;
405 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
406 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
408 case BUSSTATE_TRISTATE
:
409 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
410 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
415 hwif
->bus_state
= state
;
420 * siimage_reset_poll - wait for sata reset
421 * @drive: drive we are resetting
423 * Poll the SATA phy and see whether it has come back from the dead
427 static int siimage_reset_poll (ide_drive_t
*drive
)
429 if (SATA_STATUS_REG
) {
430 ide_hwif_t
*hwif
= HWIF(drive
);
432 /* SATA_STATUS_REG is valid only when in MMIO mode */
433 if ((readl((void __iomem
*)SATA_STATUS_REG
) & 0x03) != 0x03) {
434 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
435 hwif
->name
, readl((void __iomem
*)SATA_STATUS_REG
));
436 HWGROUP(drive
)->polling
= 0;
446 * siimage_pre_reset - reset hook
447 * @drive: IDE device being reset
449 * For the SATA devices we need to handle recalibration/geometry
453 static void siimage_pre_reset (ide_drive_t
*drive
)
455 if (drive
->media
!= ide_disk
)
458 if (is_sata(HWIF(drive
)))
460 drive
->special
.b
.set_geometry
= 0;
461 drive
->special
.b
.recalibrate
= 0;
466 * siimage_reset - reset a device on an siimage controller
467 * @drive: drive to reset
469 * Perform a controller level reset fo the device. For
470 * SATA we must also check the PHY.
473 static void siimage_reset (ide_drive_t
*drive
)
475 ide_hwif_t
*hwif
= HWIF(drive
);
477 unsigned long addr
= siimage_selreg(hwif
, 0);
480 reset
= hwif
->INB(addr
);
481 hwif
->OUTB((reset
|0x03), addr
);
484 hwif
->OUTB(reset
, addr
);
485 (void) hwif
->INB(addr
);
487 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
488 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
|0x03);
490 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
);
491 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
494 if (SATA_STATUS_REG
) {
495 /* SATA_STATUS_REG is valid only when in MMIO mode */
496 u32 sata_stat
= readl((void __iomem
*)SATA_STATUS_REG
);
497 printk(KERN_WARNING
"%s: reset phy, status=0x%08x, %s\n",
498 hwif
->name
, sata_stat
, __FUNCTION__
);
500 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
501 hwif
->name
, sata_stat
);
509 * proc_reports_siimage - add siimage controller to proc
511 * @clocking: SCSC value
512 * @name: controller name
514 * Report the clocking mode of the controller and add it to
515 * the /proc interface layer
518 static void proc_reports_siimage (struct pci_dev
*dev
, u8 clocking
, const char *name
)
520 if (!pdev_is_sata(dev
)) {
521 printk(KERN_INFO
"%s: BASE CLOCK ", name
);
524 case 0x03: printk("DISABLED!\n"); break;
525 case 0x02: printk("== 2X PCI\n"); break;
526 case 0x01: printk("== 133\n"); break;
527 case 0x00: printk("== 100\n"); break;
533 * setup_mmio_siimage - switch an SI controller into MMIO
534 * @dev: PCI device we are configuring
537 * Attempt to put the device into mmio mode. There are some slight
538 * complications here with certain systems where the mmio bar isnt
539 * mapped so we have to be sure we can fall back to I/O.
542 static unsigned int setup_mmio_siimage (struct pci_dev
*dev
, const char *name
)
544 unsigned long bar5
= pci_resource_start(dev
, 5);
545 unsigned long barsize
= pci_resource_len(dev
, 5);
547 void __iomem
*ioaddr
;
551 * Drop back to PIO if we can't map the mmio. Some
552 * systems seem to get terminally confused in the PCI
556 if(!request_mem_region(bar5
, barsize
, name
))
558 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not available.\n");
562 ioaddr
= ioremap(bar5
, barsize
);
566 release_mem_region(bar5
, barsize
);
571 pci_set_drvdata(dev
, (void *) ioaddr
);
573 if (pdev_is_sata(dev
)) {
574 /* make sure IDE0/1 interrupts are not masked */
575 irq_mask
= (1 << 22) | (1 << 23);
576 tmp
= readl(ioaddr
+ 0x48);
577 if (tmp
& irq_mask
) {
579 writel(tmp
, ioaddr
+ 0x48);
580 readl(ioaddr
+ 0x48); /* flush */
582 writel(0, ioaddr
+ 0x148);
583 writel(0, ioaddr
+ 0x1C8);
586 writeb(0, ioaddr
+ 0xB4);
587 writeb(0, ioaddr
+ 0xF4);
588 tmpbyte
= readb(ioaddr
+ 0x4A);
590 switch(tmpbyte
& 0x30) {
592 /* In 100 MHz clocking, try and switch to 133 */
593 writeb(tmpbyte
|0x10, ioaddr
+ 0x4A);
596 /* On 133Mhz clocking */
599 /* On PCIx2 clocking */
602 /* Clocking is disabled */
603 /* 133 clock attempt to force it on */
604 writeb(tmpbyte
& ~0x20, ioaddr
+ 0x4A);
608 writeb( 0x72, ioaddr
+ 0xA1);
609 writew( 0x328A, ioaddr
+ 0xA2);
610 writel(0x62DD62DD, ioaddr
+ 0xA4);
611 writel(0x43924392, ioaddr
+ 0xA8);
612 writel(0x40094009, ioaddr
+ 0xAC);
613 writeb( 0x72, ioaddr
+ 0xE1);
614 writew( 0x328A, ioaddr
+ 0xE2);
615 writel(0x62DD62DD, ioaddr
+ 0xE4);
616 writel(0x43924392, ioaddr
+ 0xE8);
617 writel(0x40094009, ioaddr
+ 0xEC);
619 if (pdev_is_sata(dev
)) {
620 writel(0xFFFF0000, ioaddr
+ 0x108);
621 writel(0xFFFF0000, ioaddr
+ 0x188);
622 writel(0x00680000, ioaddr
+ 0x148);
623 writel(0x00680000, ioaddr
+ 0x1C8);
626 tmpbyte
= readb(ioaddr
+ 0x4A);
628 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
633 * init_chipset_siimage - set up an SI device
637 * Perform the initial PCI set up for this device. Attempt to switch
638 * to 133MHz clocking if the system isn't already set up to do it.
641 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
, const char *name
)
647 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
649 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (class_rev
) ? 1 : 255);
651 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
652 if ((BA5_EN
& 0x01) || (pci_resource_start(dev
, 5))) {
653 if (setup_mmio_siimage(dev
, name
)) {
658 pci_write_config_byte(dev
, 0x80, 0x00);
659 pci_write_config_byte(dev
, 0x84, 0x00);
660 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
661 switch(tmpbyte
& 0x30) {
663 /* 133 clock attempt to force it on */
664 pci_write_config_byte(dev
, 0x8A, tmpbyte
|0x10);
666 /* if clocking is disabled */
667 /* 133 clock attempt to force it on */
668 pci_write_config_byte(dev
, 0x8A, tmpbyte
& ~0x20);
673 /* BIOS set PCI x2 clocking */
677 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
679 pci_write_config_byte(dev
, 0xA1, 0x72);
680 pci_write_config_word(dev
, 0xA2, 0x328A);
681 pci_write_config_dword(dev
, 0xA4, 0x62DD62DD);
682 pci_write_config_dword(dev
, 0xA8, 0x43924392);
683 pci_write_config_dword(dev
, 0xAC, 0x40094009);
684 pci_write_config_byte(dev
, 0xB1, 0x72);
685 pci_write_config_word(dev
, 0xB2, 0x328A);
686 pci_write_config_dword(dev
, 0xB4, 0x62DD62DD);
687 pci_write_config_dword(dev
, 0xB8, 0x43924392);
688 pci_write_config_dword(dev
, 0xBC, 0x40094009);
690 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
695 * init_mmio_iops_siimage - set up the iops for MMIO
696 * @hwif: interface to set up
698 * The basic setup here is fairly simple, we can use standard MMIO
699 * operations. However we do have to set the taskfile register offsets
700 * by hand as there isnt a standard defined layout for them this
703 * The hardware supports buffered taskfiles and also some rather nice
704 * extended PRD tables. For better SI3112 support use the libata driver
707 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
709 struct pci_dev
*dev
= hwif
->pci_dev
;
710 void *addr
= pci_get_drvdata(dev
);
711 u8 ch
= hwif
->channel
;
716 * Fill in the basic HWIF bits
719 default_hwif_mmiops(hwif
);
720 hwif
->hwif_data
= addr
;
723 * Now set up the hw. We have to do this ourselves as
724 * the MMIO layout isnt the same as the standard port
728 memset(&hw
, 0, sizeof(hw_regs_t
));
730 base
= (unsigned long)addr
;
737 * The buffered task file doesn't have status/control
738 * so we can't currently use it sanely since we want to
741 hw
.io_ports
[IDE_DATA_OFFSET
] = base
;
742 hw
.io_ports
[IDE_ERROR_OFFSET
] = base
+ 1;
743 hw
.io_ports
[IDE_NSECTOR_OFFSET
] = base
+ 2;
744 hw
.io_ports
[IDE_SECTOR_OFFSET
] = base
+ 3;
745 hw
.io_ports
[IDE_LCYL_OFFSET
] = base
+ 4;
746 hw
.io_ports
[IDE_HCYL_OFFSET
] = base
+ 5;
747 hw
.io_ports
[IDE_SELECT_OFFSET
] = base
+ 6;
748 hw
.io_ports
[IDE_STATUS_OFFSET
] = base
+ 7;
749 hw
.io_ports
[IDE_CONTROL_OFFSET
] = base
+ 10;
751 hw
.io_ports
[IDE_IRQ_OFFSET
] = 0;
753 if (pdev_is_sata(dev
)) {
754 base
= (unsigned long)addr
;
757 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
758 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
759 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
760 hwif
->sata_misc
[SATA_MISC_OFFSET
] = base
+ 0x140;
761 hwif
->sata_misc
[SATA_PHY_OFFSET
] = base
+ 0x144;
762 hwif
->sata_misc
[SATA_IEN_OFFSET
] = base
+ 0x148;
765 hw
.irq
= hwif
->pci_dev
->irq
;
767 memcpy(&hwif
->hw
, &hw
, sizeof(hw
));
768 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->hw
.io_ports
));
772 base
= (unsigned long) addr
;
774 hwif
->dma_base
= base
+ (ch
? 0x08 : 0x00);
779 static int is_dev_seagate_sata(ide_drive_t
*drive
)
781 const char *s
= &drive
->id
->model
[0];
787 len
= strnlen(s
, sizeof(drive
->id
->model
));
789 if ((len
> 4) && (!memcmp(s
, "ST", 2))) {
790 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
791 (!memcmp(s
+ len
- 3, "ASL", 3))) {
792 printk(KERN_INFO
"%s: applying pessimistic Seagate "
793 "errata fix\n", drive
->name
);
801 * siimage_fixup - post probe fixups
802 * @hwif: interface to fix up
804 * Called after drive probe we use this to decide whether the
805 * Seagate fixup must be applied. This used to be in init_iops but
806 * that can occur before we know what drives are present.
809 static void __devinit
siimage_fixup(ide_hwif_t
*hwif
)
811 /* Try and raise the rqsize */
812 if (!is_sata(hwif
) || !is_dev_seagate_sata(&hwif
->drives
[0]))
817 * init_iops_siimage - set up iops
818 * @hwif: interface to set up
820 * Do the basic setup for the SIIMAGE hardware interface
821 * and then do the MMIO setup if we can. This is the first
822 * look in we get for setting up the hwif so that we
823 * can get the iops right before using them.
826 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
828 struct pci_dev
*dev
= hwif
->pci_dev
;
831 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
834 hwif
->hwif_data
= NULL
;
836 /* Pessimal until we finish probing */
839 if (pci_get_drvdata(dev
) == NULL
)
841 init_mmio_iops_siimage(hwif
);
845 * ata66_siimage - check for 80 pin cable
846 * @hwif: interface to check
848 * Check for the presence of an ATA66 capable cable on the
852 static u8 __devinit
ata66_siimage(ide_hwif_t
*hwif
)
854 unsigned long addr
= siimage_selreg(hwif
, 0);
857 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
)
858 pci_read_config_byte(hwif
->pci_dev
, addr
, &ata66
);
860 ata66
= hwif
->INB(addr
);
862 return (ata66
& 0x01) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
866 * init_hwif_siimage - set up hwif structs
867 * @hwif: interface to set up
869 * We do the basic set up of the interface structure. The SIIMAGE
870 * requires several custom handlers so we override the default
871 * ide DMA handlers appropriately
874 static void __devinit
init_hwif_siimage(ide_hwif_t
*hwif
)
876 hwif
->resetproc
= &siimage_reset
;
877 hwif
->set_pio_mode
= &sil_set_pio_mode
;
878 hwif
->set_dma_mode
= &sil_set_dma_mode
;
879 hwif
->reset_poll
= &siimage_reset_poll
;
880 hwif
->pre_reset
= &siimage_pre_reset
;
881 hwif
->udma_filter
= &sil_udma_filter
;
884 static int first
= 1;
886 hwif
->busproc
= &siimage_busproc
;
889 printk(KERN_INFO
"siimage: For full SATA support you should use the libata sata_sil module.\n");
894 hwif
->drives
[0].autotune
= hwif
->drives
[1].autotune
= 1;
896 if (hwif
->dma_base
== 0)
899 hwif
->ultra_mask
= 0x7f;
900 hwif
->mwdma_mask
= 0x07;
903 hwif
->host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
905 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
906 hwif
->cbl
= ata66_siimage(hwif
);
909 hwif
->ide_dma_test_irq
= &siimage_mmio_ide_dma_test_irq
;
911 hwif
->ide_dma_test_irq
= & siimage_io_ide_dma_test_irq
;
915 #define DECLARE_SII_DEV(name_str) \
918 .init_chipset = init_chipset_siimage, \
919 .init_iops = init_iops_siimage, \
920 .init_hwif = init_hwif_siimage, \
921 .fixup = siimage_fixup, \
922 .autodma = AUTODMA, \
923 .host_flags = IDE_HFLAG_BOOTABLE, \
924 .pio_mask = ATA_PIO4, \
927 static ide_pci_device_t siimage_chipsets
[] __devinitdata
= {
928 /* 0 */ DECLARE_SII_DEV("SiI680"),
929 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
930 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
934 * siimage_init_one - pci layer discovery entry
936 * @id: ident table entry
938 * Called by the PCI code when it finds an SI680 or SI3112 controller.
939 * We then use the IDE PCI generic helper to do most of the work.
942 static int __devinit
siimage_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
944 return ide_setup_pci_device(dev
, &siimage_chipsets
[id
->driver_data
]);
947 static const struct pci_device_id siimage_pci_tbl
[] = {
948 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_680
), 0 },
949 #ifdef CONFIG_BLK_DEV_IDE_SATA
950 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_3112
), 1 },
951 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_1210SA
), 2 },
955 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
957 static struct pci_driver driver
= {
959 .id_table
= siimage_pci_tbl
,
960 .probe
= siimage_init_one
,
963 static int __init
siimage_ide_init(void)
965 return ide_pci_register_driver(&driver
);
968 module_init(siimage_ide_init
);
970 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
971 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
972 MODULE_LICENSE("GPL");