| blob | 593285419e759fff9b36ba6408f51ea6d16b1cde |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
33 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34 #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
35 #define PMD_FLAGS_UP PMD_SECT_WB
37 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38 #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
41 ENTRY(cpu_v7_proc_init)
42 mov pc, lr
43 ENDPROC(cpu_v7_proc_init)
45 ENTRY(cpu_v7_proc_fin)
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x0006 @ .............ca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mov pc, lr
51 ENDPROC(cpu_v7_proc_fin)
53 /*
54 * cpu_v7_reset(loc)
55 *
56 * Perform a soft reset of the system. Put the CPU into the
57 * same state as it would be if it had been reset, and branch
58 * to what would be the reset vector.
59 *
60 * - loc - location to jump to for soft reset
61 */
62 .align 5
63 ENTRY(cpu_v7_reset)
64 mov pc, r0
65 ENDPROC(cpu_v7_reset)
67 /*
68 * cpu_v7_do_idle()
69 *
70 * Idle the processor (eg, wait for interrupt).
71 *
72 * IRQs are already disabled.
73 */
74 ENTRY(cpu_v7_do_idle)
75 dsb @ WFI may enter a low-power mode
76 wfi
77 mov pc, lr
78 ENDPROC(cpu_v7_do_idle)
80 ENTRY(cpu_v7_dcache_clean_area)
81 #ifndef TLB_CAN_READ_FROM_L1_CACHE
82 dcache_line_size r2, r3
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, r2
85 subs r1, r1, r2
86 bhi 1b
87 dsb
88 #endif
89 mov pc, lr
90 ENDPROC(cpu_v7_dcache_clean_area)
92 /*
93 * cpu_v7_switch_mm(pgd_phys, tsk)
94 *
95 * Set the translation table base pointer to be pgd_phys
96 *
97 * - pgd_phys - physical address of new TTB
98 *
99 * It is assumed that:
100 * - we are not using split page tables
101 */
102 ENTRY(cpu_v7_switch_mm)
103 #ifdef CONFIG_MMU
104 mov r2, #0
105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
108 #ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110 #endif
111 #ifdef CONFIG_ARM_ERRATA_754322
112 dsb
113 #endif
114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
115 isb
116 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
117 isb
118 #ifdef CONFIG_ARM_ERRATA_754322
119 dsb
120 #endif
121 mcr p15, 0, r1, c13, c0, 1 @ set context ID
122 isb
123 #endif
124 mov pc, lr
125 ENDPROC(cpu_v7_switch_mm)
127 /*
128 * cpu_v7_set_pte_ext(ptep, pte)
129 *
130 * Set a level 2 translation table entry.
131 *
132 * - ptep - pointer to level 2 translation table entry
133 * (hardware version is stored at +2048 bytes)
134 * - pte - PTE value to store
135 * - ext - value for extended PTE bits
136 */
137 ENTRY(cpu_v7_set_pte_ext)
138 #ifdef CONFIG_MMU
139 str r1, [r0] @ linux version
141 bic r3, r1, #0x000003f0
142 bic r3, r3, #PTE_TYPE_MASK
143 orr r3, r3, r2
144 orr r3, r3, #PTE_EXT_AP0 | 2
146 tst r1, #1 << 4
147 orrne r3, r3, #PTE_EXT_TEX(1)
149 eor r1, r1, #L_PTE_DIRTY
150 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
151 orrne r3, r3, #PTE_EXT_APX
153 tst r1, #L_PTE_USER
154 orrne r3, r3, #PTE_EXT_AP1
155 #ifdef CONFIG_CPU_USE_DOMAINS
156 @ allow kernel read/write access to read-only user pages
157 tstne r3, #PTE_EXT_APX
158 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
159 #endif
161 tst r1, #L_PTE_XN
162 orrne r3, r3, #PTE_EXT_XN
164 tst r1, #L_PTE_YOUNG
165 tstne r1, #L_PTE_PRESENT
166 moveq r3, #0
168 ARM( str r3, [r0, #2048]! )
169 THUMB( add r0, r0, #2048 )
170 THUMB( str r3, [r0] )
171 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
172 #endif
173 mov pc, lr
174 ENDPROC(cpu_v7_set_pte_ext)
176 string cpu_v7_name, "ARMv7 Processor"
177 .align
179 /*
180 * Memory region attributes with SCTLR.TRE=1
181 *
182 * n = TEX[0],C,B
183 * TR = PRRR[2n+1:2n] - memory type
184 * IR = NMRR[2n+1:2n] - inner cacheable property
185 * OR = NMRR[2n+17:2n+16] - outer cacheable property
186 *
187 * n TR IR OR
188 * UNCACHED 000 00
189 * BUFFERABLE 001 10 00 00
190 * WRITETHROUGH 010 10 10 10
191 * WRITEBACK 011 10 11 11
192 * reserved 110
193 * WRITEALLOC 111 10 01 01
194 * DEV_SHARED 100 01
195 * DEV_NONSHARED 100 01
196 * DEV_WC 001 10
197 * DEV_CACHED 011 10
198 *
199 * Other attributes:
200 *
201 * DS0 = PRRR[16] = 0 - device shareable property
202 * DS1 = PRRR[17] = 1 - device shareable property
203 * NS0 = PRRR[18] = 0 - normal shareable property
204 * NS1 = PRRR[19] = 1 - normal shareable property
205 * NOS = PRRR[24+n] = 1 - not outer shareable
206 */
207 .equ PRRR, 0xff0a81a8
208 .equ NMRR, 0x40e040e0
210 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
211 .globl cpu_v7_suspend_size
212 .equ cpu_v7_suspend_size, 4 * 9
213 #ifdef CONFIG_PM_SLEEP
214 ENTRY(cpu_v7_do_suspend)
215 stmfd sp!, {r4 - r11, lr}
216 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
217 mrc p15, 0, r5, c13, c0, 1 @ Context ID
218 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
219 stmia r0!, {r4 - r6}
220 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
221 mrc p15, 0, r7, c2, c0, 0 @ TTB 0
222 mrc p15, 0, r8, c2, c0, 1 @ TTB 1
223 mrc p15, 0, r9, c1, c0, 0 @ Control register
224 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
225 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
226 stmia r0, {r6 - r11}
227 ldmfd sp!, {r4 - r11, pc}
228 ENDPROC(cpu_v7_do_suspend)
230 ENTRY(cpu_v7_do_resume)
231 mov ip, #0
232 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
233 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
234 ldmia r0!, {r4 - r6}
235 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
236 mcr p15, 0, r5, c13, c0, 1 @ Context ID
237 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
238 ldmia r0, {r6 - r11}
239 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
240 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
241 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
242 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
243 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
244 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
245 ldr r4, =PRRR @ PRRR
246 ldr r5, =NMRR @ NMRR
247 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
248 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
249 isb
250 mov r0, r9 @ control register
251 mov r2, r7, lsr #14 @ get TTB0 base
252 mov r2, r2, lsl #14
253 ldr r3, cpu_resume_l1_flags
254 b cpu_resume_mmu
255 ENDPROC(cpu_v7_do_resume)
256 cpu_resume_l1_flags:
257 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
258 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
259 #else
260 #define cpu_v7_do_suspend 0
261 #define cpu_v7_do_resume 0
262 #endif
264 __CPUINIT
266 /*
267 * __v7_setup
268 *
269 * Initialise TLB, Caches, and MMU state ready to switch the MMU
270 * on. Return in r0 the new CP15 C1 control register setting.
271 *
272 * We automatically detect if we have a Harvard cache, and use the
273 * Harvard cache control instructions insead of the unified cache
274 * control instructions.
275 *
276 * This should be able to cover all ARMv7 cores.
277 *
278 * It is assumed that:
279 * - cache type register is implemented
280 */
281 __v7_ca5mp_setup:
282 __v7_ca9mp_setup:
283 mov r10, #(1 << 0) @ TLB ops broadcasting
284 b 1f
285 __v7_ca15mp_setup:
286 mov r10, #0
287 1:
288 #ifdef CONFIG_SMP
289 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
290 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
291 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
292 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
293 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
294 mcreq p15, 0, r0, c1, c0, 1
295 #endif
296 __v7_setup:
297 adr r12, __v7_setup_stack @ the local stack
298 stmia r12, {r0-r5, r7, r9, r11, lr}
299 bl v7_flush_dcache_all
300 ldmia r12, {r0-r5, r7, r9, r11, lr}
302 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
303 and r10, r0, #0xff000000 @ ARM?
304 teq r10, #0x41000000
305 bne 3f
306 and r5, r0, #0x00f00000 @ variant
307 and r6, r0, #0x0000000f @ revision
308 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
309 ubfx r0, r0, #4, #12 @ primary part number
311 /* Cortex-A8 Errata */
312 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
313 teq r0, r10
314 bne 2f
315 #ifdef CONFIG_ARM_ERRATA_430973
316 teq r5, #0x00100000 @ only present in r1p*
317 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
318 orreq r10, r10, #(1 << 6) @ set IBE to 1
319 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
320 #endif
321 #ifdef CONFIG_ARM_ERRATA_458693
322 teq r6, #0x20 @ only present in r2p0
323 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
324 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
325 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
326 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
327 #endif
328 #ifdef CONFIG_ARM_ERRATA_460075
329 teq r6, #0x20 @ only present in r2p0
330 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
331 tsteq r10, #1 << 22
332 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
333 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
334 #endif
335 b 3f
337 /* Cortex-A9 Errata */
338 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
339 teq r0, r10
340 bne 3f
341 #ifdef CONFIG_ARM_ERRATA_742230
342 cmp r6, #0x22 @ only present up to r2p2
343 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
344 orrle r10, r10, #1 << 4 @ set bit #4
345 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
346 #endif
347 #ifdef CONFIG_ARM_ERRATA_742231
348 teq r6, #0x20 @ present in r2p0
349 teqne r6, #0x21 @ present in r2p1
350 teqne r6, #0x22 @ present in r2p2
351 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
352 orreq r10, r10, #1 << 12 @ set bit #12
353 orreq r10, r10, #1 << 22 @ set bit #22
354 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
355 #endif
356 #ifdef CONFIG_ARM_ERRATA_743622
357 teq r6, #0x20 @ present in r2p0
358 teqne r6, #0x21 @ present in r2p1
359 teqne r6, #0x22 @ present in r2p2
360 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
361 orreq r10, r10, #1 << 6 @ set bit #6
362 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
363 #endif
364 #ifdef CONFIG_ARM_ERRATA_751472
365 cmp r6, #0x30 @ present prior to r3p0
366 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
367 orrlt r10, r10, #1 << 11 @ set bit #11
368 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
369 #endif
371 3: mov r10, #0
372 #ifdef HARVARD_CACHE
373 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
374 #endif
375 dsb
376 #ifdef CONFIG_MMU
377 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
378 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
379 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
380 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
381 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
382 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
383 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
384 ldr r5, =PRRR @ PRRR
385 ldr r6, =NMRR @ NMRR
386 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
387 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
388 #endif
389 adr r5, v7_crval
390 ldmia r5, {r5, r6}
391 #ifdef CONFIG_CPU_ENDIAN_BE8
392 orr r6, r6, #1 << 25 @ big-endian page tables
393 #endif
394 #ifdef CONFIG_SWP_EMULATE
395 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
396 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
397 #endif
398 mrc p15, 0, r0, c1, c0, 0 @ read control register
399 bic r0, r0, r5 @ clear bits them
400 orr r0, r0, r6 @ set them
401 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
402 mov pc, lr @ return to head.S:__ret
403 ENDPROC(__v7_setup)
405 /* AT
406 * TFR EV X F I D LR S
407 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
408 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
409 * 1 0 110 0011 1100 .111 1101 < we want
410 */
411 .type v7_crval, #object
412 v7_crval:
413 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
415 __v7_setup_stack:
416 .space 4 * 11 @ 11 registers
418 __INITDATA
420 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
421 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
423 .section ".rodata"
425 string cpu_arch_name, "armv7"
426 string cpu_elf_name, "v7"
427 .align
429 .section ".proc.info.init", #alloc, #execinstr
431 /*
432 * Standard v7 proc info content
433 */
434 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
435 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
436 PMD_FLAGS_SMP | \mm_mmuflags)
437 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
438 PMD_FLAGS_UP | \mm_mmuflags)
439 .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
440 PMD_SECT_AP_READ | \io_mmuflags
441 W(b) \initfunc
442 .long cpu_arch_name
443 .long cpu_elf_name
444 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
445 HWCAP_EDSP | HWCAP_TLS | \hwcaps
446 .long cpu_v7_name
447 .long v7_processor_functions
448 .long v7wbi_tlb_fns
449 .long v6_user_fns
450 .long v7_cache_fns
451 .endm
453 /*
454 * ARM Ltd. Cortex A5 processor.
455 */
456 .type __v7_ca5mp_proc_info, #object
457 __v7_ca5mp_proc_info:
458 .long 0x410fc050
459 .long 0xff0ffff0
460 __v7_proc __v7_ca5mp_setup
461 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
463 /*
464 * ARM Ltd. Cortex A9 processor.
465 */
466 .type __v7_ca9mp_proc_info, #object
467 __v7_ca9mp_proc_info:
468 .long 0x410fc090
469 .long 0xff0ffff0
470 __v7_proc __v7_ca9mp_setup
471 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
473 /*
474 * ARM Ltd. Cortex A15 processor.
475 */
476 .type __v7_ca15mp_proc_info, #object
477 __v7_ca15mp_proc_info:
478 .long 0x410fc0f0
479 .long 0xff0ffff0
480 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
481 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
483 /*
484 * Match any ARMv7 processor core.
485 */
486 .type __v7_proc_info, #object
487 __v7_proc_info:
488 .long 0x000f0000 @ Required ID value
489 .long 0x000f0000 @ Mask for ID
490 __v7_proc __v7_setup
491 .size __v7_proc_info, . - __v7_proc_info