1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
29 #include "workarounds.h"
31 /* Hardware control for SFC4000 (aka Falcon). */
33 static const unsigned int
34 /* "Large" EEPROM device: Atmel AT25640 or similar
35 * 8 KB, 16-bit address, 32 B write block */
36 large_eeprom_type
= ((13 << SPI_DEV_TYPE_SIZE_LBN
)
37 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
38 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
)),
39 /* Default flash device: Atmel AT25F1024
40 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
41 default_flash_type
= ((17 << SPI_DEV_TYPE_SIZE_LBN
)
42 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
43 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN
)
44 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN
)
45 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
));
47 /**************************************************************************
49 * I2C bus - this is a bit-bashing interface using GPIO pins
50 * Note that it uses the output enables to tristate the outputs
51 * SDA is the data pin and SCL is the clock
53 **************************************************************************
55 static void falcon_setsda(void *data
, int state
)
57 struct efx_nic
*efx
= (struct efx_nic
*)data
;
60 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
61 EFX_SET_OWORD_FIELD(reg
, FRF_AB_GPIO3_OEN
, !state
);
62 efx_writeo(efx
, ®
, FR_AB_GPIO_CTL
);
65 static void falcon_setscl(void *data
, int state
)
67 struct efx_nic
*efx
= (struct efx_nic
*)data
;
70 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
71 EFX_SET_OWORD_FIELD(reg
, FRF_AB_GPIO0_OEN
, !state
);
72 efx_writeo(efx
, ®
, FR_AB_GPIO_CTL
);
75 static int falcon_getsda(void *data
)
77 struct efx_nic
*efx
= (struct efx_nic
*)data
;
80 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
81 return EFX_OWORD_FIELD(reg
, FRF_AB_GPIO3_IN
);
84 static int falcon_getscl(void *data
)
86 struct efx_nic
*efx
= (struct efx_nic
*)data
;
89 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
90 return EFX_OWORD_FIELD(reg
, FRF_AB_GPIO0_IN
);
93 static struct i2c_algo_bit_data falcon_i2c_bit_operations
= {
94 .setsda
= falcon_setsda
,
95 .setscl
= falcon_setscl
,
96 .getsda
= falcon_getsda
,
97 .getscl
= falcon_getscl
,
99 /* Wait up to 50 ms for slave to let us pull SCL high */
100 .timeout
= DIV_ROUND_UP(HZ
, 20),
103 static void falcon_push_irq_moderation(struct efx_channel
*channel
)
105 efx_dword_t timer_cmd
;
106 struct efx_nic
*efx
= channel
->efx
;
108 /* Set timer register */
109 if (channel
->irq_moderation
) {
110 EFX_POPULATE_DWORD_2(timer_cmd
,
111 FRF_AB_TC_TIMER_MODE
,
112 FFE_BB_TIMER_MODE_INT_HLDOFF
,
114 channel
->irq_moderation
- 1);
116 EFX_POPULATE_DWORD_2(timer_cmd
,
117 FRF_AB_TC_TIMER_MODE
,
118 FFE_BB_TIMER_MODE_DIS
,
119 FRF_AB_TC_TIMER_VAL
, 0);
121 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER
!= FR_BZ_TIMER_COMMAND_P0
);
122 efx_writed_page_locked(efx
, &timer_cmd
, FR_BZ_TIMER_COMMAND_P0
,
126 static void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
);
128 static void falcon_prepare_flush(struct efx_nic
*efx
)
130 falcon_deconfigure_mac_wrapper(efx
);
132 /* Wait for the tx and rx fifo's to get to the next packet boundary
133 * (~1ms without back-pressure), then to drain the remainder of the
134 * fifo's at data path speeds (negligible), with a healthy margin. */
138 /* Acknowledge a legacy interrupt from Falcon
140 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
142 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
143 * BIU. Interrupt acknowledge is read sensitive so must write instead
144 * (then read to ensure the BIU collector is flushed)
146 * NB most hardware supports MSI interrupts
148 inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
152 EFX_POPULATE_DWORD_1(reg
, FRF_AA_INT_ACK_KER_FIELD
, 0xb7eb7e);
153 efx_writed(efx
, ®
, FR_AA_INT_ACK_KER
);
154 efx_readd(efx
, ®
, FR_AA_WORK_AROUND_BROKEN_PCI_READS
);
158 irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
160 struct efx_nic
*efx
= dev_id
;
161 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
165 /* Check to see if this is our interrupt. If it isn't, we
166 * exit without having touched the hardware.
168 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
169 netif_vdbg(efx
, intr
, efx
->net_dev
,
170 "IRQ %d on CPU %d not for me\n", irq
,
171 raw_smp_processor_id());
174 efx
->last_irq_cpu
= raw_smp_processor_id();
175 netif_vdbg(efx
, intr
, efx
->net_dev
,
176 "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
177 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
179 /* Determine interrupting queues, clear interrupt status
180 * register and acknowledge the device interrupt.
182 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH
> EFX_MAX_CHANNELS
);
183 queues
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_INT_Q
);
185 /* Check to see if we have a serious error condition */
186 if (queues
& (1U << efx
->fatal_irq_level
)) {
187 syserr
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_FATAL_INT
);
188 if (unlikely(syserr
))
189 return efx_nic_fatal_interrupt(efx
);
192 EFX_ZERO_OWORD(*int_ker
);
193 wmb(); /* Ensure the vector is cleared before interrupt ack */
194 falcon_irq_ack_a1(efx
);
197 efx_schedule_channel(efx_get_channel(efx
, 0));
199 efx_schedule_channel(efx_get_channel(efx
, 1));
202 /**************************************************************************
206 **************************************************************************
209 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
211 static int falcon_spi_poll(struct efx_nic
*efx
)
214 efx_reado(efx
, ®
, FR_AB_EE_SPI_HCMD
);
215 return EFX_OWORD_FIELD(reg
, FRF_AB_EE_SPI_HCMD_CMD_EN
) ? -EBUSY
: 0;
218 /* Wait for SPI command completion */
219 static int falcon_spi_wait(struct efx_nic
*efx
)
221 /* Most commands will finish quickly, so we start polling at
222 * very short intervals. Sometimes the command may have to
223 * wait for VPD or expansion ROM access outside of our
224 * control, so we allow up to 100 ms. */
225 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 10);
228 for (i
= 0; i
< 10; i
++) {
229 if (!falcon_spi_poll(efx
))
235 if (!falcon_spi_poll(efx
))
237 if (time_after_eq(jiffies
, timeout
)) {
238 netif_err(efx
, hw
, efx
->net_dev
,
239 "timed out waiting for SPI\n");
242 schedule_timeout_uninterruptible(1);
246 int falcon_spi_cmd(struct efx_nic
*efx
, const struct efx_spi_device
*spi
,
247 unsigned int command
, int address
,
248 const void *in
, void *out
, size_t len
)
250 bool addressed
= (address
>= 0);
251 bool reading
= (out
!= NULL
);
255 /* Input validation */
256 if (len
> FALCON_SPI_MAX_LEN
)
258 BUG_ON(!mutex_is_locked(&efx
->spi_lock
));
260 /* Check that previous command is not still running */
261 rc
= falcon_spi_poll(efx
);
265 /* Program address register, if we have an address */
267 EFX_POPULATE_OWORD_1(reg
, FRF_AB_EE_SPI_HADR_ADR
, address
);
268 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HADR
);
271 /* Program data register, if we have data */
273 memcpy(®
, in
, len
);
274 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HDATA
);
277 /* Issue read/write command */
278 EFX_POPULATE_OWORD_7(reg
,
279 FRF_AB_EE_SPI_HCMD_CMD_EN
, 1,
280 FRF_AB_EE_SPI_HCMD_SF_SEL
, spi
->device_id
,
281 FRF_AB_EE_SPI_HCMD_DABCNT
, len
,
282 FRF_AB_EE_SPI_HCMD_READ
, reading
,
283 FRF_AB_EE_SPI_HCMD_DUBCNT
, 0,
284 FRF_AB_EE_SPI_HCMD_ADBCNT
,
285 (addressed
? spi
->addr_len
: 0),
286 FRF_AB_EE_SPI_HCMD_ENC
, command
);
287 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HCMD
);
289 /* Wait for read/write to complete */
290 rc
= falcon_spi_wait(efx
);
296 efx_reado(efx
, ®
, FR_AB_EE_SPI_HDATA
);
297 memcpy(out
, ®
, len
);
304 falcon_spi_write_limit(const struct efx_spi_device
*spi
, size_t start
)
306 return min(FALCON_SPI_MAX_LEN
,
307 (spi
->block_size
- (start
& (spi
->block_size
- 1))));
311 efx_spi_munge_command(const struct efx_spi_device
*spi
,
312 const u8 command
, const unsigned int address
)
314 return command
| (((address
>> 8) & spi
->munge_address
) << 3);
317 /* Wait up to 10 ms for buffered write completion */
319 falcon_spi_wait_write(struct efx_nic
*efx
, const struct efx_spi_device
*spi
)
321 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 100);
326 rc
= falcon_spi_cmd(efx
, spi
, SPI_RDSR
, -1, NULL
,
327 &status
, sizeof(status
));
330 if (!(status
& SPI_STATUS_NRDY
))
332 if (time_after_eq(jiffies
, timeout
)) {
333 netif_err(efx
, hw
, efx
->net_dev
,
334 "SPI write timeout on device %d"
335 " last status=0x%02x\n",
336 spi
->device_id
, status
);
339 schedule_timeout_uninterruptible(1);
343 int falcon_spi_read(struct efx_nic
*efx
, const struct efx_spi_device
*spi
,
344 loff_t start
, size_t len
, size_t *retlen
, u8
*buffer
)
346 size_t block_len
, pos
= 0;
347 unsigned int command
;
351 block_len
= min(len
- pos
, FALCON_SPI_MAX_LEN
);
353 command
= efx_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
354 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
, NULL
,
355 buffer
+ pos
, block_len
);
360 /* Avoid locking up the system */
362 if (signal_pending(current
)) {
374 falcon_spi_write(struct efx_nic
*efx
, const struct efx_spi_device
*spi
,
375 loff_t start
, size_t len
, size_t *retlen
, const u8
*buffer
)
377 u8 verify_buffer
[FALCON_SPI_MAX_LEN
];
378 size_t block_len
, pos
= 0;
379 unsigned int command
;
383 rc
= falcon_spi_cmd(efx
, spi
, SPI_WREN
, -1, NULL
, NULL
, 0);
387 block_len
= min(len
- pos
,
388 falcon_spi_write_limit(spi
, start
+ pos
));
389 command
= efx_spi_munge_command(spi
, SPI_WRITE
, start
+ pos
);
390 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
,
391 buffer
+ pos
, NULL
, block_len
);
395 rc
= falcon_spi_wait_write(efx
, spi
);
399 command
= efx_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
400 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
,
401 NULL
, verify_buffer
, block_len
);
402 if (memcmp(verify_buffer
, buffer
+ pos
, block_len
)) {
409 /* Avoid locking up the system */
411 if (signal_pending(current
)) {
422 /**************************************************************************
426 **************************************************************************
429 static void falcon_push_multicast_hash(struct efx_nic
*efx
)
431 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
433 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
435 efx_writeo(efx
, &mc_hash
->oword
[0], FR_AB_MAC_MC_HASH_REG0
);
436 efx_writeo(efx
, &mc_hash
->oword
[1], FR_AB_MAC_MC_HASH_REG1
);
439 static void falcon_reset_macs(struct efx_nic
*efx
)
441 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
442 efx_oword_t reg
, mac_ctrl
;
445 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) {
446 /* It's not safe to use GLB_CTL_REG to reset the
447 * macs, so instead use the internal MAC resets
449 EFX_POPULATE_OWORD_1(reg
, FRF_AB_XM_CORE_RST
, 1);
450 efx_writeo(efx
, ®
, FR_AB_XM_GLB_CFG
);
452 for (count
= 0; count
< 10000; count
++) {
453 efx_reado(efx
, ®
, FR_AB_XM_GLB_CFG
);
454 if (EFX_OWORD_FIELD(reg
, FRF_AB_XM_CORE_RST
) ==
460 netif_err(efx
, hw
, efx
->net_dev
,
461 "timed out waiting for XMAC core reset\n");
464 /* Mac stats will fail whist the TX fifo is draining */
465 WARN_ON(nic_data
->stats_disable_count
== 0);
467 efx_reado(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
468 EFX_SET_OWORD_FIELD(mac_ctrl
, FRF_BB_TXFIFO_DRAIN_EN
, 1);
469 efx_writeo(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
471 efx_reado(efx
, ®
, FR_AB_GLB_CTL
);
472 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_XGTX
, 1);
473 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_XGRX
, 1);
474 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_EM
, 1);
475 efx_writeo(efx
, ®
, FR_AB_GLB_CTL
);
479 efx_reado(efx
, ®
, FR_AB_GLB_CTL
);
480 if (!EFX_OWORD_FIELD(reg
, FRF_AB_RST_XGTX
) &&
481 !EFX_OWORD_FIELD(reg
, FRF_AB_RST_XGRX
) &&
482 !EFX_OWORD_FIELD(reg
, FRF_AB_RST_EM
)) {
483 netif_dbg(efx
, hw
, efx
->net_dev
,
484 "Completed MAC reset after %d loops\n",
489 netif_err(efx
, hw
, efx
->net_dev
, "MAC reset failed\n");
496 /* Ensure the correct MAC is selected before statistics
497 * are re-enabled by the caller */
498 efx_writeo(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
500 falcon_setup_xaui(efx
);
503 void falcon_drain_tx_fifo(struct efx_nic
*efx
)
507 if ((efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) ||
508 (efx
->loopback_mode
!= LOOPBACK_NONE
))
511 efx_reado(efx
, ®
, FR_AB_MAC_CTRL
);
512 /* There is no point in draining more than once */
513 if (EFX_OWORD_FIELD(reg
, FRF_BB_TXFIFO_DRAIN_EN
))
516 falcon_reset_macs(efx
);
519 static void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
523 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
)
526 /* Isolate the MAC -> RX */
527 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
528 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, 0);
529 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
531 /* Isolate TX -> MAC */
532 falcon_drain_tx_fifo(efx
);
535 void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
537 struct efx_link_state
*link_state
= &efx
->link_state
;
539 int link_speed
, isolate
;
541 isolate
= (efx
->reset_pending
!= RESET_TYPE_NONE
);
543 switch (link_state
->speed
) {
544 case 10000: link_speed
= 3; break;
545 case 1000: link_speed
= 2; break;
546 case 100: link_speed
= 1; break;
547 default: link_speed
= 0; break;
549 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
550 * as advertised. Disable to ensure packets are not
551 * indefinitely held and TX queue can be flushed at any point
552 * while the link is down. */
553 EFX_POPULATE_OWORD_5(reg
,
554 FRF_AB_MAC_XOFF_VAL
, 0xffff /* max pause time */,
555 FRF_AB_MAC_BCAD_ACPT
, 1,
556 FRF_AB_MAC_UC_PROM
, efx
->promiscuous
,
557 FRF_AB_MAC_LINK_STATUS
, 1, /* always set */
558 FRF_AB_MAC_SPEED
, link_speed
);
559 /* On B0, MAC backpressure can be disabled and packets get
561 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
562 EFX_SET_OWORD_FIELD(reg
, FRF_BB_TXFIFO_DRAIN_EN
,
563 !link_state
->up
|| isolate
);
566 efx_writeo(efx
, ®
, FR_AB_MAC_CTRL
);
568 /* Restore the multicast hash registers. */
569 falcon_push_multicast_hash(efx
);
571 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
572 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
573 * initialisation but it may read back as 0) */
574 EFX_SET_OWORD_FIELD(reg
, FRF_AZ_RX_XOFF_MAC_EN
, 1);
575 /* Unisolate the MAC -> RX */
576 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
577 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, !isolate
);
578 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
581 static void falcon_stats_request(struct efx_nic
*efx
)
583 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
586 WARN_ON(nic_data
->stats_pending
);
587 WARN_ON(nic_data
->stats_disable_count
);
589 if (nic_data
->stats_dma_done
== NULL
)
590 return; /* no mac selected */
592 *nic_data
->stats_dma_done
= FALCON_STATS_NOT_DONE
;
593 nic_data
->stats_pending
= true;
594 wmb(); /* ensure done flag is clear */
596 /* Initiate DMA transfer of stats */
597 EFX_POPULATE_OWORD_2(reg
,
598 FRF_AB_MAC_STAT_DMA_CMD
, 1,
599 FRF_AB_MAC_STAT_DMA_ADR
,
600 efx
->stats_buffer
.dma_addr
);
601 efx_writeo(efx
, ®
, FR_AB_MAC_STAT_DMA
);
603 mod_timer(&nic_data
->stats_timer
, round_jiffies_up(jiffies
+ HZ
/ 2));
606 static void falcon_stats_complete(struct efx_nic
*efx
)
608 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
610 if (!nic_data
->stats_pending
)
613 nic_data
->stats_pending
= 0;
614 if (*nic_data
->stats_dma_done
== FALCON_STATS_DONE
) {
615 rmb(); /* read the done flag before the stats */
616 efx
->mac_op
->update_stats(efx
);
618 netif_err(efx
, hw
, efx
->net_dev
,
619 "timed out waiting for statistics\n");
623 static void falcon_stats_timer_func(unsigned long context
)
625 struct efx_nic
*efx
= (struct efx_nic
*)context
;
626 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
628 spin_lock(&efx
->stats_lock
);
630 falcon_stats_complete(efx
);
631 if (nic_data
->stats_disable_count
== 0)
632 falcon_stats_request(efx
);
634 spin_unlock(&efx
->stats_lock
);
637 static bool falcon_loopback_link_poll(struct efx_nic
*efx
)
639 struct efx_link_state old_state
= efx
->link_state
;
641 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
642 WARN_ON(!LOOPBACK_INTERNAL(efx
));
644 efx
->link_state
.fd
= true;
645 efx
->link_state
.fc
= efx
->wanted_fc
;
646 efx
->link_state
.up
= true;
647 efx
->link_state
.speed
= 10000;
649 return !efx_link_state_equal(&efx
->link_state
, &old_state
);
652 static int falcon_reconfigure_port(struct efx_nic
*efx
)
656 WARN_ON(efx_nic_rev(efx
) > EFX_REV_FALCON_B0
);
658 /* Poll the PHY link state *before* reconfiguring it. This means we
659 * will pick up the correct speed (in loopback) to select the correct
662 if (LOOPBACK_INTERNAL(efx
))
663 falcon_loopback_link_poll(efx
);
665 efx
->phy_op
->poll(efx
);
667 falcon_stop_nic_stats(efx
);
668 falcon_deconfigure_mac_wrapper(efx
);
670 falcon_reset_macs(efx
);
672 efx
->phy_op
->reconfigure(efx
);
673 rc
= efx
->mac_op
->reconfigure(efx
);
676 falcon_start_nic_stats(efx
);
678 /* Synchronise efx->link_state with the kernel */
679 efx_link_status_changed(efx
);
684 /**************************************************************************
686 * PHY access via GMII
688 **************************************************************************
691 /* Wait for GMII access to complete */
692 static int falcon_gmii_wait(struct efx_nic
*efx
)
697 /* wait upto 50ms - taken max from datasheet */
698 for (count
= 0; count
< 5000; count
++) {
699 efx_reado(efx
, &md_stat
, FR_AB_MD_STAT
);
700 if (EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_BSY
) == 0) {
701 if (EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_LNFL
) != 0 ||
702 EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_BSERR
) != 0) {
703 netif_err(efx
, hw
, efx
->net_dev
,
704 "error from GMII access "
706 EFX_OWORD_VAL(md_stat
));
713 netif_err(efx
, hw
, efx
->net_dev
, "timed out waiting for GMII\n");
717 /* Write an MDIO register of a PHY connected to Falcon. */
718 static int falcon_mdio_write(struct net_device
*net_dev
,
719 int prtad
, int devad
, u16 addr
, u16 value
)
721 struct efx_nic
*efx
= netdev_priv(net_dev
);
725 netif_vdbg(efx
, hw
, efx
->net_dev
,
726 "writing MDIO %d register %d.%d with 0x%04x\n",
727 prtad
, devad
, addr
, value
);
729 mutex_lock(&efx
->mdio_lock
);
731 /* Check MDIO not currently being accessed */
732 rc
= falcon_gmii_wait(efx
);
736 /* Write the address/ID register */
737 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_PHY_ADR
, addr
);
738 efx_writeo(efx
, ®
, FR_AB_MD_PHY_ADR
);
740 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_PRT_ADR
, prtad
,
741 FRF_AB_MD_DEV_ADR
, devad
);
742 efx_writeo(efx
, ®
, FR_AB_MD_ID
);
745 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_TXD
, value
);
746 efx_writeo(efx
, ®
, FR_AB_MD_TXD
);
748 EFX_POPULATE_OWORD_2(reg
,
751 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
753 /* Wait for data to be written */
754 rc
= falcon_gmii_wait(efx
);
756 /* Abort the write operation */
757 EFX_POPULATE_OWORD_2(reg
,
760 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
765 mutex_unlock(&efx
->mdio_lock
);
769 /* Read an MDIO register of a PHY connected to Falcon. */
770 static int falcon_mdio_read(struct net_device
*net_dev
,
771 int prtad
, int devad
, u16 addr
)
773 struct efx_nic
*efx
= netdev_priv(net_dev
);
777 mutex_lock(&efx
->mdio_lock
);
779 /* Check MDIO not currently being accessed */
780 rc
= falcon_gmii_wait(efx
);
784 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_PHY_ADR
, addr
);
785 efx_writeo(efx
, ®
, FR_AB_MD_PHY_ADR
);
787 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_PRT_ADR
, prtad
,
788 FRF_AB_MD_DEV_ADR
, devad
);
789 efx_writeo(efx
, ®
, FR_AB_MD_ID
);
791 /* Request data to be read */
792 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_RDC
, 1, FRF_AB_MD_GC
, 0);
793 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
795 /* Wait for data to become available */
796 rc
= falcon_gmii_wait(efx
);
798 efx_reado(efx
, ®
, FR_AB_MD_RXD
);
799 rc
= EFX_OWORD_FIELD(reg
, FRF_AB_MD_RXD
);
800 netif_vdbg(efx
, hw
, efx
->net_dev
,
801 "read from MDIO %d register %d.%d, got %04x\n",
802 prtad
, devad
, addr
, rc
);
804 /* Abort the read operation */
805 EFX_POPULATE_OWORD_2(reg
,
808 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
810 netif_dbg(efx
, hw
, efx
->net_dev
,
811 "read from MDIO %d register %d.%d, got error %d\n",
812 prtad
, devad
, addr
, rc
);
816 mutex_unlock(&efx
->mdio_lock
);
820 /* This call is responsible for hooking in the MAC and PHY operations */
821 static int falcon_probe_port(struct efx_nic
*efx
)
823 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
826 switch (efx
->phy_type
) {
827 case PHY_TYPE_SFX7101
:
828 efx
->phy_op
= &falcon_sfx7101_phy_ops
;
830 case PHY_TYPE_QT2022C2
:
831 case PHY_TYPE_QT2025C
:
832 efx
->phy_op
= &falcon_qt202x_phy_ops
;
834 case PHY_TYPE_TXC43128
:
835 efx
->phy_op
= &falcon_txc_phy_ops
;
838 netif_err(efx
, probe
, efx
->net_dev
, "Unknown PHY type %d\n",
843 /* Fill out MDIO structure and loopback modes */
844 efx
->mdio
.mdio_read
= falcon_mdio_read
;
845 efx
->mdio
.mdio_write
= falcon_mdio_write
;
846 rc
= efx
->phy_op
->probe(efx
);
850 /* Initial assumption */
851 efx
->link_state
.speed
= 10000;
852 efx
->link_state
.fd
= true;
854 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
855 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
856 efx
->wanted_fc
= EFX_FC_RX
| EFX_FC_TX
;
858 efx
->wanted_fc
= EFX_FC_RX
;
859 if (efx
->mdio
.mmds
& MDIO_DEVS_AN
)
860 efx
->wanted_fc
|= EFX_FC_AUTO
;
862 /* Allocate buffer for stats */
863 rc
= efx_nic_alloc_buffer(efx
, &efx
->stats_buffer
,
864 FALCON_MAC_STATS_SIZE
);
867 netif_dbg(efx
, probe
, efx
->net_dev
,
868 "stats buffer at %llx (virt %p phys %llx)\n",
869 (u64
)efx
->stats_buffer
.dma_addr
,
870 efx
->stats_buffer
.addr
,
871 (u64
)virt_to_phys(efx
->stats_buffer
.addr
));
872 nic_data
->stats_dma_done
= efx
->stats_buffer
.addr
+ XgDmaDone_offset
;
877 static void falcon_remove_port(struct efx_nic
*efx
)
879 efx
->phy_op
->remove(efx
);
880 efx_nic_free_buffer(efx
, &efx
->stats_buffer
);
883 /**************************************************************************
887 **************************************************************************/
890 falcon_read_nvram(struct efx_nic
*efx
, struct falcon_nvconfig
*nvconfig_out
)
892 struct falcon_nvconfig
*nvconfig
;
893 struct efx_spi_device
*spi
;
895 int rc
, magic_num
, struct_ver
;
896 __le16
*word
, *limit
;
899 spi
= efx
->spi_flash
? efx
->spi_flash
: efx
->spi_eeprom
;
903 region
= kmalloc(FALCON_NVCONFIG_END
, GFP_KERNEL
);
906 nvconfig
= region
+ FALCON_NVCONFIG_OFFSET
;
908 mutex_lock(&efx
->spi_lock
);
909 rc
= falcon_spi_read(efx
, spi
, 0, FALCON_NVCONFIG_END
, NULL
, region
);
910 mutex_unlock(&efx
->spi_lock
);
912 netif_err(efx
, hw
, efx
->net_dev
, "Failed to read %s\n",
913 efx
->spi_flash
? "flash" : "EEPROM");
918 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
919 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
922 if (magic_num
!= FALCON_NVCONFIG_BOARD_MAGIC_NUM
) {
923 netif_err(efx
, hw
, efx
->net_dev
,
924 "NVRAM bad magic 0x%x\n", magic_num
);
927 if (struct_ver
< 2) {
928 netif_err(efx
, hw
, efx
->net_dev
,
929 "NVRAM has ancient version 0x%x\n", struct_ver
);
931 } else if (struct_ver
< 4) {
932 word
= &nvconfig
->board_magic_num
;
933 limit
= (__le16
*) (nvconfig
+ 1);
936 limit
= region
+ FALCON_NVCONFIG_END
;
938 for (csum
= 0; word
< limit
; ++word
)
939 csum
+= le16_to_cpu(*word
);
941 if (~csum
& 0xffff) {
942 netif_err(efx
, hw
, efx
->net_dev
,
943 "NVRAM has incorrect checksum\n");
949 memcpy(nvconfig_out
, nvconfig
, sizeof(*nvconfig
));
956 static int falcon_test_nvram(struct efx_nic
*efx
)
958 return falcon_read_nvram(efx
, NULL
);
961 static const struct efx_nic_register_test falcon_b0_register_tests
[] = {
963 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
965 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
967 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
969 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
971 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
972 { FR_AZ_SRM_TX_DC_CFG
,
973 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
975 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
977 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
979 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
981 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
983 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
985 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
987 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
989 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
991 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
993 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
995 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
997 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1000 static int falcon_b0_test_registers(struct efx_nic
*efx
)
1002 return efx_nic_test_registers(efx
, falcon_b0_register_tests
,
1003 ARRAY_SIZE(falcon_b0_register_tests
));
1006 /**************************************************************************
1010 **************************************************************************
1013 /* Resets NIC to known state. This routine must be called in process
1014 * context and is allowed to sleep. */
1015 static int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
1017 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1018 efx_oword_t glb_ctl_reg_ker
;
1021 netif_dbg(efx
, hw
, efx
->net_dev
, "performing %s hardware reset\n",
1022 RESET_TYPE(method
));
1024 /* Initiate device reset */
1025 if (method
== RESET_TYPE_WORLD
) {
1026 rc
= pci_save_state(efx
->pci_dev
);
1028 netif_err(efx
, drv
, efx
->net_dev
,
1029 "failed to backup PCI state of primary "
1030 "function prior to hardware reset\n");
1033 if (efx_nic_is_dual_func(efx
)) {
1034 rc
= pci_save_state(nic_data
->pci_dev2
);
1036 netif_err(efx
, drv
, efx
->net_dev
,
1037 "failed to backup PCI state of "
1038 "secondary function prior to "
1039 "hardware reset\n");
1044 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
1045 FRF_AB_EXT_PHY_RST_DUR
,
1046 FFE_AB_EXT_PHY_RST_DUR_10240US
,
1049 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
1050 /* exclude PHY from "invisible" reset */
1051 FRF_AB_EXT_PHY_RST_CTL
,
1052 method
== RESET_TYPE_INVISIBLE
,
1053 /* exclude EEPROM/flash and PCIe */
1054 FRF_AB_PCIE_CORE_RST_CTL
, 1,
1055 FRF_AB_PCIE_NSTKY_RST_CTL
, 1,
1056 FRF_AB_PCIE_SD_RST_CTL
, 1,
1057 FRF_AB_EE_RST_CTL
, 1,
1058 FRF_AB_EXT_PHY_RST_DUR
,
1059 FFE_AB_EXT_PHY_RST_DUR_10240US
,
1062 efx_writeo(efx
, &glb_ctl_reg_ker
, FR_AB_GLB_CTL
);
1064 netif_dbg(efx
, hw
, efx
->net_dev
, "waiting for hardware reset\n");
1065 schedule_timeout_uninterruptible(HZ
/ 20);
1067 /* Restore PCI configuration if needed */
1068 if (method
== RESET_TYPE_WORLD
) {
1069 if (efx_nic_is_dual_func(efx
)) {
1070 rc
= pci_restore_state(nic_data
->pci_dev2
);
1072 netif_err(efx
, drv
, efx
->net_dev
,
1073 "failed to restore PCI config for "
1074 "the secondary function\n");
1078 rc
= pci_restore_state(efx
->pci_dev
);
1080 netif_err(efx
, drv
, efx
->net_dev
,
1081 "failed to restore PCI config for the "
1082 "primary function\n");
1085 netif_dbg(efx
, drv
, efx
->net_dev
,
1086 "successfully restored PCI config\n");
1089 /* Assert that reset complete */
1090 efx_reado(efx
, &glb_ctl_reg_ker
, FR_AB_GLB_CTL
);
1091 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, FRF_AB_SWRST
) != 0) {
1093 netif_err(efx
, hw
, efx
->net_dev
,
1094 "timed out waiting for hardware reset\n");
1097 netif_dbg(efx
, hw
, efx
->net_dev
, "hardware reset complete\n");
1101 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1104 pci_restore_state(efx
->pci_dev
);
1111 static void falcon_monitor(struct efx_nic
*efx
)
1116 BUG_ON(!mutex_is_locked(&efx
->mac_lock
));
1118 rc
= falcon_board(efx
)->type
->monitor(efx
);
1120 netif_err(efx
, hw
, efx
->net_dev
,
1121 "Board sensor %s; shutting down PHY\n",
1122 (rc
== -ERANGE
) ? "reported fault" : "failed");
1123 efx
->phy_mode
|= PHY_MODE_LOW_POWER
;
1124 rc
= __efx_reconfigure_port(efx
);
1128 if (LOOPBACK_INTERNAL(efx
))
1129 link_changed
= falcon_loopback_link_poll(efx
);
1131 link_changed
= efx
->phy_op
->poll(efx
);
1134 falcon_stop_nic_stats(efx
);
1135 falcon_deconfigure_mac_wrapper(efx
);
1137 falcon_reset_macs(efx
);
1138 rc
= efx
->mac_op
->reconfigure(efx
);
1141 falcon_start_nic_stats(efx
);
1143 efx_link_status_changed(efx
);
1146 falcon_poll_xmac(efx
);
1149 /* Zeroes out the SRAM contents. This routine must be called in
1150 * process context and is allowed to sleep.
1152 static int falcon_reset_sram(struct efx_nic
*efx
)
1154 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
1157 /* Set the SRAM wake/sleep GPIO appropriately. */
1158 efx_reado(efx
, &gpio_cfg_reg_ker
, FR_AB_GPIO_CTL
);
1159 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, FRF_AB_GPIO1_OEN
, 1);
1160 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, FRF_AB_GPIO1_OUT
, 1);
1161 efx_writeo(efx
, &gpio_cfg_reg_ker
, FR_AB_GPIO_CTL
);
1163 /* Initiate SRAM reset */
1164 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
1165 FRF_AZ_SRM_INIT_EN
, 1,
1166 FRF_AZ_SRM_NB_SZ
, 0);
1167 efx_writeo(efx
, &srm_cfg_reg_ker
, FR_AZ_SRM_CFG
);
1169 /* Wait for SRAM reset to complete */
1172 netif_dbg(efx
, hw
, efx
->net_dev
,
1173 "waiting for SRAM reset (attempt %d)...\n", count
);
1175 /* SRAM reset is slow; expect around 16ms */
1176 schedule_timeout_uninterruptible(HZ
/ 50);
1178 /* Check for reset complete */
1179 efx_reado(efx
, &srm_cfg_reg_ker
, FR_AZ_SRM_CFG
);
1180 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, FRF_AZ_SRM_INIT_EN
)) {
1181 netif_dbg(efx
, hw
, efx
->net_dev
,
1182 "SRAM reset complete\n");
1186 } while (++count
< 20); /* wait upto 0.4 sec */
1188 netif_err(efx
, hw
, efx
->net_dev
, "timed out waiting for SRAM reset\n");
1192 static int falcon_spi_device_init(struct efx_nic
*efx
,
1193 struct efx_spi_device
**spi_device_ret
,
1194 unsigned int device_id
, u32 device_type
)
1196 struct efx_spi_device
*spi_device
;
1198 if (device_type
!= 0) {
1199 spi_device
= kzalloc(sizeof(*spi_device
), GFP_KERNEL
);
1202 spi_device
->device_id
= device_id
;
1204 1 << SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_SIZE
);
1205 spi_device
->addr_len
=
1206 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ADDR_LEN
);
1207 spi_device
->munge_address
= (spi_device
->size
== 1 << 9 &&
1208 spi_device
->addr_len
== 1);
1209 spi_device
->erase_command
=
1210 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ERASE_CMD
);
1211 spi_device
->erase_size
=
1212 1 << SPI_DEV_TYPE_FIELD(device_type
,
1213 SPI_DEV_TYPE_ERASE_SIZE
);
1214 spi_device
->block_size
=
1215 1 << SPI_DEV_TYPE_FIELD(device_type
,
1216 SPI_DEV_TYPE_BLOCK_SIZE
);
1221 kfree(*spi_device_ret
);
1222 *spi_device_ret
= spi_device
;
1226 static void falcon_remove_spi_devices(struct efx_nic
*efx
)
1228 kfree(efx
->spi_eeprom
);
1229 efx
->spi_eeprom
= NULL
;
1230 kfree(efx
->spi_flash
);
1231 efx
->spi_flash
= NULL
;
1234 /* Extract non-volatile configuration */
1235 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
1237 struct falcon_nvconfig
*nvconfig
;
1240 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
1244 rc
= falcon_read_nvram(efx
, nvconfig
);
1248 efx
->phy_type
= nvconfig
->board_v2
.port0_phy_type
;
1249 efx
->mdio
.prtad
= nvconfig
->board_v2
.port0_phy_addr
;
1251 if (le16_to_cpu(nvconfig
->board_struct_ver
) >= 3) {
1252 rc
= falcon_spi_device_init(
1253 efx
, &efx
->spi_flash
, FFE_AB_SPI_DEVICE_FLASH
,
1254 le32_to_cpu(nvconfig
->board_v3
1255 .spi_device_type
[FFE_AB_SPI_DEVICE_FLASH
]));
1258 rc
= falcon_spi_device_init(
1259 efx
, &efx
->spi_eeprom
, FFE_AB_SPI_DEVICE_EEPROM
,
1260 le32_to_cpu(nvconfig
->board_v3
1261 .spi_device_type
[FFE_AB_SPI_DEVICE_EEPROM
]));
1266 /* Read the MAC addresses */
1267 memcpy(efx
->mac_address
, nvconfig
->mac_address
[0], ETH_ALEN
);
1269 netif_dbg(efx
, probe
, efx
->net_dev
, "PHY is %d phy_id %d\n",
1270 efx
->phy_type
, efx
->mdio
.prtad
);
1272 rc
= falcon_probe_board(efx
,
1273 le16_to_cpu(nvconfig
->board_v2
.board_revision
));
1281 falcon_remove_spi_devices(efx
);
1287 /* Probe all SPI devices on the NIC */
1288 static void falcon_probe_spi_devices(struct efx_nic
*efx
)
1290 efx_oword_t nic_stat
, gpio_ctl
, ee_vpd_cfg
;
1293 efx_reado(efx
, &gpio_ctl
, FR_AB_GPIO_CTL
);
1294 efx_reado(efx
, &nic_stat
, FR_AB_NIC_STAT
);
1295 efx_reado(efx
, &ee_vpd_cfg
, FR_AB_EE_VPD_CFG0
);
1297 if (EFX_OWORD_FIELD(gpio_ctl
, FRF_AB_GPIO3_PWRUP_VALUE
)) {
1298 boot_dev
= (EFX_OWORD_FIELD(nic_stat
, FRF_AB_SF_PRST
) ?
1299 FFE_AB_SPI_DEVICE_FLASH
: FFE_AB_SPI_DEVICE_EEPROM
);
1300 netif_dbg(efx
, probe
, efx
->net_dev
, "Booted from %s\n",
1301 boot_dev
== FFE_AB_SPI_DEVICE_FLASH
?
1302 "flash" : "EEPROM");
1304 /* Disable VPD and set clock dividers to safe
1305 * values for initial programming. */
1307 netif_dbg(efx
, probe
, efx
->net_dev
,
1308 "Booted from internal ASIC settings;"
1309 " setting SPI config\n");
1310 EFX_POPULATE_OWORD_3(ee_vpd_cfg
, FRF_AB_EE_VPD_EN
, 0,
1311 /* 125 MHz / 7 ~= 20 MHz */
1312 FRF_AB_EE_SF_CLOCK_DIV
, 7,
1313 /* 125 MHz / 63 ~= 2 MHz */
1314 FRF_AB_EE_EE_CLOCK_DIV
, 63);
1315 efx_writeo(efx
, &ee_vpd_cfg
, FR_AB_EE_VPD_CFG0
);
1318 if (boot_dev
== FFE_AB_SPI_DEVICE_FLASH
)
1319 falcon_spi_device_init(efx
, &efx
->spi_flash
,
1320 FFE_AB_SPI_DEVICE_FLASH
,
1321 default_flash_type
);
1322 if (boot_dev
== FFE_AB_SPI_DEVICE_EEPROM
)
1323 falcon_spi_device_init(efx
, &efx
->spi_eeprom
,
1324 FFE_AB_SPI_DEVICE_EEPROM
,
1328 static int falcon_probe_nic(struct efx_nic
*efx
)
1330 struct falcon_nic_data
*nic_data
;
1331 struct falcon_board
*board
;
1334 /* Allocate storage for hardware specific data */
1335 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
1338 efx
->nic_data
= nic_data
;
1342 if (efx_nic_fpga_ver(efx
) != 0) {
1343 netif_err(efx
, probe
, efx
->net_dev
,
1344 "Falcon FPGA not supported\n");
1348 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
) {
1349 efx_oword_t nic_stat
;
1350 struct pci_dev
*dev
;
1351 u8 pci_rev
= efx
->pci_dev
->revision
;
1353 if ((pci_rev
== 0xff) || (pci_rev
== 0)) {
1354 netif_err(efx
, probe
, efx
->net_dev
,
1355 "Falcon rev A0 not supported\n");
1358 efx_reado(efx
, &nic_stat
, FR_AB_NIC_STAT
);
1359 if (EFX_OWORD_FIELD(nic_stat
, FRF_AB_STRAP_10G
) == 0) {
1360 netif_err(efx
, probe
, efx
->net_dev
,
1361 "Falcon rev A1 1G not supported\n");
1364 if (EFX_OWORD_FIELD(nic_stat
, FRF_AA_STRAP_PCIE
) == 0) {
1365 netif_err(efx
, probe
, efx
->net_dev
,
1366 "Falcon rev A1 PCI-X not supported\n");
1370 dev
= pci_dev_get(efx
->pci_dev
);
1371 while ((dev
= pci_get_device(EFX_VENDID_SFC
, FALCON_A_S_DEVID
,
1373 if (dev
->bus
== efx
->pci_dev
->bus
&&
1374 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
1375 nic_data
->pci_dev2
= dev
;
1379 if (!nic_data
->pci_dev2
) {
1380 netif_err(efx
, probe
, efx
->net_dev
,
1381 "failed to find secondary function\n");
1387 /* Now we can reset the NIC */
1388 rc
= falcon_reset_hw(efx
, RESET_TYPE_ALL
);
1390 netif_err(efx
, probe
, efx
->net_dev
, "failed to reset NIC\n");
1394 /* Allocate memory for INT_KER */
1395 rc
= efx_nic_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
));
1398 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
1400 netif_dbg(efx
, probe
, efx
->net_dev
,
1401 "INT_KER at %llx (virt %p phys %llx)\n",
1402 (u64
)efx
->irq_status
.dma_addr
,
1403 efx
->irq_status
.addr
,
1404 (u64
)virt_to_phys(efx
->irq_status
.addr
));
1406 falcon_probe_spi_devices(efx
);
1408 /* Read in the non-volatile configuration */
1409 rc
= falcon_probe_nvconfig(efx
);
1412 netif_err(efx
, probe
, efx
->net_dev
, "NVRAM is invalid\n");
1416 /* Initialise I2C adapter */
1417 board
= falcon_board(efx
);
1418 board
->i2c_adap
.owner
= THIS_MODULE
;
1419 board
->i2c_data
= falcon_i2c_bit_operations
;
1420 board
->i2c_data
.data
= efx
;
1421 board
->i2c_adap
.algo_data
= &board
->i2c_data
;
1422 board
->i2c_adap
.dev
.parent
= &efx
->pci_dev
->dev
;
1423 strlcpy(board
->i2c_adap
.name
, "SFC4000 GPIO",
1424 sizeof(board
->i2c_adap
.name
));
1425 rc
= i2c_bit_add_bus(&board
->i2c_adap
);
1429 rc
= falcon_board(efx
)->type
->init(efx
);
1431 netif_err(efx
, probe
, efx
->net_dev
,
1432 "failed to initialise board\n");
1436 nic_data
->stats_disable_count
= 1;
1437 setup_timer(&nic_data
->stats_timer
, &falcon_stats_timer_func
,
1438 (unsigned long)efx
);
1443 BUG_ON(i2c_del_adapter(&board
->i2c_adap
));
1444 memset(&board
->i2c_adap
, 0, sizeof(board
->i2c_adap
));
1446 falcon_remove_spi_devices(efx
);
1447 efx_nic_free_buffer(efx
, &efx
->irq_status
);
1450 if (nic_data
->pci_dev2
) {
1451 pci_dev_put(nic_data
->pci_dev2
);
1452 nic_data
->pci_dev2
= NULL
;
1456 kfree(efx
->nic_data
);
1460 static void falcon_init_rx_cfg(struct efx_nic
*efx
)
1462 /* Prior to Siena the RX DMA engine will split each frame at
1463 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1464 * be so large that that never happens. */
1465 const unsigned huge_buf_size
= (3 * 4096) >> 5;
1466 /* RX control FIFO thresholds (32 entries) */
1467 const unsigned ctrl_xon_thr
= 20;
1468 const unsigned ctrl_xoff_thr
= 25;
1469 /* RX data FIFO thresholds (256-byte units; size varies) */
1470 int data_xon_thr
= efx_nic_rx_xon_thresh
>> 8;
1471 int data_xoff_thr
= efx_nic_rx_xoff_thresh
>> 8;
1474 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
1475 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
) {
1476 /* Data FIFO size is 5.5K */
1477 if (data_xon_thr
< 0)
1478 data_xon_thr
= 512 >> 8;
1479 if (data_xoff_thr
< 0)
1480 data_xoff_thr
= 2048 >> 8;
1481 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_DESC_PUSH_EN
, 0);
1482 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_USR_BUF_SIZE
,
1484 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XON_MAC_TH
, data_xon_thr
);
1485 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XOFF_MAC_TH
, data_xoff_thr
);
1486 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XON_TX_TH
, ctrl_xon_thr
);
1487 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XOFF_TX_TH
, ctrl_xoff_thr
);
1489 /* Data FIFO size is 80K; register fields moved */
1490 if (data_xon_thr
< 0)
1491 data_xon_thr
= 27648 >> 8; /* ~3*max MTU */
1492 if (data_xoff_thr
< 0)
1493 data_xoff_thr
= 54272 >> 8; /* ~80Kb - 3*max MTU */
1494 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_DESC_PUSH_EN
, 0);
1495 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_USR_BUF_SIZE
,
1497 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XON_MAC_TH
, data_xon_thr
);
1498 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XOFF_MAC_TH
, data_xoff_thr
);
1499 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XON_TX_TH
, ctrl_xon_thr
);
1500 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XOFF_TX_TH
, ctrl_xoff_thr
);
1501 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, 1);
1503 /* Enable hash insertion. This is broken for the
1504 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1506 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_HASH_INSRT_HDR
, 1);
1507 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_HASH_ALG
, 1);
1508 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_IP_HASH
, 1);
1510 /* Always enable XOFF signal from RX FIFO. We enable
1511 * or disable transmission of pause frames at the MAC. */
1512 EFX_SET_OWORD_FIELD(reg
, FRF_AZ_RX_XOFF_MAC_EN
, 1);
1513 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
1516 /* This call performs hardware-specific global initialisation, such as
1517 * defining the descriptor cache sizes and number of RSS channels.
1518 * It does not set up any buffers, descriptor rings or event queues.
1520 static int falcon_init_nic(struct efx_nic
*efx
)
1525 /* Use on-chip SRAM */
1526 efx_reado(efx
, &temp
, FR_AB_NIC_STAT
);
1527 EFX_SET_OWORD_FIELD(temp
, FRF_AB_ONCHIP_SRAM
, 1);
1528 efx_writeo(efx
, &temp
, FR_AB_NIC_STAT
);
1530 rc
= falcon_reset_sram(efx
);
1534 /* Clear the parity enables on the TX data fifos as
1535 * they produce false parity errors because of timing issues
1537 if (EFX_WORKAROUND_5129(efx
)) {
1538 efx_reado(efx
, &temp
, FR_AZ_CSR_SPARE
);
1539 EFX_SET_OWORD_FIELD(temp
, FRF_AB_MEM_PERR_EN_TX_DATA
, 0);
1540 efx_writeo(efx
, &temp
, FR_AZ_CSR_SPARE
);
1543 if (EFX_WORKAROUND_7244(efx
)) {
1544 efx_reado(efx
, &temp
, FR_BZ_RX_FILTER_CTL
);
1545 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_UDP_FULL_SRCH_LIMIT
, 8);
1546 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_UDP_WILD_SRCH_LIMIT
, 8);
1547 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TCP_FULL_SRCH_LIMIT
, 8);
1548 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TCP_WILD_SRCH_LIMIT
, 8);
1549 efx_writeo(efx
, &temp
, FR_BZ_RX_FILTER_CTL
);
1552 /* XXX This is documented only for Falcon A0/A1 */
1553 /* Setup RX. Wait for descriptor is broken and must
1554 * be disabled. RXDP recovery shouldn't be needed, but is.
1556 efx_reado(efx
, &temp
, FR_AA_RX_SELF_RST
);
1557 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_NODESC_WAIT_DIS
, 1);
1558 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_SELF_RST_EN
, 1);
1559 if (EFX_WORKAROUND_5583(efx
))
1560 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_ISCSI_DIS
, 1);
1561 efx_writeo(efx
, &temp
, FR_AA_RX_SELF_RST
);
1563 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1564 * descriptors (which is bad).
1566 efx_reado(efx
, &temp
, FR_AZ_TX_CFG
);
1567 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_NO_EOP_DISC_EN
, 0);
1568 efx_writeo(efx
, &temp
, FR_AZ_TX_CFG
);
1570 falcon_init_rx_cfg(efx
);
1572 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
1573 /* Set hash key for IPv4 */
1574 memcpy(&temp
, efx
->rx_hash_key
, sizeof(temp
));
1575 efx_writeo(efx
, &temp
, FR_BZ_RX_RSS_TKEY
);
1577 /* Set destination of both TX and RX Flush events */
1578 EFX_POPULATE_OWORD_1(temp
, FRF_BZ_FLS_EVQ_ID
, 0);
1579 efx_writeo(efx
, &temp
, FR_BZ_DP_CTRL
);
1582 efx_nic_init_common(efx
);
1587 static void falcon_remove_nic(struct efx_nic
*efx
)
1589 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1590 struct falcon_board
*board
= falcon_board(efx
);
1593 board
->type
->fini(efx
);
1595 /* Remove I2C adapter and clear it in preparation for a retry */
1596 rc
= i2c_del_adapter(&board
->i2c_adap
);
1598 memset(&board
->i2c_adap
, 0, sizeof(board
->i2c_adap
));
1600 falcon_remove_spi_devices(efx
);
1601 efx_nic_free_buffer(efx
, &efx
->irq_status
);
1603 falcon_reset_hw(efx
, RESET_TYPE_ALL
);
1605 /* Release the second function after the reset */
1606 if (nic_data
->pci_dev2
) {
1607 pci_dev_put(nic_data
->pci_dev2
);
1608 nic_data
->pci_dev2
= NULL
;
1611 /* Tear down the private nic state */
1612 kfree(efx
->nic_data
);
1613 efx
->nic_data
= NULL
;
1616 static void falcon_update_nic_stats(struct efx_nic
*efx
)
1618 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1621 if (nic_data
->stats_disable_count
)
1624 efx_reado(efx
, &cnt
, FR_AZ_RX_NODESC_DROP
);
1625 efx
->n_rx_nodesc_drop_cnt
+=
1626 EFX_OWORD_FIELD(cnt
, FRF_AB_RX_NODESC_DROP_CNT
);
1628 if (nic_data
->stats_pending
&&
1629 *nic_data
->stats_dma_done
== FALCON_STATS_DONE
) {
1630 nic_data
->stats_pending
= false;
1631 rmb(); /* read the done flag before the stats */
1632 efx
->mac_op
->update_stats(efx
);
1636 void falcon_start_nic_stats(struct efx_nic
*efx
)
1638 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1640 spin_lock_bh(&efx
->stats_lock
);
1641 if (--nic_data
->stats_disable_count
== 0)
1642 falcon_stats_request(efx
);
1643 spin_unlock_bh(&efx
->stats_lock
);
1646 void falcon_stop_nic_stats(struct efx_nic
*efx
)
1648 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1653 spin_lock_bh(&efx
->stats_lock
);
1654 ++nic_data
->stats_disable_count
;
1655 spin_unlock_bh(&efx
->stats_lock
);
1657 del_timer_sync(&nic_data
->stats_timer
);
1659 /* Wait enough time for the most recent transfer to
1661 for (i
= 0; i
< 4 && nic_data
->stats_pending
; i
++) {
1662 if (*nic_data
->stats_dma_done
== FALCON_STATS_DONE
)
1667 spin_lock_bh(&efx
->stats_lock
);
1668 falcon_stats_complete(efx
);
1669 spin_unlock_bh(&efx
->stats_lock
);
1672 static void falcon_set_id_led(struct efx_nic
*efx
, enum efx_led_mode mode
)
1674 falcon_board(efx
)->type
->set_id_led(efx
, mode
);
1677 /**************************************************************************
1681 **************************************************************************
1684 static void falcon_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1688 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1691 static int falcon_set_wol(struct efx_nic
*efx
, u32 type
)
1698 /**************************************************************************
1700 * Revision-dependent attributes used by efx.c and nic.c
1702 **************************************************************************
1705 struct efx_nic_type falcon_a1_nic_type
= {
1706 .probe
= falcon_probe_nic
,
1707 .remove
= falcon_remove_nic
,
1708 .init
= falcon_init_nic
,
1709 .fini
= efx_port_dummy_op_void
,
1710 .monitor
= falcon_monitor
,
1711 .reset
= falcon_reset_hw
,
1712 .probe_port
= falcon_probe_port
,
1713 .remove_port
= falcon_remove_port
,
1714 .prepare_flush
= falcon_prepare_flush
,
1715 .update_stats
= falcon_update_nic_stats
,
1716 .start_stats
= falcon_start_nic_stats
,
1717 .stop_stats
= falcon_stop_nic_stats
,
1718 .set_id_led
= falcon_set_id_led
,
1719 .push_irq_moderation
= falcon_push_irq_moderation
,
1720 .push_multicast_hash
= falcon_push_multicast_hash
,
1721 .reconfigure_port
= falcon_reconfigure_port
,
1722 .get_wol
= falcon_get_wol
,
1723 .set_wol
= falcon_set_wol
,
1724 .resume_wol
= efx_port_dummy_op_void
,
1725 .test_nvram
= falcon_test_nvram
,
1726 .default_mac_ops
= &falcon_xmac_operations
,
1728 .revision
= EFX_REV_FALCON_A1
,
1729 .mem_map_size
= 0x20000,
1730 .txd_ptr_tbl_base
= FR_AA_TX_DESC_PTR_TBL_KER
,
1731 .rxd_ptr_tbl_base
= FR_AA_RX_DESC_PTR_TBL_KER
,
1732 .buf_tbl_base
= FR_AA_BUF_FULL_TBL_KER
,
1733 .evq_ptr_tbl_base
= FR_AA_EVQ_PTR_TBL_KER
,
1734 .evq_rptr_tbl_base
= FR_AA_EVQ_RPTR_KER
,
1735 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
1736 .rx_buffer_padding
= 0x24,
1737 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
1738 .phys_addr_channels
= 4,
1739 .tx_dc_base
= 0x130000,
1740 .rx_dc_base
= 0x100000,
1741 .offload_features
= NETIF_F_IP_CSUM
,
1742 .reset_world_flags
= ETH_RESET_IRQ
,
1745 struct efx_nic_type falcon_b0_nic_type
= {
1746 .probe
= falcon_probe_nic
,
1747 .remove
= falcon_remove_nic
,
1748 .init
= falcon_init_nic
,
1749 .fini
= efx_port_dummy_op_void
,
1750 .monitor
= falcon_monitor
,
1751 .reset
= falcon_reset_hw
,
1752 .probe_port
= falcon_probe_port
,
1753 .remove_port
= falcon_remove_port
,
1754 .prepare_flush
= falcon_prepare_flush
,
1755 .update_stats
= falcon_update_nic_stats
,
1756 .start_stats
= falcon_start_nic_stats
,
1757 .stop_stats
= falcon_stop_nic_stats
,
1758 .set_id_led
= falcon_set_id_led
,
1759 .push_irq_moderation
= falcon_push_irq_moderation
,
1760 .push_multicast_hash
= falcon_push_multicast_hash
,
1761 .reconfigure_port
= falcon_reconfigure_port
,
1762 .get_wol
= falcon_get_wol
,
1763 .set_wol
= falcon_set_wol
,
1764 .resume_wol
= efx_port_dummy_op_void
,
1765 .test_registers
= falcon_b0_test_registers
,
1766 .test_nvram
= falcon_test_nvram
,
1767 .default_mac_ops
= &falcon_xmac_operations
,
1769 .revision
= EFX_REV_FALCON_B0
,
1770 /* Map everything up to and including the RSS indirection
1771 * table. Don't map MSI-X table, MSI-X PBA since Linux
1772 * requires that they not be mapped. */
1773 .mem_map_size
= (FR_BZ_RX_INDIRECTION_TBL
+
1774 FR_BZ_RX_INDIRECTION_TBL_STEP
*
1775 FR_BZ_RX_INDIRECTION_TBL_ROWS
),
1776 .txd_ptr_tbl_base
= FR_BZ_TX_DESC_PTR_TBL
,
1777 .rxd_ptr_tbl_base
= FR_BZ_RX_DESC_PTR_TBL
,
1778 .buf_tbl_base
= FR_BZ_BUF_FULL_TBL
,
1779 .evq_ptr_tbl_base
= FR_BZ_EVQ_PTR_TBL
,
1780 .evq_rptr_tbl_base
= FR_BZ_EVQ_RPTR
,
1781 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
1782 .rx_buffer_hash_size
= 0x10,
1783 .rx_buffer_padding
= 0,
1784 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
1785 .phys_addr_channels
= 32, /* Hardware limit is 64, but the legacy
1786 * interrupt handler only supports 32
1788 .tx_dc_base
= 0x130000,
1789 .rx_dc_base
= 0x100000,
1790 .offload_features
= NETIF_F_IP_CSUM
| NETIF_F_RXHASH
| NETIF_F_NTUPLE
,
1791 .reset_world_flags
= ETH_RESET_IRQ
,