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[PATCH] x86-64: Use irq_domain in ioapic_retrigger_irq
[linux-2.6/cjktty.git] / arch / x86_64 / kernel / io_apic.c
blob8a9a357875b72d66a4ce0ddae14a5d347c973045
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
35 #ifdef CONFIG_ACPI
36 #include <acpi/acpi_bus.h>
37 #endif
38
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
51
52 #define __apicdebuginit __init
53
54 int sis_apic_bug; /* not actually supported, dummy for compile */
55
56 static int no_timer_check;
57
58 static int disable_timer_pin_1 __initdata;
59
60 int timer_over_8254 __initdata = 0;
61
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
64
65 static DEFINE_SPINLOCK(ioapic_lock);
66 static DEFINE_SPINLOCK(vector_lock);
67
68 /*
69 * # of IRQ routing registers
70 */
71 int nr_ioapic_registers[MAX_IO_APICS];
72
73 /*
74 * Rough estimation of how many shared IRQs there are, can
75 * be changed anytime.
76 */
77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79
80 /*
81 * This is performance-critical, we want to do it O(1)
82 *
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
85 */
86
87 static struct irq_pin_list {
88 short apic, pin, next;
89 } irq_2_pin[PIN_MAP_SIZE];
90
91 #define __DO_ACTION(R, ACTION, FINAL) \
92 \
93 { \
94 int pin; \
95 struct irq_pin_list *entry = irq_2_pin + irq; \
96 \
97 BUG_ON(irq >= NR_IRQS); \
98 for (;;) { \
99 unsigned int reg; \
100 pin = entry->pin; \
101 if (pin == -1) \
102 break; \
103 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
104 reg ACTION; \
105 io_apic_modify(entry->apic, reg); \
106 if (!entry->next) \
107 break; \
108 entry = irq_2_pin + entry->next; \
109 } \
110 FINAL; \
111 }
112
113 union entry_union {
114 struct { u32 w1, w2; };
115 struct IO_APIC_route_entry entry;
116 };
117
118 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
119 {
120 union entry_union eu;
121 unsigned long flags;
122 spin_lock_irqsave(&ioapic_lock, flags);
123 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
124 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
125 spin_unlock_irqrestore(&ioapic_lock, flags);
126 return eu.entry;
127 }
128
129 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
130 {
131 unsigned long flags;
132 union entry_union eu;
133 eu.entry = e;
134 spin_lock_irqsave(&ioapic_lock, flags);
135 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
136 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
137 spin_unlock_irqrestore(&ioapic_lock, flags);
138 }
139
140 #ifdef CONFIG_SMP
141 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
142 {
143 int apic, pin;
144 struct irq_pin_list *entry = irq_2_pin + irq;
145
146 BUG_ON(irq >= NR_IRQS);
147 for (;;) {
148 unsigned int reg;
149 apic = entry->apic;
150 pin = entry->pin;
151 if (pin == -1)
152 break;
153 io_apic_write(apic, 0x11 + pin*2, dest);
154 reg = io_apic_read(apic, 0x10 + pin*2);
155 reg &= ~0x000000ff;
156 reg |= vector;
157 io_apic_modify(apic, reg);
158 if (!entry->next)
159 break;
160 entry = irq_2_pin + entry->next;
161 }
162 }
163
164 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
165 {
166 unsigned long flags;
167 unsigned int dest;
168 cpumask_t tmp;
169 int vector;
170
171 cpus_and(tmp, mask, cpu_online_map);
172 if (cpus_empty(tmp))
173 tmp = TARGET_CPUS;
174
175 cpus_and(mask, tmp, CPU_MASK_ALL);
176
177 vector = assign_irq_vector(irq, mask, &tmp);
178 if (vector < 0)
179 return;
180
181 dest = cpu_mask_to_apicid(tmp);
182
183 /*
184 * Only the high 8 bits are valid.
185 */
186 dest = SET_APIC_LOGICAL_ID(dest);
187
188 spin_lock_irqsave(&ioapic_lock, flags);
189 __target_IO_APIC_irq(irq, dest, vector);
190 set_native_irq_info(irq, mask);
191 spin_unlock_irqrestore(&ioapic_lock, flags);
192 }
193 #endif
194
195 /*
196 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
197 * shared ISA-space IRQs, so we have to support them. We are super
198 * fast in the common case, and fast for shared ISA-space IRQs.
199 */
200 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
201 {
202 static int first_free_entry = NR_IRQS;
203 struct irq_pin_list *entry = irq_2_pin + irq;
204
205 BUG_ON(irq >= NR_IRQS);
206 while (entry->next)
207 entry = irq_2_pin + entry->next;
208
209 if (entry->pin != -1) {
210 entry->next = first_free_entry;
211 entry = irq_2_pin + entry->next;
212 if (++first_free_entry >= PIN_MAP_SIZE)
213 panic("io_apic.c: ran out of irq_2_pin entries!");
214 }
215 entry->apic = apic;
216 entry->pin = pin;
217 }
218
219
220 #define DO_ACTION(name,R,ACTION, FINAL) \
221 \
222 static void name##_IO_APIC_irq (unsigned int irq) \
223 __DO_ACTION(R, ACTION, FINAL)
224
225 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
226 /* mask = 1 */
227 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
228 /* mask = 0 */
229
230 static void mask_IO_APIC_irq (unsigned int irq)
231 {
232 unsigned long flags;
233
234 spin_lock_irqsave(&ioapic_lock, flags);
235 __mask_IO_APIC_irq(irq);
236 spin_unlock_irqrestore(&ioapic_lock, flags);
237 }
238
239 static void unmask_IO_APIC_irq (unsigned int irq)
240 {
241 unsigned long flags;
242
243 spin_lock_irqsave(&ioapic_lock, flags);
244 __unmask_IO_APIC_irq(irq);
245 spin_unlock_irqrestore(&ioapic_lock, flags);
246 }
247
248 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
249 {
250 struct IO_APIC_route_entry entry;
251
252 /* Check delivery_mode to be sure we're not clearing an SMI pin */
253 entry = ioapic_read_entry(apic, pin);
254 if (entry.delivery_mode == dest_SMI)
255 return;
256 /*
257 * Disable it in the IO-APIC irq-routing table:
258 */
259 memset(&entry, 0, sizeof(entry));
260 entry.mask = 1;
261 ioapic_write_entry(apic, pin, entry);
262 }
263
264 static void clear_IO_APIC (void)
265 {
266 int apic, pin;
267
268 for (apic = 0; apic < nr_ioapics; apic++)
269 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
270 clear_IO_APIC_pin(apic, pin);
271 }
272
273 int skip_ioapic_setup;
274 int ioapic_force;
275
276 /* dummy parsing: see setup.c */
277
278 static int __init disable_ioapic_setup(char *str)
279 {
280 skip_ioapic_setup = 1;
281 return 0;
282 }
283 early_param("noapic", disable_ioapic_setup);
284
285 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
286 static int __init disable_timer_pin_setup(char *arg)
287 {
288 disable_timer_pin_1 = 1;
289 return 1;
290 }
291 __setup("disable_timer_pin_1", disable_timer_pin_setup);
292
293 static int __init setup_disable_8254_timer(char *s)
294 {
295 timer_over_8254 = -1;
296 return 1;
297 }
298 static int __init setup_enable_8254_timer(char *s)
299 {
300 timer_over_8254 = 2;
301 return 1;
302 }
303
304 __setup("disable_8254_timer", setup_disable_8254_timer);
305 __setup("enable_8254_timer", setup_enable_8254_timer);
306
307
308 /*
309 * Find the IRQ entry number of a certain pin.
310 */
311 static int find_irq_entry(int apic, int pin, int type)
312 {
313 int i;
314
315 for (i = 0; i < mp_irq_entries; i++)
316 if (mp_irqs[i].mpc_irqtype == type &&
317 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
318 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
319 mp_irqs[i].mpc_dstirq == pin)
320 return i;
321
322 return -1;
323 }
324
325 /*
326 * Find the pin to which IRQ[irq] (ISA) is connected
327 */
328 static int __init find_isa_irq_pin(int irq, int type)
329 {
330 int i;
331
332 for (i = 0; i < mp_irq_entries; i++) {
333 int lbus = mp_irqs[i].mpc_srcbus;
334
335 if (test_bit(lbus, mp_bus_not_pci) &&
336 (mp_irqs[i].mpc_irqtype == type) &&
337 (mp_irqs[i].mpc_srcbusirq == irq))
338
339 return mp_irqs[i].mpc_dstirq;
340 }
341 return -1;
342 }
343
344 static int __init find_isa_irq_apic(int irq, int type)
345 {
346 int i;
347
348 for (i = 0; i < mp_irq_entries; i++) {
349 int lbus = mp_irqs[i].mpc_srcbus;
350
351 if (test_bit(lbus, mp_bus_not_pci) &&
352 (mp_irqs[i].mpc_irqtype == type) &&
353 (mp_irqs[i].mpc_srcbusirq == irq))
354 break;
355 }
356 if (i < mp_irq_entries) {
357 int apic;
358 for(apic = 0; apic < nr_ioapics; apic++) {
359 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
360 return apic;
361 }
362 }
363
364 return -1;
365 }
366
367 /*
368 * Find a specific PCI IRQ entry.
369 * Not an __init, possibly needed by modules
370 */
371 static int pin_2_irq(int idx, int apic, int pin);
372
373 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
374 {
375 int apic, i, best_guess = -1;
376
377 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
378 bus, slot, pin);
379 if (mp_bus_id_to_pci_bus[bus] == -1) {
380 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
381 return -1;
382 }
383 for (i = 0; i < mp_irq_entries; i++) {
384 int lbus = mp_irqs[i].mpc_srcbus;
385
386 for (apic = 0; apic < nr_ioapics; apic++)
387 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
388 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
389 break;
390
391 if (!test_bit(lbus, mp_bus_not_pci) &&
392 !mp_irqs[i].mpc_irqtype &&
393 (bus == lbus) &&
394 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
395 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
396
397 if (!(apic || IO_APIC_IRQ(irq)))
398 continue;
399
400 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
401 return irq;
402 /*
403 * Use the first all-but-pin matching entry as a
404 * best-guess fuzzy result for broken mptables.
405 */
406 if (best_guess < 0)
407 best_guess = irq;
408 }
409 }
410 BUG_ON(best_guess >= NR_IRQS);
411 return best_guess;
412 }
413
414 /* ISA interrupts are always polarity zero edge triggered,
415 * when listed as conforming in the MP table. */
416
417 #define default_ISA_trigger(idx) (0)
418 #define default_ISA_polarity(idx) (0)
419
420 /* PCI interrupts are always polarity one level triggered,
421 * when listed as conforming in the MP table. */
422
423 #define default_PCI_trigger(idx) (1)
424 #define default_PCI_polarity(idx) (1)
425
426 static int __init MPBIOS_polarity(int idx)
427 {
428 int bus = mp_irqs[idx].mpc_srcbus;
429 int polarity;
430
431 /*
432 * Determine IRQ line polarity (high active or low active):
433 */
434 switch (mp_irqs[idx].mpc_irqflag & 3)
435 {
436 case 0: /* conforms, ie. bus-type dependent polarity */
437 if (test_bit(bus, mp_bus_not_pci))
438 polarity = default_ISA_polarity(idx);
439 else
440 polarity = default_PCI_polarity(idx);
441 break;
442 case 1: /* high active */
443 {
444 polarity = 0;
445 break;
446 }
447 case 2: /* reserved */
448 {
449 printk(KERN_WARNING "broken BIOS!!\n");
450 polarity = 1;
451 break;
452 }
453 case 3: /* low active */
454 {
455 polarity = 1;
456 break;
457 }
458 default: /* invalid */
459 {
460 printk(KERN_WARNING "broken BIOS!!\n");
461 polarity = 1;
462 break;
463 }
464 }
465 return polarity;
466 }
467
468 static int MPBIOS_trigger(int idx)
469 {
470 int bus = mp_irqs[idx].mpc_srcbus;
471 int trigger;
472
473 /*
474 * Determine IRQ trigger mode (edge or level sensitive):
475 */
476 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
477 {
478 case 0: /* conforms, ie. bus-type dependent */
479 if (test_bit(bus, mp_bus_not_pci))
480 trigger = default_ISA_trigger(idx);
481 else
482 trigger = default_PCI_trigger(idx);
483 break;
484 case 1: /* edge */
485 {
486 trigger = 0;
487 break;
488 }
489 case 2: /* reserved */
490 {
491 printk(KERN_WARNING "broken BIOS!!\n");
492 trigger = 1;
493 break;
494 }
495 case 3: /* level */
496 {
497 trigger = 1;
498 break;
499 }
500 default: /* invalid */
501 {
502 printk(KERN_WARNING "broken BIOS!!\n");
503 trigger = 0;
504 break;
505 }
506 }
507 return trigger;
508 }
509
510 static inline int irq_polarity(int idx)
511 {
512 return MPBIOS_polarity(idx);
513 }
514
515 static inline int irq_trigger(int idx)
516 {
517 return MPBIOS_trigger(idx);
518 }
519
520 static int pin_2_irq(int idx, int apic, int pin)
521 {
522 int irq, i;
523 int bus = mp_irqs[idx].mpc_srcbus;
524
525 /*
526 * Debugging check, we are in big trouble if this message pops up!
527 */
528 if (mp_irqs[idx].mpc_dstirq != pin)
529 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
530
531 if (test_bit(bus, mp_bus_not_pci)) {
532 irq = mp_irqs[idx].mpc_srcbusirq;
533 } else {
534 /*
535 * PCI IRQs are mapped in order
536 */
537 i = irq = 0;
538 while (i < apic)
539 irq += nr_ioapic_registers[i++];
540 irq += pin;
541 }
542 BUG_ON(irq >= NR_IRQS);
543 return irq;
544 }
545
546 static inline int IO_APIC_irq_trigger(int irq)
547 {
548 int apic, idx, pin;
549
550 for (apic = 0; apic < nr_ioapics; apic++) {
551 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
552 idx = find_irq_entry(apic,pin,mp_INT);
553 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
554 return irq_trigger(idx);
555 }
556 }
557 /*
558 * nonexistent IRQs are edge default
559 */
560 return 0;
561 }
562
563 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
564 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
565 [0] = FIRST_EXTERNAL_VECTOR + 0,
566 [1] = FIRST_EXTERNAL_VECTOR + 1,
567 [2] = FIRST_EXTERNAL_VECTOR + 2,
568 [3] = FIRST_EXTERNAL_VECTOR + 3,
569 [4] = FIRST_EXTERNAL_VECTOR + 4,
570 [5] = FIRST_EXTERNAL_VECTOR + 5,
571 [6] = FIRST_EXTERNAL_VECTOR + 6,
572 [7] = FIRST_EXTERNAL_VECTOR + 7,
573 [8] = FIRST_EXTERNAL_VECTOR + 8,
574 [9] = FIRST_EXTERNAL_VECTOR + 9,
575 [10] = FIRST_EXTERNAL_VECTOR + 10,
576 [11] = FIRST_EXTERNAL_VECTOR + 11,
577 [12] = FIRST_EXTERNAL_VECTOR + 12,
578 [13] = FIRST_EXTERNAL_VECTOR + 13,
579 [14] = FIRST_EXTERNAL_VECTOR + 14,
580 [15] = FIRST_EXTERNAL_VECTOR + 15,
581 };
582
583 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
584 [0] = CPU_MASK_ALL,
585 [1] = CPU_MASK_ALL,
586 [2] = CPU_MASK_ALL,
587 [3] = CPU_MASK_ALL,
588 [4] = CPU_MASK_ALL,
589 [5] = CPU_MASK_ALL,
590 [6] = CPU_MASK_ALL,
591 [7] = CPU_MASK_ALL,
592 [8] = CPU_MASK_ALL,
593 [9] = CPU_MASK_ALL,
594 [10] = CPU_MASK_ALL,
595 [11] = CPU_MASK_ALL,
596 [12] = CPU_MASK_ALL,
597 [13] = CPU_MASK_ALL,
598 [14] = CPU_MASK_ALL,
599 [15] = CPU_MASK_ALL,
600 };
601
602 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
603 {
604 /*
605 * NOTE! The local APIC isn't very good at handling
606 * multiple interrupts at the same interrupt level.
607 * As the interrupt level is determined by taking the
608 * vector number and shifting that right by 4, we
609 * want to spread these out a bit so that they don't
610 * all fall in the same interrupt level.
611 *
612 * Also, we've got to be careful not to trash gate
613 * 0x80, because int 0x80 is hm, kind of importantish. ;)
614 */
615 static struct {
616 int vector;
617 int offset;
618 } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
619 int old_vector = -1;
620 int cpu;
621
622 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
623
624 if (irq_vector[irq] > 0)
625 old_vector = irq_vector[irq];
626 if (old_vector > 0) {
627 cpus_and(*result, irq_domain[irq], mask);
628 if (!cpus_empty(*result))
629 return old_vector;
630 }
631
632 for_each_cpu_mask(cpu, mask) {
633 cpumask_t domain;
634 int first, new_cpu;
635 int vector, offset;
636
637 domain = vector_allocation_domain(cpu);
638 first = first_cpu(domain);
639
640 vector = pos[first].vector;
641 offset = pos[first].offset;
642 next:
643 vector += 8;
644 if (vector >= FIRST_SYSTEM_VECTOR) {
645 /* If we run out of vectors on large boxen, must share them. */
646 offset = (offset + 1) % 8;
647 vector = FIRST_DEVICE_VECTOR + offset;
648 }
649 if (unlikely(pos[first].vector == vector))
650 continue;
651 if (vector == IA32_SYSCALL_VECTOR)
652 goto next;
653 for_each_cpu_mask(new_cpu, domain)
654 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
655 goto next;
656 /* Found one! */
657 for_each_cpu_mask(new_cpu, domain) {
658 pos[new_cpu].vector = vector;
659 pos[new_cpu].offset = offset;
660 }
661 if (old_vector >= 0) {
662 int old_cpu;
663 for_each_cpu_mask(old_cpu, irq_domain[irq])
664 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
665 }
666 for_each_cpu_mask(new_cpu, domain)
667 per_cpu(vector_irq, new_cpu)[vector] = irq;
668 irq_vector[irq] = vector;
669 irq_domain[irq] = domain;
670 cpus_and(*result, domain, mask);
671 return vector;
672 }
673 return -ENOSPC;
674 }
675
676 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
677 {
678 int vector;
679 unsigned long flags;
680
681 spin_lock_irqsave(&vector_lock, flags);
682 vector = __assign_irq_vector(irq, mask, result);
683 spin_unlock_irqrestore(&vector_lock, flags);
684 return vector;
685 }
686
687 extern void (*interrupt[NR_IRQS])(void);
688
689 static struct irq_chip ioapic_chip;
690
691 #define IOAPIC_AUTO -1
692 #define IOAPIC_EDGE 0
693 #define IOAPIC_LEVEL 1
694
695 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
696 {
697 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
698 trigger == IOAPIC_LEVEL)
699 set_irq_chip_and_handler_name(irq, &ioapic_chip,
700 handle_fasteoi_irq, "fasteoi");
701 else
702 set_irq_chip_and_handler_name(irq, &ioapic_chip,
703 handle_edge_irq, "edge");
704 }
705
706 static void __init setup_IO_APIC_irqs(void)
707 {
708 struct IO_APIC_route_entry entry;
709 int apic, pin, idx, irq, first_notcon = 1, vector;
710 unsigned long flags;
711
712 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
713
714 for (apic = 0; apic < nr_ioapics; apic++) {
715 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
716
717 /*
718 * add it to the IO-APIC irq-routing table:
719 */
720 memset(&entry,0,sizeof(entry));
721
722 entry.delivery_mode = INT_DELIVERY_MODE;
723 entry.dest_mode = INT_DEST_MODE;
724 entry.mask = 0; /* enable IRQ */
725 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
726
727 idx = find_irq_entry(apic,pin,mp_INT);
728 if (idx == -1) {
729 if (first_notcon) {
730 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
731 first_notcon = 0;
732 } else
733 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
734 continue;
735 }
736
737 entry.trigger = irq_trigger(idx);
738 entry.polarity = irq_polarity(idx);
739
740 if (irq_trigger(idx)) {
741 entry.trigger = 1;
742 entry.mask = 1;
743 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
744 }
745
746 irq = pin_2_irq(idx, apic, pin);
747 add_pin_to_irq(irq, apic, pin);
748
749 if (!apic && !IO_APIC_IRQ(irq))
750 continue;
751
752 if (IO_APIC_IRQ(irq)) {
753 cpumask_t mask;
754 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
755 if (vector < 0)
756 continue;
757
758 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
759 entry.vector = vector;
760
761 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
762 if (!apic && (irq < 16))
763 disable_8259A_irq(irq);
764 }
765 ioapic_write_entry(apic, pin, entry);
766
767 spin_lock_irqsave(&ioapic_lock, flags);
768 set_native_irq_info(irq, TARGET_CPUS);
769 spin_unlock_irqrestore(&ioapic_lock, flags);
770 }
771 }
772
773 if (!first_notcon)
774 apic_printk(APIC_VERBOSE," not connected.\n");
775 }
776
777 /*
778 * Set up the 8259A-master output pin as broadcast to all
779 * CPUs.
780 */
781 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
782 {
783 struct IO_APIC_route_entry entry;
784 unsigned long flags;
785
786 memset(&entry,0,sizeof(entry));
787
788 disable_8259A_irq(0);
789
790 /* mask LVT0 */
791 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
792
793 /*
794 * We use logical delivery to get the timer IRQ
795 * to the first CPU.
796 */
797 entry.dest_mode = INT_DEST_MODE;
798 entry.mask = 0; /* unmask IRQ now */
799 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
800 entry.delivery_mode = INT_DELIVERY_MODE;
801 entry.polarity = 0;
802 entry.trigger = 0;
803 entry.vector = vector;
804
805 /*
806 * The timer IRQ doesn't have to know that behind the
807 * scene we have a 8259A-master in AEOI mode ...
808 */
809 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
810
811 /*
812 * Add it to the IO-APIC irq-routing table:
813 */
814 spin_lock_irqsave(&ioapic_lock, flags);
815 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
816 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
817 spin_unlock_irqrestore(&ioapic_lock, flags);
818
819 enable_8259A_irq(0);
820 }
821
822 void __init UNEXPECTED_IO_APIC(void)
823 {
824 }
825
826 void __apicdebuginit print_IO_APIC(void)
827 {
828 int apic, i;
829 union IO_APIC_reg_00 reg_00;
830 union IO_APIC_reg_01 reg_01;
831 union IO_APIC_reg_02 reg_02;
832 unsigned long flags;
833
834 if (apic_verbosity == APIC_QUIET)
835 return;
836
837 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
838 for (i = 0; i < nr_ioapics; i++)
839 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
840 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
841
842 /*
843 * We are a bit conservative about what we expect. We have to
844 * know about every hardware change ASAP.
845 */
846 printk(KERN_INFO "testing the IO APIC.......................\n");
847
848 for (apic = 0; apic < nr_ioapics; apic++) {
849
850 spin_lock_irqsave(&ioapic_lock, flags);
851 reg_00.raw = io_apic_read(apic, 0);
852 reg_01.raw = io_apic_read(apic, 1);
853 if (reg_01.bits.version >= 0x10)
854 reg_02.raw = io_apic_read(apic, 2);
855 spin_unlock_irqrestore(&ioapic_lock, flags);
856
857 printk("\n");
858 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
859 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
860 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
861 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
862 UNEXPECTED_IO_APIC();
863
864 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
865 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
866 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
867 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
868 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
869 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
870 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
871 (reg_01.bits.entries != 0x2E) &&
872 (reg_01.bits.entries != 0x3F) &&
873 (reg_01.bits.entries != 0x03)
874 )
875 UNEXPECTED_IO_APIC();
876
877 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
878 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
879 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
880 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
881 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
882 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
883 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
884 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
885 )
886 UNEXPECTED_IO_APIC();
887 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
888 UNEXPECTED_IO_APIC();
889
890 if (reg_01.bits.version >= 0x10) {
891 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
892 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
893 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
894 UNEXPECTED_IO_APIC();
895 }
896
897 printk(KERN_DEBUG ".... IRQ redirection table:\n");
898
899 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
900 " Stat Dest Deli Vect: \n");
901
902 for (i = 0; i <= reg_01.bits.entries; i++) {
903 struct IO_APIC_route_entry entry;
904
905 entry = ioapic_read_entry(apic, i);
906
907 printk(KERN_DEBUG " %02x %03X %02X ",
908 i,
909 entry.dest.logical.logical_dest,
910 entry.dest.physical.physical_dest
911 );
912
913 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
914 entry.mask,
915 entry.trigger,
916 entry.irr,
917 entry.polarity,
918 entry.delivery_status,
919 entry.dest_mode,
920 entry.delivery_mode,
921 entry.vector
922 );
923 }
924 }
925 printk(KERN_DEBUG "IRQ to pin mappings:\n");
926 for (i = 0; i < NR_IRQS; i++) {
927 struct irq_pin_list *entry = irq_2_pin + i;
928 if (entry->pin < 0)
929 continue;
930 printk(KERN_DEBUG "IRQ%d ", i);
931 for (;;) {
932 printk("-> %d:%d", entry->apic, entry->pin);
933 if (!entry->next)
934 break;
935 entry = irq_2_pin + entry->next;
936 }
937 printk("\n");
938 }
939
940 printk(KERN_INFO ".................................... done.\n");
941
942 return;
943 }
944
945 #if 0
946
947 static __apicdebuginit void print_APIC_bitfield (int base)
948 {
949 unsigned int v;
950 int i, j;
951
952 if (apic_verbosity == APIC_QUIET)
953 return;
954
955 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
956 for (i = 0; i < 8; i++) {
957 v = apic_read(base + i*0x10);
958 for (j = 0; j < 32; j++) {
959 if (v & (1<<j))
960 printk("1");
961 else
962 printk("0");
963 }
964 printk("\n");
965 }
966 }
967
968 void __apicdebuginit print_local_APIC(void * dummy)
969 {
970 unsigned int v, ver, maxlvt;
971
972 if (apic_verbosity == APIC_QUIET)
973 return;
974
975 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
976 smp_processor_id(), hard_smp_processor_id());
977 v = apic_read(APIC_ID);
978 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
979 v = apic_read(APIC_LVR);
980 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
981 ver = GET_APIC_VERSION(v);
982 maxlvt = get_maxlvt();
983
984 v = apic_read(APIC_TASKPRI);
985 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
986
987 v = apic_read(APIC_ARBPRI);
988 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
989 v & APIC_ARBPRI_MASK);
990 v = apic_read(APIC_PROCPRI);
991 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
992
993 v = apic_read(APIC_EOI);
994 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
995 v = apic_read(APIC_RRR);
996 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
997 v = apic_read(APIC_LDR);
998 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
999 v = apic_read(APIC_DFR);
1000 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1001 v = apic_read(APIC_SPIV);
1002 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1003
1004 printk(KERN_DEBUG "... APIC ISR field:\n");
1005 print_APIC_bitfield(APIC_ISR);
1006 printk(KERN_DEBUG "... APIC TMR field:\n");
1007 print_APIC_bitfield(APIC_TMR);
1008 printk(KERN_DEBUG "... APIC IRR field:\n");
1009 print_APIC_bitfield(APIC_IRR);
1010
1011 v = apic_read(APIC_ESR);
1012 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1013
1014 v = apic_read(APIC_ICR);
1015 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1016 v = apic_read(APIC_ICR2);
1017 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1018
1019 v = apic_read(APIC_LVTT);
1020 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1021
1022 if (maxlvt > 3) { /* PC is LVT#4. */
1023 v = apic_read(APIC_LVTPC);
1024 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1025 }
1026 v = apic_read(APIC_LVT0);
1027 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1028 v = apic_read(APIC_LVT1);
1029 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1030
1031 if (maxlvt > 2) { /* ERR is LVT#3. */
1032 v = apic_read(APIC_LVTERR);
1033 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1034 }
1035
1036 v = apic_read(APIC_TMICT);
1037 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1038 v = apic_read(APIC_TMCCT);
1039 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1040 v = apic_read(APIC_TDCR);
1041 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1042 printk("\n");
1043 }
1044
1045 void print_all_local_APICs (void)
1046 {
1047 on_each_cpu(print_local_APIC, NULL, 1, 1);
1048 }
1049
1050 void __apicdebuginit print_PIC(void)
1051 {
1052 unsigned int v;
1053 unsigned long flags;
1054
1055 if (apic_verbosity == APIC_QUIET)
1056 return;
1057
1058 printk(KERN_DEBUG "\nprinting PIC contents\n");
1059
1060 spin_lock_irqsave(&i8259A_lock, flags);
1061
1062 v = inb(0xa1) << 8 | inb(0x21);
1063 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1064
1065 v = inb(0xa0) << 8 | inb(0x20);
1066 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1067
1068 outb(0x0b,0xa0);
1069 outb(0x0b,0x20);
1070 v = inb(0xa0) << 8 | inb(0x20);
1071 outb(0x0a,0xa0);
1072 outb(0x0a,0x20);
1073
1074 spin_unlock_irqrestore(&i8259A_lock, flags);
1075
1076 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1077
1078 v = inb(0x4d1) << 8 | inb(0x4d0);
1079 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1080 }
1081
1082 #endif /* 0 */
1083
1084 static void __init enable_IO_APIC(void)
1085 {
1086 union IO_APIC_reg_01 reg_01;
1087 int i8259_apic, i8259_pin;
1088 int i, apic;
1089 unsigned long flags;
1090
1091 for (i = 0; i < PIN_MAP_SIZE; i++) {
1092 irq_2_pin[i].pin = -1;
1093 irq_2_pin[i].next = 0;
1094 }
1095
1096 /*
1097 * The number of IO-APIC IRQ registers (== #pins):
1098 */
1099 for (apic = 0; apic < nr_ioapics; apic++) {
1100 spin_lock_irqsave(&ioapic_lock, flags);
1101 reg_01.raw = io_apic_read(apic, 1);
1102 spin_unlock_irqrestore(&ioapic_lock, flags);
1103 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1104 }
1105 for(apic = 0; apic < nr_ioapics; apic++) {
1106 int pin;
1107 /* See if any of the pins is in ExtINT mode */
1108 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1109 struct IO_APIC_route_entry entry;
1110 entry = ioapic_read_entry(apic, pin);
1111
1112 /* If the interrupt line is enabled and in ExtInt mode
1113 * I have found the pin where the i8259 is connected.
1114 */
1115 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1116 ioapic_i8259.apic = apic;
1117 ioapic_i8259.pin = pin;
1118 goto found_i8259;
1119 }
1120 }
1121 }
1122 found_i8259:
1123 /* Look to see what if the MP table has reported the ExtINT */
1124 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1125 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1126 /* Trust the MP table if nothing is setup in the hardware */
1127 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1128 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1129 ioapic_i8259.pin = i8259_pin;
1130 ioapic_i8259.apic = i8259_apic;
1131 }
1132 /* Complain if the MP table and the hardware disagree */
1133 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1134 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1135 {
1136 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1137 }
1138
1139 /*
1140 * Do not trust the IO-APIC being empty at bootup
1141 */
1142 clear_IO_APIC();
1143 }
1144
1145 /*
1146 * Not an __init, needed by the reboot code
1147 */
1148 void disable_IO_APIC(void)
1149 {
1150 /*
1151 * Clear the IO-APIC before rebooting:
1152 */
1153 clear_IO_APIC();
1154
1155 /*
1156 * If the i8259 is routed through an IOAPIC
1157 * Put that IOAPIC in virtual wire mode
1158 * so legacy interrupts can be delivered.
1159 */
1160 if (ioapic_i8259.pin != -1) {
1161 struct IO_APIC_route_entry entry;
1162
1163 memset(&entry, 0, sizeof(entry));
1164 entry.mask = 0; /* Enabled */
1165 entry.trigger = 0; /* Edge */
1166 entry.irr = 0;
1167 entry.polarity = 0; /* High */
1168 entry.delivery_status = 0;
1169 entry.dest_mode = 0; /* Physical */
1170 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1171 entry.vector = 0;
1172 entry.dest.physical.physical_dest =
1173 GET_APIC_ID(apic_read(APIC_ID));
1174
1175 /*
1176 * Add it to the IO-APIC irq-routing table:
1177 */
1178 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1179 }
1180
1181 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1182 }
1183
1184 /*
1185 * There is a nasty bug in some older SMP boards, their mptable lies
1186 * about the timer IRQ. We do the following to work around the situation:
1187 *
1188 * - timer IRQ defaults to IO-APIC IRQ
1189 * - if this function detects that timer IRQs are defunct, then we fall
1190 * back to ISA timer IRQs
1191 */
1192 static int __init timer_irq_works(void)
1193 {
1194 unsigned long t1 = jiffies;
1195
1196 local_irq_enable();
1197 /* Let ten ticks pass... */
1198 mdelay((10 * 1000) / HZ);
1199
1200 /*
1201 * Expect a few ticks at least, to be sure some possible
1202 * glue logic does not lock up after one or two first
1203 * ticks in a non-ExtINT mode. Also the local APIC
1204 * might have cached one ExtINT interrupt. Finally, at
1205 * least one tick may be lost due to delays.
1206 */
1207
1208 /* jiffies wrap? */
1209 if (jiffies - t1 > 4)
1210 return 1;
1211 return 0;
1212 }
1213
1214 /*
1215 * In the SMP+IOAPIC case it might happen that there are an unspecified
1216 * number of pending IRQ events unhandled. These cases are very rare,
1217 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1218 * better to do it this way as thus we do not have to be aware of
1219 * 'pending' interrupts in the IRQ path, except at this point.
1220 */
1221 /*
1222 * Edge triggered needs to resend any interrupt
1223 * that was delayed but this is now handled in the device
1224 * independent code.
1225 */
1226
1227 /*
1228 * Starting up a edge-triggered IO-APIC interrupt is
1229 * nasty - we need to make sure that we get the edge.
1230 * If it is already asserted for some reason, we need
1231 * return 1 to indicate that is was pending.
1232 *
1233 * This is not complete - we should be able to fake
1234 * an edge even if it isn't on the 8259A...
1235 */
1236
1237 static unsigned int startup_ioapic_irq(unsigned int irq)
1238 {
1239 int was_pending = 0;
1240 unsigned long flags;
1241
1242 spin_lock_irqsave(&ioapic_lock, flags);
1243 if (irq < 16) {
1244 disable_8259A_irq(irq);
1245 if (i8259A_irq_pending(irq))
1246 was_pending = 1;
1247 }
1248 __unmask_IO_APIC_irq(irq);
1249 spin_unlock_irqrestore(&ioapic_lock, flags);
1250
1251 return was_pending;
1252 }
1253
1254 static int ioapic_retrigger_irq(unsigned int irq)
1255 {
1256 cpumask_t mask;
1257 unsigned vector;
1258 unsigned long flags;
1259
1260 spin_lock_irqsave(&vector_lock, flags);
1261 vector = irq_vector[irq];
1262 cpus_clear(mask);
1263 cpu_set(first_cpu(irq_domain[irq]), mask);
1264
1265 send_IPI_mask(mask, vector);
1266 spin_unlock_irqrestore(&vector_lock, flags);
1267
1268 return 1;
1269 }
1270
1271 /*
1272 * Level and edge triggered IO-APIC interrupts need different handling,
1273 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1274 * handled with the level-triggered descriptor, but that one has slightly
1275 * more overhead. Level-triggered interrupts cannot be handled with the
1276 * edge-triggered handler, without risking IRQ storms and other ugly
1277 * races.
1278 */
1279
1280 static void ack_apic_edge(unsigned int irq)
1281 {
1282 move_native_irq(irq);
1283 ack_APIC_irq();
1284 }
1285
1286 static void ack_apic_level(unsigned int irq)
1287 {
1288 int do_unmask_irq = 0;
1289
1290 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1291 /* If we are moving the irq we need to mask it */
1292 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1293 do_unmask_irq = 1;
1294 mask_IO_APIC_irq(irq);
1295 }
1296 #endif
1297
1298 /*
1299 * We must acknowledge the irq before we move it or the acknowledge will
1300 * not propogate properly.
1301 */
1302 ack_APIC_irq();
1303
1304 /* Now we can move and renable the irq */
1305 move_masked_irq(irq);
1306 if (unlikely(do_unmask_irq))
1307 unmask_IO_APIC_irq(irq);
1308 }
1309
1310 static struct irq_chip ioapic_chip __read_mostly = {
1311 .name = "IO-APIC",
1312 .startup = startup_ioapic_irq,
1313 .mask = mask_IO_APIC_irq,
1314 .unmask = unmask_IO_APIC_irq,
1315 .ack = ack_apic_edge,
1316 .eoi = ack_apic_level,
1317 #ifdef CONFIG_SMP
1318 .set_affinity = set_ioapic_affinity_irq,
1319 #endif
1320 .retrigger = ioapic_retrigger_irq,
1321 };
1322
1323 static inline void init_IO_APIC_traps(void)
1324 {
1325 int irq;
1326
1327 /*
1328 * NOTE! The local APIC isn't very good at handling
1329 * multiple interrupts at the same interrupt level.
1330 * As the interrupt level is determined by taking the
1331 * vector number and shifting that right by 4, we
1332 * want to spread these out a bit so that they don't
1333 * all fall in the same interrupt level.
1334 *
1335 * Also, we've got to be careful not to trash gate
1336 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1337 */
1338 for (irq = 0; irq < NR_IRQS ; irq++) {
1339 int tmp = irq;
1340 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1341 /*
1342 * Hmm.. We don't have an entry for this,
1343 * so default to an old-fashioned 8259
1344 * interrupt if we can..
1345 */
1346 if (irq < 16)
1347 make_8259A_irq(irq);
1348 else
1349 /* Strange. Oh, well.. */
1350 irq_desc[irq].chip = &no_irq_chip;
1351 }
1352 }
1353 }
1354
1355 static void enable_lapic_irq (unsigned int irq)
1356 {
1357 unsigned long v;
1358
1359 v = apic_read(APIC_LVT0);
1360 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1361 }
1362
1363 static void disable_lapic_irq (unsigned int irq)
1364 {
1365 unsigned long v;
1366
1367 v = apic_read(APIC_LVT0);
1368 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1369 }
1370
1371 static void ack_lapic_irq (unsigned int irq)
1372 {
1373 ack_APIC_irq();
1374 }
1375
1376 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1377
1378 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1379 .typename = "local-APIC-edge",
1380 .startup = NULL, /* startup_irq() not used for IRQ0 */
1381 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1382 .enable = enable_lapic_irq,
1383 .disable = disable_lapic_irq,
1384 .ack = ack_lapic_irq,
1385 .end = end_lapic_irq,
1386 };
1387
1388 static void setup_nmi (void)
1389 {
1390 /*
1391 * Dirty trick to enable the NMI watchdog ...
1392 * We put the 8259A master into AEOI mode and
1393 * unmask on all local APICs LVT0 as NMI.
1394 *
1395 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1396 * is from Maciej W. Rozycki - so we do not have to EOI from
1397 * the NMI handler or the timer interrupt.
1398 */
1399 printk(KERN_INFO "activating NMI Watchdog ...");
1400
1401 enable_NMI_through_LVT0(NULL);
1402
1403 printk(" done.\n");
1404 }
1405
1406 /*
1407 * This looks a bit hackish but it's about the only one way of sending
1408 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1409 * not support the ExtINT mode, unfortunately. We need to send these
1410 * cycles as some i82489DX-based boards have glue logic that keeps the
1411 * 8259A interrupt line asserted until INTA. --macro
1412 */
1413 static inline void unlock_ExtINT_logic(void)
1414 {
1415 int apic, pin, i;
1416 struct IO_APIC_route_entry entry0, entry1;
1417 unsigned char save_control, save_freq_select;
1418 unsigned long flags;
1419
1420 pin = find_isa_irq_pin(8, mp_INT);
1421 apic = find_isa_irq_apic(8, mp_INT);
1422 if (pin == -1)
1423 return;
1424
1425 spin_lock_irqsave(&ioapic_lock, flags);
1426 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1427 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1428 spin_unlock_irqrestore(&ioapic_lock, flags);
1429 clear_IO_APIC_pin(apic, pin);
1430
1431 memset(&entry1, 0, sizeof(entry1));
1432
1433 entry1.dest_mode = 0; /* physical delivery */
1434 entry1.mask = 0; /* unmask IRQ now */
1435 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1436 entry1.delivery_mode = dest_ExtINT;
1437 entry1.polarity = entry0.polarity;
1438 entry1.trigger = 0;
1439 entry1.vector = 0;
1440
1441 spin_lock_irqsave(&ioapic_lock, flags);
1442 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1443 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1444 spin_unlock_irqrestore(&ioapic_lock, flags);
1445
1446 save_control = CMOS_READ(RTC_CONTROL);
1447 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1448 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1449 RTC_FREQ_SELECT);
1450 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1451
1452 i = 100;
1453 while (i-- > 0) {
1454 mdelay(10);
1455 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1456 i -= 10;
1457 }
1458
1459 CMOS_WRITE(save_control, RTC_CONTROL);
1460 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1461 clear_IO_APIC_pin(apic, pin);
1462
1463 spin_lock_irqsave(&ioapic_lock, flags);
1464 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1465 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1466 spin_unlock_irqrestore(&ioapic_lock, flags);
1467 }
1468
1469 /*
1470 * This code may look a bit paranoid, but it's supposed to cooperate with
1471 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1472 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1473 * fanatically on his truly buggy board.
1474 *
1475 * FIXME: really need to revamp this for modern platforms only.
1476 */
1477 static inline void check_timer(void)
1478 {
1479 int apic1, pin1, apic2, pin2;
1480 int vector;
1481 cpumask_t mask;
1482
1483 /*
1484 * get/set the timer IRQ vector:
1485 */
1486 disable_8259A_irq(0);
1487 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1488
1489 /*
1490 * Subtle, code in do_timer_interrupt() expects an AEOI
1491 * mode for the 8259A whenever interrupts are routed
1492 * through I/O APICs. Also IRQ0 has to be enabled in
1493 * the 8259A which implies the virtual wire has to be
1494 * disabled in the local APIC.
1495 */
1496 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1497 init_8259A(1);
1498 if (timer_over_8254 > 0)
1499 enable_8259A_irq(0);
1500
1501 pin1 = find_isa_irq_pin(0, mp_INT);
1502 apic1 = find_isa_irq_apic(0, mp_INT);
1503 pin2 = ioapic_i8259.pin;
1504 apic2 = ioapic_i8259.apic;
1505
1506 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1507 vector, apic1, pin1, apic2, pin2);
1508
1509 if (pin1 != -1) {
1510 /*
1511 * Ok, does IRQ0 through the IOAPIC work?
1512 */
1513 unmask_IO_APIC_irq(0);
1514 if (!no_timer_check && timer_irq_works()) {
1515 nmi_watchdog_default();
1516 if (nmi_watchdog == NMI_IO_APIC) {
1517 disable_8259A_irq(0);
1518 setup_nmi();
1519 enable_8259A_irq(0);
1520 }
1521 if (disable_timer_pin_1 > 0)
1522 clear_IO_APIC_pin(0, pin1);
1523 return;
1524 }
1525 clear_IO_APIC_pin(apic1, pin1);
1526 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1527 "connected to IO-APIC\n");
1528 }
1529
1530 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1531 "through the 8259A ... ");
1532 if (pin2 != -1) {
1533 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1534 apic2, pin2);
1535 /*
1536 * legacy devices should be connected to IO APIC #0
1537 */
1538 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1539 if (timer_irq_works()) {
1540 apic_printk(APIC_VERBOSE," works.\n");
1541 nmi_watchdog_default();
1542 if (nmi_watchdog == NMI_IO_APIC) {
1543 setup_nmi();
1544 }
1545 return;
1546 }
1547 /*
1548 * Cleanup, just in case ...
1549 */
1550 clear_IO_APIC_pin(apic2, pin2);
1551 }
1552 apic_printk(APIC_VERBOSE," failed.\n");
1553
1554 if (nmi_watchdog == NMI_IO_APIC) {
1555 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1556 nmi_watchdog = 0;
1557 }
1558
1559 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1560
1561 disable_8259A_irq(0);
1562 irq_desc[0].chip = &lapic_irq_type;
1563 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1564 enable_8259A_irq(0);
1565
1566 if (timer_irq_works()) {
1567 apic_printk(APIC_VERBOSE," works.\n");
1568 return;
1569 }
1570 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1571 apic_printk(APIC_VERBOSE," failed.\n");
1572
1573 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1574
1575 init_8259A(0);
1576 make_8259A_irq(0);
1577 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1578
1579 unlock_ExtINT_logic();
1580
1581 if (timer_irq_works()) {
1582 apic_printk(APIC_VERBOSE," works.\n");
1583 return;
1584 }
1585 apic_printk(APIC_VERBOSE," failed :(.\n");
1586 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1587 }
1588
1589 static int __init notimercheck(char *s)
1590 {
1591 no_timer_check = 1;
1592 return 1;
1593 }
1594 __setup("no_timer_check", notimercheck);
1595
1596 /*
1597 *
1598 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1599 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1600 * Linux doesn't really care, as it's not actually used
1601 * for any interrupt handling anyway.
1602 */
1603 #define PIC_IRQS (1<<2)
1604
1605 void __init setup_IO_APIC(void)
1606 {
1607 enable_IO_APIC();
1608
1609 if (acpi_ioapic)
1610 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1611 else
1612 io_apic_irqs = ~PIC_IRQS;
1613
1614 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1615
1616 sync_Arb_IDs();
1617 setup_IO_APIC_irqs();
1618 init_IO_APIC_traps();
1619 check_timer();
1620 if (!acpi_ioapic)
1621 print_IO_APIC();
1622 }
1623
1624 struct sysfs_ioapic_data {
1625 struct sys_device dev;
1626 struct IO_APIC_route_entry entry[0];
1627 };
1628 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1629
1630 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1631 {
1632 struct IO_APIC_route_entry *entry;
1633 struct sysfs_ioapic_data *data;
1634 int i;
1635
1636 data = container_of(dev, struct sysfs_ioapic_data, dev);
1637 entry = data->entry;
1638 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1639 *entry = ioapic_read_entry(dev->id, i);
1640
1641 return 0;
1642 }
1643
1644 static int ioapic_resume(struct sys_device *dev)
1645 {
1646 struct IO_APIC_route_entry *entry;
1647 struct sysfs_ioapic_data *data;
1648 unsigned long flags;
1649 union IO_APIC_reg_00 reg_00;
1650 int i;
1651
1652 data = container_of(dev, struct sysfs_ioapic_data, dev);
1653 entry = data->entry;
1654
1655 spin_lock_irqsave(&ioapic_lock, flags);
1656 reg_00.raw = io_apic_read(dev->id, 0);
1657 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1658 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1659 io_apic_write(dev->id, 0, reg_00.raw);
1660 }
1661 spin_unlock_irqrestore(&ioapic_lock, flags);
1662 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1663 ioapic_write_entry(dev->id, i, entry[i]);
1664
1665 return 0;
1666 }
1667
1668 static struct sysdev_class ioapic_sysdev_class = {
1669 set_kset_name("ioapic"),
1670 .suspend = ioapic_suspend,
1671 .resume = ioapic_resume,
1672 };
1673
1674 static int __init ioapic_init_sysfs(void)
1675 {
1676 struct sys_device * dev;
1677 int i, size, error = 0;
1678
1679 error = sysdev_class_register(&ioapic_sysdev_class);
1680 if (error)
1681 return error;
1682
1683 for (i = 0; i < nr_ioapics; i++ ) {
1684 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1685 * sizeof(struct IO_APIC_route_entry);
1686 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1687 if (!mp_ioapic_data[i]) {
1688 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1689 continue;
1690 }
1691 memset(mp_ioapic_data[i], 0, size);
1692 dev = &mp_ioapic_data[i]->dev;
1693 dev->id = i;
1694 dev->cls = &ioapic_sysdev_class;
1695 error = sysdev_register(dev);
1696 if (error) {
1697 kfree(mp_ioapic_data[i]);
1698 mp_ioapic_data[i] = NULL;
1699 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1700 continue;
1701 }
1702 }
1703
1704 return 0;
1705 }
1706
1707 device_initcall(ioapic_init_sysfs);
1708
1709 /*
1710 * Dynamic irq allocate and deallocation
1711 */
1712 int create_irq(void)
1713 {
1714 /* Allocate an unused irq */
1715 int irq;
1716 int new;
1717 int vector = 0;
1718 unsigned long flags;
1719 cpumask_t mask;
1720
1721 irq = -ENOSPC;
1722 spin_lock_irqsave(&vector_lock, flags);
1723 for (new = (NR_IRQS - 1); new >= 0; new--) {
1724 if (platform_legacy_irq(new))
1725 continue;
1726 if (irq_vector[new] != 0)
1727 continue;
1728 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1729 if (likely(vector > 0))
1730 irq = new;
1731 break;
1732 }
1733 spin_unlock_irqrestore(&vector_lock, flags);
1734
1735 if (irq >= 0) {
1736 dynamic_irq_init(irq);
1737 }
1738 return irq;
1739 }
1740
1741 void destroy_irq(unsigned int irq)
1742 {
1743 unsigned long flags;
1744
1745 dynamic_irq_cleanup(irq);
1746
1747 spin_lock_irqsave(&vector_lock, flags);
1748 irq_vector[irq] = 0;
1749 spin_unlock_irqrestore(&vector_lock, flags);
1750 }
1751
1752 /*
1753 * MSI mesage composition
1754 */
1755 #ifdef CONFIG_PCI_MSI
1756 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1757 {
1758 int vector;
1759 unsigned dest;
1760 cpumask_t tmp;
1761
1762 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1763 if (vector >= 0) {
1764 dest = cpu_mask_to_apicid(tmp);
1765
1766 msg->address_hi = MSI_ADDR_BASE_HI;
1767 msg->address_lo =
1768 MSI_ADDR_BASE_LO |
1769 ((INT_DEST_MODE == 0) ?
1770 MSI_ADDR_DEST_MODE_PHYSICAL:
1771 MSI_ADDR_DEST_MODE_LOGICAL) |
1772 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1773 MSI_ADDR_REDIRECTION_CPU:
1774 MSI_ADDR_REDIRECTION_LOWPRI) |
1775 MSI_ADDR_DEST_ID(dest);
1776
1777 msg->data =
1778 MSI_DATA_TRIGGER_EDGE |
1779 MSI_DATA_LEVEL_ASSERT |
1780 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1781 MSI_DATA_DELIVERY_FIXED:
1782 MSI_DATA_DELIVERY_LOWPRI) |
1783 MSI_DATA_VECTOR(vector);
1784 }
1785 return vector;
1786 }
1787
1788 #ifdef CONFIG_SMP
1789 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1790 {
1791 struct msi_msg msg;
1792 unsigned int dest;
1793 cpumask_t tmp;
1794 int vector;
1795
1796 cpus_and(tmp, mask, cpu_online_map);
1797 if (cpus_empty(tmp))
1798 tmp = TARGET_CPUS;
1799
1800 cpus_and(mask, tmp, CPU_MASK_ALL);
1801
1802 vector = assign_irq_vector(irq, mask, &tmp);
1803 if (vector < 0)
1804 return;
1805
1806 dest = cpu_mask_to_apicid(tmp);
1807
1808 read_msi_msg(irq, &msg);
1809
1810 msg.data &= ~MSI_DATA_VECTOR_MASK;
1811 msg.data |= MSI_DATA_VECTOR(vector);
1812 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1813 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1814
1815 write_msi_msg(irq, &msg);
1816 set_native_irq_info(irq, mask);
1817 }
1818 #endif /* CONFIG_SMP */
1819
1820 /*
1821 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1822 * which implement the MSI or MSI-X Capability Structure.
1823 */
1824 static struct irq_chip msi_chip = {
1825 .name = "PCI-MSI",
1826 .unmask = unmask_msi_irq,
1827 .mask = mask_msi_irq,
1828 .ack = ack_apic_edge,
1829 #ifdef CONFIG_SMP
1830 .set_affinity = set_msi_irq_affinity,
1831 #endif
1832 .retrigger = ioapic_retrigger_irq,
1833 };
1834
1835 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1836 {
1837 struct msi_msg msg;
1838 int ret;
1839 ret = msi_compose_msg(dev, irq, &msg);
1840 if (ret < 0)
1841 return ret;
1842
1843 write_msi_msg(irq, &msg);
1844
1845 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1846
1847 return 0;
1848 }
1849
1850 void arch_teardown_msi_irq(unsigned int irq)
1851 {
1852 return;
1853 }
1854
1855 #endif /* CONFIG_PCI_MSI */
1856
1857 /*
1858 * Hypertransport interrupt support
1859 */
1860 #ifdef CONFIG_HT_IRQ
1861
1862 #ifdef CONFIG_SMP
1863
1864 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1865 {
1866 u32 low, high;
1867 low = read_ht_irq_low(irq);
1868 high = read_ht_irq_high(irq);
1869
1870 low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1871 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1872
1873 low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1874 high |= HT_IRQ_HIGH_DEST_ID(dest);
1875
1876 write_ht_irq_low(irq, low);
1877 write_ht_irq_high(irq, high);
1878 }
1879
1880 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1881 {
1882 unsigned int dest;
1883 cpumask_t tmp;
1884 int vector;
1885
1886 cpus_and(tmp, mask, cpu_online_map);
1887 if (cpus_empty(tmp))
1888 tmp = TARGET_CPUS;
1889
1890 cpus_and(mask, tmp, CPU_MASK_ALL);
1891
1892 vector = assign_irq_vector(irq, mask, &tmp);
1893 if (vector < 0)
1894 return;
1895
1896 dest = cpu_mask_to_apicid(tmp);
1897
1898 target_ht_irq(irq, dest, vector & 0xff);
1899 set_native_irq_info(irq, mask);
1900 }
1901 #endif
1902
1903 static struct irq_chip ht_irq_chip = {
1904 .name = "PCI-HT",
1905 .mask = mask_ht_irq,
1906 .unmask = unmask_ht_irq,
1907 .ack = ack_apic_edge,
1908 #ifdef CONFIG_SMP
1909 .set_affinity = set_ht_irq_affinity,
1910 #endif
1911 .retrigger = ioapic_retrigger_irq,
1912 };
1913
1914 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1915 {
1916 int vector;
1917 cpumask_t tmp;
1918
1919 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1920 if (vector >= 0) {
1921 u32 low, high;
1922 unsigned dest;
1923
1924 dest = cpu_mask_to_apicid(tmp);
1925
1926 high = HT_IRQ_HIGH_DEST_ID(dest);
1927
1928 low = HT_IRQ_LOW_BASE |
1929 HT_IRQ_LOW_DEST_ID(dest) |
1930 HT_IRQ_LOW_VECTOR(vector) |
1931 ((INT_DEST_MODE == 0) ?
1932 HT_IRQ_LOW_DM_PHYSICAL :
1933 HT_IRQ_LOW_DM_LOGICAL) |
1934 HT_IRQ_LOW_RQEOI_EDGE |
1935 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1936 HT_IRQ_LOW_MT_FIXED :
1937 HT_IRQ_LOW_MT_ARBITRATED);
1938
1939 write_ht_irq_low(irq, low);
1940 write_ht_irq_high(irq, high);
1941
1942 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
1943 handle_edge_irq, "edge");
1944 }
1945 return vector;
1946 }
1947 #endif /* CONFIG_HT_IRQ */
1948
1949 /* --------------------------------------------------------------------------
1950 ACPI-based IOAPIC Configuration
1951 -------------------------------------------------------------------------- */
1952
1953 #ifdef CONFIG_ACPI
1954
1955 #define IO_APIC_MAX_ID 0xFE
1956
1957 int __init io_apic_get_redir_entries (int ioapic)
1958 {
1959 union IO_APIC_reg_01 reg_01;
1960 unsigned long flags;
1961
1962 spin_lock_irqsave(&ioapic_lock, flags);
1963 reg_01.raw = io_apic_read(ioapic, 1);
1964 spin_unlock_irqrestore(&ioapic_lock, flags);
1965
1966 return reg_01.bits.entries;
1967 }
1968
1969
1970 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1971 {
1972 struct IO_APIC_route_entry entry;
1973 unsigned long flags;
1974 int vector;
1975 cpumask_t mask;
1976
1977 if (!IO_APIC_IRQ(irq)) {
1978 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1979 ioapic);
1980 return -EINVAL;
1981 }
1982
1983 /*
1984 * IRQs < 16 are already in the irq_2_pin[] map
1985 */
1986 if (irq >= 16)
1987 add_pin_to_irq(irq, ioapic, pin);
1988
1989
1990 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
1991 if (vector < 0)
1992 return vector;
1993
1994 /*
1995 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1996 * Note that we mask (disable) IRQs now -- these get enabled when the
1997 * corresponding device driver registers for this IRQ.
1998 */
1999
2000 memset(&entry,0,sizeof(entry));
2001
2002 entry.delivery_mode = INT_DELIVERY_MODE;
2003 entry.dest_mode = INT_DEST_MODE;
2004 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2005 entry.trigger = triggering;
2006 entry.polarity = polarity;
2007 entry.mask = 1; /* Disabled (masked) */
2008 entry.vector = vector & 0xff;
2009
2010 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2011 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2012 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2013 triggering, polarity);
2014
2015 ioapic_register_intr(irq, entry.vector, triggering);
2016
2017 if (!ioapic && (irq < 16))
2018 disable_8259A_irq(irq);
2019
2020 ioapic_write_entry(ioapic, pin, entry);
2021
2022 spin_lock_irqsave(&ioapic_lock, flags);
2023 set_native_irq_info(irq, TARGET_CPUS);
2024 spin_unlock_irqrestore(&ioapic_lock, flags);
2025
2026 return 0;
2027 }
2028
2029 #endif /* CONFIG_ACPI */
2030
2031
2032 /*
2033 * This function currently is only a helper for the i386 smp boot process where
2034 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2035 * so mask in all cases should simply be TARGET_CPUS
2036 */
2037 #ifdef CONFIG_SMP
2038 void __init setup_ioapic_dest(void)
2039 {
2040 int pin, ioapic, irq, irq_entry;
2041
2042 if (skip_ioapic_setup == 1)
2043 return;
2044
2045 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2046 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2047 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2048 if (irq_entry == -1)
2049 continue;
2050 irq = pin_2_irq(irq_entry, ioapic, pin);
2051 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2052 }
2053
2054 }
2055 }
2056 #endif
CJK support for tty framebuffer vt