drivers/net/wireless/iwlwifi/iwl-3945-hw.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 /*
  64  * Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
  65  * Please use iwl-3945-commands.h for uCode API definitions.
  66  * Please use iwl-3945.h for driver implementation definitions.
  67  */
  68
  69 #ifndef __iwl_3945_hw__
  70 #define __iwl_3945_hw__
  71
  72 /*
  73  * uCode queue management definitions ...
  74  * Queue #4 is the command queue for 3945 and 4965.
  75  */
  76 #define IWL_CMD_QUEUE_NUM       4
  77
  78 /* Time constants */
  79 #define SHORT_SLOT_TIME 9
  80 #define LONG_SLOT_TIME 20
  81
  82 /* RSSI to dBm */
  83 #define IWL_RSSI_OFFSET 95
  84
  85 /*
  86  * EEPROM related constants, enums, and structures.
  87  */
  88
  89 /*
  90  * EEPROM access time values:
  91  *
  92  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
  93  *   then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
  94  *   CSR_EEPROM_REG_BIT_CMD (0x2).
  95  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
  96  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
  97  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
  98  */
  99 #define IWL_EEPROM_ACCESS_TIMEOUT       5000 /* uSec */
 100
 101 /*
 102  * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags.
 103  *
 104  * IBSS and/or AP operation is allowed *only* on those channels with
 105  * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
 106  * RADAR detection is not supported by the 3945 driver, but is a
 107  * requirement for establishing a new network for legal operation on channels
 108  * requiring RADAR detection or restricting ACTIVE scanning.
 109  *
 110  * NOTE:  "WIDE" flag indicates that 20 MHz channel is supported;
 111  *        3945 does not support FAT 40 MHz-wide channels.
 112  *
 113  * NOTE:  Using a channel inappropriately will result in a uCode error!
 114  */
 115 enum {
 116         EEPROM_CHANNEL_VALID = (1 << 0),        /* usable for this SKU/geo */
 117         EEPROM_CHANNEL_IBSS = (1 << 1),         /* usable as an IBSS channel */
 118         /* Bit 2 Reserved */
 119         EEPROM_CHANNEL_ACTIVE = (1 << 3),       /* active scanning allowed */
 120         EEPROM_CHANNEL_RADAR = (1 << 4),        /* radar detection required */
 121         EEPROM_CHANNEL_WIDE = (1 << 5),         /* 20 MHz channel okay */
 122         /* Bit 6 Reserved (was Narrow Channel) */
 123         EEPROM_CHANNEL_DFS = (1 << 7),  /* dynamic freq selection candidate */
 124 };
 125
 126 /* SKU Capabilities */
 127 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
 128 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
 129 #define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)
 130
 131 /* *regulatory* channel data from eeprom, one for each channel */
 132 struct iwl3945_eeprom_channel {
 133         u8 flags;               /* flags copied from EEPROM */
 134         s8 max_power_avg;       /* max power (dBm) on this chnl, limit 31 */
 135 } __attribute__ ((packed));
 136
 137 /*
 138  * Mapping of a Tx power level, at factory calibration temperature,
 139  *   to a radio/DSP gain table index.
 140  * One for each of 5 "sample" power levels in each band.
 141  * v_det is measured at the factory, using the 3945's built-in power amplifier
 142  *   (PA) output voltage detector.  This same detector is used during Tx of
 143  *   long packets in normal operation to provide feedback as to proper output
 144  *   level.
 145  * Data copied from EEPROM.
 146  * DO NOT ALTER THIS STRUCTURE!!!
 147  */
 148 struct iwl3945_eeprom_txpower_sample {
 149         u8 gain_index;          /* index into power (gain) setup table ... */
 150         s8 power;               /* ... for this pwr level for this chnl group */
 151         u16 v_det;              /* PA output voltage */
 152 } __attribute__ ((packed));
 153
 154 /*
 155  * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
 156  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
 157  * Tx power setup code interpolates between the 5 "sample" power levels
 158  *    to determine the nominal setup for a requested power level.
 159  * Data copied from EEPROM.
 160  * DO NOT ALTER THIS STRUCTURE!!!
 161  */
 162 struct iwl3945_eeprom_txpower_group {
 163         struct iwl3945_eeprom_txpower_sample samples[5];  /* 5 power levels */
 164         s32 a, b, c, d, e;      /* coefficients for voltage->power
 165                                  * formula (signed) */
 166         s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
 167                                  * frequency (signed) */
 168         s8 saturation_power;    /* highest power possible by h/w in this
 169                                  * band */
 170         u8 group_channel;       /* "representative" channel # in this band */
 171         s16 temperature;        /* h/w temperature at factory calib this band
 172                                  * (signed) */
 173 } __attribute__ ((packed));
 174
 175 /*
 176  * Temperature-based Tx-power compensation data, not band-specific.
 177  * These coefficients are use to modify a/b/c/d/e coeffs based on
 178  *   difference between current temperature and factory calib temperature.
 179  * Data copied from EEPROM.
 180  */
 181 struct iwl3945_eeprom_temperature_corr {
 182         u32 Ta;
 183         u32 Tb;
 184         u32 Tc;
 185         u32 Td;
 186         u32 Te;
 187 } __attribute__ ((packed));
 188
 189 /*
 190  * EEPROM map
 191  */
 192 struct iwl3945_eeprom {
 193         u8 reserved0[16];
 194         u16 device_id;  /* abs.ofs: 16 */
 195         u8 reserved1[2];
 196         u16 pmc;                /* abs.ofs: 20 */
 197         u8 reserved2[20];
 198         u8 mac_address[6];      /* abs.ofs: 42 */
 199         u8 reserved3[58];
 200         u16 board_revision;     /* abs.ofs: 106 */
 201         u8 reserved4[11];
 202         u8 board_pba_number[9]; /* abs.ofs: 119 */
 203         u8 reserved5[8];
 204         u16 version;            /* abs.ofs: 136 */
 205         u8 sku_cap;             /* abs.ofs: 138 */
 206         u8 leds_mode;           /* abs.ofs: 139 */
 207         u16 oem_mode;
 208         u16 wowlan_mode;        /* abs.ofs: 142 */
 209         u16 leds_time_interval; /* abs.ofs: 144 */
 210         u8 leds_off_time;       /* abs.ofs: 146 */
 211         u8 leds_on_time;        /* abs.ofs: 147 */
 212         u8 almgor_m_version;    /* abs.ofs: 148 */
 213         u8 antenna_switch_type; /* abs.ofs: 149 */
 214         u8 reserved6[42];
 215         u8 sku_id[4];           /* abs.ofs: 192 */
 216
 217 /*
 218  * Per-channel regulatory data.
 219  *
 220  * Each channel that *might* be supported by 3945 or 4965 has a fixed location
 221  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 222  * txpower (MSB).
 223  *
 224  * Entries immediately below are for 20 MHz channel width.  FAT (40 MHz)
 225  * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
 226  *
 227  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 228  */
 229         u16 band_1_count;       /* abs.ofs: 196 */
 230         struct iwl3945_eeprom_channel band_1_channels[14];  /* abs.ofs: 196 */
 231
 232 /*
 233  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 234  * 5.0 GHz channels 7, 8, 11, 12, 16
 235  * (4915-5080MHz) (none of these is ever supported)
 236  */
 237         u16 band_2_count;       /* abs.ofs: 226 */
 238         struct iwl3945_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */
 239
 240 /*
 241  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 242  * (5170-5320MHz)
 243  */
 244         u16 band_3_count;       /* abs.ofs: 254 */
 245         struct iwl3945_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */
 246
 247 /*
 248  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 249  * (5500-5700MHz)
 250  */
 251         u16 band_4_count;       /* abs.ofs: 280 */
 252         struct iwl3945_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */
 253
 254 /*
 255  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 256  * (5725-5825MHz)
 257  */
 258         u16 band_5_count;       /* abs.ofs: 304 */
 259         struct iwl3945_eeprom_channel band_5_channels[6];  /* abs.ofs: 306 */
 260
 261         u8 reserved9[194];
 262
 263 /*
 264  * 3945 Txpower calibration data.
 265  */
 266 #define IWL_NUM_TX_CALIB_GROUPS 5
 267         struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
 268 /* abs.ofs: 512 */
 269         struct iwl3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */
 270         u8 reserved16[172];     /* fill out to full 1024 byte block */
 271 } __attribute__ ((packed));
 272
 273 #define IWL_EEPROM_IMAGE_SIZE 1024
 274
 275 /* End of EEPROM */
 276
 277
 278 #define PCI_LINK_CTRL      0x0F0
 279 #define PCI_POWER_SOURCE   0x0C8
 280 #define PCI_REG_WUM8       0x0E8
 281 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT         (0x80000000)
 282
 283 #define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)      /* bit 6    */
 284 #define PCI_CFG_REV_ID_BIT_RTP                      (0x80)      /* bit 7    */
 285
 286 #define TFD_QUEUE_MIN           0
 287 #define TFD_QUEUE_MAX           6
 288 #define TFD_QUEUE_SIZE_MAX      (256)
 289
 290 #define IWL_NUM_SCAN_RATES         (2)
 291
 292 #define IWL_DEFAULT_TX_RETRY  15
 293
 294 /*********************************************/
 295
 296 #define RFD_SIZE                              4
 297 #define NUM_TFD_CHUNKS                        4
 298
 299 #define RX_QUEUE_SIZE                         256
 300 #define RX_QUEUE_MASK                         255
 301 #define RX_QUEUE_SIZE_LOG                     8
 302
 303 #define U32_PAD(n)              ((4-(n))&0x3)
 304
 305 #define TFD_CTL_COUNT_SET(n)       (n << 24)
 306 #define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)
 307 #define TFD_CTL_PAD_SET(n)         (n << 28)
 308 #define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)
 309
 310 #define TFD_TX_CMD_SLOTS 256
 311 #define TFD_CMD_SLOTS 32
 312
 313 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl3945_cmd) - \
 314                               sizeof(struct iwl3945_cmd_meta))
 315
 316 /*
 317  * RX related structures and functions
 318  */
 319 #define RX_FREE_BUFFERS 64
 320 #define RX_LOW_WATERMARK 8
 321
 322 /* Sizes and addresses for instruction and data memory (SRAM) in
 323  * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
 324 #define RTC_INST_LOWER_BOUND                    (0x000000)
 325 #define ALM_RTC_INST_UPPER_BOUND                (0x014000)
 326
 327 #define RTC_DATA_LOWER_BOUND                    (0x800000)
 328 #define ALM_RTC_DATA_UPPER_BOUND                (0x808000)
 329
 330 #define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
 331 #define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
 332
 333 #define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE
 334 #define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE
 335
 336 /* Size of uCode instruction memory in bootstrap state machine */
 337 #define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE
 338
 339 #define IWL39_MAX_NUM_QUEUES    8
 340
 341 static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
 342 {
 343         return (addr >= RTC_DATA_LOWER_BOUND) &&
 344                (addr < ALM_RTC_DATA_UPPER_BOUND);
 345 }
 346
 347 /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
 348  * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
 349 struct iwl3945_shared {
 350         __le32 tx_base_ptr[8];
 351         __le32 rx_read_ptr[3];
 352 } __attribute__ ((packed));
 353
 354 struct iwl3945_tfd_frame_data {
 355         __le32 addr;
 356         __le32 len;
 357 } __attribute__ ((packed));
 358
 359 struct iwl3945_tfd_frame {
 360         __le32 control_flags;
 361         struct iwl3945_tfd_frame_data pa[4];
 362         u8 reserved[28];
 363 } __attribute__ ((packed));
 364
 365 static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
 366 {
 367         return le16_to_cpu(rate_n_flags) & 0xFF;
 368 }
 369
 370 static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
 371 {
 372         return le16_to_cpu(rate_n_flags);
 373 }
 374
 375 static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
 376 {
 377         return cpu_to_le16((u16)rate|flags);
 378 }
 379 #endif