drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34
  35 /* General customization:
  36  */
  37
  38 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  39
  40 #define DRIVER_NAME             "i915"
  41 #define DRIVER_DESC             "Intel Graphics"
  42 #define DRIVER_DATE             "20080730"
  43
  44 enum pipe {
  45         PIPE_A = 0,
  46         PIPE_B,
  47 };
  48
  49 /* Interface history:
  50  *
  51  * 1.1: Original.
  52  * 1.2: Add Power Management
  53  * 1.3: Add vblank support
  54  * 1.4: Fix cmdbuffer path, add heap destroy
  55  * 1.5: Add vblank pipe configuration
  56  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  57  *      - Support vertical blank on secondary display pipe
  58  */
  59 #define DRIVER_MAJOR            1
  60 #define DRIVER_MINOR            6
  61 #define DRIVER_PATCHLEVEL       0
  62
  63 #define WATCH_COHERENCY 0
  64 #define WATCH_BUF       0
  65 #define WATCH_EXEC      0
  66 #define WATCH_LRU       0
  67 #define WATCH_RELOC     0
  68 #define WATCH_INACTIVE  0
  69 #define WATCH_PWRITE    0
  70
  71 typedef struct _drm_i915_ring_buffer {
  72         int tail_mask;
  73         unsigned long Size;
  74         u8 *virtual_start;
  75         int head;
  76         int tail;
  77         int space;
  78         drm_local_map_t map;
  79         struct drm_gem_object *ring_obj;
  80 } drm_i915_ring_buffer_t;
  81
  82 struct mem_block {
  83         struct mem_block *next;
  84         struct mem_block *prev;
  85         int start;
  86         int size;
  87         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  88 };
  89
  90 typedef struct _drm_i915_vbl_swap {
  91         struct list_head head;
  92         drm_drawable_t drw_id;
  93         unsigned int pipe;
  94         unsigned int sequence;
  95 } drm_i915_vbl_swap_t;
  96
  97 struct opregion_header;
  98 struct opregion_acpi;
  99 struct opregion_swsci;
 100 struct opregion_asle;
 101
 102 struct intel_opregion {
 103         struct opregion_header *header;
 104         struct opregion_acpi *acpi;
 105         struct opregion_swsci *swsci;
 106         struct opregion_asle *asle;
 107         int enabled;
 108 };
 109
 110 typedef struct drm_i915_private {
 111         struct drm_device *dev;
 112
 113         void __iomem *regs;
 114         drm_local_map_t *sarea;
 115
 116         drm_i915_sarea_t *sarea_priv;
 117         drm_i915_ring_buffer_t ring;
 118
 119         drm_dma_handle_t *status_page_dmah;
 120         void *hw_status_page;
 121         dma_addr_t dma_status_page;
 122         uint32_t counter;
 123         unsigned int status_gfx_addr;
 124         drm_local_map_t hws_map;
 125         struct drm_gem_object *hws_obj;
 126
 127         unsigned int cpp;
 128         int back_offset;
 129         int front_offset;
 130         int current_page;
 131         int page_flipping;
 132
 133         wait_queue_head_t irq_queue;
 134         atomic_t irq_received;
 135         /** Protects user_irq_refcount and irq_mask_reg */
 136         spinlock_t user_irq_lock;
 137         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 138         int user_irq_refcount;
 139         /** Cached value of IMR to avoid reads in updating the bitfield */
 140         u32 irq_mask_reg;
 141
 142         int tex_lru_log_granularity;
 143         int allow_batchbuffer;
 144         struct mem_block *agp_heap;
 145         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 146         int vblank_pipe;
 147
 148         spinlock_t swaps_lock;
 149         drm_i915_vbl_swap_t vbl_swaps;
 150         unsigned int swaps_pending;
 151
 152         struct intel_opregion opregion;
 153
 154         /* Register state */
 155         u8 saveLBB;
 156         u32 saveDSPACNTR;
 157         u32 saveDSPBCNTR;
 158         u32 saveDSPARB;
 159         u32 savePIPEACONF;
 160         u32 savePIPEBCONF;
 161         u32 savePIPEASRC;
 162         u32 savePIPEBSRC;
 163         u32 saveFPA0;
 164         u32 saveFPA1;
 165         u32 saveDPLL_A;
 166         u32 saveDPLL_A_MD;
 167         u32 saveHTOTAL_A;
 168         u32 saveHBLANK_A;
 169         u32 saveHSYNC_A;
 170         u32 saveVTOTAL_A;
 171         u32 saveVBLANK_A;
 172         u32 saveVSYNC_A;
 173         u32 saveBCLRPAT_A;
 174         u32 savePIPEASTAT;
 175         u32 saveDSPASTRIDE;
 176         u32 saveDSPASIZE;
 177         u32 saveDSPAPOS;
 178         u32 saveDSPAADDR;
 179         u32 saveDSPASURF;
 180         u32 saveDSPATILEOFF;
 181         u32 savePFIT_PGM_RATIOS;
 182         u32 saveBLC_PWM_CTL;
 183         u32 saveBLC_PWM_CTL2;
 184         u32 saveFPB0;
 185         u32 saveFPB1;
 186         u32 saveDPLL_B;
 187         u32 saveDPLL_B_MD;
 188         u32 saveHTOTAL_B;
 189         u32 saveHBLANK_B;
 190         u32 saveHSYNC_B;
 191         u32 saveVTOTAL_B;
 192         u32 saveVBLANK_B;
 193         u32 saveVSYNC_B;
 194         u32 saveBCLRPAT_B;
 195         u32 savePIPEBSTAT;
 196         u32 saveDSPBSTRIDE;
 197         u32 saveDSPBSIZE;
 198         u32 saveDSPBPOS;
 199         u32 saveDSPBADDR;
 200         u32 saveDSPBSURF;
 201         u32 saveDSPBTILEOFF;
 202         u32 saveVGA0;
 203         u32 saveVGA1;
 204         u32 saveVGA_PD;
 205         u32 saveVGACNTRL;
 206         u32 saveADPA;
 207         u32 saveLVDS;
 208         u32 savePP_ON_DELAYS;
 209         u32 savePP_OFF_DELAYS;
 210         u32 saveDVOA;
 211         u32 saveDVOB;
 212         u32 saveDVOC;
 213         u32 savePP_ON;
 214         u32 savePP_OFF;
 215         u32 savePP_CONTROL;
 216         u32 savePP_DIVISOR;
 217         u32 savePFIT_CONTROL;
 218         u32 save_palette_a[256];
 219         u32 save_palette_b[256];
 220         u32 saveFBC_CFB_BASE;
 221         u32 saveFBC_LL_BASE;
 222         u32 saveFBC_CONTROL;
 223         u32 saveFBC_CONTROL2;
 224         u32 saveIER;
 225         u32 saveIIR;
 226         u32 saveIMR;
 227         u32 saveCACHE_MODE_0;
 228         u32 saveD_STATE;
 229         u32 saveCG_2D_DIS;
 230         u32 saveMI_ARB_STATE;
 231         u32 saveSWF0[16];
 232         u32 saveSWF1[16];
 233         u32 saveSWF2[3];
 234         u8 saveMSR;
 235         u8 saveSR[8];
 236         u8 saveGR[25];
 237         u8 saveAR_INDEX;
 238         u8 saveAR[21];
 239         u8 saveDACMASK;
 240         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
 241         u8 saveCR[37];
 242
 243         /** Work task for vblank-related ring access */
 244         struct work_struct vblank_work;
 245
 246         struct {
 247                 struct drm_mm gtt_space;
 248
 249                 /**
 250                  * List of objects currently involved in rendering from the
 251                  * ringbuffer.
 252                  *
 253                  * A reference is held on the buffer while on this list.
 254                  */
 255                 struct list_head active_list;
 256
 257                 /**
 258                  * List of objects which are not in the ringbuffer but which
 259                  * still have a write_domain which needs to be flushed before
 260                  * unbinding.
 261                  *
 262                  * A reference is held on the buffer while on this list.
 263                  */
 264                 struct list_head flushing_list;
 265
 266                 /**
 267                  * LRU list of objects which are not in the ringbuffer and
 268                  * are ready to unbind, but are still in the GTT.
 269                  *
 270                  * A reference is not held on the buffer while on this list,
 271                  * as merely being GTT-bound shouldn't prevent its being
 272                  * freed, and we'll pull it off the list in the free path.
 273                  */
 274                 struct list_head inactive_list;
 275
 276                 /**
 277                  * List of breadcrumbs associated with GPU requests currently
 278                  * outstanding.
 279                  */
 280                 struct list_head request_list;
 281
 282                 /**
 283                  * We leave the user IRQ off as much as possible,
 284                  * but this means that requests will finish and never
 285                  * be retired once the system goes idle. Set a timer to
 286                  * fire periodically while the ring is running. When it
 287                  * fires, go retire requests.
 288                  */
 289                 struct delayed_work retire_work;
 290
 291                 uint32_t next_gem_seqno;
 292
 293                 /**
 294                  * Waiting sequence number, if any
 295                  */
 296                 uint32_t waiting_gem_seqno;
 297
 298                 /**
 299                  * Last seq seen at irq time
 300                  */
 301                 uint32_t irq_gem_seqno;
 302
 303                 /**
 304                  * Flag if the X Server, and thus DRM, is not currently in
 305                  * control of the device.
 306                  *
 307                  * This is set between LeaveVT and EnterVT.  It needs to be
 308                  * replaced with a semaphore.  It also needs to be
 309                  * transitioned away from for kernel modesetting.
 310                  */
 311                 int suspended;
 312
 313                 /**
 314                  * Flag if the hardware appears to be wedged.
 315                  *
 316                  * This is set when attempts to idle the device timeout.
 317                  * It prevents command submission from occuring and makes
 318                  * every pending request fail
 319                  */
 320                 int wedged;
 321
 322                 /** Bit 6 swizzling required for X tiling */
 323                 uint32_t bit_6_swizzle_x;
 324                 /** Bit 6 swizzling required for Y tiling */
 325                 uint32_t bit_6_swizzle_y;
 326         } mm;
 327 } drm_i915_private_t;
 328
 329 /** driver private structure attached to each drm_gem_object */
 330 struct drm_i915_gem_object {
 331         struct drm_gem_object *obj;
 332
 333         /** Current space allocated to this object in the GTT, if any. */
 334         struct drm_mm_node *gtt_space;
 335
 336         /** This object's place on the active/flushing/inactive lists */
 337         struct list_head list;
 338
 339         /**
 340          * This is set if the object is on the active or flushing lists
 341          * (has pending rendering), and is not set if it's on inactive (ready
 342          * to be unbound).
 343          */
 344         int active;
 345
 346         /**
 347          * This is set if the object has been written to since last bound
 348          * to the GTT
 349          */
 350         int dirty;
 351
 352         /** AGP memory structure for our GTT binding. */
 353         DRM_AGP_MEM *agp_mem;
 354
 355         struct page **page_list;
 356
 357         /**
 358          * Current offset of the object in GTT space.
 359          *
 360          * This is the same as gtt_space->start
 361          */
 362         uint32_t gtt_offset;
 363
 364         /** Boolean whether this object has a valid gtt offset. */
 365         int gtt_bound;
 366
 367         /** How many users have pinned this object in GTT space */
 368         int pin_count;
 369
 370         /** Breadcrumb of last rendering to the buffer. */
 371         uint32_t last_rendering_seqno;
 372
 373         /** Current tiling mode for the object. */
 374         uint32_t tiling_mode;
 375
 376         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 377         uint32_t agp_type;
 378
 379         /**
 380          * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
 381          * GEM_DOMAIN_CPU is not in the object's read domain.
 382          */
 383         uint8_t *page_cpu_valid;
 384 };
 385
 386 /**
 387  * Request queue structure.
 388  *
 389  * The request queue allows us to note sequence numbers that have been emitted
 390  * and may be associated with active buffers to be retired.
 391  *
 392  * By keeping this list, we can avoid having to do questionable
 393  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 394  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 395  */
 396 struct drm_i915_gem_request {
 397         /** GEM sequence number associated with this request. */
 398         uint32_t seqno;
 399
 400         /** Time at which this request was emitted, in jiffies. */
 401         unsigned long emitted_jiffies;
 402
 403         /** Cache domains that were flushed at the start of the request. */
 404         uint32_t flush_domains;
 405
 406         struct list_head list;
 407 };
 408
 409 struct drm_i915_file_private {
 410         struct {
 411                 uint32_t last_gem_seqno;
 412                 uint32_t last_gem_throttle_seqno;
 413         } mm;
 414 };
 415
 416 extern struct drm_ioctl_desc i915_ioctls[];
 417 extern int i915_max_ioctl;
 418
 419                                 /* i915_dma.c */
 420 extern void i915_kernel_lost_context(struct drm_device * dev);
 421 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 422 extern int i915_driver_unload(struct drm_device *);
 423 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 424 extern void i915_driver_lastclose(struct drm_device * dev);
 425 extern void i915_driver_preclose(struct drm_device *dev,
 426                                  struct drm_file *file_priv);
 427 extern void i915_driver_postclose(struct drm_device *dev,
 428                                   struct drm_file *file_priv);
 429 extern int i915_driver_device_is_agp(struct drm_device * dev);
 430 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 431                               unsigned long arg);
 432 extern int i915_emit_box(struct drm_device *dev,
 433                          struct drm_clip_rect __user *boxes,
 434                          int i, int DR1, int DR4);
 435
 436 /* i915_irq.c */
 437 extern int i915_irq_emit(struct drm_device *dev, void *data,
 438                          struct drm_file *file_priv);
 439 extern int i915_irq_wait(struct drm_device *dev, void *data,
 440                          struct drm_file *file_priv);
 441 void i915_user_irq_get(struct drm_device *dev);
 442 void i915_user_irq_put(struct drm_device *dev);
 443
 444 extern void i915_vblank_work_handler(struct work_struct *work);
 445 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 446 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 447 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 448 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 449 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 450                                 struct drm_file *file_priv);
 451 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 452                                 struct drm_file *file_priv);
 453 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 454 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 455 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 456 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 457                             struct drm_file *file_priv);
 458 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 459
 460 /* i915_mem.c */
 461 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 462                           struct drm_file *file_priv);
 463 extern int i915_mem_free(struct drm_device *dev, void *data,
 464                          struct drm_file *file_priv);
 465 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 466                               struct drm_file *file_priv);
 467 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 468                                  struct drm_file *file_priv);
 469 extern void i915_mem_takedown(struct mem_block **heap);
 470 extern void i915_mem_release(struct drm_device * dev,
 471                              struct drm_file *file_priv, struct mem_block *heap);
 472 /* i915_gem.c */
 473 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 474                         struct drm_file *file_priv);
 475 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 476                           struct drm_file *file_priv);
 477 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 478                          struct drm_file *file_priv);
 479 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 480                           struct drm_file *file_priv);
 481 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 482                         struct drm_file *file_priv);
 483 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 484                               struct drm_file *file_priv);
 485 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 486                              struct drm_file *file_priv);
 487 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 488                         struct drm_file *file_priv);
 489 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 490                        struct drm_file *file_priv);
 491 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 492                          struct drm_file *file_priv);
 493 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 494                         struct drm_file *file_priv);
 495 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 496                             struct drm_file *file_priv);
 497 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 498                            struct drm_file *file_priv);
 499 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 500                            struct drm_file *file_priv);
 501 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 502                         struct drm_file *file_priv);
 503 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 504                         struct drm_file *file_priv);
 505 void i915_gem_load(struct drm_device *dev);
 506 int i915_gem_proc_init(struct drm_minor *minor);
 507 void i915_gem_proc_cleanup(struct drm_minor *minor);
 508 int i915_gem_init_object(struct drm_gem_object *obj);
 509 void i915_gem_free_object(struct drm_gem_object *obj);
 510 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 511 void i915_gem_object_unpin(struct drm_gem_object *obj);
 512 void i915_gem_lastclose(struct drm_device *dev);
 513 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 514 void i915_gem_retire_requests(struct drm_device *dev);
 515 void i915_gem_retire_work_handler(struct work_struct *work);
 516 void i915_gem_clflush_object(struct drm_gem_object *obj);
 517
 518 /* i915_gem_tiling.c */
 519 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 520
 521 /* i915_gem_debug.c */
 522 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 523                           const char *where, uint32_t mark);
 524 #if WATCH_INACTIVE
 525 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 526 #else
 527 #define i915_verify_inactive(dev, file, line)
 528 #endif
 529 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 530 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 531                           const char *where, uint32_t mark);
 532 void i915_dump_lru(struct drm_device *dev, const char *where);
 533
 534 /* i915_suspend.c */
 535 extern int i915_save_state(struct drm_device *dev);
 536 extern int i915_restore_state(struct drm_device *dev);
 537
 538 /* i915_suspend.c */
 539 extern int i915_save_state(struct drm_device *dev);
 540 extern int i915_restore_state(struct drm_device *dev);
 541
 542 #ifdef CONFIG_ACPI
 543 /* i915_opregion.c */
 544 extern int intel_opregion_init(struct drm_device *dev);
 545 extern void intel_opregion_free(struct drm_device *dev);
 546 extern void opregion_asle_intr(struct drm_device *dev);
 547 extern void opregion_enable_asle(struct drm_device *dev);
 548 #else
 549 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
 550 static inline void intel_opregion_free(struct drm_device *dev) { return; }
 551 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 552 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 553 #endif
 554
 555 /**
 556  * Lock test for when it's just for synchronization of ring access.
 557  *
 558  * In that case, we don't need to do it when GEM is initialized as nobody else
 559  * has access to the ring.
 560  */
 561 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 562         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 563                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 564 } while (0)
 565
 566 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 567 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 568 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 569 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 570 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 571 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 572
 573 #define I915_VERBOSE 0
 574
 575 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 576                         volatile char *virt;
 577
 578 #define BEGIN_LP_RING(n) do {                           \
 579         if (I915_VERBOSE)                               \
 580                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 581         if (dev_priv->ring.space < (n)*4)               \
 582                 i915_wait_ring(dev, (n)*4, __func__);           \
 583         outcount = 0;                                   \
 584         outring = dev_priv->ring.tail;                  \
 585         ringmask = dev_priv->ring.tail_mask;            \
 586         virt = dev_priv->ring.virtual_start;            \
 587 } while (0)
 588
 589 #define OUT_RING(n) do {                                        \
 590         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 591         *(volatile unsigned int *)(virt + outring) = (n);       \
 592         outcount++;                                             \
 593         outring += 4;                                           \
 594         outring &= ringmask;                                    \
 595 } while (0)
 596
 597 #define ADVANCE_LP_RING() do {                                          \
 598         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 599         dev_priv->ring.tail = outring;                                  \
 600         dev_priv->ring.space -= outcount * 4;                           \
 601         I915_WRITE(PRB0_TAIL, outring);                 \
 602 } while(0)
 603
 604 /**
 605  * Reads a dword out of the status page, which is written to from the command
 606  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 607  * MI_STORE_DATA_IMM.
 608  *
 609  * The following dwords have a reserved meaning:
 610  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 611  * 0x04: ring 0 head pointer
 612  * 0x05: ring 1 head pointer (915-class)
 613  * 0x06: ring 2 head pointer (915-class)
 614  * 0x10-0x1b: Context status DWords (GM45)
 615  * 0x1f: Last written status offset. (GM45)
 616  *
 617  * The area from dword 0x20 to 0x3ff is available for driver usage.
 618  */
 619 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 620 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
 621 #define I915_GEM_HWS_INDEX              0x20
 622
 623 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 624
 625 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 626 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 627 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 628 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 629 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 630
 631 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 632 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 633 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 634 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 635                         (dev)->pci_device == 0x27AE)
 636 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 637                        (dev)->pci_device == 0x2982 || \
 638                        (dev)->pci_device == 0x2992 || \
 639                        (dev)->pci_device == 0x29A2 || \
 640                        (dev)->pci_device == 0x2A02 || \
 641                        (dev)->pci_device == 0x2A12 || \
 642                        (dev)->pci_device == 0x2A42 || \
 643                        (dev)->pci_device == 0x2E02 || \
 644                        (dev)->pci_device == 0x2E12 || \
 645                        (dev)->pci_device == 0x2E22)
 646
 647 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 648
 649 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 650
 651 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 652                      (dev)->pci_device == 0x2E12 || \
 653                      (dev)->pci_device == 0x2E22)
 654
 655 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 656                         (dev)->pci_device == 0x29B2 ||  \
 657                         (dev)->pci_device == 0x29D2)
 658
 659 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 660                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 661
 662 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 663                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
 664
 665 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 666
 667 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 668
 669 #endif