2 * C-Media CMI8788 driver - main driver module
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <sound/ac97_codec.h>
26 #include <sound/asoundef.h>
27 #include <sound/core.h>
28 #include <sound/info.h>
29 #include <sound/mpu401.h>
30 #include <sound/pcm.h>
34 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
35 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
36 MODULE_LICENSE("GPL v2");
38 #define DRIVER "oxygen"
40 static inline int oxygen_uart_input_ready(struct oxygen
*chip
)
42 return !(oxygen_read8(chip
, OXYGEN_MPU401
+ 1) & MPU401_RX_EMPTY
);
45 static void oxygen_read_uart(struct oxygen
*chip
)
47 if (unlikely(!oxygen_uart_input_ready(chip
))) {
48 /* no data, but read it anyway to clear the interrupt */
49 oxygen_read8(chip
, OXYGEN_MPU401
);
53 u8 data
= oxygen_read8(chip
, OXYGEN_MPU401
);
54 if (data
== MPU401_ACK
)
56 if (chip
->uart_input_count
>= ARRAY_SIZE(chip
->uart_input
))
57 chip
->uart_input_count
= 0;
58 chip
->uart_input
[chip
->uart_input_count
++] = data
;
59 } while (oxygen_uart_input_ready(chip
));
60 if (chip
->model
.uart_input
)
61 chip
->model
.uart_input(chip
);
64 static irqreturn_t
oxygen_interrupt(int dummy
, void *dev_id
)
66 struct oxygen
*chip
= dev_id
;
67 unsigned int status
, clear
, elapsed_streams
, i
;
69 status
= oxygen_read16(chip
, OXYGEN_INTERRUPT_STATUS
);
73 spin_lock(&chip
->reg_lock
);
75 clear
= status
& (OXYGEN_CHANNEL_A
|
78 OXYGEN_CHANNEL_SPDIF
|
79 OXYGEN_CHANNEL_MULTICH
|
81 OXYGEN_INT_SPDIF_IN_DETECT
|
85 if (clear
& OXYGEN_INT_SPDIF_IN_DETECT
)
86 chip
->interrupt_mask
&= ~OXYGEN_INT_SPDIF_IN_DETECT
;
87 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
,
88 chip
->interrupt_mask
& ~clear
);
89 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
,
90 chip
->interrupt_mask
);
93 elapsed_streams
= status
& chip
->pcm_running
;
95 spin_unlock(&chip
->reg_lock
);
97 for (i
= 0; i
< PCM_COUNT
; ++i
)
98 if ((elapsed_streams
& (1 << i
)) && chip
->streams
[i
])
99 snd_pcm_period_elapsed(chip
->streams
[i
]);
101 if (status
& OXYGEN_INT_SPDIF_IN_DETECT
) {
102 spin_lock(&chip
->reg_lock
);
103 i
= oxygen_read32(chip
, OXYGEN_SPDIF_CONTROL
);
104 if (i
& (OXYGEN_SPDIF_SENSE_INT
| OXYGEN_SPDIF_LOCK_INT
|
105 OXYGEN_SPDIF_RATE_INT
)) {
106 /* write the interrupt bit(s) to clear */
107 oxygen_write32(chip
, OXYGEN_SPDIF_CONTROL
, i
);
108 schedule_work(&chip
->spdif_input_bits_work
);
110 spin_unlock(&chip
->reg_lock
);
113 if (status
& OXYGEN_INT_GPIO
)
114 schedule_work(&chip
->gpio_work
);
116 if (status
& OXYGEN_INT_MIDI
) {
118 snd_mpu401_uart_interrupt(0, chip
->midi
->private_data
);
120 oxygen_read_uart(chip
);
123 if (status
& OXYGEN_INT_AC97
)
124 wake_up(&chip
->ac97_waitqueue
);
129 static void oxygen_spdif_input_bits_changed(struct work_struct
*work
)
131 struct oxygen
*chip
= container_of(work
, struct oxygen
,
132 spdif_input_bits_work
);
136 * This function gets called when there is new activity on the SPDIF
137 * input, or when we lose lock on the input signal, or when the rate
141 spin_lock_irq(&chip
->reg_lock
);
142 reg
= oxygen_read32(chip
, OXYGEN_SPDIF_CONTROL
);
143 if ((reg
& (OXYGEN_SPDIF_SENSE_STATUS
|
144 OXYGEN_SPDIF_LOCK_STATUS
))
145 == OXYGEN_SPDIF_SENSE_STATUS
) {
147 * If we detect activity on the SPDIF input but cannot lock to
148 * a signal, the clock bit is likely to be wrong.
150 reg
^= OXYGEN_SPDIF_IN_CLOCK_MASK
;
151 oxygen_write32(chip
, OXYGEN_SPDIF_CONTROL
, reg
);
152 spin_unlock_irq(&chip
->reg_lock
);
154 spin_lock_irq(&chip
->reg_lock
);
155 reg
= oxygen_read32(chip
, OXYGEN_SPDIF_CONTROL
);
156 if ((reg
& (OXYGEN_SPDIF_SENSE_STATUS
|
157 OXYGEN_SPDIF_LOCK_STATUS
))
158 == OXYGEN_SPDIF_SENSE_STATUS
) {
159 /* nothing detected with either clock; give up */
160 if ((reg
& OXYGEN_SPDIF_IN_CLOCK_MASK
)
161 == OXYGEN_SPDIF_IN_CLOCK_192
) {
163 * Reset clock to <= 96 kHz because this is
164 * more likely to be received next time.
166 reg
&= ~OXYGEN_SPDIF_IN_CLOCK_MASK
;
167 reg
|= OXYGEN_SPDIF_IN_CLOCK_96
;
168 oxygen_write32(chip
, OXYGEN_SPDIF_CONTROL
, reg
);
172 spin_unlock_irq(&chip
->reg_lock
);
174 if (chip
->controls
[CONTROL_SPDIF_INPUT_BITS
]) {
175 spin_lock_irq(&chip
->reg_lock
);
176 chip
->interrupt_mask
|= OXYGEN_INT_SPDIF_IN_DETECT
;
177 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
,
178 chip
->interrupt_mask
);
179 spin_unlock_irq(&chip
->reg_lock
);
182 * We don't actually know that any channel status bits have
183 * changed, but let's send a notification just to be sure.
185 snd_ctl_notify(chip
->card
, SNDRV_CTL_EVENT_MASK_VALUE
,
186 &chip
->controls
[CONTROL_SPDIF_INPUT_BITS
]->id
);
190 static void oxygen_gpio_changed(struct work_struct
*work
)
192 struct oxygen
*chip
= container_of(work
, struct oxygen
, gpio_work
);
194 if (chip
->model
.gpio_changed
)
195 chip
->model
.gpio_changed(chip
);
198 #ifdef CONFIG_PROC_FS
199 static void oxygen_proc_read(struct snd_info_entry
*entry
,
200 struct snd_info_buffer
*buffer
)
202 struct oxygen
*chip
= entry
->private_data
;
205 snd_iprintf(buffer
, "CMI8788\n\n");
206 for (i
= 0; i
< OXYGEN_IO_SIZE
; i
+= 0x10) {
207 snd_iprintf(buffer
, "%02x:", i
);
208 for (j
= 0; j
< 0x10; ++j
)
209 snd_iprintf(buffer
, " %02x", oxygen_read8(chip
, i
+ j
));
210 snd_iprintf(buffer
, "\n");
212 if (mutex_lock_interruptible(&chip
->mutex
) < 0)
214 if (chip
->has_ac97_0
) {
215 snd_iprintf(buffer
, "\nAC97\n");
216 for (i
= 0; i
< 0x80; i
+= 0x10) {
217 snd_iprintf(buffer
, "%02x:", i
);
218 for (j
= 0; j
< 0x10; j
+= 2)
219 snd_iprintf(buffer
, " %04x",
220 oxygen_read_ac97(chip
, 0, i
+ j
));
221 snd_iprintf(buffer
, "\n");
224 if (chip
->has_ac97_1
) {
225 snd_iprintf(buffer
, "\nAC97 2\n");
226 for (i
= 0; i
< 0x80; i
+= 0x10) {
227 snd_iprintf(buffer
, "%02x:", i
);
228 for (j
= 0; j
< 0x10; j
+= 2)
229 snd_iprintf(buffer
, " %04x",
230 oxygen_read_ac97(chip
, 1, i
+ j
));
231 snd_iprintf(buffer
, "\n");
234 mutex_unlock(&chip
->mutex
);
237 static void oxygen_proc_init(struct oxygen
*chip
)
239 struct snd_info_entry
*entry
;
241 if (!snd_card_proc_new(chip
->card
, "cmi8788", &entry
))
242 snd_info_set_text_ops(entry
, chip
, oxygen_proc_read
);
245 #define oxygen_proc_init(chip)
248 static const struct pci_device_id
*
249 oxygen_search_pci_id(struct oxygen
*chip
, const struct pci_device_id ids
[])
254 * Make sure the EEPROM pins are available, i.e., not used for SPI.
255 * (This function is called before we initialize or use SPI.)
257 oxygen_clear_bits8(chip
, OXYGEN_FUNCTION
,
258 OXYGEN_FUNCTION_ENABLE_SPI_4_5
);
260 * Read the subsystem device ID directly from the EEPROM, because the
261 * chip didn't if the first EEPROM word was overwritten.
263 subdevice
= oxygen_read_eeprom(chip
, 2);
264 /* use default ID if EEPROM is missing */
265 if (subdevice
== 0xffff)
268 * We use only the subsystem device ID for searching because it is
269 * unique even without the subsystem vendor ID, which may have been
270 * overwritten in the EEPROM.
272 for (; ids
->vendor
; ++ids
)
273 if (ids
->subdevice
== subdevice
&&
274 ids
->driver_data
!= BROKEN_EEPROM_DRIVER_DATA
)
279 static void oxygen_restore_eeprom(struct oxygen
*chip
,
280 const struct pci_device_id
*id
)
284 eeprom_id
= oxygen_read_eeprom(chip
, 0);
285 if (eeprom_id
!= OXYGEN_EEPROM_ID
&&
286 (eeprom_id
!= 0xffff || id
->subdevice
!= 0x8788)) {
288 * This function gets called only when a known card model has
289 * been detected, i.e., we know there is a valid subsystem
290 * product ID at index 2 in the EEPROM. Therefore, we have
291 * been able to deduce the correct subsystem vendor ID, and
292 * this is enough information to restore the original EEPROM
295 oxygen_write_eeprom(chip
, 1, id
->subvendor
);
296 oxygen_write_eeprom(chip
, 0, OXYGEN_EEPROM_ID
);
298 oxygen_set_bits8(chip
, OXYGEN_MISC
,
299 OXYGEN_MISC_WRITE_PCI_SUBID
);
300 pci_write_config_word(chip
->pci
, PCI_SUBSYSTEM_VENDOR_ID
,
302 pci_write_config_word(chip
->pci
, PCI_SUBSYSTEM_ID
,
304 oxygen_clear_bits8(chip
, OXYGEN_MISC
,
305 OXYGEN_MISC_WRITE_PCI_SUBID
);
307 snd_printk(KERN_INFO
"EEPROM ID restored\n");
311 static void configure_pcie_bridge(struct pci_dev
*pci
)
313 enum { PEX811X
, PI7C9X110
};
314 static const struct pci_device_id bridge_ids
[] = {
315 { PCI_VDEVICE(PLX
, 0x8111), .driver_data
= PEX811X
},
316 { PCI_VDEVICE(PLX
, 0x8112), .driver_data
= PEX811X
},
317 { PCI_DEVICE(0x12d8, 0xe110), .driver_data
= PI7C9X110
},
320 struct pci_dev
*bridge
;
321 const struct pci_device_id
*id
;
324 if (!pci
->bus
|| !pci
->bus
->self
)
326 bridge
= pci
->bus
->self
;
328 id
= pci_match_id(bridge_ids
, bridge
);
332 switch (id
->driver_data
) {
333 case PEX811X
: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
334 pci_read_config_dword(bridge
, 0x48, &tmp
);
335 tmp
|= 1; /* enable blind prefetching */
336 tmp
|= 1 << 11; /* enable beacon generation */
337 pci_write_config_dword(bridge
, 0x48, tmp
);
339 pci_write_config_dword(bridge
, 0x84, 0x0c);
340 pci_read_config_dword(bridge
, 0x88, &tmp
);
342 tmp
|= 2 << 27; /* set prefetch size to 128 bytes */
343 pci_write_config_dword(bridge
, 0x88, tmp
);
346 case PI7C9X110
: /* Pericom PI7C9X110 PCIe/PCI bridge */
347 pci_read_config_dword(bridge
, 0x40, &tmp
);
348 tmp
|= 1; /* park the PCI arbiter to the sound chip */
349 pci_write_config_dword(bridge
, 0x40, tmp
);
354 static void oxygen_init(struct oxygen
*chip
)
358 chip
->dac_routing
= 1;
359 for (i
= 0; i
< 8; ++i
)
360 chip
->dac_volume
[i
] = chip
->model
.dac_volume_min
;
362 chip
->spdif_playback_enable
= 1;
363 chip
->spdif_bits
= OXYGEN_SPDIF_C
| OXYGEN_SPDIF_ORIGINAL
|
364 (IEC958_AES1_CON_PCM_CODER
<< OXYGEN_SPDIF_CATEGORY_SHIFT
);
365 chip
->spdif_pcm_bits
= chip
->spdif_bits
;
367 if (oxygen_read8(chip
, OXYGEN_REVISION
) & OXYGEN_REVISION_2
)
372 if (chip
->revision
== 1)
373 oxygen_set_bits8(chip
, OXYGEN_MISC
,
374 OXYGEN_MISC_PCI_MEM_W_1_CLOCK
);
376 i
= oxygen_read16(chip
, OXYGEN_AC97_CONTROL
);
377 chip
->has_ac97_0
= (i
& OXYGEN_AC97_CODEC_0
) != 0;
378 chip
->has_ac97_1
= (i
& OXYGEN_AC97_CODEC_1
) != 0;
380 oxygen_write8_masked(chip
, OXYGEN_FUNCTION
,
381 OXYGEN_FUNCTION_RESET_CODEC
|
382 chip
->model
.function_flags
,
383 OXYGEN_FUNCTION_RESET_CODEC
|
384 OXYGEN_FUNCTION_2WIRE_SPI_MASK
|
385 OXYGEN_FUNCTION_ENABLE_SPI_4_5
);
386 oxygen_write8(chip
, OXYGEN_DMA_STATUS
, 0);
387 oxygen_write8(chip
, OXYGEN_DMA_PAUSE
, 0);
388 oxygen_write8(chip
, OXYGEN_PLAY_CHANNELS
,
389 OXYGEN_PLAY_CHANNELS_2
|
390 OXYGEN_DMA_A_BURST_8
|
391 OXYGEN_DMA_MULTICH_BURST_8
);
392 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
, 0);
393 oxygen_write8_masked(chip
, OXYGEN_MISC
,
394 chip
->model
.misc_flags
,
395 OXYGEN_MISC_WRITE_PCI_SUBID
|
396 OXYGEN_MISC_REC_C_FROM_SPDIF
|
397 OXYGEN_MISC_REC_B_FROM_AC97
|
398 OXYGEN_MISC_REC_A_FROM_MULTICH
|
400 oxygen_write8(chip
, OXYGEN_REC_FORMAT
,
401 (OXYGEN_FORMAT_16
<< OXYGEN_REC_FORMAT_A_SHIFT
) |
402 (OXYGEN_FORMAT_16
<< OXYGEN_REC_FORMAT_B_SHIFT
) |
403 (OXYGEN_FORMAT_16
<< OXYGEN_REC_FORMAT_C_SHIFT
));
404 oxygen_write8(chip
, OXYGEN_PLAY_FORMAT
,
405 (OXYGEN_FORMAT_16
<< OXYGEN_SPDIF_FORMAT_SHIFT
) |
406 (OXYGEN_FORMAT_16
<< OXYGEN_MULTICH_FORMAT_SHIFT
));
407 oxygen_write8(chip
, OXYGEN_REC_CHANNELS
, OXYGEN_REC_CHANNELS_2_2_2
);
408 oxygen_write16(chip
, OXYGEN_I2S_MULTICH_FORMAT
,
409 OXYGEN_RATE_48000
| chip
->model
.dac_i2s_format
|
410 OXYGEN_I2S_MCLK_256
| OXYGEN_I2S_BITS_16
|
411 OXYGEN_I2S_MASTER
| OXYGEN_I2S_BCLK_64
);
412 if (chip
->model
.device_config
& CAPTURE_0_FROM_I2S_1
)
413 oxygen_write16(chip
, OXYGEN_I2S_A_FORMAT
,
414 OXYGEN_RATE_48000
| chip
->model
.adc_i2s_format
|
415 OXYGEN_I2S_MCLK_256
| OXYGEN_I2S_BITS_16
|
416 OXYGEN_I2S_MASTER
| OXYGEN_I2S_BCLK_64
);
418 oxygen_write16(chip
, OXYGEN_I2S_A_FORMAT
,
419 OXYGEN_I2S_MASTER
| OXYGEN_I2S_MUTE_MCLK
);
420 if (chip
->model
.device_config
& (CAPTURE_0_FROM_I2S_2
|
421 CAPTURE_2_FROM_I2S_2
))
422 oxygen_write16(chip
, OXYGEN_I2S_B_FORMAT
,
423 OXYGEN_RATE_48000
| chip
->model
.adc_i2s_format
|
424 OXYGEN_I2S_MCLK_256
| OXYGEN_I2S_BITS_16
|
425 OXYGEN_I2S_MASTER
| OXYGEN_I2S_BCLK_64
);
427 oxygen_write16(chip
, OXYGEN_I2S_B_FORMAT
,
428 OXYGEN_I2S_MASTER
| OXYGEN_I2S_MUTE_MCLK
);
429 oxygen_write16(chip
, OXYGEN_I2S_C_FORMAT
,
430 OXYGEN_I2S_MASTER
| OXYGEN_I2S_MUTE_MCLK
);
431 oxygen_clear_bits32(chip
, OXYGEN_SPDIF_CONTROL
,
432 OXYGEN_SPDIF_OUT_ENABLE
|
433 OXYGEN_SPDIF_LOOPBACK
);
434 if (chip
->model
.device_config
& CAPTURE_1_FROM_SPDIF
)
435 oxygen_write32_masked(chip
, OXYGEN_SPDIF_CONTROL
,
436 OXYGEN_SPDIF_SENSE_MASK
|
437 OXYGEN_SPDIF_LOCK_MASK
|
438 OXYGEN_SPDIF_RATE_MASK
|
439 OXYGEN_SPDIF_LOCK_PAR
|
440 OXYGEN_SPDIF_IN_CLOCK_96
,
441 OXYGEN_SPDIF_SENSE_MASK
|
442 OXYGEN_SPDIF_LOCK_MASK
|
443 OXYGEN_SPDIF_RATE_MASK
|
444 OXYGEN_SPDIF_SENSE_PAR
|
445 OXYGEN_SPDIF_LOCK_PAR
|
446 OXYGEN_SPDIF_IN_CLOCK_MASK
);
448 oxygen_clear_bits32(chip
, OXYGEN_SPDIF_CONTROL
,
449 OXYGEN_SPDIF_SENSE_MASK
|
450 OXYGEN_SPDIF_LOCK_MASK
|
451 OXYGEN_SPDIF_RATE_MASK
);
452 oxygen_write32(chip
, OXYGEN_SPDIF_OUTPUT_BITS
, chip
->spdif_bits
);
453 oxygen_write16(chip
, OXYGEN_2WIRE_BUS_STATUS
,
454 OXYGEN_2WIRE_LENGTH_8
|
455 OXYGEN_2WIRE_INTERRUPT_MASK
|
456 OXYGEN_2WIRE_SPEED_STANDARD
);
457 oxygen_clear_bits8(chip
, OXYGEN_MPU401_CONTROL
, OXYGEN_MPU401_LOOPBACK
);
458 oxygen_write8(chip
, OXYGEN_GPI_INTERRUPT_MASK
, 0);
459 oxygen_write16(chip
, OXYGEN_GPIO_INTERRUPT_MASK
, 0);
460 oxygen_write16(chip
, OXYGEN_PLAY_ROUTING
,
461 OXYGEN_PLAY_MULTICH_I2S_DAC
|
462 OXYGEN_PLAY_SPDIF_SPDIF
|
463 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT
) |
464 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT
) |
465 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT
) |
466 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT
));
467 oxygen_write8(chip
, OXYGEN_REC_ROUTING
,
468 OXYGEN_REC_A_ROUTE_I2S_ADC_1
|
469 OXYGEN_REC_B_ROUTE_I2S_ADC_2
|
470 OXYGEN_REC_C_ROUTE_SPDIF
);
471 oxygen_write8(chip
, OXYGEN_ADC_MONITOR
, 0);
472 oxygen_write8(chip
, OXYGEN_A_MONITOR_ROUTING
,
473 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT
) |
474 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT
) |
475 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT
) |
476 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT
));
478 if (chip
->has_ac97_0
| chip
->has_ac97_1
)
479 oxygen_write8(chip
, OXYGEN_AC97_INTERRUPT_MASK
,
480 OXYGEN_AC97_INT_READ_DONE
|
481 OXYGEN_AC97_INT_WRITE_DONE
);
483 oxygen_write8(chip
, OXYGEN_AC97_INTERRUPT_MASK
, 0);
484 oxygen_write32(chip
, OXYGEN_AC97_OUT_CONFIG
, 0);
485 oxygen_write32(chip
, OXYGEN_AC97_IN_CONFIG
, 0);
486 if (!(chip
->has_ac97_0
| chip
->has_ac97_1
))
487 oxygen_set_bits16(chip
, OXYGEN_AC97_CONTROL
,
488 OXYGEN_AC97_CLOCK_DISABLE
);
489 if (!chip
->has_ac97_0
) {
490 oxygen_set_bits16(chip
, OXYGEN_AC97_CONTROL
,
491 OXYGEN_AC97_NO_CODEC_0
);
493 oxygen_write_ac97(chip
, 0, AC97_RESET
, 0);
495 oxygen_ac97_set_bits(chip
, 0, CM9780_GPIO_SETUP
,
496 CM9780_GPIO0IO
| CM9780_GPIO1IO
);
497 oxygen_ac97_set_bits(chip
, 0, CM9780_MIXER
,
498 CM9780_BSTSEL
| CM9780_STRO_MIC
|
499 CM9780_MIX2FR
| CM9780_PCBSW
);
500 oxygen_ac97_set_bits(chip
, 0, CM9780_JACK
,
501 CM9780_RSOE
| CM9780_CBOE
|
502 CM9780_SSOE
| CM9780_FROE
|
503 CM9780_MIC2MIC
| CM9780_LI2LI
);
504 oxygen_write_ac97(chip
, 0, AC97_MASTER
, 0x0000);
505 oxygen_write_ac97(chip
, 0, AC97_PC_BEEP
, 0x8000);
506 oxygen_write_ac97(chip
, 0, AC97_MIC
, 0x8808);
507 oxygen_write_ac97(chip
, 0, AC97_LINE
, 0x0808);
508 oxygen_write_ac97(chip
, 0, AC97_CD
, 0x8808);
509 oxygen_write_ac97(chip
, 0, AC97_VIDEO
, 0x8808);
510 oxygen_write_ac97(chip
, 0, AC97_AUX
, 0x8808);
511 oxygen_write_ac97(chip
, 0, AC97_REC_GAIN
, 0x8000);
512 oxygen_write_ac97(chip
, 0, AC97_CENTER_LFE_MASTER
, 0x8080);
513 oxygen_write_ac97(chip
, 0, AC97_SURROUND_MASTER
, 0x8080);
514 oxygen_ac97_clear_bits(chip
, 0, CM9780_GPIO_STATUS
,
516 /* power down unused ADCs and DACs */
517 oxygen_ac97_set_bits(chip
, 0, AC97_POWERDOWN
,
518 AC97_PD_PR0
| AC97_PD_PR1
);
519 oxygen_ac97_set_bits(chip
, 0, AC97_EXTENDED_STATUS
,
520 AC97_EA_PRI
| AC97_EA_PRJ
| AC97_EA_PRK
);
522 if (chip
->has_ac97_1
) {
523 oxygen_set_bits32(chip
, OXYGEN_AC97_OUT_CONFIG
,
524 OXYGEN_AC97_CODEC1_SLOT3
|
525 OXYGEN_AC97_CODEC1_SLOT4
);
526 oxygen_write_ac97(chip
, 1, AC97_RESET
, 0);
528 oxygen_write_ac97(chip
, 1, AC97_MASTER
, 0x0000);
529 oxygen_write_ac97(chip
, 1, AC97_HEADPHONE
, 0x8000);
530 oxygen_write_ac97(chip
, 1, AC97_PC_BEEP
, 0x8000);
531 oxygen_write_ac97(chip
, 1, AC97_MIC
, 0x8808);
532 oxygen_write_ac97(chip
, 1, AC97_LINE
, 0x8808);
533 oxygen_write_ac97(chip
, 1, AC97_CD
, 0x8808);
534 oxygen_write_ac97(chip
, 1, AC97_VIDEO
, 0x8808);
535 oxygen_write_ac97(chip
, 1, AC97_AUX
, 0x8808);
536 oxygen_write_ac97(chip
, 1, AC97_PCM
, 0x0808);
537 oxygen_write_ac97(chip
, 1, AC97_REC_SEL
, 0x0000);
538 oxygen_write_ac97(chip
, 1, AC97_REC_GAIN
, 0x0000);
539 oxygen_ac97_set_bits(chip
, 1, 0x6a, 0x0040);
543 static void oxygen_shutdown(struct oxygen
*chip
)
545 spin_lock_irq(&chip
->reg_lock
);
546 chip
->interrupt_mask
= 0;
547 chip
->pcm_running
= 0;
548 oxygen_write16(chip
, OXYGEN_DMA_STATUS
, 0);
549 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
, 0);
550 spin_unlock_irq(&chip
->reg_lock
);
553 static void oxygen_card_free(struct snd_card
*card
)
555 struct oxygen
*chip
= card
->private_data
;
557 oxygen_shutdown(chip
);
559 free_irq(chip
->irq
, chip
);
560 flush_work_sync(&chip
->spdif_input_bits_work
);
561 flush_work_sync(&chip
->gpio_work
);
562 chip
->model
.cleanup(chip
);
563 kfree(chip
->model_data
);
564 mutex_destroy(&chip
->mutex
);
565 pci_release_regions(chip
->pci
);
566 pci_disable_device(chip
->pci
);
569 int oxygen_pci_probe(struct pci_dev
*pci
, int index
, char *id
,
570 struct module
*owner
,
571 const struct pci_device_id
*ids
,
572 int (*get_model
)(struct oxygen
*chip
,
573 const struct pci_device_id
*id
577 struct snd_card
*card
;
579 const struct pci_device_id
*pci_id
;
582 err
= snd_card_create(index
, id
, owner
, sizeof(*chip
), &card
);
586 chip
= card
->private_data
;
590 spin_lock_init(&chip
->reg_lock
);
591 mutex_init(&chip
->mutex
);
592 INIT_WORK(&chip
->spdif_input_bits_work
,
593 oxygen_spdif_input_bits_changed
);
594 INIT_WORK(&chip
->gpio_work
, oxygen_gpio_changed
);
595 init_waitqueue_head(&chip
->ac97_waitqueue
);
597 err
= pci_enable_device(pci
);
601 err
= pci_request_regions(pci
, DRIVER
);
603 snd_printk(KERN_ERR
"cannot reserve PCI resources\n");
607 if (!(pci_resource_flags(pci
, 0) & IORESOURCE_IO
) ||
608 pci_resource_len(pci
, 0) < OXYGEN_IO_SIZE
) {
609 snd_printk(KERN_ERR
"invalid PCI I/O range\n");
611 goto err_pci_regions
;
613 chip
->addr
= pci_resource_start(pci
, 0);
615 pci_id
= oxygen_search_pci_id(chip
, ids
);
618 goto err_pci_regions
;
620 oxygen_restore_eeprom(chip
, pci_id
);
621 err
= get_model(chip
, pci_id
);
623 goto err_pci_regions
;
625 if (chip
->model
.model_data_size
) {
626 chip
->model_data
= kzalloc(chip
->model
.model_data_size
,
628 if (!chip
->model_data
) {
630 goto err_pci_regions
;
635 snd_card_set_dev(card
, &pci
->dev
);
636 card
->private_free
= oxygen_card_free
;
638 configure_pcie_bridge(pci
);
640 chip
->model
.init(chip
);
642 err
= request_irq(pci
->irq
, oxygen_interrupt
, IRQF_SHARED
,
645 snd_printk(KERN_ERR
"cannot grab interrupt %d\n", pci
->irq
);
648 chip
->irq
= pci
->irq
;
650 strcpy(card
->driver
, chip
->model
.chip
);
651 strcpy(card
->shortname
, chip
->model
.shortname
);
652 sprintf(card
->longname
, "%s (rev %u) at %#lx, irq %i",
653 chip
->model
.longname
, chip
->revision
, chip
->addr
, chip
->irq
);
654 strcpy(card
->mixername
, chip
->model
.chip
);
655 snd_component_add(card
, chip
->model
.chip
);
657 err
= oxygen_pcm_init(chip
);
661 err
= oxygen_mixer_init(chip
);
665 if (chip
->model
.device_config
& (MIDI_OUTPUT
| MIDI_INPUT
)) {
666 unsigned int info_flags
= MPU401_INFO_INTEGRATED
;
667 if (chip
->model
.device_config
& MIDI_OUTPUT
)
668 info_flags
|= MPU401_INFO_OUTPUT
;
669 if (chip
->model
.device_config
& MIDI_INPUT
)
670 info_flags
|= MPU401_INFO_INPUT
;
671 err
= snd_mpu401_uart_new(card
, 0, MPU401_HW_CMIPCI
,
672 chip
->addr
+ OXYGEN_MPU401
,
679 oxygen_proc_init(chip
);
681 spin_lock_irq(&chip
->reg_lock
);
682 if (chip
->model
.device_config
& CAPTURE_1_FROM_SPDIF
)
683 chip
->interrupt_mask
|= OXYGEN_INT_SPDIF_IN_DETECT
;
684 if (chip
->has_ac97_0
| chip
->has_ac97_1
)
685 chip
->interrupt_mask
|= OXYGEN_INT_AC97
;
686 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
, chip
->interrupt_mask
);
687 spin_unlock_irq(&chip
->reg_lock
);
689 err
= snd_card_register(card
);
693 pci_set_drvdata(pci
, card
);
697 pci_release_regions(pci
);
699 pci_disable_device(pci
);
704 EXPORT_SYMBOL(oxygen_pci_probe
);
706 void oxygen_pci_remove(struct pci_dev
*pci
)
708 snd_card_free(pci_get_drvdata(pci
));
709 pci_set_drvdata(pci
, NULL
);
711 EXPORT_SYMBOL(oxygen_pci_remove
);
714 int oxygen_pci_suspend(struct pci_dev
*pci
, pm_message_t state
)
716 struct snd_card
*card
= pci_get_drvdata(pci
);
717 struct oxygen
*chip
= card
->private_data
;
718 unsigned int i
, saved_interrupt_mask
;
720 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
722 for (i
= 0; i
< PCM_COUNT
; ++i
)
723 if (chip
->streams
[i
])
724 snd_pcm_suspend(chip
->streams
[i
]);
726 if (chip
->model
.suspend
)
727 chip
->model
.suspend(chip
);
729 spin_lock_irq(&chip
->reg_lock
);
730 saved_interrupt_mask
= chip
->interrupt_mask
;
731 chip
->interrupt_mask
= 0;
732 oxygen_write16(chip
, OXYGEN_DMA_STATUS
, 0);
733 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
, 0);
734 spin_unlock_irq(&chip
->reg_lock
);
736 synchronize_irq(chip
->irq
);
737 flush_work_sync(&chip
->spdif_input_bits_work
);
738 flush_work_sync(&chip
->gpio_work
);
739 chip
->interrupt_mask
= saved_interrupt_mask
;
741 pci_disable_device(pci
);
743 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
746 EXPORT_SYMBOL(oxygen_pci_suspend
);
748 static const u32 registers_to_restore
[OXYGEN_IO_SIZE
/ 32] = {
749 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
750 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
752 static const u32 ac97_registers_to_restore
[2][0x40 / 32] = {
753 { 0x18284fa2, 0x03060000 },
754 { 0x00007fa6, 0x00200000 }
757 static inline int is_bit_set(const u32
*bitmap
, unsigned int bit
)
759 return bitmap
[bit
/ 32] & (1 << (bit
& 31));
762 static void oxygen_restore_ac97(struct oxygen
*chip
, unsigned int codec
)
766 oxygen_write_ac97(chip
, codec
, AC97_RESET
, 0);
768 for (i
= 1; i
< 0x40; ++i
)
769 if (is_bit_set(ac97_registers_to_restore
[codec
], i
))
770 oxygen_write_ac97(chip
, codec
, i
* 2,
771 chip
->saved_ac97_registers
[codec
][i
]);
774 int oxygen_pci_resume(struct pci_dev
*pci
)
776 struct snd_card
*card
= pci_get_drvdata(pci
);
777 struct oxygen
*chip
= card
->private_data
;
780 pci_set_power_state(pci
, PCI_D0
);
781 pci_restore_state(pci
);
782 if (pci_enable_device(pci
) < 0) {
783 snd_printk(KERN_ERR
"cannot reenable device");
784 snd_card_disconnect(card
);
789 oxygen_write16(chip
, OXYGEN_DMA_STATUS
, 0);
790 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
, 0);
791 for (i
= 0; i
< OXYGEN_IO_SIZE
; ++i
)
792 if (is_bit_set(registers_to_restore
, i
))
793 oxygen_write8(chip
, i
, chip
->saved_registers
._8
[i
]);
794 if (chip
->has_ac97_0
)
795 oxygen_restore_ac97(chip
, 0);
796 if (chip
->has_ac97_1
)
797 oxygen_restore_ac97(chip
, 1);
799 if (chip
->model
.resume
)
800 chip
->model
.resume(chip
);
802 oxygen_write16(chip
, OXYGEN_INTERRUPT_MASK
, chip
->interrupt_mask
);
804 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
807 EXPORT_SYMBOL(oxygen_pci_resume
);
808 #endif /* CONFIG_PM */
810 void oxygen_pci_shutdown(struct pci_dev
*pci
)
812 struct snd_card
*card
= pci_get_drvdata(pci
);
813 struct oxygen
*chip
= card
->private_data
;
815 oxygen_shutdown(chip
);
816 chip
->model
.cleanup(chip
);
818 EXPORT_SYMBOL(oxygen_pci_shutdown
);