drivers/scsi/qla2xxx/qla_dbg.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 /*
   8  * Driver debug definitions.
   9  */
  10 /* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
  11 /* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
  12 /* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
  13 /* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
  14 /* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
  15 /* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
  16 /* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
  17 /* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
  18 /* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
  19 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
  20 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
  21 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
  22 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
  23 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
  24 /* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
  25
  26 /*
  27 * Macros use for debugging the driver.
  28 */
  29
  30 #define DEBUG(x)        do { if (ql2xextended_error_logging) { x; } } while (0)
  31
  32 #if defined(QL_DEBUG_LEVEL_1)
  33 #define DEBUG1(x)       do {x;} while (0)
  34 #else
  35 #define DEBUG1(x)       do {} while (0)
  36 #endif
  37
  38 #define DEBUG2(x)       do { if (ql2xextended_error_logging) { x; } } while (0)
  39 #define DEBUG2_3(x)     do { if (ql2xextended_error_logging) { x; } } while (0)
  40 #define DEBUG2_3_11(x)  do { if (ql2xextended_error_logging) { x; } } while (0)
  41 #define DEBUG2_9_10(x)  do { if (ql2xextended_error_logging) { x; } } while (0)
  42 #define DEBUG2_11(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  43 #define DEBUG2_13(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  44
  45 #if defined(QL_DEBUG_LEVEL_3)
  46 #define DEBUG3(x)       do {x;} while (0)
  47 #define DEBUG3_11(x)    do {x;} while (0)
  48 #else
  49 #define DEBUG3(x)       do {} while (0)
  50 #endif
  51
  52 #if defined(QL_DEBUG_LEVEL_4)
  53 #define DEBUG4(x)       do {x;} while (0)
  54 #else
  55 #define DEBUG4(x)       do {} while (0)
  56 #endif
  57
  58 #if defined(QL_DEBUG_LEVEL_5)
  59 #define DEBUG5(x)          do {x;} while (0)
  60 #else
  61 #define DEBUG5(x)       do {} while (0)
  62 #endif
  63
  64 #if defined(QL_DEBUG_LEVEL_7)
  65 #define DEBUG7(x)          do {x;} while (0)
  66 #else
  67 #define DEBUG7(x)          do {} while (0)
  68 #endif
  69
  70 #if defined(QL_DEBUG_LEVEL_9)
  71 #define DEBUG9(x)       do {x;} while (0)
  72 #define DEBUG9_10(x)    do {x;} while (0)
  73 #else
  74 #define DEBUG9(x)       do {} while (0)
  75 #endif
  76
  77 #if defined(QL_DEBUG_LEVEL_10)
  78 #define DEBUG10(x)      do {x;} while (0)
  79 #define DEBUG9_10(x)    do {x;} while (0)
  80 #else
  81 #define DEBUG10(x)      do {} while (0)
  82   #if !defined(DEBUG9_10)
  83   #define DEBUG9_10(x)  do {} while (0)
  84   #endif
  85 #endif
  86
  87 #if defined(QL_DEBUG_LEVEL_11)
  88 #define DEBUG11(x)      do{x;} while(0)
  89 #if !defined(DEBUG3_11)
  90 #define DEBUG3_11(x)    do{x;} while(0)
  91 #endif
  92 #else
  93 #define DEBUG11(x)      do{} while(0)
  94   #if !defined(QL_DEBUG_LEVEL_3)
  95   #define DEBUG3_11(x)  do{} while(0)
  96   #endif
  97 #endif
  98
  99 #if defined(QL_DEBUG_LEVEL_12)
 100 #define DEBUG12(x)      do {x;} while (0)
 101 #else
 102 #define DEBUG12(x)      do {} while (0)
 103 #endif
 104
 105 #if defined(QL_DEBUG_LEVEL_13)
 106 #define DEBUG13(x)      do {x;} while (0)
 107 #else
 108 #define DEBUG13(x)      do {} while (0)
 109 #endif
 110
 111 #if defined(QL_DEBUG_LEVEL_14)
 112 #define DEBUG14(x)      do {x;} while (0)
 113 #else
 114 #define DEBUG14(x)      do {} while (0)
 115 #endif
 116
 117 #if defined(QL_DEBUG_LEVEL_15)
 118 #define DEBUG15(x)      do {x;} while (0)
 119 #else
 120 #define DEBUG15(x)      do {} while (0)
 121 #endif
 122
 123 /*
 124  * Firmware Dump structure definition
 125  */
 126
 127 struct qla2300_fw_dump {
 128         uint16_t hccr;
 129         uint16_t pbiu_reg[8];
 130         uint16_t risc_host_reg[8];
 131         uint16_t mailbox_reg[32];
 132         uint16_t resp_dma_reg[32];
 133         uint16_t dma_reg[48];
 134         uint16_t risc_hdw_reg[16];
 135         uint16_t risc_gp0_reg[16];
 136         uint16_t risc_gp1_reg[16];
 137         uint16_t risc_gp2_reg[16];
 138         uint16_t risc_gp3_reg[16];
 139         uint16_t risc_gp4_reg[16];
 140         uint16_t risc_gp5_reg[16];
 141         uint16_t risc_gp6_reg[16];
 142         uint16_t risc_gp7_reg[16];
 143         uint16_t frame_buf_hdw_reg[64];
 144         uint16_t fpm_b0_reg[64];
 145         uint16_t fpm_b1_reg[64];
 146         uint16_t risc_ram[0xf800];
 147         uint16_t stack_ram[0x1000];
 148         uint16_t data_ram[1];
 149 };
 150
 151 struct qla2100_fw_dump {
 152         uint16_t hccr;
 153         uint16_t pbiu_reg[8];
 154         uint16_t mailbox_reg[32];
 155         uint16_t dma_reg[48];
 156         uint16_t risc_hdw_reg[16];
 157         uint16_t risc_gp0_reg[16];
 158         uint16_t risc_gp1_reg[16];
 159         uint16_t risc_gp2_reg[16];
 160         uint16_t risc_gp3_reg[16];
 161         uint16_t risc_gp4_reg[16];
 162         uint16_t risc_gp5_reg[16];
 163         uint16_t risc_gp6_reg[16];
 164         uint16_t risc_gp7_reg[16];
 165         uint16_t frame_buf_hdw_reg[16];
 166         uint16_t fpm_b0_reg[64];
 167         uint16_t fpm_b1_reg[64];
 168         uint16_t risc_ram[0xf000];
 169 };
 170
 171 struct qla24xx_fw_dump {
 172         uint32_t host_status;
 173         uint32_t host_reg[32];
 174         uint32_t shadow_reg[7];
 175         uint16_t mailbox_reg[32];
 176         uint32_t xseq_gp_reg[128];
 177         uint32_t xseq_0_reg[16];
 178         uint32_t xseq_1_reg[16];
 179         uint32_t rseq_gp_reg[128];
 180         uint32_t rseq_0_reg[16];
 181         uint32_t rseq_1_reg[16];
 182         uint32_t rseq_2_reg[16];
 183         uint32_t cmd_dma_reg[16];
 184         uint32_t req0_dma_reg[15];
 185         uint32_t resp0_dma_reg[15];
 186         uint32_t req1_dma_reg[15];
 187         uint32_t xmt0_dma_reg[32];
 188         uint32_t xmt1_dma_reg[32];
 189         uint32_t xmt2_dma_reg[32];
 190         uint32_t xmt3_dma_reg[32];
 191         uint32_t xmt4_dma_reg[32];
 192         uint32_t xmt_data_dma_reg[16];
 193         uint32_t rcvt0_data_dma_reg[32];
 194         uint32_t rcvt1_data_dma_reg[32];
 195         uint32_t risc_gp_reg[128];
 196         uint32_t lmc_reg[112];
 197         uint32_t fpm_hdw_reg[192];
 198         uint32_t fb_hdw_reg[176];
 199         uint32_t code_ram[0x2000];
 200         uint32_t ext_mem[1];
 201 };
 202
 203 struct qla25xx_fw_dump {
 204         uint32_t host_status;
 205         uint32_t host_risc_reg[32];
 206         uint32_t pcie_regs[4];
 207         uint32_t host_reg[32];
 208         uint32_t shadow_reg[11];
 209         uint32_t risc_io_reg;
 210         uint16_t mailbox_reg[32];
 211         uint32_t xseq_gp_reg[128];
 212         uint32_t xseq_0_reg[48];
 213         uint32_t xseq_1_reg[16];
 214         uint32_t rseq_gp_reg[128];
 215         uint32_t rseq_0_reg[32];
 216         uint32_t rseq_1_reg[16];
 217         uint32_t rseq_2_reg[16];
 218         uint32_t aseq_gp_reg[128];
 219         uint32_t aseq_0_reg[32];
 220         uint32_t aseq_1_reg[16];
 221         uint32_t aseq_2_reg[16];
 222         uint32_t cmd_dma_reg[16];
 223         uint32_t req0_dma_reg[15];
 224         uint32_t resp0_dma_reg[15];
 225         uint32_t req1_dma_reg[15];
 226         uint32_t xmt0_dma_reg[32];
 227         uint32_t xmt1_dma_reg[32];
 228         uint32_t xmt2_dma_reg[32];
 229         uint32_t xmt3_dma_reg[32];
 230         uint32_t xmt4_dma_reg[32];
 231         uint32_t xmt_data_dma_reg[16];
 232         uint32_t rcvt0_data_dma_reg[32];
 233         uint32_t rcvt1_data_dma_reg[32];
 234         uint32_t risc_gp_reg[128];
 235         uint32_t lmc_reg[128];
 236         uint32_t fpm_hdw_reg[192];
 237         uint32_t fb_hdw_reg[192];
 238         uint32_t code_ram[0x2000];
 239         uint32_t ext_mem[1];
 240 };
 241
 242 #define EFT_NUM_BUFFERS         4
 243 #define EFT_BYTES_PER_BUFFER    0x4000
 244 #define EFT_SIZE                ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
 245
 246 #define FCE_NUM_BUFFERS         64
 247 #define FCE_BYTES_PER_BUFFER    0x400
 248 #define FCE_SIZE                ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
 249 #define fce_calc_size(b)        ((FCE_BYTES_PER_BUFFER) * (b))
 250
 251 struct qla2xxx_fce_chain {
 252         uint32_t type;
 253         uint32_t chain_size;
 254
 255         uint32_t size;
 256         uint32_t addr_l;
 257         uint32_t addr_h;
 258         uint32_t eregs[8];
 259 };
 260
 261 #define DUMP_CHAIN_VARIANT      0x80000000
 262 #define DUMP_CHAIN_FCE          0x7FFFFAF0
 263 #define DUMP_CHAIN_LAST         0x80000000
 264
 265 struct qla2xxx_fw_dump {
 266         uint8_t signature[4];
 267         uint32_t version;
 268
 269         uint32_t fw_major_version;
 270         uint32_t fw_minor_version;
 271         uint32_t fw_subminor_version;
 272         uint32_t fw_attributes;
 273
 274         uint32_t vendor;
 275         uint32_t device;
 276         uint32_t subsystem_vendor;
 277         uint32_t subsystem_device;
 278
 279         uint32_t fixed_size;
 280         uint32_t mem_size;
 281         uint32_t req_q_size;
 282         uint32_t rsp_q_size;
 283
 284         uint32_t eft_size;
 285         uint32_t eft_addr_l;
 286         uint32_t eft_addr_h;
 287
 288         uint32_t header_size;
 289
 290         union {
 291                 struct qla2100_fw_dump isp21;
 292                 struct qla2300_fw_dump isp23;
 293                 struct qla24xx_fw_dump isp24;
 294                 struct qla25xx_fw_dump isp25;
 295         } isp;
 296 };