2 * Intel Medfield MSIC GPIO driver>
3 * Copyright (c) 2011, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Based on intel_pmic_gpio.c
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/gpio.h>
29 #include <linux/platform_device.h>
30 #include <linux/mfd/intel_msic.h>
32 /* the offset for the mapping of global gpio pin to irq */
33 #define MSIC_GPIO_IRQ_OFFSET 0x100
35 #define MSIC_GPIO_DIR_IN 0
36 #define MSIC_GPIO_DIR_OUT BIT(5)
37 #define MSIC_GPIO_TRIG_FALL BIT(1)
38 #define MSIC_GPIO_TRIG_RISE BIT(2)
40 /* masks for msic gpio output GPIOxxxxCTLO registers */
41 #define MSIC_GPIO_DIR_MASK BIT(5)
42 #define MSIC_GPIO_DRV_MASK BIT(4)
43 #define MSIC_GPIO_REN_MASK BIT(3)
44 #define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1))
45 #define MSIC_GPIO_DOUT_MASK BIT(0)
47 /* masks for msic gpio input GPIOxxxxCTLI registers */
48 #define MSIC_GPIO_GLBYP_MASK BIT(5)
49 #define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3))
50 #define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1))
51 #define MSIC_GPIO_DIN_MASK BIT(0)
53 #define MSIC_NUM_GPIO 24
56 struct platform_device
*pdev
;
58 struct gpio_chip chip
;
61 unsigned long trig_change_mask
;
66 * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
67 * Both the high and low voltage gpios are divided in two banks.
68 * GPIOs are numbered with GPIO0LV0 as gpio_base in the following order:
69 * GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base
70 * GPIO1LV0..GPIO1LV7: low voltage, bank 1, gpio_base + 8
71 * GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16
72 * GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20
75 static int msic_gpio_to_ireg(unsigned offset
)
77 if (offset
>= MSIC_NUM_GPIO
)
81 return INTEL_MSIC_GPIO0LV0CTLI
- offset
;
83 return INTEL_MSIC_GPIO1LV0CTLI
- offset
+ 8;
85 return INTEL_MSIC_GPIO0HV0CTLI
- offset
+ 16;
87 return INTEL_MSIC_GPIO1HV0CTLI
- offset
+ 20;
90 static int msic_gpio_to_oreg(unsigned offset
)
92 if (offset
>= MSIC_NUM_GPIO
)
96 return INTEL_MSIC_GPIO0LV0CTLO
- offset
;
98 return INTEL_MSIC_GPIO1LV0CTLO
- offset
+ 8;
100 return INTEL_MSIC_GPIO0HV0CTLO
- offset
+ 16;
102 return INTEL_MSIC_GPIO1HV0CTLO
- offset
+ 20;
105 static int msic_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
109 reg
= msic_gpio_to_oreg(offset
);
113 return intel_msic_reg_update(reg
, MSIC_GPIO_DIR_IN
, MSIC_GPIO_DIR_MASK
);
116 static int msic_gpio_direction_output(struct gpio_chip
*chip
,
117 unsigned offset
, int value
)
122 value
= (!!value
) | MSIC_GPIO_DIR_OUT
;
123 mask
= MSIC_GPIO_DIR_MASK
| MSIC_GPIO_DOUT_MASK
;
125 reg
= msic_gpio_to_oreg(offset
);
129 return intel_msic_reg_update(reg
, value
, mask
);
132 static int msic_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
138 reg
= msic_gpio_to_ireg(offset
);
142 ret
= intel_msic_reg_read(reg
, &r
);
146 return r
& MSIC_GPIO_DIN_MASK
;
149 static void msic_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
153 reg
= msic_gpio_to_oreg(offset
);
157 intel_msic_reg_update(reg
, !!value
, MSIC_GPIO_DOUT_MASK
);
161 * This is called from genirq with mg->buslock locked and
162 * irq_desc->lock held. We can not access the scu bus here, so we
163 * store the change and update in the bus_sync_unlock() function below
165 static int msic_irq_type(struct irq_data
*data
, unsigned type
)
167 struct msic_gpio
*mg
= irq_data_get_irq_chip_data(data
);
168 u32 gpio
= data
->irq
- mg
->irq_base
;
170 if (gpio
>= mg
->chip
.ngpio
)
173 /* mark for which gpio the trigger changed, protected by buslock */
174 mg
->trig_change_mask
|= (1 << gpio
);
175 mg
->trig_type
= type
;
180 static int msic_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
182 struct msic_gpio
*mg
= container_of(chip
, struct msic_gpio
, chip
);
183 return mg
->irq_base
+ offset
;
186 static void msic_bus_lock(struct irq_data
*data
)
188 struct msic_gpio
*mg
= irq_data_get_irq_chip_data(data
);
189 mutex_lock(&mg
->buslock
);
192 static void msic_bus_sync_unlock(struct irq_data
*data
)
194 struct msic_gpio
*mg
= irq_data_get_irq_chip_data(data
);
199 /* We can only get one change at a time as the buslock covers the
200 entire transaction. The irq_desc->lock is dropped before we are
201 called but that is fine */
202 if (mg
->trig_change_mask
) {
203 offset
= __ffs(mg
->trig_change_mask
);
205 reg
= msic_gpio_to_ireg(offset
);
209 if (mg
->trig_type
& IRQ_TYPE_EDGE_RISING
)
210 trig
|= MSIC_GPIO_TRIG_RISE
;
211 if (mg
->trig_type
& IRQ_TYPE_EDGE_FALLING
)
212 trig
|= MSIC_GPIO_TRIG_FALL
;
214 intel_msic_reg_update(reg
, trig
, MSIC_GPIO_INTCNT_MASK
);
215 mg
->trig_change_mask
= 0;
218 mutex_unlock(&mg
->buslock
);
221 /* Firmware does all the masking and unmasking for us, no masking here. */
222 static void msic_irq_unmask(struct irq_data
*data
) { }
224 static void msic_irq_mask(struct irq_data
*data
) { }
226 static struct irq_chip msic_irqchip
= {
228 .irq_mask
= msic_irq_mask
,
229 .irq_unmask
= msic_irq_unmask
,
230 .irq_set_type
= msic_irq_type
,
231 .irq_bus_lock
= msic_bus_lock
,
232 .irq_bus_sync_unlock
= msic_bus_sync_unlock
,
235 static void msic_gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
237 struct irq_data
*data
= irq_desc_get_irq_data(desc
);
238 struct msic_gpio
*mg
= irq_data_get_irq_handler_data(data
);
239 struct irq_chip
*chip
= irq_data_get_irq_chip(data
);
240 struct intel_msic
*msic
= pdev_to_intel_msic(mg
->pdev
);
244 unsigned long pending
= 0;
246 for (i
= 0; i
< (mg
->chip
.ngpio
/ BITS_PER_BYTE
); i
++) {
247 intel_msic_irq_read(msic
, INTEL_MSIC_GPIO0LVIRQ
+ i
, &pin
);
251 for_each_set_bit(bitnr
, &pending
, BITS_PER_BYTE
)
252 generic_handle_irq(mg
->irq_base
+
253 (i
* BITS_PER_BYTE
) + bitnr
);
259 static int platform_msic_gpio_probe(struct platform_device
*pdev
)
261 struct device
*dev
= &pdev
->dev
;
262 struct intel_msic_gpio_pdata
*pdata
= dev
->platform_data
;
263 struct msic_gpio
*mg
;
264 int irq
= platform_get_irq(pdev
, 0);
269 dev_err(dev
, "no IRQ line\n");
273 if (!pdata
|| !pdata
->gpio_base
) {
274 dev_err(dev
, "incorrect or missing platform data\n");
278 mg
= kzalloc(sizeof(*mg
), GFP_KERNEL
);
282 dev_set_drvdata(dev
, mg
);
286 mg
->irq_base
= pdata
->gpio_base
+ MSIC_GPIO_IRQ_OFFSET
;
287 mg
->chip
.label
= "msic_gpio";
288 mg
->chip
.direction_input
= msic_gpio_direction_input
;
289 mg
->chip
.direction_output
= msic_gpio_direction_output
;
290 mg
->chip
.get
= msic_gpio_get
;
291 mg
->chip
.set
= msic_gpio_set
;
292 mg
->chip
.to_irq
= msic_gpio_to_irq
;
293 mg
->chip
.base
= pdata
->gpio_base
;
294 mg
->chip
.ngpio
= MSIC_NUM_GPIO
;
295 mg
->chip
.can_sleep
= 1;
298 mutex_init(&mg
->buslock
);
300 retval
= gpiochip_add(&mg
->chip
);
302 dev_err(dev
, "Adding MSIC gpio chip failed\n");
306 for (i
= 0; i
< mg
->chip
.ngpio
; i
++) {
307 irq_set_chip_data(i
+ mg
->irq_base
, mg
);
308 irq_set_chip_and_handler_name(i
+ mg
->irq_base
,
313 irq_set_chained_handler(mg
->irq
, msic_gpio_irq_handler
);
314 irq_set_handler_data(mg
->irq
, mg
);
322 static struct platform_driver platform_msic_gpio_driver
= {
325 .owner
= THIS_MODULE
,
327 .probe
= platform_msic_gpio_probe
,
330 static int __init
platform_msic_gpio_init(void)
332 return platform_driver_register(&platform_msic_gpio_driver
);
335 subsys_initcall(platform_msic_gpio_init
);
337 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
338 MODULE_DESCRIPTION("Intel Medfield MSIC GPIO driver");
339 MODULE_LICENSE("GPL v2");