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net-forcedeth: fix possible stats inaccuracies on 32b hosts
[linux-2.6/cjktty.git] / drivers / net / ethernet / nvidia / forcedeth.c
blob49905347e0b273a11fab43e7674a4e064f2037f3
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/u64_stats_sync.h>
69 #include <linux/io.h>
70
71 #include <asm/irq.h>
72 #include <asm/system.h>
73
74 #define TX_WORK_PER_LOOP 64
75 #define RX_WORK_PER_LOOP 64
76
77 /*
78 * Hardware access:
79 */
80
81 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
82 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
83 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
84 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
85 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
86 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
87 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
88 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
89 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
90 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
91 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
92 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
93 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
94 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
95 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
96 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
97 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
98 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
99 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
100 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
101 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
102 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
103 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
104 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
105 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
106 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
107 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
108
109 enum {
110 NvRegIrqStatus = 0x000,
111 #define NVREG_IRQSTAT_MIIEVENT 0x040
112 #define NVREG_IRQSTAT_MASK 0x83ff
113 NvRegIrqMask = 0x004,
114 #define NVREG_IRQ_RX_ERROR 0x0001
115 #define NVREG_IRQ_RX 0x0002
116 #define NVREG_IRQ_RX_NOBUF 0x0004
117 #define NVREG_IRQ_TX_ERR 0x0008
118 #define NVREG_IRQ_TX_OK 0x0010
119 #define NVREG_IRQ_TIMER 0x0020
120 #define NVREG_IRQ_LINK 0x0040
121 #define NVREG_IRQ_RX_FORCED 0x0080
122 #define NVREG_IRQ_TX_FORCED 0x0100
123 #define NVREG_IRQ_RECOVER_ERROR 0x8200
124 #define NVREG_IRQMASK_THROUGHPUT 0x00df
125 #define NVREG_IRQMASK_CPU 0x0060
126 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
127 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
128 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
129
130 NvRegUnknownSetupReg6 = 0x008,
131 #define NVREG_UNKSETUP6_VAL 3
132
133 /*
134 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
135 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
136 */
137 NvRegPollingInterval = 0x00c,
138 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
139 #define NVREG_POLL_DEFAULT_CPU 13
140 NvRegMSIMap0 = 0x020,
141 NvRegMSIMap1 = 0x024,
142 NvRegMSIIrqMask = 0x030,
143 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
144 NvRegMisc1 = 0x080,
145 #define NVREG_MISC1_PAUSE_TX 0x01
146 #define NVREG_MISC1_HD 0x02
147 #define NVREG_MISC1_FORCE 0x3b0f3c
148
149 NvRegMacReset = 0x34,
150 #define NVREG_MAC_RESET_ASSERT 0x0F3
151 NvRegTransmitterControl = 0x084,
152 #define NVREG_XMITCTL_START 0x01
153 #define NVREG_XMITCTL_MGMT_ST 0x40000000
154 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
155 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
156 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
157 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
158 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
159 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
160 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
161 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
162 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
163 #define NVREG_XMITCTL_DATA_START 0x00100000
164 #define NVREG_XMITCTL_DATA_READY 0x00010000
165 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
166 NvRegTransmitterStatus = 0x088,
167 #define NVREG_XMITSTAT_BUSY 0x01
168
169 NvRegPacketFilterFlags = 0x8c,
170 #define NVREG_PFF_PAUSE_RX 0x08
171 #define NVREG_PFF_ALWAYS 0x7F0000
172 #define NVREG_PFF_PROMISC 0x80
173 #define NVREG_PFF_MYADDR 0x20
174 #define NVREG_PFF_LOOPBACK 0x10
175
176 NvRegOffloadConfig = 0x90,
177 #define NVREG_OFFLOAD_HOMEPHY 0x601
178 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
179 NvRegReceiverControl = 0x094,
180 #define NVREG_RCVCTL_START 0x01
181 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
182 NvRegReceiverStatus = 0x98,
183 #define NVREG_RCVSTAT_BUSY 0x01
184
185 NvRegSlotTime = 0x9c,
186 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
187 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
188 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
189 #define NVREG_SLOTTIME_HALF 0x0000ff00
190 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
191 #define NVREG_SLOTTIME_MASK 0x000000ff
192
193 NvRegTxDeferral = 0xA0,
194 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
195 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
196 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
198 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
199 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
200 NvRegRxDeferral = 0xA4,
201 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
202 NvRegMacAddrA = 0xA8,
203 NvRegMacAddrB = 0xAC,
204 NvRegMulticastAddrA = 0xB0,
205 #define NVREG_MCASTADDRA_FORCE 0x01
206 NvRegMulticastAddrB = 0xB4,
207 NvRegMulticastMaskA = 0xB8,
208 #define NVREG_MCASTMASKA_NONE 0xffffffff
209 NvRegMulticastMaskB = 0xBC,
210 #define NVREG_MCASTMASKB_NONE 0xffff
211
212 NvRegPhyInterface = 0xC0,
213 #define PHY_RGMII 0x10000000
214 NvRegBackOffControl = 0xC4,
215 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
216 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
217 #define NVREG_BKOFFCTRL_SELECT 24
218 #define NVREG_BKOFFCTRL_GEAR 12
219
220 NvRegTxRingPhysAddr = 0x100,
221 NvRegRxRingPhysAddr = 0x104,
222 NvRegRingSizes = 0x108,
223 #define NVREG_RINGSZ_TXSHIFT 0
224 #define NVREG_RINGSZ_RXSHIFT 16
225 NvRegTransmitPoll = 0x10c,
226 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
227 NvRegLinkSpeed = 0x110,
228 #define NVREG_LINKSPEED_FORCE 0x10000
229 #define NVREG_LINKSPEED_10 1000
230 #define NVREG_LINKSPEED_100 100
231 #define NVREG_LINKSPEED_1000 50
232 #define NVREG_LINKSPEED_MASK (0xFFF)
233 NvRegUnknownSetupReg5 = 0x130,
234 #define NVREG_UNKSETUP5_BIT31 (1<<31)
235 NvRegTxWatermark = 0x13c,
236 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
237 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
238 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
239 NvRegTxRxControl = 0x144,
240 #define NVREG_TXRXCTL_KICK 0x0001
241 #define NVREG_TXRXCTL_BIT1 0x0002
242 #define NVREG_TXRXCTL_BIT2 0x0004
243 #define NVREG_TXRXCTL_IDLE 0x0008
244 #define NVREG_TXRXCTL_RESET 0x0010
245 #define NVREG_TXRXCTL_RXCHECK 0x0400
246 #define NVREG_TXRXCTL_DESC_1 0
247 #define NVREG_TXRXCTL_DESC_2 0x002100
248 #define NVREG_TXRXCTL_DESC_3 0xc02200
249 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
250 #define NVREG_TXRXCTL_VLANINS 0x00080
251 NvRegTxRingPhysAddrHigh = 0x148,
252 NvRegRxRingPhysAddrHigh = 0x14C,
253 NvRegTxPauseFrame = 0x170,
254 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
257 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
258 NvRegTxPauseFrameLimit = 0x174,
259 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
260 NvRegMIIStatus = 0x180,
261 #define NVREG_MIISTAT_ERROR 0x0001
262 #define NVREG_MIISTAT_LINKCHANGE 0x0008
263 #define NVREG_MIISTAT_MASK_RW 0x0007
264 #define NVREG_MIISTAT_MASK_ALL 0x000f
265 NvRegMIIMask = 0x184,
266 #define NVREG_MII_LINKCHANGE 0x0008
267
268 NvRegAdapterControl = 0x188,
269 #define NVREG_ADAPTCTL_START 0x02
270 #define NVREG_ADAPTCTL_LINKUP 0x04
271 #define NVREG_ADAPTCTL_PHYVALID 0x40000
272 #define NVREG_ADAPTCTL_RUNNING 0x100000
273 #define NVREG_ADAPTCTL_PHYSHIFT 24
274 NvRegMIISpeed = 0x18c,
275 #define NVREG_MIISPEED_BIT8 (1<<8)
276 #define NVREG_MIIDELAY 5
277 NvRegMIIControl = 0x190,
278 #define NVREG_MIICTL_INUSE 0x08000
279 #define NVREG_MIICTL_WRITE 0x00400
280 #define NVREG_MIICTL_ADDRSHIFT 5
281 NvRegMIIData = 0x194,
282 NvRegTxUnicast = 0x1a0,
283 NvRegTxMulticast = 0x1a4,
284 NvRegTxBroadcast = 0x1a8,
285 NvRegWakeUpFlags = 0x200,
286 #define NVREG_WAKEUPFLAGS_VAL 0x7770
287 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
288 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
289 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
290 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
291 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
292 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
293 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
294 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
295 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
296 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
297
298 NvRegMgmtUnitGetVersion = 0x204,
299 #define NVREG_MGMTUNITGETVERSION 0x01
300 NvRegMgmtUnitVersion = 0x208,
301 #define NVREG_MGMTUNITVERSION 0x08
302 NvRegPowerCap = 0x268,
303 #define NVREG_POWERCAP_D3SUPP (1<<30)
304 #define NVREG_POWERCAP_D2SUPP (1<<26)
305 #define NVREG_POWERCAP_D1SUPP (1<<25)
306 NvRegPowerState = 0x26c,
307 #define NVREG_POWERSTATE_POWEREDUP 0x8000
308 #define NVREG_POWERSTATE_VALID 0x0100
309 #define NVREG_POWERSTATE_MASK 0x0003
310 #define NVREG_POWERSTATE_D0 0x0000
311 #define NVREG_POWERSTATE_D1 0x0001
312 #define NVREG_POWERSTATE_D2 0x0002
313 #define NVREG_POWERSTATE_D3 0x0003
314 NvRegMgmtUnitControl = 0x278,
315 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
316 NvRegTxCnt = 0x280,
317 NvRegTxZeroReXmt = 0x284,
318 NvRegTxOneReXmt = 0x288,
319 NvRegTxManyReXmt = 0x28c,
320 NvRegTxLateCol = 0x290,
321 NvRegTxUnderflow = 0x294,
322 NvRegTxLossCarrier = 0x298,
323 NvRegTxExcessDef = 0x29c,
324 NvRegTxRetryErr = 0x2a0,
325 NvRegRxFrameErr = 0x2a4,
326 NvRegRxExtraByte = 0x2a8,
327 NvRegRxLateCol = 0x2ac,
328 NvRegRxRunt = 0x2b0,
329 NvRegRxFrameTooLong = 0x2b4,
330 NvRegRxOverflow = 0x2b8,
331 NvRegRxFCSErr = 0x2bc,
332 NvRegRxFrameAlignErr = 0x2c0,
333 NvRegRxLenErr = 0x2c4,
334 NvRegRxUnicast = 0x2c8,
335 NvRegRxMulticast = 0x2cc,
336 NvRegRxBroadcast = 0x2d0,
337 NvRegTxDef = 0x2d4,
338 NvRegTxFrame = 0x2d8,
339 NvRegRxCnt = 0x2dc,
340 NvRegTxPause = 0x2e0,
341 NvRegRxPause = 0x2e4,
342 NvRegRxDropFrame = 0x2e8,
343 NvRegVlanControl = 0x300,
344 #define NVREG_VLANCONTROL_ENABLE 0x2000
345 NvRegMSIXMap0 = 0x3e0,
346 NvRegMSIXMap1 = 0x3e4,
347 NvRegMSIXIrqStatus = 0x3f0,
348
349 NvRegPowerState2 = 0x600,
350 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
351 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
352 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
353 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
354 };
355
356 /* Big endian: should work, but is untested */
357 struct ring_desc {
358 __le32 buf;
359 __le32 flaglen;
360 };
361
362 struct ring_desc_ex {
363 __le32 bufhigh;
364 __le32 buflow;
365 __le32 txvlan;
366 __le32 flaglen;
367 };
368
369 union ring_type {
370 struct ring_desc *orig;
371 struct ring_desc_ex *ex;
372 };
373
374 #define FLAG_MASK_V1 0xffff0000
375 #define FLAG_MASK_V2 0xffffc000
376 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
377 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
378
379 #define NV_TX_LASTPACKET (1<<16)
380 #define NV_TX_RETRYERROR (1<<19)
381 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
382 #define NV_TX_FORCED_INTERRUPT (1<<24)
383 #define NV_TX_DEFERRED (1<<26)
384 #define NV_TX_CARRIERLOST (1<<27)
385 #define NV_TX_LATECOLLISION (1<<28)
386 #define NV_TX_UNDERFLOW (1<<29)
387 #define NV_TX_ERROR (1<<30)
388 #define NV_TX_VALID (1<<31)
389
390 #define NV_TX2_LASTPACKET (1<<29)
391 #define NV_TX2_RETRYERROR (1<<18)
392 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
393 #define NV_TX2_FORCED_INTERRUPT (1<<30)
394 #define NV_TX2_DEFERRED (1<<25)
395 #define NV_TX2_CARRIERLOST (1<<26)
396 #define NV_TX2_LATECOLLISION (1<<27)
397 #define NV_TX2_UNDERFLOW (1<<28)
398 /* error and valid are the same for both */
399 #define NV_TX2_ERROR (1<<30)
400 #define NV_TX2_VALID (1<<31)
401 #define NV_TX2_TSO (1<<28)
402 #define NV_TX2_TSO_SHIFT 14
403 #define NV_TX2_TSO_MAX_SHIFT 14
404 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
405 #define NV_TX2_CHECKSUM_L3 (1<<27)
406 #define NV_TX2_CHECKSUM_L4 (1<<26)
407
408 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
409
410 #define NV_RX_DESCRIPTORVALID (1<<16)
411 #define NV_RX_MISSEDFRAME (1<<17)
412 #define NV_RX_SUBSTRACT1 (1<<18)
413 #define NV_RX_ERROR1 (1<<23)
414 #define NV_RX_ERROR2 (1<<24)
415 #define NV_RX_ERROR3 (1<<25)
416 #define NV_RX_ERROR4 (1<<26)
417 #define NV_RX_CRCERR (1<<27)
418 #define NV_RX_OVERFLOW (1<<28)
419 #define NV_RX_FRAMINGERR (1<<29)
420 #define NV_RX_ERROR (1<<30)
421 #define NV_RX_AVAIL (1<<31)
422 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
423
424 #define NV_RX2_CHECKSUMMASK (0x1C000000)
425 #define NV_RX2_CHECKSUM_IP (0x10000000)
426 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
427 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
428 #define NV_RX2_DESCRIPTORVALID (1<<29)
429 #define NV_RX2_SUBSTRACT1 (1<<25)
430 #define NV_RX2_ERROR1 (1<<18)
431 #define NV_RX2_ERROR2 (1<<19)
432 #define NV_RX2_ERROR3 (1<<20)
433 #define NV_RX2_ERROR4 (1<<21)
434 #define NV_RX2_CRCERR (1<<22)
435 #define NV_RX2_OVERFLOW (1<<23)
436 #define NV_RX2_FRAMINGERR (1<<24)
437 /* error and avail are the same for both */
438 #define NV_RX2_ERROR (1<<30)
439 #define NV_RX2_AVAIL (1<<31)
440 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
441
442 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
443 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
444
445 /* Miscellaneous hardware related defines: */
446 #define NV_PCI_REGSZ_VER1 0x270
447 #define NV_PCI_REGSZ_VER2 0x2d4
448 #define NV_PCI_REGSZ_VER3 0x604
449 #define NV_PCI_REGSZ_MAX 0x604
450
451 /* various timeout delays: all in usec */
452 #define NV_TXRX_RESET_DELAY 4
453 #define NV_TXSTOP_DELAY1 10
454 #define NV_TXSTOP_DELAY1MAX 500000
455 #define NV_TXSTOP_DELAY2 100
456 #define NV_RXSTOP_DELAY1 10
457 #define NV_RXSTOP_DELAY1MAX 500000
458 #define NV_RXSTOP_DELAY2 100
459 #define NV_SETUP5_DELAY 5
460 #define NV_SETUP5_DELAYMAX 50000
461 #define NV_POWERUP_DELAY 5
462 #define NV_POWERUP_DELAYMAX 5000
463 #define NV_MIIBUSY_DELAY 50
464 #define NV_MIIPHY_DELAY 10
465 #define NV_MIIPHY_DELAYMAX 10000
466 #define NV_MAC_RESET_DELAY 64
467
468 #define NV_WAKEUPPATTERNS 5
469 #define NV_WAKEUPMASKENTRIES 4
470
471 /* General driver defaults */
472 #define NV_WATCHDOG_TIMEO (5*HZ)
473
474 #define RX_RING_DEFAULT 512
475 #define TX_RING_DEFAULT 256
476 #define RX_RING_MIN 128
477 #define TX_RING_MIN 64
478 #define RING_MAX_DESC_VER_1 1024
479 #define RING_MAX_DESC_VER_2_3 16384
480
481 /* rx/tx mac addr + type + vlan + align + slack*/
482 #define NV_RX_HEADERS (64)
483 /* even more slack. */
484 #define NV_RX_ALLOC_PAD (64)
485
486 /* maximum mtu size */
487 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
488 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
489
490 #define OOM_REFILL (1+HZ/20)
491 #define POLL_WAIT (1+HZ/100)
492 #define LINK_TIMEOUT (3*HZ)
493 #define STATS_INTERVAL (10*HZ)
494
495 /*
496 * desc_ver values:
497 * The nic supports three different descriptor types:
498 * - DESC_VER_1: Original
499 * - DESC_VER_2: support for jumbo frames.
500 * - DESC_VER_3: 64-bit format.
501 */
502 #define DESC_VER_1 1
503 #define DESC_VER_2 2
504 #define DESC_VER_3 3
505
506 /* PHY defines */
507 #define PHY_OUI_MARVELL 0x5043
508 #define PHY_OUI_CICADA 0x03f1
509 #define PHY_OUI_VITESSE 0x01c1
510 #define PHY_OUI_REALTEK 0x0732
511 #define PHY_OUI_REALTEK2 0x0020
512 #define PHYID1_OUI_MASK 0x03ff
513 #define PHYID1_OUI_SHFT 6
514 #define PHYID2_OUI_MASK 0xfc00
515 #define PHYID2_OUI_SHFT 10
516 #define PHYID2_MODEL_MASK 0x03f0
517 #define PHY_MODEL_REALTEK_8211 0x0110
518 #define PHY_REV_MASK 0x0001
519 #define PHY_REV_REALTEK_8211B 0x0000
520 #define PHY_REV_REALTEK_8211C 0x0001
521 #define PHY_MODEL_REALTEK_8201 0x0200
522 #define PHY_MODEL_MARVELL_E3016 0x0220
523 #define PHY_MARVELL_E3016_INITMASK 0x0300
524 #define PHY_CICADA_INIT1 0x0f000
525 #define PHY_CICADA_INIT2 0x0e00
526 #define PHY_CICADA_INIT3 0x01000
527 #define PHY_CICADA_INIT4 0x0200
528 #define PHY_CICADA_INIT5 0x0004
529 #define PHY_CICADA_INIT6 0x02000
530 #define PHY_VITESSE_INIT_REG1 0x1f
531 #define PHY_VITESSE_INIT_REG2 0x10
532 #define PHY_VITESSE_INIT_REG3 0x11
533 #define PHY_VITESSE_INIT_REG4 0x12
534 #define PHY_VITESSE_INIT_MSK1 0xc
535 #define PHY_VITESSE_INIT_MSK2 0x0180
536 #define PHY_VITESSE_INIT1 0x52b5
537 #define PHY_VITESSE_INIT2 0xaf8a
538 #define PHY_VITESSE_INIT3 0x8
539 #define PHY_VITESSE_INIT4 0x8f8a
540 #define PHY_VITESSE_INIT5 0xaf86
541 #define PHY_VITESSE_INIT6 0x8f86
542 #define PHY_VITESSE_INIT7 0xaf82
543 #define PHY_VITESSE_INIT8 0x0100
544 #define PHY_VITESSE_INIT9 0x8f82
545 #define PHY_VITESSE_INIT10 0x0
546 #define PHY_REALTEK_INIT_REG1 0x1f
547 #define PHY_REALTEK_INIT_REG2 0x19
548 #define PHY_REALTEK_INIT_REG3 0x13
549 #define PHY_REALTEK_INIT_REG4 0x14
550 #define PHY_REALTEK_INIT_REG5 0x18
551 #define PHY_REALTEK_INIT_REG6 0x11
552 #define PHY_REALTEK_INIT_REG7 0x01
553 #define PHY_REALTEK_INIT1 0x0000
554 #define PHY_REALTEK_INIT2 0x8e00
555 #define PHY_REALTEK_INIT3 0x0001
556 #define PHY_REALTEK_INIT4 0xad17
557 #define PHY_REALTEK_INIT5 0xfb54
558 #define PHY_REALTEK_INIT6 0xf5c7
559 #define PHY_REALTEK_INIT7 0x1000
560 #define PHY_REALTEK_INIT8 0x0003
561 #define PHY_REALTEK_INIT9 0x0008
562 #define PHY_REALTEK_INIT10 0x0005
563 #define PHY_REALTEK_INIT11 0x0200
564 #define PHY_REALTEK_INIT_MSK1 0x0003
565
566 #define PHY_GIGABIT 0x0100
567
568 #define PHY_TIMEOUT 0x1
569 #define PHY_ERROR 0x2
570
571 #define PHY_100 0x1
572 #define PHY_1000 0x2
573 #define PHY_HALF 0x100
574
575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
577 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
578 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
579 #define NV_PAUSEFRAME_RX_REQ 0x0010
580 #define NV_PAUSEFRAME_TX_REQ 0x0020
581 #define NV_PAUSEFRAME_AUTONEG 0x0040
582
583 /* MSI/MSI-X defines */
584 #define NV_MSI_X_MAX_VECTORS 8
585 #define NV_MSI_X_VECTORS_MASK 0x000f
586 #define NV_MSI_CAPABLE 0x0010
587 #define NV_MSI_X_CAPABLE 0x0020
588 #define NV_MSI_ENABLED 0x0040
589 #define NV_MSI_X_ENABLED 0x0080
590
591 #define NV_MSI_X_VECTOR_ALL 0x0
592 #define NV_MSI_X_VECTOR_RX 0x0
593 #define NV_MSI_X_VECTOR_TX 0x1
594 #define NV_MSI_X_VECTOR_OTHER 0x2
595
596 #define NV_MSI_PRIV_OFFSET 0x68
597 #define NV_MSI_PRIV_VALUE 0xffffffff
598
599 #define NV_RESTART_TX 0x1
600 #define NV_RESTART_RX 0x2
601
602 #define NV_TX_LIMIT_COUNT 16
603
604 #define NV_DYNAMIC_THRESHOLD 4
605 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
606
607 /* statistics */
608 struct nv_ethtool_str {
609 char name[ETH_GSTRING_LEN];
610 };
611
612 static const struct nv_ethtool_str nv_estats_str[] = {
613 { "tx_bytes" }, /* includes Ethernet FCS CRC */
614 { "tx_zero_rexmt" },
615 { "tx_one_rexmt" },
616 { "tx_many_rexmt" },
617 { "tx_late_collision" },
618 { "tx_fifo_errors" },
619 { "tx_carrier_errors" },
620 { "tx_excess_deferral" },
621 { "tx_retry_error" },
622 { "rx_frame_error" },
623 { "rx_extra_byte" },
624 { "rx_late_collision" },
625 { "rx_runt" },
626 { "rx_frame_too_long" },
627 { "rx_over_errors" },
628 { "rx_crc_errors" },
629 { "rx_frame_align_error" },
630 { "rx_length_error" },
631 { "rx_unicast" },
632 { "rx_multicast" },
633 { "rx_broadcast" },
634 { "rx_packets" },
635 { "rx_errors_total" },
636 { "tx_errors_total" },
637
638 /* version 2 stats */
639 { "tx_deferral" },
640 { "tx_packets" },
641 { "rx_bytes" }, /* includes Ethernet FCS CRC */
642 { "tx_pause" },
643 { "rx_pause" },
644 { "rx_drop_frame" },
645
646 /* version 3 stats */
647 { "tx_unicast" },
648 { "tx_multicast" },
649 { "tx_broadcast" }
650 };
651
652 struct nv_ethtool_stats {
653 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
654 u64 tx_zero_rexmt;
655 u64 tx_one_rexmt;
656 u64 tx_many_rexmt;
657 u64 tx_late_collision;
658 u64 tx_fifo_errors;
659 u64 tx_carrier_errors;
660 u64 tx_excess_deferral;
661 u64 tx_retry_error;
662 u64 rx_frame_error;
663 u64 rx_extra_byte;
664 u64 rx_late_collision;
665 u64 rx_runt;
666 u64 rx_frame_too_long;
667 u64 rx_over_errors;
668 u64 rx_crc_errors;
669 u64 rx_frame_align_error;
670 u64 rx_length_error;
671 u64 rx_unicast;
672 u64 rx_multicast;
673 u64 rx_broadcast;
674 u64 rx_packets; /* should be ifconfig->rx_packets */
675 u64 rx_errors_total;
676 u64 tx_errors_total;
677
678 /* version 2 stats */
679 u64 tx_deferral;
680 u64 tx_packets; /* should be ifconfig->tx_packets */
681 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
682 u64 tx_pause;
683 u64 rx_pause;
684 u64 rx_drop_frame;
685
686 /* version 3 stats */
687 u64 tx_unicast;
688 u64 tx_multicast;
689 u64 tx_broadcast;
690 };
691
692 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
693 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
694 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
695
696 /* diagnostics */
697 #define NV_TEST_COUNT_BASE 3
698 #define NV_TEST_COUNT_EXTENDED 4
699
700 static const struct nv_ethtool_str nv_etests_str[] = {
701 { "link (online/offline)" },
702 { "register (offline) " },
703 { "interrupt (offline) " },
704 { "loopback (offline) " }
705 };
706
707 struct register_test {
708 __u32 reg;
709 __u32 mask;
710 };
711
712 static const struct register_test nv_registers_test[] = {
713 { NvRegUnknownSetupReg6, 0x01 },
714 { NvRegMisc1, 0x03c },
715 { NvRegOffloadConfig, 0x03ff },
716 { NvRegMulticastAddrA, 0xffffffff },
717 { NvRegTxWatermark, 0x0ff },
718 { NvRegWakeUpFlags, 0x07777 },
719 { 0, 0 }
720 };
721
722 struct nv_skb_map {
723 struct sk_buff *skb;
724 dma_addr_t dma;
725 unsigned int dma_len:31;
726 unsigned int dma_single:1;
727 struct ring_desc_ex *first_tx_desc;
728 struct nv_skb_map *next_tx_ctx;
729 };
730
731 /*
732 * SMP locking:
733 * All hardware access under netdev_priv(dev)->lock, except the performance
734 * critical parts:
735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
736 * by the arch code for interrupts.
737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
738 * needs netdev_priv(dev)->lock :-(
739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
740 *
741 * Hardware stats updates are protected by hwstats_lock:
742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
743 * integer wraparound in the NIC stats registers, at low frequency
744 * (0.1 Hz)
745 * - updated by nv_get_ethtool_stats + nv_get_stats64
746 *
747 * Software stats are accessed only through 64b synchronization points
748 * and are not subject to other synchronization techniques (single
749 * update thread on the TX or RX paths).
750 */
751
752 /* in dev: base, irq */
753 struct fe_priv {
754 spinlock_t lock;
755
756 struct net_device *dev;
757 struct napi_struct napi;
758
759 /* hardware stats are updated in syscall and timer */
760 spinlock_t hwstats_lock;
761 struct nv_ethtool_stats estats;
762
763 int in_shutdown;
764 u32 linkspeed;
765 int duplex;
766 int autoneg;
767 int fixed_mode;
768 int phyaddr;
769 int wolenabled;
770 unsigned int phy_oui;
771 unsigned int phy_model;
772 unsigned int phy_rev;
773 u16 gigabit;
774 int intr_test;
775 int recover_error;
776 int quiet_count;
777
778 /* General data: RO fields */
779 dma_addr_t ring_addr;
780 struct pci_dev *pci_dev;
781 u32 orig_mac[2];
782 u32 events;
783 u32 irqmask;
784 u32 desc_ver;
785 u32 txrxctl_bits;
786 u32 vlanctl_bits;
787 u32 driver_data;
788 u32 device_id;
789 u32 register_size;
790 u32 mac_in_use;
791 int mgmt_version;
792 int mgmt_sema;
793
794 void __iomem *base;
795
796 /* rx specific fields.
797 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
798 */
799 union ring_type get_rx, put_rx, first_rx, last_rx;
800 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
801 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
802 struct nv_skb_map *rx_skb;
803
804 union ring_type rx_ring;
805 unsigned int rx_buf_sz;
806 unsigned int pkt_limit;
807 struct timer_list oom_kick;
808 struct timer_list nic_poll;
809 struct timer_list stats_poll;
810 u32 nic_poll_irq;
811 int rx_ring_size;
812
813 /* RX software stats */
814 struct u64_stats_sync swstats_rx_syncp;
815 u64 stat_rx_packets;
816 u64 stat_rx_bytes; /* not always available in HW */
817 u64 stat_rx_missed_errors;
818 u64 stat_rx_dropped;
819
820 /* media detection workaround.
821 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
822 */
823 int need_linktimer;
824 unsigned long link_timeout;
825 /*
826 * tx specific fields.
827 */
828 union ring_type get_tx, put_tx, first_tx, last_tx;
829 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
830 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
831 struct nv_skb_map *tx_skb;
832
833 union ring_type tx_ring;
834 u32 tx_flags;
835 int tx_ring_size;
836 int tx_limit;
837 u32 tx_pkts_in_progress;
838 struct nv_skb_map *tx_change_owner;
839 struct nv_skb_map *tx_end_flip;
840 int tx_stop;
841
842 /* TX software stats */
843 struct u64_stats_sync swstats_tx_syncp;
844 u64 stat_tx_packets; /* not always available in HW */
845 u64 stat_tx_bytes;
846 u64 stat_tx_dropped;
847
848 /* msi/msi-x fields */
849 u32 msi_flags;
850 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
851
852 /* flow control */
853 u32 pause_flags;
854
855 /* power saved state */
856 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
857
858 /* for different msi-x irq type */
859 char name_rx[IFNAMSIZ + 3]; /* -rx */
860 char name_tx[IFNAMSIZ + 3]; /* -tx */
861 char name_other[IFNAMSIZ + 6]; /* -other */
862 };
863
864 /*
865 * Maximum number of loops until we assume that a bit in the irq mask
866 * is stuck. Overridable with module param.
867 */
868 static int max_interrupt_work = 4;
869
870 /*
871 * Optimization can be either throuput mode or cpu mode
872 *
873 * Throughput Mode: Every tx and rx packet will generate an interrupt.
874 * CPU Mode: Interrupts are controlled by a timer.
875 */
876 enum {
877 NV_OPTIMIZATION_MODE_THROUGHPUT,
878 NV_OPTIMIZATION_MODE_CPU,
879 NV_OPTIMIZATION_MODE_DYNAMIC
880 };
881 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
882
883 /*
884 * Poll interval for timer irq
885 *
886 * This interval determines how frequent an interrupt is generated.
887 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
888 * Min = 0, and Max = 65535
889 */
890 static int poll_interval = -1;
891
892 /*
893 * MSI interrupts
894 */
895 enum {
896 NV_MSI_INT_DISABLED,
897 NV_MSI_INT_ENABLED
898 };
899 static int msi = NV_MSI_INT_ENABLED;
900
901 /*
902 * MSIX interrupts
903 */
904 enum {
905 NV_MSIX_INT_DISABLED,
906 NV_MSIX_INT_ENABLED
907 };
908 static int msix = NV_MSIX_INT_ENABLED;
909
910 /*
911 * DMA 64bit
912 */
913 enum {
914 NV_DMA_64BIT_DISABLED,
915 NV_DMA_64BIT_ENABLED
916 };
917 static int dma_64bit = NV_DMA_64BIT_ENABLED;
918
919 /*
920 * Debug output control for tx_timeout
921 */
922 static bool debug_tx_timeout = false;
923
924 /*
925 * Crossover Detection
926 * Realtek 8201 phy + some OEM boards do not work properly.
927 */
928 enum {
929 NV_CROSSOVER_DETECTION_DISABLED,
930 NV_CROSSOVER_DETECTION_ENABLED
931 };
932 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
933
934 /*
935 * Power down phy when interface is down (persists through reboot;
936 * older Linux and other OSes may not power it up again)
937 */
938 static int phy_power_down;
939
940 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
941 {
942 return netdev_priv(dev);
943 }
944
945 static inline u8 __iomem *get_hwbase(struct net_device *dev)
946 {
947 return ((struct fe_priv *)netdev_priv(dev))->base;
948 }
949
950 static inline void pci_push(u8 __iomem *base)
951 {
952 /* force out pending posted writes */
953 readl(base);
954 }
955
956 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
957 {
958 return le32_to_cpu(prd->flaglen)
959 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
960 }
961
962 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
963 {
964 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
965 }
966
967 static bool nv_optimized(struct fe_priv *np)
968 {
969 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
970 return false;
971 return true;
972 }
973
974 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
975 int delay, int delaymax)
976 {
977 u8 __iomem *base = get_hwbase(dev);
978
979 pci_push(base);
980 do {
981 udelay(delay);
982 delaymax -= delay;
983 if (delaymax < 0)
984 return 1;
985 } while ((readl(base + offset) & mask) != target);
986 return 0;
987 }
988
989 #define NV_SETUP_RX_RING 0x01
990 #define NV_SETUP_TX_RING 0x02
991
992 static inline u32 dma_low(dma_addr_t addr)
993 {
994 return addr;
995 }
996
997 static inline u32 dma_high(dma_addr_t addr)
998 {
999 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
1000 }
1001
1002 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1003 {
1004 struct fe_priv *np = get_nvpriv(dev);
1005 u8 __iomem *base = get_hwbase(dev);
1006
1007 if (!nv_optimized(np)) {
1008 if (rxtx_flags & NV_SETUP_RX_RING)
1009 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1010 if (rxtx_flags & NV_SETUP_TX_RING)
1011 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1012 } else {
1013 if (rxtx_flags & NV_SETUP_RX_RING) {
1014 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1015 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1016 }
1017 if (rxtx_flags & NV_SETUP_TX_RING) {
1018 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1019 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1020 }
1021 }
1022 }
1023
1024 static void free_rings(struct net_device *dev)
1025 {
1026 struct fe_priv *np = get_nvpriv(dev);
1027
1028 if (!nv_optimized(np)) {
1029 if (np->rx_ring.orig)
1030 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1031 np->rx_ring.orig, np->ring_addr);
1032 } else {
1033 if (np->rx_ring.ex)
1034 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1035 np->rx_ring.ex, np->ring_addr);
1036 }
1037 kfree(np->rx_skb);
1038 kfree(np->tx_skb);
1039 }
1040
1041 static int using_multi_irqs(struct net_device *dev)
1042 {
1043 struct fe_priv *np = get_nvpriv(dev);
1044
1045 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1046 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1047 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1048 return 0;
1049 else
1050 return 1;
1051 }
1052
1053 static void nv_txrx_gate(struct net_device *dev, bool gate)
1054 {
1055 struct fe_priv *np = get_nvpriv(dev);
1056 u8 __iomem *base = get_hwbase(dev);
1057 u32 powerstate;
1058
1059 if (!np->mac_in_use &&
1060 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1061 powerstate = readl(base + NvRegPowerState2);
1062 if (gate)
1063 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1064 else
1065 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1066 writel(powerstate, base + NvRegPowerState2);
1067 }
1068 }
1069
1070 static void nv_enable_irq(struct net_device *dev)
1071 {
1072 struct fe_priv *np = get_nvpriv(dev);
1073
1074 if (!using_multi_irqs(dev)) {
1075 if (np->msi_flags & NV_MSI_X_ENABLED)
1076 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1077 else
1078 enable_irq(np->pci_dev->irq);
1079 } else {
1080 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1081 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1082 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1083 }
1084 }
1085
1086 static void nv_disable_irq(struct net_device *dev)
1087 {
1088 struct fe_priv *np = get_nvpriv(dev);
1089
1090 if (!using_multi_irqs(dev)) {
1091 if (np->msi_flags & NV_MSI_X_ENABLED)
1092 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1093 else
1094 disable_irq(np->pci_dev->irq);
1095 } else {
1096 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1097 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1098 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1099 }
1100 }
1101
1102 /* In MSIX mode, a write to irqmask behaves as XOR */
1103 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1104 {
1105 u8 __iomem *base = get_hwbase(dev);
1106
1107 writel(mask, base + NvRegIrqMask);
1108 }
1109
1110 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1111 {
1112 struct fe_priv *np = get_nvpriv(dev);
1113 u8 __iomem *base = get_hwbase(dev);
1114
1115 if (np->msi_flags & NV_MSI_X_ENABLED) {
1116 writel(mask, base + NvRegIrqMask);
1117 } else {
1118 if (np->msi_flags & NV_MSI_ENABLED)
1119 writel(0, base + NvRegMSIIrqMask);
1120 writel(0, base + NvRegIrqMask);
1121 }
1122 }
1123
1124 static void nv_napi_enable(struct net_device *dev)
1125 {
1126 struct fe_priv *np = get_nvpriv(dev);
1127
1128 napi_enable(&np->napi);
1129 }
1130
1131 static void nv_napi_disable(struct net_device *dev)
1132 {
1133 struct fe_priv *np = get_nvpriv(dev);
1134
1135 napi_disable(&np->napi);
1136 }
1137
1138 #define MII_READ (-1)
1139 /* mii_rw: read/write a register on the PHY.
1140 *
1141 * Caller must guarantee serialization
1142 */
1143 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1144 {
1145 u8 __iomem *base = get_hwbase(dev);
1146 u32 reg;
1147 int retval;
1148
1149 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1150
1151 reg = readl(base + NvRegMIIControl);
1152 if (reg & NVREG_MIICTL_INUSE) {
1153 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1154 udelay(NV_MIIBUSY_DELAY);
1155 }
1156
1157 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1158 if (value != MII_READ) {
1159 writel(value, base + NvRegMIIData);
1160 reg |= NVREG_MIICTL_WRITE;
1161 }
1162 writel(reg, base + NvRegMIIControl);
1163
1164 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1165 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1166 retval = -1;
1167 } else if (value != MII_READ) {
1168 /* it was a write operation - fewer failures are detectable */
1169 retval = 0;
1170 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1171 retval = -1;
1172 } else {
1173 retval = readl(base + NvRegMIIData);
1174 }
1175
1176 return retval;
1177 }
1178
1179 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1180 {
1181 struct fe_priv *np = netdev_priv(dev);
1182 u32 miicontrol;
1183 unsigned int tries = 0;
1184
1185 miicontrol = BMCR_RESET | bmcr_setup;
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1187 return -1;
1188
1189 /* wait for 500ms */
1190 msleep(500);
1191
1192 /* must wait till reset is deasserted */
1193 while (miicontrol & BMCR_RESET) {
1194 usleep_range(10000, 20000);
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1196 /* FIXME: 100 tries seem excessive */
1197 if (tries++ > 100)
1198 return -1;
1199 }
1200 return 0;
1201 }
1202
1203 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1204 {
1205 static const struct {
1206 int reg;
1207 int init;
1208 } ri[] = {
1209 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1210 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1211 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1212 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1213 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1214 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1215 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1216 };
1217 int i;
1218
1219 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1221 return PHY_ERROR;
1222 }
1223
1224 return 0;
1225 }
1226
1227 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1228 {
1229 u32 reg;
1230 u8 __iomem *base = get_hwbase(dev);
1231 u32 powerstate = readl(base + NvRegPowerState2);
1232
1233 /* need to perform hw phy reset */
1234 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1235 writel(powerstate, base + NvRegPowerState2);
1236 msleep(25);
1237
1238 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1239 writel(powerstate, base + NvRegPowerState2);
1240 msleep(25);
1241
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1243 reg |= PHY_REALTEK_INIT9;
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1245 return PHY_ERROR;
1246 if (mii_rw(dev, np->phyaddr,
1247 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1248 return PHY_ERROR;
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1250 if (!(reg & PHY_REALTEK_INIT11)) {
1251 reg |= PHY_REALTEK_INIT11;
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1253 return PHY_ERROR;
1254 }
1255 if (mii_rw(dev, np->phyaddr,
1256 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1257 return PHY_ERROR;
1258
1259 return 0;
1260 }
1261
1262 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1263 {
1264 u32 phy_reserved;
1265
1266 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1267 phy_reserved = mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG6, MII_READ);
1269 phy_reserved |= PHY_REALTEK_INIT7;
1270 if (mii_rw(dev, np->phyaddr,
1271 PHY_REALTEK_INIT_REG6, phy_reserved))
1272 return PHY_ERROR;
1273 }
1274
1275 return 0;
1276 }
1277
1278 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1279 {
1280 u32 phy_reserved;
1281
1282 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1283 if (mii_rw(dev, np->phyaddr,
1284 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1285 return PHY_ERROR;
1286 phy_reserved = mii_rw(dev, np->phyaddr,
1287 PHY_REALTEK_INIT_REG2, MII_READ);
1288 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1289 phy_reserved |= PHY_REALTEK_INIT3;
1290 if (mii_rw(dev, np->phyaddr,
1291 PHY_REALTEK_INIT_REG2, phy_reserved))
1292 return PHY_ERROR;
1293 if (mii_rw(dev, np->phyaddr,
1294 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1295 return PHY_ERROR;
1296 }
1297
1298 return 0;
1299 }
1300
1301 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1302 u32 phyinterface)
1303 {
1304 u32 phy_reserved;
1305
1306 if (phyinterface & PHY_RGMII) {
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1308 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1309 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1311 return PHY_ERROR;
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1313 phy_reserved |= PHY_CICADA_INIT5;
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1315 return PHY_ERROR;
1316 }
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1318 phy_reserved |= PHY_CICADA_INIT6;
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1320 return PHY_ERROR;
1321
1322 return 0;
1323 }
1324
1325 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1326 {
1327 u32 phy_reserved;
1328
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1331 return PHY_ERROR;
1332 if (mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1334 return PHY_ERROR;
1335 phy_reserved = mii_rw(dev, np->phyaddr,
1336 PHY_VITESSE_INIT_REG4, MII_READ);
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1338 return PHY_ERROR;
1339 phy_reserved = mii_rw(dev, np->phyaddr,
1340 PHY_VITESSE_INIT_REG3, MII_READ);
1341 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1342 phy_reserved |= PHY_VITESSE_INIT3;
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1347 return PHY_ERROR;
1348 if (mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1350 return PHY_ERROR;
1351 phy_reserved = mii_rw(dev, np->phyaddr,
1352 PHY_VITESSE_INIT_REG4, MII_READ);
1353 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1354 phy_reserved |= PHY_VITESSE_INIT3;
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1356 return PHY_ERROR;
1357 phy_reserved = mii_rw(dev, np->phyaddr,
1358 PHY_VITESSE_INIT_REG3, MII_READ);
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1363 return PHY_ERROR;
1364 if (mii_rw(dev, np->phyaddr,
1365 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1366 return PHY_ERROR;
1367 phy_reserved = mii_rw(dev, np->phyaddr,
1368 PHY_VITESSE_INIT_REG4, MII_READ);
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1370 return PHY_ERROR;
1371 phy_reserved = mii_rw(dev, np->phyaddr,
1372 PHY_VITESSE_INIT_REG3, MII_READ);
1373 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1374 phy_reserved |= PHY_VITESSE_INIT8;
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1376 return PHY_ERROR;
1377 if (mii_rw(dev, np->phyaddr,
1378 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1379 return PHY_ERROR;
1380 if (mii_rw(dev, np->phyaddr,
1381 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1382 return PHY_ERROR;
1383
1384 return 0;
1385 }
1386
1387 static int phy_init(struct net_device *dev)
1388 {
1389 struct fe_priv *np = get_nvpriv(dev);
1390 u8 __iomem *base = get_hwbase(dev);
1391 u32 phyinterface;
1392 u32 mii_status, mii_control, mii_control_1000, reg;
1393
1394 /* phy errata for E3016 phy */
1395 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1397 reg &= ~PHY_MARVELL_E3016_INITMASK;
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1399 netdev_info(dev, "%s: phy write to errata reg failed\n",
1400 pci_name(np->pci_dev));
1401 return PHY_ERROR;
1402 }
1403 }
1404 if (np->phy_oui == PHY_OUI_REALTEK) {
1405 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1406 np->phy_rev == PHY_REV_REALTEK_8211B) {
1407 if (init_realtek_8211b(dev, np)) {
1408 netdev_info(dev, "%s: phy init failed\n",
1409 pci_name(np->pci_dev));
1410 return PHY_ERROR;
1411 }
1412 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1413 np->phy_rev == PHY_REV_REALTEK_8211C) {
1414 if (init_realtek_8211c(dev, np)) {
1415 netdev_info(dev, "%s: phy init failed\n",
1416 pci_name(np->pci_dev));
1417 return PHY_ERROR;
1418 }
1419 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1420 if (init_realtek_8201(dev, np)) {
1421 netdev_info(dev, "%s: phy init failed\n",
1422 pci_name(np->pci_dev));
1423 return PHY_ERROR;
1424 }
1425 }
1426 }
1427
1428 /* set advertise register */
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1430 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1431 ADVERTISE_100HALF | ADVERTISE_100FULL |
1432 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1434 netdev_info(dev, "%s: phy write to advertise failed\n",
1435 pci_name(np->pci_dev));
1436 return PHY_ERROR;
1437 }
1438
1439 /* get phy interface type */
1440 phyinterface = readl(base + NvRegPhyInterface);
1441
1442 /* see if gigabit phy */
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1444 if (mii_status & PHY_GIGABIT) {
1445 np->gigabit = PHY_GIGABIT;
1446 mii_control_1000 = mii_rw(dev, np->phyaddr,
1447 MII_CTRL1000, MII_READ);
1448 mii_control_1000 &= ~ADVERTISE_1000HALF;
1449 if (phyinterface & PHY_RGMII)
1450 mii_control_1000 |= ADVERTISE_1000FULL;
1451 else
1452 mii_control_1000 &= ~ADVERTISE_1000FULL;
1453
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1455 netdev_info(dev, "%s: phy init failed\n",
1456 pci_name(np->pci_dev));
1457 return PHY_ERROR;
1458 }
1459 } else
1460 np->gigabit = 0;
1461
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1463 mii_control |= BMCR_ANENABLE;
1464
1465 if (np->phy_oui == PHY_OUI_REALTEK &&
1466 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1467 np->phy_rev == PHY_REV_REALTEK_8211C) {
1468 /* start autoneg since we already performed hw reset above */
1469 mii_control |= BMCR_ANRESTART;
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1471 netdev_info(dev, "%s: phy init failed\n",
1472 pci_name(np->pci_dev));
1473 return PHY_ERROR;
1474 }
1475 } else {
1476 /* reset the phy
1477 * (certain phys need bmcr to be setup with reset)
1478 */
1479 if (phy_reset(dev, mii_control)) {
1480 netdev_info(dev, "%s: phy reset failed\n",
1481 pci_name(np->pci_dev));
1482 return PHY_ERROR;
1483 }
1484 }
1485
1486 /* phy vendor specific configuration */
1487 if ((np->phy_oui == PHY_OUI_CICADA)) {
1488 if (init_cicada(dev, np, phyinterface)) {
1489 netdev_info(dev, "%s: phy init failed\n",
1490 pci_name(np->pci_dev));
1491 return PHY_ERROR;
1492 }
1493 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1494 if (init_vitesse(dev, np)) {
1495 netdev_info(dev, "%s: phy init failed\n",
1496 pci_name(np->pci_dev));
1497 return PHY_ERROR;
1498 }
1499 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1500 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1501 np->phy_rev == PHY_REV_REALTEK_8211B) {
1502 /* reset could have cleared these out, set them back */
1503 if (init_realtek_8211b(dev, np)) {
1504 netdev_info(dev, "%s: phy init failed\n",
1505 pci_name(np->pci_dev));
1506 return PHY_ERROR;
1507 }
1508 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1509 if (init_realtek_8201(dev, np) ||
1510 init_realtek_8201_cross(dev, np)) {
1511 netdev_info(dev, "%s: phy init failed\n",
1512 pci_name(np->pci_dev));
1513 return PHY_ERROR;
1514 }
1515 }
1516 }
1517
1518 /* some phys clear out pause advertisement on reset, set it back */
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1520
1521 /* restart auto negotiation, power down phy */
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1523 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1524 if (phy_power_down)
1525 mii_control |= BMCR_PDOWN;
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1527 return PHY_ERROR;
1528
1529 return 0;
1530 }
1531
1532 static void nv_start_rx(struct net_device *dev)
1533 {
1534 struct fe_priv *np = netdev_priv(dev);
1535 u8 __iomem *base = get_hwbase(dev);
1536 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1537
1538 /* Already running? Stop it. */
1539 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1540 rx_ctrl &= ~NVREG_RCVCTL_START;
1541 writel(rx_ctrl, base + NvRegReceiverControl);
1542 pci_push(base);
1543 }
1544 writel(np->linkspeed, base + NvRegLinkSpeed);
1545 pci_push(base);
1546 rx_ctrl |= NVREG_RCVCTL_START;
1547 if (np->mac_in_use)
1548 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1549 writel(rx_ctrl, base + NvRegReceiverControl);
1550 pci_push(base);
1551 }
1552
1553 static void nv_stop_rx(struct net_device *dev)
1554 {
1555 struct fe_priv *np = netdev_priv(dev);
1556 u8 __iomem *base = get_hwbase(dev);
1557 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1558
1559 if (!np->mac_in_use)
1560 rx_ctrl &= ~NVREG_RCVCTL_START;
1561 else
1562 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1563 writel(rx_ctrl, base + NvRegReceiverControl);
1564 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1565 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1566 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1567 __func__);
1568
1569 udelay(NV_RXSTOP_DELAY2);
1570 if (!np->mac_in_use)
1571 writel(0, base + NvRegLinkSpeed);
1572 }
1573
1574 static void nv_start_tx(struct net_device *dev)
1575 {
1576 struct fe_priv *np = netdev_priv(dev);
1577 u8 __iomem *base = get_hwbase(dev);
1578 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579
1580 tx_ctrl |= NVREG_XMITCTL_START;
1581 if (np->mac_in_use)
1582 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1583 writel(tx_ctrl, base + NvRegTransmitterControl);
1584 pci_push(base);
1585 }
1586
1587 static void nv_stop_tx(struct net_device *dev)
1588 {
1589 struct fe_priv *np = netdev_priv(dev);
1590 u8 __iomem *base = get_hwbase(dev);
1591 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1592
1593 if (!np->mac_in_use)
1594 tx_ctrl &= ~NVREG_XMITCTL_START;
1595 else
1596 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1597 writel(tx_ctrl, base + NvRegTransmitterControl);
1598 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1599 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1600 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1601 __func__);
1602
1603 udelay(NV_TXSTOP_DELAY2);
1604 if (!np->mac_in_use)
1605 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1606 base + NvRegTransmitPoll);
1607 }
1608
1609 static void nv_start_rxtx(struct net_device *dev)
1610 {
1611 nv_start_rx(dev);
1612 nv_start_tx(dev);
1613 }
1614
1615 static void nv_stop_rxtx(struct net_device *dev)
1616 {
1617 nv_stop_rx(dev);
1618 nv_stop_tx(dev);
1619 }
1620
1621 static void nv_txrx_reset(struct net_device *dev)
1622 {
1623 struct fe_priv *np = netdev_priv(dev);
1624 u8 __iomem *base = get_hwbase(dev);
1625
1626 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627 pci_push(base);
1628 udelay(NV_TXRX_RESET_DELAY);
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1631 }
1632
1633 static void nv_mac_reset(struct net_device *dev)
1634 {
1635 struct fe_priv *np = netdev_priv(dev);
1636 u8 __iomem *base = get_hwbase(dev);
1637 u32 temp1, temp2, temp3;
1638
1639 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1640 pci_push(base);
1641
1642 /* save registers since they will be cleared on reset */
1643 temp1 = readl(base + NvRegMacAddrA);
1644 temp2 = readl(base + NvRegMacAddrB);
1645 temp3 = readl(base + NvRegTransmitPoll);
1646
1647 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1648 pci_push(base);
1649 udelay(NV_MAC_RESET_DELAY);
1650 writel(0, base + NvRegMacReset);
1651 pci_push(base);
1652 udelay(NV_MAC_RESET_DELAY);
1653
1654 /* restore saved registers */
1655 writel(temp1, base + NvRegMacAddrA);
1656 writel(temp2, base + NvRegMacAddrB);
1657 writel(temp3, base + NvRegTransmitPoll);
1658
1659 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1660 pci_push(base);
1661 }
1662
1663 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1664 static void nv_update_stats(struct net_device *dev)
1665 {
1666 struct fe_priv *np = netdev_priv(dev);
1667 u8 __iomem *base = get_hwbase(dev);
1668
1669 /* If it happens that this is run in top-half context, then
1670 * replace the spin_lock of hwstats_lock with
1671 * spin_lock_irqsave() in calling functions. */
1672 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1673 assert_spin_locked(&np->hwstats_lock);
1674
1675 /* query hardware */
1676 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1677 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1678 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1679 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1680 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1681 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1682 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1683 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1684 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1685 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1686 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1687 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1688 np->estats.rx_runt += readl(base + NvRegRxRunt);
1689 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1690 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1691 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1692 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1693 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1694 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1695 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1696 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1697 np->estats.rx_packets =
1698 np->estats.rx_unicast +
1699 np->estats.rx_multicast +
1700 np->estats.rx_broadcast;
1701 np->estats.rx_errors_total =
1702 np->estats.rx_crc_errors +
1703 np->estats.rx_over_errors +
1704 np->estats.rx_frame_error +
1705 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1706 np->estats.rx_late_collision +
1707 np->estats.rx_runt +
1708 np->estats.rx_frame_too_long;
1709 np->estats.tx_errors_total =
1710 np->estats.tx_late_collision +
1711 np->estats.tx_fifo_errors +
1712 np->estats.tx_carrier_errors +
1713 np->estats.tx_excess_deferral +
1714 np->estats.tx_retry_error;
1715
1716 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1717 np->estats.tx_deferral += readl(base + NvRegTxDef);
1718 np->estats.tx_packets += readl(base + NvRegTxFrame);
1719 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1720 np->estats.tx_pause += readl(base + NvRegTxPause);
1721 np->estats.rx_pause += readl(base + NvRegRxPause);
1722 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1723 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1724 }
1725
1726 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1727 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1728 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1729 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1730 }
1731 }
1732
1733 /*
1734 * nv_get_stats64: dev->ndo_get_stats64 function
1735 * Get latest stats value from the nic.
1736 * Called with read_lock(&dev_base_lock) held for read -
1737 * only synchronized against unregister_netdevice.
1738 */
1739 static struct rtnl_link_stats64*
1740 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1741 __acquires(&netdev_priv(dev)->hwstats_lock)
1742 __releases(&netdev_priv(dev)->hwstats_lock)
1743 {
1744 struct fe_priv *np = netdev_priv(dev);
1745 unsigned int syncp_start;
1746
1747 /*
1748 * Note: because HW stats are not always available and for
1749 * consistency reasons, the following ifconfig stats are
1750 * managed by software: rx_bytes, tx_bytes, rx_packets and
1751 * tx_packets. The related hardware stats reported by ethtool
1752 * should be equivalent to these ifconfig stats, with 4
1753 * additional bytes per packet (Ethernet FCS CRC), except for
1754 * tx_packets when TSO kicks in.
1755 */
1756
1757 /* software stats */
1758 do {
1759 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1760 storage->rx_packets = np->stat_rx_packets;
1761 storage->rx_bytes = np->stat_rx_bytes;
1762 storage->rx_dropped = np->stat_rx_dropped;
1763 storage->rx_missed_errors = np->stat_rx_missed_errors;
1764 } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1765
1766 do {
1767 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1768 storage->tx_packets = np->stat_tx_packets;
1769 storage->tx_bytes = np->stat_tx_bytes;
1770 storage->tx_dropped = np->stat_tx_dropped;
1771 } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1772
1773 /* If the nic supports hw counters then retrieve latest values */
1774 if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1775 spin_lock_bh(&np->hwstats_lock);
1776
1777 nv_update_stats(dev);
1778
1779 /* generic stats */
1780 storage->rx_errors = np->estats.rx_errors_total;
1781 storage->tx_errors = np->estats.tx_errors_total;
1782
1783 /* meaningful only when NIC supports stats v3 */
1784 storage->multicast = np->estats.rx_multicast;
1785
1786 /* detailed rx_errors */
1787 storage->rx_length_errors = np->estats.rx_length_error;
1788 storage->rx_over_errors = np->estats.rx_over_errors;
1789 storage->rx_crc_errors = np->estats.rx_crc_errors;
1790 storage->rx_frame_errors = np->estats.rx_frame_align_error;
1791 storage->rx_fifo_errors = np->estats.rx_drop_frame;
1792
1793 /* detailed tx_errors */
1794 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1795 storage->tx_fifo_errors = np->estats.tx_fifo_errors;
1796
1797 spin_unlock_bh(&np->hwstats_lock);
1798 }
1799
1800 return storage;
1801 }
1802
1803 /*
1804 * nv_alloc_rx: fill rx ring entries.
1805 * Return 1 if the allocations for the skbs failed and the
1806 * rx engine is without Available descriptors
1807 */
1808 static int nv_alloc_rx(struct net_device *dev)
1809 {
1810 struct fe_priv *np = netdev_priv(dev);
1811 struct ring_desc *less_rx;
1812
1813 less_rx = np->get_rx.orig;
1814 if (less_rx-- == np->first_rx.orig)
1815 less_rx = np->last_rx.orig;
1816
1817 while (np->put_rx.orig != less_rx) {
1818 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1819 if (skb) {
1820 np->put_rx_ctx->skb = skb;
1821 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1822 skb->data,
1823 skb_tailroom(skb),
1824 PCI_DMA_FROMDEVICE);
1825 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1826 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1827 wmb();
1828 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1829 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1830 np->put_rx.orig = np->first_rx.orig;
1831 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1832 np->put_rx_ctx = np->first_rx_ctx;
1833 } else {
1834 u64_stats_update_begin(&np->swstats_rx_syncp);
1835 np->stat_rx_dropped++;
1836 u64_stats_update_end(&np->swstats_rx_syncp);
1837 return 1;
1838 }
1839 }
1840 return 0;
1841 }
1842
1843 static int nv_alloc_rx_optimized(struct net_device *dev)
1844 {
1845 struct fe_priv *np = netdev_priv(dev);
1846 struct ring_desc_ex *less_rx;
1847
1848 less_rx = np->get_rx.ex;
1849 if (less_rx-- == np->first_rx.ex)
1850 less_rx = np->last_rx.ex;
1851
1852 while (np->put_rx.ex != less_rx) {
1853 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1854 if (skb) {
1855 np->put_rx_ctx->skb = skb;
1856 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1857 skb->data,
1858 skb_tailroom(skb),
1859 PCI_DMA_FROMDEVICE);
1860 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1861 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1862 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1863 wmb();
1864 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1865 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1866 np->put_rx.ex = np->first_rx.ex;
1867 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1868 np->put_rx_ctx = np->first_rx_ctx;
1869 } else {
1870 u64_stats_update_begin(&np->swstats_rx_syncp);
1871 np->stat_rx_dropped++;
1872 u64_stats_update_end(&np->swstats_rx_syncp);
1873 return 1;
1874 }
1875 }
1876 return 0;
1877 }
1878
1879 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1880 static void nv_do_rx_refill(unsigned long data)
1881 {
1882 struct net_device *dev = (struct net_device *) data;
1883 struct fe_priv *np = netdev_priv(dev);
1884
1885 /* Just reschedule NAPI rx processing */
1886 napi_schedule(&np->napi);
1887 }
1888
1889 static void nv_init_rx(struct net_device *dev)
1890 {
1891 struct fe_priv *np = netdev_priv(dev);
1892 int i;
1893
1894 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1895
1896 if (!nv_optimized(np))
1897 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1898 else
1899 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1900 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1901 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1902
1903 for (i = 0; i < np->rx_ring_size; i++) {
1904 if (!nv_optimized(np)) {
1905 np->rx_ring.orig[i].flaglen = 0;
1906 np->rx_ring.orig[i].buf = 0;
1907 } else {
1908 np->rx_ring.ex[i].flaglen = 0;
1909 np->rx_ring.ex[i].txvlan = 0;
1910 np->rx_ring.ex[i].bufhigh = 0;
1911 np->rx_ring.ex[i].buflow = 0;
1912 }
1913 np->rx_skb[i].skb = NULL;
1914 np->rx_skb[i].dma = 0;
1915 }
1916 }
1917
1918 static void nv_init_tx(struct net_device *dev)
1919 {
1920 struct fe_priv *np = netdev_priv(dev);
1921 int i;
1922
1923 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1924
1925 if (!nv_optimized(np))
1926 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1927 else
1928 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1929 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1930 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1931 np->tx_pkts_in_progress = 0;
1932 np->tx_change_owner = NULL;
1933 np->tx_end_flip = NULL;
1934 np->tx_stop = 0;
1935
1936 for (i = 0; i < np->tx_ring_size; i++) {
1937 if (!nv_optimized(np)) {
1938 np->tx_ring.orig[i].flaglen = 0;
1939 np->tx_ring.orig[i].buf = 0;
1940 } else {
1941 np->tx_ring.ex[i].flaglen = 0;
1942 np->tx_ring.ex[i].txvlan = 0;
1943 np->tx_ring.ex[i].bufhigh = 0;
1944 np->tx_ring.ex[i].buflow = 0;
1945 }
1946 np->tx_skb[i].skb = NULL;
1947 np->tx_skb[i].dma = 0;
1948 np->tx_skb[i].dma_len = 0;
1949 np->tx_skb[i].dma_single = 0;
1950 np->tx_skb[i].first_tx_desc = NULL;
1951 np->tx_skb[i].next_tx_ctx = NULL;
1952 }
1953 }
1954
1955 static int nv_init_ring(struct net_device *dev)
1956 {
1957 struct fe_priv *np = netdev_priv(dev);
1958
1959 nv_init_tx(dev);
1960 nv_init_rx(dev);
1961
1962 if (!nv_optimized(np))
1963 return nv_alloc_rx(dev);
1964 else
1965 return nv_alloc_rx_optimized(dev);
1966 }
1967
1968 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1969 {
1970 if (tx_skb->dma) {
1971 if (tx_skb->dma_single)
1972 pci_unmap_single(np->pci_dev, tx_skb->dma,
1973 tx_skb->dma_len,
1974 PCI_DMA_TODEVICE);
1975 else
1976 pci_unmap_page(np->pci_dev, tx_skb->dma,
1977 tx_skb->dma_len,
1978 PCI_DMA_TODEVICE);
1979 tx_skb->dma = 0;
1980 }
1981 }
1982
1983 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1984 {
1985 nv_unmap_txskb(np, tx_skb);
1986 if (tx_skb->skb) {
1987 dev_kfree_skb_any(tx_skb->skb);
1988 tx_skb->skb = NULL;
1989 return 1;
1990 }
1991 return 0;
1992 }
1993
1994 static void nv_drain_tx(struct net_device *dev)
1995 {
1996 struct fe_priv *np = netdev_priv(dev);
1997 unsigned int i;
1998
1999 for (i = 0; i < np->tx_ring_size; i++) {
2000 if (!nv_optimized(np)) {
2001 np->tx_ring.orig[i].flaglen = 0;
2002 np->tx_ring.orig[i].buf = 0;
2003 } else {
2004 np->tx_ring.ex[i].flaglen = 0;
2005 np->tx_ring.ex[i].txvlan = 0;
2006 np->tx_ring.ex[i].bufhigh = 0;
2007 np->tx_ring.ex[i].buflow = 0;
2008 }
2009 if (nv_release_txskb(np, &np->tx_skb[i])) {
2010 u64_stats_update_begin(&np->swstats_tx_syncp);
2011 np->stat_tx_dropped++;
2012 u64_stats_update_end(&np->swstats_tx_syncp);
2013 }
2014 np->tx_skb[i].dma = 0;
2015 np->tx_skb[i].dma_len = 0;
2016 np->tx_skb[i].dma_single = 0;
2017 np->tx_skb[i].first_tx_desc = NULL;
2018 np->tx_skb[i].next_tx_ctx = NULL;
2019 }
2020 np->tx_pkts_in_progress = 0;
2021 np->tx_change_owner = NULL;
2022 np->tx_end_flip = NULL;
2023 }
2024
2025 static void nv_drain_rx(struct net_device *dev)
2026 {
2027 struct fe_priv *np = netdev_priv(dev);
2028 int i;
2029
2030 for (i = 0; i < np->rx_ring_size; i++) {
2031 if (!nv_optimized(np)) {
2032 np->rx_ring.orig[i].flaglen = 0;
2033 np->rx_ring.orig[i].buf = 0;
2034 } else {
2035 np->rx_ring.ex[i].flaglen = 0;
2036 np->rx_ring.ex[i].txvlan = 0;
2037 np->rx_ring.ex[i].bufhigh = 0;
2038 np->rx_ring.ex[i].buflow = 0;
2039 }
2040 wmb();
2041 if (np->rx_skb[i].skb) {
2042 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2043 (skb_end_pointer(np->rx_skb[i].skb) -
2044 np->rx_skb[i].skb->data),
2045 PCI_DMA_FROMDEVICE);
2046 dev_kfree_skb(np->rx_skb[i].skb);
2047 np->rx_skb[i].skb = NULL;
2048 }
2049 }
2050 }
2051
2052 static void nv_drain_rxtx(struct net_device *dev)
2053 {
2054 nv_drain_tx(dev);
2055 nv_drain_rx(dev);
2056 }
2057
2058 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2059 {
2060 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2061 }
2062
2063 static void nv_legacybackoff_reseed(struct net_device *dev)
2064 {
2065 u8 __iomem *base = get_hwbase(dev);
2066 u32 reg;
2067 u32 low;
2068 int tx_status = 0;
2069
2070 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2071 get_random_bytes(&low, sizeof(low));
2072 reg |= low & NVREG_SLOTTIME_MASK;
2073
2074 /* Need to stop tx before change takes effect.
2075 * Caller has already gained np->lock.
2076 */
2077 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2078 if (tx_status)
2079 nv_stop_tx(dev);
2080 nv_stop_rx(dev);
2081 writel(reg, base + NvRegSlotTime);
2082 if (tx_status)
2083 nv_start_tx(dev);
2084 nv_start_rx(dev);
2085 }
2086
2087 /* Gear Backoff Seeds */
2088 #define BACKOFF_SEEDSET_ROWS 8
2089 #define BACKOFF_SEEDSET_LFSRS 15
2090
2091 /* Known Good seed sets */
2092 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2093 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2094 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2095 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2096 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2097 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2098 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2099 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2100 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2101
2102 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2103 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2104 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2105 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2106 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2107 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2108 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2109 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2110 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2111
2112 static void nv_gear_backoff_reseed(struct net_device *dev)
2113 {
2114 u8 __iomem *base = get_hwbase(dev);
2115 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2116 u32 temp, seedset, combinedSeed;
2117 int i;
2118
2119 /* Setup seed for free running LFSR */
2120 /* We are going to read the time stamp counter 3 times
2121 and swizzle bits around to increase randomness */
2122 get_random_bytes(&miniseed1, sizeof(miniseed1));
2123 miniseed1 &= 0x0fff;
2124 if (miniseed1 == 0)
2125 miniseed1 = 0xabc;
2126
2127 get_random_bytes(&miniseed2, sizeof(miniseed2));
2128 miniseed2 &= 0x0fff;
2129 if (miniseed2 == 0)
2130 miniseed2 = 0xabc;
2131 miniseed2_reversed =
2132 ((miniseed2 & 0xF00) >> 8) |
2133 (miniseed2 & 0x0F0) |
2134 ((miniseed2 & 0x00F) << 8);
2135
2136 get_random_bytes(&miniseed3, sizeof(miniseed3));
2137 miniseed3 &= 0x0fff;
2138 if (miniseed3 == 0)
2139 miniseed3 = 0xabc;
2140 miniseed3_reversed =
2141 ((miniseed3 & 0xF00) >> 8) |
2142 (miniseed3 & 0x0F0) |
2143 ((miniseed3 & 0x00F) << 8);
2144
2145 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2146 (miniseed2 ^ miniseed3_reversed);
2147
2148 /* Seeds can not be zero */
2149 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2150 combinedSeed |= 0x08;
2151 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2152 combinedSeed |= 0x8000;
2153
2154 /* No need to disable tx here */
2155 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2156 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2157 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2158 writel(temp, base + NvRegBackOffControl);
2159
2160 /* Setup seeds for all gear LFSRs. */
2161 get_random_bytes(&seedset, sizeof(seedset));
2162 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2163 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2164 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2165 temp |= main_seedset[seedset][i-1] & 0x3ff;
2166 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2167 writel(temp, base + NvRegBackOffControl);
2168 }
2169 }
2170
2171 /*
2172 * nv_start_xmit: dev->hard_start_xmit function
2173 * Called with netif_tx_lock held.
2174 */
2175 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2176 {
2177 struct fe_priv *np = netdev_priv(dev);
2178 u32 tx_flags = 0;
2179 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2180 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2181 unsigned int i;
2182 u32 offset = 0;
2183 u32 bcnt;
2184 u32 size = skb_headlen(skb);
2185 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2186 u32 empty_slots;
2187 struct ring_desc *put_tx;
2188 struct ring_desc *start_tx;
2189 struct ring_desc *prev_tx;
2190 struct nv_skb_map *prev_tx_ctx;
2191 unsigned long flags;
2192
2193 /* add fragments to entries count */
2194 for (i = 0; i < fragments; i++) {
2195 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2196
2197 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2198 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2199 }
2200
2201 spin_lock_irqsave(&np->lock, flags);
2202 empty_slots = nv_get_empty_tx_slots(np);
2203 if (unlikely(empty_slots <= entries)) {
2204 netif_stop_queue(dev);
2205 np->tx_stop = 1;
2206 spin_unlock_irqrestore(&np->lock, flags);
2207 return NETDEV_TX_BUSY;
2208 }
2209 spin_unlock_irqrestore(&np->lock, flags);
2210
2211 start_tx = put_tx = np->put_tx.orig;
2212
2213 /* setup the header buffer */
2214 do {
2215 prev_tx = put_tx;
2216 prev_tx_ctx = np->put_tx_ctx;
2217 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2218 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2219 PCI_DMA_TODEVICE);
2220 np->put_tx_ctx->dma_len = bcnt;
2221 np->put_tx_ctx->dma_single = 1;
2222 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2223 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2224
2225 tx_flags = np->tx_flags;
2226 offset += bcnt;
2227 size -= bcnt;
2228 if (unlikely(put_tx++ == np->last_tx.orig))
2229 put_tx = np->first_tx.orig;
2230 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2231 np->put_tx_ctx = np->first_tx_ctx;
2232 } while (size);
2233
2234 /* setup the fragments */
2235 for (i = 0; i < fragments; i++) {
2236 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2237 u32 frag_size = skb_frag_size(frag);
2238 offset = 0;
2239
2240 do {
2241 prev_tx = put_tx;
2242 prev_tx_ctx = np->put_tx_ctx;
2243 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2244 np->put_tx_ctx->dma = skb_frag_dma_map(
2245 &np->pci_dev->dev,
2246 frag, offset,
2247 bcnt,
2248 DMA_TO_DEVICE);
2249 np->put_tx_ctx->dma_len = bcnt;
2250 np->put_tx_ctx->dma_single = 0;
2251 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2252 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2253
2254 offset += bcnt;
2255 frag_size -= bcnt;
2256 if (unlikely(put_tx++ == np->last_tx.orig))
2257 put_tx = np->first_tx.orig;
2258 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2259 np->put_tx_ctx = np->first_tx_ctx;
2260 } while (frag_size);
2261 }
2262
2263 /* set last fragment flag */
2264 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2265
2266 /* save skb in this slot's context area */
2267 prev_tx_ctx->skb = skb;
2268
2269 if (skb_is_gso(skb))
2270 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2271 else
2272 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2273 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2274
2275 spin_lock_irqsave(&np->lock, flags);
2276
2277 /* set tx flags */
2278 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2279 np->put_tx.orig = put_tx;
2280
2281 spin_unlock_irqrestore(&np->lock, flags);
2282
2283 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2284 return NETDEV_TX_OK;
2285 }
2286
2287 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2288 struct net_device *dev)
2289 {
2290 struct fe_priv *np = netdev_priv(dev);
2291 u32 tx_flags = 0;
2292 u32 tx_flags_extra;
2293 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2294 unsigned int i;
2295 u32 offset = 0;
2296 u32 bcnt;
2297 u32 size = skb_headlen(skb);
2298 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2299 u32 empty_slots;
2300 struct ring_desc_ex *put_tx;
2301 struct ring_desc_ex *start_tx;
2302 struct ring_desc_ex *prev_tx;
2303 struct nv_skb_map *prev_tx_ctx;
2304 struct nv_skb_map *start_tx_ctx;
2305 unsigned long flags;
2306
2307 /* add fragments to entries count */
2308 for (i = 0; i < fragments; i++) {
2309 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2310
2311 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2312 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2313 }
2314
2315 spin_lock_irqsave(&np->lock, flags);
2316 empty_slots = nv_get_empty_tx_slots(np);
2317 if (unlikely(empty_slots <= entries)) {
2318 netif_stop_queue(dev);
2319 np->tx_stop = 1;
2320 spin_unlock_irqrestore(&np->lock, flags);
2321 return NETDEV_TX_BUSY;
2322 }
2323 spin_unlock_irqrestore(&np->lock, flags);
2324
2325 start_tx = put_tx = np->put_tx.ex;
2326 start_tx_ctx = np->put_tx_ctx;
2327
2328 /* setup the header buffer */
2329 do {
2330 prev_tx = put_tx;
2331 prev_tx_ctx = np->put_tx_ctx;
2332 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2333 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2334 PCI_DMA_TODEVICE);
2335 np->put_tx_ctx->dma_len = bcnt;
2336 np->put_tx_ctx->dma_single = 1;
2337 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2338 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2339 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2340
2341 tx_flags = NV_TX2_VALID;
2342 offset += bcnt;
2343 size -= bcnt;
2344 if (unlikely(put_tx++ == np->last_tx.ex))
2345 put_tx = np->first_tx.ex;
2346 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2347 np->put_tx_ctx = np->first_tx_ctx;
2348 } while (size);
2349
2350 /* setup the fragments */
2351 for (i = 0; i < fragments; i++) {
2352 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2353 u32 frag_size = skb_frag_size(frag);
2354 offset = 0;
2355
2356 do {
2357 prev_tx = put_tx;
2358 prev_tx_ctx = np->put_tx_ctx;
2359 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2360 np->put_tx_ctx->dma = skb_frag_dma_map(
2361 &np->pci_dev->dev,
2362 frag, offset,
2363 bcnt,
2364 DMA_TO_DEVICE);
2365 np->put_tx_ctx->dma_len = bcnt;
2366 np->put_tx_ctx->dma_single = 0;
2367 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2368 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2369 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2370
2371 offset += bcnt;
2372 frag_size -= bcnt;
2373 if (unlikely(put_tx++ == np->last_tx.ex))
2374 put_tx = np->first_tx.ex;
2375 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2376 np->put_tx_ctx = np->first_tx_ctx;
2377 } while (frag_size);
2378 }
2379
2380 /* set last fragment flag */
2381 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2382
2383 /* save skb in this slot's context area */
2384 prev_tx_ctx->skb = skb;
2385
2386 if (skb_is_gso(skb))
2387 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2388 else
2389 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2390 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2391
2392 /* vlan tag */
2393 if (vlan_tx_tag_present(skb))
2394 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2395 vlan_tx_tag_get(skb));
2396 else
2397 start_tx->txvlan = 0;
2398
2399 spin_lock_irqsave(&np->lock, flags);
2400
2401 if (np->tx_limit) {
2402 /* Limit the number of outstanding tx. Setup all fragments, but
2403 * do not set the VALID bit on the first descriptor. Save a pointer
2404 * to that descriptor and also for next skb_map element.
2405 */
2406
2407 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2408 if (!np->tx_change_owner)
2409 np->tx_change_owner = start_tx_ctx;
2410
2411 /* remove VALID bit */
2412 tx_flags &= ~NV_TX2_VALID;
2413 start_tx_ctx->first_tx_desc = start_tx;
2414 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2415 np->tx_end_flip = np->put_tx_ctx;
2416 } else {
2417 np->tx_pkts_in_progress++;
2418 }
2419 }
2420
2421 /* set tx flags */
2422 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2423 np->put_tx.ex = put_tx;
2424
2425 spin_unlock_irqrestore(&np->lock, flags);
2426
2427 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2428 return NETDEV_TX_OK;
2429 }
2430
2431 static inline void nv_tx_flip_ownership(struct net_device *dev)
2432 {
2433 struct fe_priv *np = netdev_priv(dev);
2434
2435 np->tx_pkts_in_progress--;
2436 if (np->tx_change_owner) {
2437 np->tx_change_owner->first_tx_desc->flaglen |=
2438 cpu_to_le32(NV_TX2_VALID);
2439 np->tx_pkts_in_progress++;
2440
2441 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2442 if (np->tx_change_owner == np->tx_end_flip)
2443 np->tx_change_owner = NULL;
2444
2445 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2446 }
2447 }
2448
2449 /*
2450 * nv_tx_done: check for completed packets, release the skbs.
2451 *
2452 * Caller must own np->lock.
2453 */
2454 static int nv_tx_done(struct net_device *dev, int limit)
2455 {
2456 struct fe_priv *np = netdev_priv(dev);
2457 u32 flags;
2458 int tx_work = 0;
2459 struct ring_desc *orig_get_tx = np->get_tx.orig;
2460
2461 while ((np->get_tx.orig != np->put_tx.orig) &&
2462 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2463 (tx_work < limit)) {
2464
2465 nv_unmap_txskb(np, np->get_tx_ctx);
2466
2467 if (np->desc_ver == DESC_VER_1) {
2468 if (flags & NV_TX_LASTPACKET) {
2469 if (flags & NV_TX_ERROR) {
2470 if ((flags & NV_TX_RETRYERROR)
2471 && !(flags & NV_TX_RETRYCOUNT_MASK))
2472 nv_legacybackoff_reseed(dev);
2473 } else {
2474 u64_stats_update_begin(&np->swstats_tx_syncp);
2475 np->stat_tx_packets++;
2476 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2477 u64_stats_update_end(&np->swstats_tx_syncp);
2478 }
2479 dev_kfree_skb_any(np->get_tx_ctx->skb);
2480 np->get_tx_ctx->skb = NULL;
2481 tx_work++;
2482 }
2483 } else {
2484 if (flags & NV_TX2_LASTPACKET) {
2485 if (flags & NV_TX2_ERROR) {
2486 if ((flags & NV_TX2_RETRYERROR)
2487 && !(flags & NV_TX2_RETRYCOUNT_MASK))
2488 nv_legacybackoff_reseed(dev);
2489 } else {
2490 u64_stats_update_begin(&np->swstats_tx_syncp);
2491 np->stat_tx_packets++;
2492 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2493 u64_stats_update_end(&np->swstats_tx_syncp);
2494 }
2495 dev_kfree_skb_any(np->get_tx_ctx->skb);
2496 np->get_tx_ctx->skb = NULL;
2497 tx_work++;
2498 }
2499 }
2500 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2501 np->get_tx.orig = np->first_tx.orig;
2502 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2503 np->get_tx_ctx = np->first_tx_ctx;
2504 }
2505 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2506 np->tx_stop = 0;
2507 netif_wake_queue(dev);
2508 }
2509 return tx_work;
2510 }
2511
2512 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2513 {
2514 struct fe_priv *np = netdev_priv(dev);
2515 u32 flags;
2516 int tx_work = 0;
2517 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2518
2519 while ((np->get_tx.ex != np->put_tx.ex) &&
2520 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2521 (tx_work < limit)) {
2522
2523 nv_unmap_txskb(np, np->get_tx_ctx);
2524
2525 if (flags & NV_TX2_LASTPACKET) {
2526 if (flags & NV_TX2_ERROR) {
2527 if ((flags & NV_TX2_RETRYERROR)
2528 && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2529 if (np->driver_data & DEV_HAS_GEAR_MODE)
2530 nv_gear_backoff_reseed(dev);
2531 else
2532 nv_legacybackoff_reseed(dev);
2533 }
2534 } else {
2535 u64_stats_update_begin(&np->swstats_tx_syncp);
2536 np->stat_tx_packets++;
2537 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2538 u64_stats_update_end(&np->swstats_tx_syncp);
2539 }
2540
2541 dev_kfree_skb_any(np->get_tx_ctx->skb);
2542 np->get_tx_ctx->skb = NULL;
2543 tx_work++;
2544
2545 if (np->tx_limit)
2546 nv_tx_flip_ownership(dev);
2547 }
2548 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2549 np->get_tx.ex = np->first_tx.ex;
2550 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2551 np->get_tx_ctx = np->first_tx_ctx;
2552 }
2553 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2554 np->tx_stop = 0;
2555 netif_wake_queue(dev);
2556 }
2557 return tx_work;
2558 }
2559
2560 /*
2561 * nv_tx_timeout: dev->tx_timeout function
2562 * Called with netif_tx_lock held.
2563 */
2564 static void nv_tx_timeout(struct net_device *dev)
2565 {
2566 struct fe_priv *np = netdev_priv(dev);
2567 u8 __iomem *base = get_hwbase(dev);
2568 u32 status;
2569 union ring_type put_tx;
2570 int saved_tx_limit;
2571
2572 if (np->msi_flags & NV_MSI_X_ENABLED)
2573 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2574 else
2575 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2576
2577 netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2578
2579 if (unlikely(debug_tx_timeout)) {
2580 int i;
2581
2582 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2583 netdev_info(dev, "Dumping tx registers\n");
2584 for (i = 0; i <= np->register_size; i += 32) {
2585 netdev_info(dev,
2586 "%3x: %08x %08x %08x %08x "
2587 "%08x %08x %08x %08x\n",
2588 i,
2589 readl(base + i + 0), readl(base + i + 4),
2590 readl(base + i + 8), readl(base + i + 12),
2591 readl(base + i + 16), readl(base + i + 20),
2592 readl(base + i + 24), readl(base + i + 28));
2593 }
2594 netdev_info(dev, "Dumping tx ring\n");
2595 for (i = 0; i < np->tx_ring_size; i += 4) {
2596 if (!nv_optimized(np)) {
2597 netdev_info(dev,
2598 "%03x: %08x %08x // %08x %08x "
2599 "// %08x %08x // %08x %08x\n",
2600 i,
2601 le32_to_cpu(np->tx_ring.orig[i].buf),
2602 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2603 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2604 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2605 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2606 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2607 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2608 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2609 } else {
2610 netdev_info(dev,
2611 "%03x: %08x %08x %08x "
2612 "// %08x %08x %08x "
2613 "// %08x %08x %08x "
2614 "// %08x %08x %08x\n",
2615 i,
2616 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2617 le32_to_cpu(np->tx_ring.ex[i].buflow),
2618 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2619 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2620 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2621 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2622 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2623 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2624 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2625 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2626 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2627 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2628 }
2629 }
2630 }
2631
2632 spin_lock_irq(&np->lock);
2633
2634 /* 1) stop tx engine */
2635 nv_stop_tx(dev);
2636
2637 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2638 saved_tx_limit = np->tx_limit;
2639 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2640 np->tx_stop = 0; /* prevent waking tx queue */
2641 if (!nv_optimized(np))
2642 nv_tx_done(dev, np->tx_ring_size);
2643 else
2644 nv_tx_done_optimized(dev, np->tx_ring_size);
2645
2646 /* save current HW position */
2647 if (np->tx_change_owner)
2648 put_tx.ex = np->tx_change_owner->first_tx_desc;
2649 else
2650 put_tx = np->put_tx;
2651
2652 /* 3) clear all tx state */
2653 nv_drain_tx(dev);
2654 nv_init_tx(dev);
2655
2656 /* 4) restore state to current HW position */
2657 np->get_tx = np->put_tx = put_tx;
2658 np->tx_limit = saved_tx_limit;
2659
2660 /* 5) restart tx engine */
2661 nv_start_tx(dev);
2662 netif_wake_queue(dev);
2663 spin_unlock_irq(&np->lock);
2664 }
2665
2666 /*
2667 * Called when the nic notices a mismatch between the actual data len on the
2668 * wire and the len indicated in the 802 header
2669 */
2670 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2671 {
2672 int hdrlen; /* length of the 802 header */
2673 int protolen; /* length as stored in the proto field */
2674
2675 /* 1) calculate len according to header */
2676 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2677 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2678 hdrlen = VLAN_HLEN;
2679 } else {
2680 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2681 hdrlen = ETH_HLEN;
2682 }
2683 if (protolen > ETH_DATA_LEN)
2684 return datalen; /* Value in proto field not a len, no checks possible */
2685
2686 protolen += hdrlen;
2687 /* consistency checks: */
2688 if (datalen > ETH_ZLEN) {
2689 if (datalen >= protolen) {
2690 /* more data on wire than in 802 header, trim of
2691 * additional data.
2692 */
2693 return protolen;
2694 } else {
2695 /* less data on wire than mentioned in header.
2696 * Discard the packet.
2697 */
2698 return -1;
2699 }
2700 } else {
2701 /* short packet. Accept only if 802 values are also short */
2702 if (protolen > ETH_ZLEN) {
2703 return -1;
2704 }
2705 return datalen;
2706 }
2707 }
2708
2709 static int nv_rx_process(struct net_device *dev, int limit)
2710 {
2711 struct fe_priv *np = netdev_priv(dev);
2712 u32 flags;
2713 int rx_work = 0;
2714 struct sk_buff *skb;
2715 int len;
2716
2717 while ((np->get_rx.orig != np->put_rx.orig) &&
2718 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2719 (rx_work < limit)) {
2720
2721 /*
2722 * the packet is for us - immediately tear down the pci mapping.
2723 * TODO: check if a prefetch of the first cacheline improves
2724 * the performance.
2725 */
2726 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2727 np->get_rx_ctx->dma_len,
2728 PCI_DMA_FROMDEVICE);
2729 skb = np->get_rx_ctx->skb;
2730 np->get_rx_ctx->skb = NULL;
2731
2732 /* look at what we actually got: */
2733 if (np->desc_ver == DESC_VER_1) {
2734 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2735 len = flags & LEN_MASK_V1;
2736 if (unlikely(flags & NV_RX_ERROR)) {
2737 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2738 len = nv_getlen(dev, skb->data, len);
2739 if (len < 0) {
2740 dev_kfree_skb(skb);
2741 goto next_pkt;
2742 }
2743 }
2744 /* framing errors are soft errors */
2745 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2746 if (flags & NV_RX_SUBSTRACT1)
2747 len--;
2748 }
2749 /* the rest are hard errors */
2750 else {
2751 if (flags & NV_RX_MISSEDFRAME) {
2752 u64_stats_update_begin(&np->swstats_rx_syncp);
2753 np->stat_rx_missed_errors++;
2754 u64_stats_update_end(&np->swstats_rx_syncp);
2755 }
2756 dev_kfree_skb(skb);
2757 goto next_pkt;
2758 }
2759 }
2760 } else {
2761 dev_kfree_skb(skb);
2762 goto next_pkt;
2763 }
2764 } else {
2765 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2766 len = flags & LEN_MASK_V2;
2767 if (unlikely(flags & NV_RX2_ERROR)) {
2768 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2769 len = nv_getlen(dev, skb->data, len);
2770 if (len < 0) {
2771 dev_kfree_skb(skb);
2772 goto next_pkt;
2773 }
2774 }
2775 /* framing errors are soft errors */
2776 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2777 if (flags & NV_RX2_SUBSTRACT1)
2778 len--;
2779 }
2780 /* the rest are hard errors */
2781 else {
2782 dev_kfree_skb(skb);
2783 goto next_pkt;
2784 }
2785 }
2786 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2787 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2788 skb->ip_summed = CHECKSUM_UNNECESSARY;
2789 } else {
2790 dev_kfree_skb(skb);
2791 goto next_pkt;
2792 }
2793 }
2794 /* got a valid packet - forward it to the network core */
2795 skb_put(skb, len);
2796 skb->protocol = eth_type_trans(skb, dev);
2797 napi_gro_receive(&np->napi, skb);
2798 u64_stats_update_begin(&np->swstats_rx_syncp);
2799 np->stat_rx_packets++;
2800 np->stat_rx_bytes += len;
2801 u64_stats_update_end(&np->swstats_rx_syncp);
2802 next_pkt:
2803 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2804 np->get_rx.orig = np->first_rx.orig;
2805 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2806 np->get_rx_ctx = np->first_rx_ctx;
2807
2808 rx_work++;
2809 }
2810
2811 return rx_work;
2812 }
2813
2814 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2815 {
2816 struct fe_priv *np = netdev_priv(dev);
2817 u32 flags;
2818 u32 vlanflags = 0;
2819 int rx_work = 0;
2820 struct sk_buff *skb;
2821 int len;
2822
2823 while ((np->get_rx.ex != np->put_rx.ex) &&
2824 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2825 (rx_work < limit)) {
2826
2827 /*
2828 * the packet is for us - immediately tear down the pci mapping.
2829 * TODO: check if a prefetch of the first cacheline improves
2830 * the performance.
2831 */
2832 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2833 np->get_rx_ctx->dma_len,
2834 PCI_DMA_FROMDEVICE);
2835 skb = np->get_rx_ctx->skb;
2836 np->get_rx_ctx->skb = NULL;
2837
2838 /* look at what we actually got: */
2839 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2840 len = flags & LEN_MASK_V2;
2841 if (unlikely(flags & NV_RX2_ERROR)) {
2842 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2843 len = nv_getlen(dev, skb->data, len);
2844 if (len < 0) {
2845 dev_kfree_skb(skb);
2846 goto next_pkt;
2847 }
2848 }
2849 /* framing errors are soft errors */
2850 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2851 if (flags & NV_RX2_SUBSTRACT1)
2852 len--;
2853 }
2854 /* the rest are hard errors */
2855 else {
2856 dev_kfree_skb(skb);
2857 goto next_pkt;
2858 }
2859 }
2860
2861 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2862 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2863 skb->ip_summed = CHECKSUM_UNNECESSARY;
2864
2865 /* got a valid packet - forward it to the network core */
2866 skb_put(skb, len);
2867 skb->protocol = eth_type_trans(skb, dev);
2868 prefetch(skb->data);
2869
2870 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2871
2872 /*
2873 * There's need to check for NETIF_F_HW_VLAN_RX here.
2874 * Even if vlan rx accel is disabled,
2875 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2876 */
2877 if (dev->features & NETIF_F_HW_VLAN_RX &&
2878 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2879 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2880
2881 __vlan_hwaccel_put_tag(skb, vid);
2882 }
2883 napi_gro_receive(&np->napi, skb);
2884 u64_stats_update_begin(&np->swstats_rx_syncp);
2885 np->stat_rx_packets++;
2886 np->stat_rx_bytes += len;
2887 u64_stats_update_end(&np->swstats_rx_syncp);
2888 } else {
2889 dev_kfree_skb(skb);
2890 }
2891 next_pkt:
2892 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2893 np->get_rx.ex = np->first_rx.ex;
2894 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2895 np->get_rx_ctx = np->first_rx_ctx;
2896
2897 rx_work++;
2898 }
2899
2900 return rx_work;
2901 }
2902
2903 static void set_bufsize(struct net_device *dev)
2904 {
2905 struct fe_priv *np = netdev_priv(dev);
2906
2907 if (dev->mtu <= ETH_DATA_LEN)
2908 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2909 else
2910 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2911 }
2912
2913 /*
2914 * nv_change_mtu: dev->change_mtu function
2915 * Called with dev_base_lock held for read.
2916 */
2917 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2918 {
2919 struct fe_priv *np = netdev_priv(dev);
2920 int old_mtu;
2921
2922 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2923 return -EINVAL;
2924
2925 old_mtu = dev->mtu;
2926 dev->mtu = new_mtu;
2927
2928 /* return early if the buffer sizes will not change */
2929 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2930 return 0;
2931 if (old_mtu == new_mtu)
2932 return 0;
2933
2934 /* synchronized against open : rtnl_lock() held by caller */
2935 if (netif_running(dev)) {
2936 u8 __iomem *base = get_hwbase(dev);
2937 /*
2938 * It seems that the nic preloads valid ring entries into an
2939 * internal buffer. The procedure for flushing everything is
2940 * guessed, there is probably a simpler approach.
2941 * Changing the MTU is a rare event, it shouldn't matter.
2942 */
2943 nv_disable_irq(dev);
2944 nv_napi_disable(dev);
2945 netif_tx_lock_bh(dev);
2946 netif_addr_lock(dev);
2947 spin_lock(&np->lock);
2948 /* stop engines */
2949 nv_stop_rxtx(dev);
2950 nv_txrx_reset(dev);
2951 /* drain rx queue */
2952 nv_drain_rxtx(dev);
2953 /* reinit driver view of the rx queue */
2954 set_bufsize(dev);
2955 if (nv_init_ring(dev)) {
2956 if (!np->in_shutdown)
2957 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2958 }
2959 /* reinit nic view of the rx queue */
2960 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2961 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2962 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2963 base + NvRegRingSizes);
2964 pci_push(base);
2965 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2966 pci_push(base);
2967
2968 /* restart rx engine */
2969 nv_start_rxtx(dev);
2970 spin_unlock(&np->lock);
2971 netif_addr_unlock(dev);
2972 netif_tx_unlock_bh(dev);
2973 nv_napi_enable(dev);
2974 nv_enable_irq(dev);
2975 }
2976 return 0;
2977 }
2978
2979 static void nv_copy_mac_to_hw(struct net_device *dev)
2980 {
2981 u8 __iomem *base = get_hwbase(dev);
2982 u32 mac[2];
2983
2984 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2985 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2986 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2987
2988 writel(mac[0], base + NvRegMacAddrA);
2989 writel(mac[1], base + NvRegMacAddrB);
2990 }
2991
2992 /*
2993 * nv_set_mac_address: dev->set_mac_address function
2994 * Called with rtnl_lock() held.
2995 */
2996 static int nv_set_mac_address(struct net_device *dev, void *addr)
2997 {
2998 struct fe_priv *np = netdev_priv(dev);
2999 struct sockaddr *macaddr = (struct sockaddr *)addr;
3000
3001 if (!is_valid_ether_addr(macaddr->sa_data))
3002 return -EADDRNOTAVAIL;
3003
3004 /* synchronized against open : rtnl_lock() held by caller */
3005 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3006
3007 if (netif_running(dev)) {
3008 netif_tx_lock_bh(dev);
3009 netif_addr_lock(dev);
3010 spin_lock_irq(&np->lock);
3011
3012 /* stop rx engine */
3013 nv_stop_rx(dev);
3014
3015 /* set mac address */
3016 nv_copy_mac_to_hw(dev);
3017
3018 /* restart rx engine */
3019 nv_start_rx(dev);
3020 spin_unlock_irq(&np->lock);
3021 netif_addr_unlock(dev);
3022 netif_tx_unlock_bh(dev);
3023 } else {
3024 nv_copy_mac_to_hw(dev);
3025 }
3026 return 0;
3027 }
3028
3029 /*
3030 * nv_set_multicast: dev->set_multicast function
3031 * Called with netif_tx_lock held.
3032 */
3033 static void nv_set_multicast(struct net_device *dev)
3034 {
3035 struct fe_priv *np = netdev_priv(dev);
3036 u8 __iomem *base = get_hwbase(dev);
3037 u32 addr[2];
3038 u32 mask[2];
3039 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3040
3041 memset(addr, 0, sizeof(addr));
3042 memset(mask, 0, sizeof(mask));
3043
3044 if (dev->flags & IFF_PROMISC) {
3045 pff |= NVREG_PFF_PROMISC;
3046 } else {
3047 pff |= NVREG_PFF_MYADDR;
3048
3049 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3050 u32 alwaysOff[2];
3051 u32 alwaysOn[2];
3052
3053 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3054 if (dev->flags & IFF_ALLMULTI) {
3055 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3056 } else {
3057 struct netdev_hw_addr *ha;
3058
3059 netdev_for_each_mc_addr(ha, dev) {
3060 unsigned char *hw_addr = ha->addr;
3061 u32 a, b;
3062
3063 a = le32_to_cpu(*(__le32 *) hw_addr);
3064 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3065 alwaysOn[0] &= a;
3066 alwaysOff[0] &= ~a;
3067 alwaysOn[1] &= b;
3068 alwaysOff[1] &= ~b;
3069 }
3070 }
3071 addr[0] = alwaysOn[0];
3072 addr[1] = alwaysOn[1];
3073 mask[0] = alwaysOn[0] | alwaysOff[0];
3074 mask[1] = alwaysOn[1] | alwaysOff[1];
3075 } else {
3076 mask[0] = NVREG_MCASTMASKA_NONE;
3077 mask[1] = NVREG_MCASTMASKB_NONE;
3078 }
3079 }
3080 addr[0] |= NVREG_MCASTADDRA_FORCE;
3081 pff |= NVREG_PFF_ALWAYS;
3082 spin_lock_irq(&np->lock);
3083 nv_stop_rx(dev);
3084 writel(addr[0], base + NvRegMulticastAddrA);
3085 writel(addr[1], base + NvRegMulticastAddrB);
3086 writel(mask[0], base + NvRegMulticastMaskA);
3087 writel(mask[1], base + NvRegMulticastMaskB);
3088 writel(pff, base + NvRegPacketFilterFlags);
3089 nv_start_rx(dev);
3090 spin_unlock_irq(&np->lock);
3091 }
3092
3093 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3094 {
3095 struct fe_priv *np = netdev_priv(dev);
3096 u8 __iomem *base = get_hwbase(dev);
3097
3098 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3099
3100 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3101 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3102 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3103 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3104 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3105 } else {
3106 writel(pff, base + NvRegPacketFilterFlags);
3107 }
3108 }
3109 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3110 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3111 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3112 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3113 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3114 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3115 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3116 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3117 /* limit the number of tx pause frames to a default of 8 */
3118 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3119 }
3120 writel(pause_enable, base + NvRegTxPauseFrame);
3121 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3122 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3123 } else {
3124 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3125 writel(regmisc, base + NvRegMisc1);
3126 }
3127 }
3128 }
3129
3130 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3131 {
3132 struct fe_priv *np = netdev_priv(dev);
3133 u8 __iomem *base = get_hwbase(dev);
3134 u32 phyreg, txreg;
3135 int mii_status;
3136
3137 np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3138 np->duplex = duplex;
3139
3140 /* see if gigabit phy */
3141 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3142 if (mii_status & PHY_GIGABIT) {
3143 np->gigabit = PHY_GIGABIT;
3144 phyreg = readl(base + NvRegSlotTime);
3145 phyreg &= ~(0x3FF00);
3146 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3147 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3148 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3149 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3150 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3151 phyreg |= NVREG_SLOTTIME_1000_FULL;
3152 writel(phyreg, base + NvRegSlotTime);
3153 }
3154
3155 phyreg = readl(base + NvRegPhyInterface);
3156 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3157 if (np->duplex == 0)
3158 phyreg |= PHY_HALF;
3159 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3160 phyreg |= PHY_100;
3161 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3162 NVREG_LINKSPEED_1000)
3163 phyreg |= PHY_1000;
3164 writel(phyreg, base + NvRegPhyInterface);
3165
3166 if (phyreg & PHY_RGMII) {
3167 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3168 NVREG_LINKSPEED_1000)
3169 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3170 else
3171 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3172 } else {
3173 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3174 }
3175 writel(txreg, base + NvRegTxDeferral);
3176
3177 if (np->desc_ver == DESC_VER_1) {
3178 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3179 } else {
3180 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3181 NVREG_LINKSPEED_1000)
3182 txreg = NVREG_TX_WM_DESC2_3_1000;
3183 else
3184 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3185 }
3186 writel(txreg, base + NvRegTxWatermark);
3187
3188 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3189 base + NvRegMisc1);
3190 pci_push(base);
3191 writel(np->linkspeed, base + NvRegLinkSpeed);
3192 pci_push(base);
3193
3194 return;
3195 }
3196
3197 /**
3198 * nv_update_linkspeed: Setup the MAC according to the link partner
3199 * @dev: Network device to be configured
3200 *
3201 * The function queries the PHY and checks if there is a link partner.
3202 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3203 * set to 10 MBit HD.
3204 *
3205 * The function returns 0 if there is no link partner and 1 if there is
3206 * a good link partner.
3207 */
3208 static int nv_update_linkspeed(struct net_device *dev)
3209 {
3210 struct fe_priv *np = netdev_priv(dev);
3211 u8 __iomem *base = get_hwbase(dev);
3212 int adv = 0;
3213 int lpa = 0;
3214 int adv_lpa, adv_pause, lpa_pause;
3215 int newls = np->linkspeed;
3216 int newdup = np->duplex;
3217 int mii_status;
3218 u32 bmcr;
3219 int retval = 0;
3220 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3221 u32 txrxFlags = 0;
3222 u32 phy_exp;
3223
3224 /* If device loopback is enabled, set carrier on and enable max link
3225 * speed.
3226 */
3227 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3228 if (bmcr & BMCR_LOOPBACK) {
3229 if (netif_running(dev)) {
3230 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3231 if (!netif_carrier_ok(dev))
3232 netif_carrier_on(dev);
3233 }
3234 return 1;
3235 }
3236
3237 /* BMSR_LSTATUS is latched, read it twice:
3238 * we want the current value.
3239 */
3240 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3241 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3242
3243 if (!(mii_status & BMSR_LSTATUS)) {
3244 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3245 newdup = 0;
3246 retval = 0;
3247 goto set_speed;
3248 }
3249
3250 if (np->autoneg == 0) {
3251 if (np->fixed_mode & LPA_100FULL) {
3252 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3253 newdup = 1;
3254 } else if (np->fixed_mode & LPA_100HALF) {
3255 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3256 newdup = 0;
3257 } else if (np->fixed_mode & LPA_10FULL) {
3258 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3259 newdup = 1;
3260 } else {
3261 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3262 newdup = 0;
3263 }
3264 retval = 1;
3265 goto set_speed;
3266 }
3267 /* check auto negotiation is complete */
3268 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3269 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3270 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3271 newdup = 0;
3272 retval = 0;
3273 goto set_speed;
3274 }
3275
3276 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3277 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3278
3279 retval = 1;
3280 if (np->gigabit == PHY_GIGABIT) {
3281 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3282 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3283
3284 if ((control_1000 & ADVERTISE_1000FULL) &&
3285 (status_1000 & LPA_1000FULL)) {
3286 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3287 newdup = 1;
3288 goto set_speed;
3289 }
3290 }
3291
3292 /* FIXME: handle parallel detection properly */
3293 adv_lpa = lpa & adv;
3294 if (adv_lpa & LPA_100FULL) {
3295 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3296 newdup = 1;
3297 } else if (adv_lpa & LPA_100HALF) {
3298 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3299 newdup = 0;
3300 } else if (adv_lpa & LPA_10FULL) {
3301 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3302 newdup = 1;
3303 } else if (adv_lpa & LPA_10HALF) {
3304 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3305 newdup = 0;
3306 } else {
3307 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3308 newdup = 0;
3309 }
3310
3311 set_speed:
3312 if (np->duplex == newdup && np->linkspeed == newls)
3313 return retval;
3314
3315 np->duplex = newdup;
3316 np->linkspeed = newls;
3317
3318 /* The transmitter and receiver must be restarted for safe update */
3319 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3320 txrxFlags |= NV_RESTART_TX;
3321 nv_stop_tx(dev);
3322 }
3323 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3324 txrxFlags |= NV_RESTART_RX;
3325 nv_stop_rx(dev);
3326 }
3327
3328 if (np->gigabit == PHY_GIGABIT) {
3329 phyreg = readl(base + NvRegSlotTime);
3330 phyreg &= ~(0x3FF00);
3331 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3332 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3333 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3334 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3335 phyreg |= NVREG_SLOTTIME_1000_FULL;
3336 writel(phyreg, base + NvRegSlotTime);
3337 }
3338
3339 phyreg = readl(base + NvRegPhyInterface);
3340 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3341 if (np->duplex == 0)
3342 phyreg |= PHY_HALF;
3343 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3344 phyreg |= PHY_100;
3345 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3346 phyreg |= PHY_1000;
3347 writel(phyreg, base + NvRegPhyInterface);
3348
3349 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3350 if (phyreg & PHY_RGMII) {
3351 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3352 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3353 } else {
3354 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3355 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3356 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3357 else
3358 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3359 } else {
3360 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3361 }
3362 }
3363 } else {
3364 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3365 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3366 else
3367 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3368 }
3369 writel(txreg, base + NvRegTxDeferral);
3370
3371 if (np->desc_ver == DESC_VER_1) {
3372 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3373 } else {
3374 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3375 txreg = NVREG_TX_WM_DESC2_3_1000;
3376 else
3377 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3378 }
3379 writel(txreg, base + NvRegTxWatermark);
3380
3381 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3382 base + NvRegMisc1);
3383 pci_push(base);
3384 writel(np->linkspeed, base + NvRegLinkSpeed);
3385 pci_push(base);
3386
3387 pause_flags = 0;
3388 /* setup pause frame */
3389 if (np->duplex != 0) {
3390 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3391 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3392 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3393
3394 switch (adv_pause) {
3395 case ADVERTISE_PAUSE_CAP:
3396 if (lpa_pause & LPA_PAUSE_CAP) {
3397 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3398 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3399 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3400 }
3401 break;
3402 case ADVERTISE_PAUSE_ASYM:
3403 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3404 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3405 break;
3406 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3407 if (lpa_pause & LPA_PAUSE_CAP) {
3408 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3409 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3410 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3411 }
3412 if (lpa_pause == LPA_PAUSE_ASYM)
3413 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3414 break;
3415 }
3416 } else {
3417 pause_flags = np->pause_flags;
3418 }
3419 }
3420 nv_update_pause(dev, pause_flags);
3421
3422 if (txrxFlags & NV_RESTART_TX)
3423 nv_start_tx(dev);
3424 if (txrxFlags & NV_RESTART_RX)
3425 nv_start_rx(dev);
3426
3427 return retval;
3428 }
3429
3430 static void nv_linkchange(struct net_device *dev)
3431 {
3432 if (nv_update_linkspeed(dev)) {
3433 if (!netif_carrier_ok(dev)) {
3434 netif_carrier_on(dev);
3435 netdev_info(dev, "link up\n");
3436 nv_txrx_gate(dev, false);
3437 nv_start_rx(dev);
3438 }
3439 } else {
3440 if (netif_carrier_ok(dev)) {
3441 netif_carrier_off(dev);
3442 netdev_info(dev, "link down\n");
3443 nv_txrx_gate(dev, true);
3444 nv_stop_rx(dev);
3445 }
3446 }
3447 }
3448
3449 static void nv_link_irq(struct net_device *dev)
3450 {
3451 u8 __iomem *base = get_hwbase(dev);
3452 u32 miistat;
3453
3454 miistat = readl(base + NvRegMIIStatus);
3455 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3456
3457 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3458 nv_linkchange(dev);
3459 }
3460
3461 static void nv_msi_workaround(struct fe_priv *np)
3462 {
3463
3464 /* Need to toggle the msi irq mask within the ethernet device,
3465 * otherwise, future interrupts will not be detected.
3466 */
3467 if (np->msi_flags & NV_MSI_ENABLED) {
3468 u8 __iomem *base = np->base;
3469
3470 writel(0, base + NvRegMSIIrqMask);
3471 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3472 }
3473 }
3474
3475 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3476 {
3477 struct fe_priv *np = netdev_priv(dev);
3478
3479 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3480 if (total_work > NV_DYNAMIC_THRESHOLD) {
3481 /* transition to poll based interrupts */
3482 np->quiet_count = 0;
3483 if (np->irqmask != NVREG_IRQMASK_CPU) {
3484 np->irqmask = NVREG_IRQMASK_CPU;
3485 return 1;
3486 }
3487 } else {
3488 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3489 np->quiet_count++;
3490 } else {
3491 /* reached a period of low activity, switch
3492 to per tx/rx packet interrupts */
3493 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3494 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3495 return 1;
3496 }
3497 }
3498 }
3499 }
3500 return 0;
3501 }
3502
3503 static irqreturn_t nv_nic_irq(int foo, void *data)
3504 {
3505 struct net_device *dev = (struct net_device *) data;
3506 struct fe_priv *np = netdev_priv(dev);
3507 u8 __iomem *base = get_hwbase(dev);
3508
3509 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3510 np->events = readl(base + NvRegIrqStatus);
3511 writel(np->events, base + NvRegIrqStatus);
3512 } else {
3513 np->events = readl(base + NvRegMSIXIrqStatus);
3514 writel(np->events, base + NvRegMSIXIrqStatus);
3515 }
3516 if (!(np->events & np->irqmask))
3517 return IRQ_NONE;
3518
3519 nv_msi_workaround(np);
3520
3521 if (napi_schedule_prep(&np->napi)) {
3522 /*
3523 * Disable further irq's (msix not enabled with napi)
3524 */
3525 writel(0, base + NvRegIrqMask);
3526 __napi_schedule(&np->napi);
3527 }
3528
3529 return IRQ_HANDLED;
3530 }
3531
3532 /**
3533 * All _optimized functions are used to help increase performance
3534 * (reduce CPU and increase throughput). They use descripter version 3,
3535 * compiler directives, and reduce memory accesses.
3536 */
3537 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3538 {
3539 struct net_device *dev = (struct net_device *) data;
3540 struct fe_priv *np = netdev_priv(dev);
3541 u8 __iomem *base = get_hwbase(dev);
3542
3543 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3544 np->events = readl(base + NvRegIrqStatus);
3545 writel(np->events, base + NvRegIrqStatus);
3546 } else {
3547 np->events = readl(base + NvRegMSIXIrqStatus);
3548 writel(np->events, base + NvRegMSIXIrqStatus);
3549 }
3550 if (!(np->events & np->irqmask))
3551 return IRQ_NONE;
3552
3553 nv_msi_workaround(np);
3554
3555 if (napi_schedule_prep(&np->napi)) {
3556 /*
3557 * Disable further irq's (msix not enabled with napi)
3558 */
3559 writel(0, base + NvRegIrqMask);
3560 __napi_schedule(&np->napi);
3561 }
3562
3563 return IRQ_HANDLED;
3564 }
3565
3566 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3567 {
3568 struct net_device *dev = (struct net_device *) data;
3569 struct fe_priv *np = netdev_priv(dev);
3570 u8 __iomem *base = get_hwbase(dev);
3571 u32 events;
3572 int i;
3573 unsigned long flags;
3574
3575 for (i = 0;; i++) {
3576 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3577 writel(events, base + NvRegMSIXIrqStatus);
3578 netdev_dbg(dev, "tx irq events: %08x\n", events);
3579 if (!(events & np->irqmask))
3580 break;
3581
3582 spin_lock_irqsave(&np->lock, flags);
3583 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3584 spin_unlock_irqrestore(&np->lock, flags);
3585
3586 if (unlikely(i > max_interrupt_work)) {
3587 spin_lock_irqsave(&np->lock, flags);
3588 /* disable interrupts on the nic */
3589 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3590 pci_push(base);
3591
3592 if (!np->in_shutdown) {
3593 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3594 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3595 }
3596 spin_unlock_irqrestore(&np->lock, flags);
3597 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3598 __func__, i);
3599 break;
3600 }
3601
3602 }
3603
3604 return IRQ_RETVAL(i);
3605 }
3606
3607 static int nv_napi_poll(struct napi_struct *napi, int budget)
3608 {
3609 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3610 struct net_device *dev = np->dev;
3611 u8 __iomem *base = get_hwbase(dev);
3612 unsigned long flags;
3613 int retcode;
3614 int rx_count, tx_work = 0, rx_work = 0;
3615
3616 do {
3617 if (!nv_optimized(np)) {
3618 spin_lock_irqsave(&np->lock, flags);
3619 tx_work += nv_tx_done(dev, np->tx_ring_size);
3620 spin_unlock_irqrestore(&np->lock, flags);
3621
3622 rx_count = nv_rx_process(dev, budget - rx_work);
3623 retcode = nv_alloc_rx(dev);
3624 } else {
3625 spin_lock_irqsave(&np->lock, flags);
3626 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3627 spin_unlock_irqrestore(&np->lock, flags);
3628
3629 rx_count = nv_rx_process_optimized(dev,
3630 budget - rx_work);
3631 retcode = nv_alloc_rx_optimized(dev);
3632 }
3633 } while (retcode == 0 &&
3634 rx_count > 0 && (rx_work += rx_count) < budget);
3635
3636 if (retcode) {
3637 spin_lock_irqsave(&np->lock, flags);
3638 if (!np->in_shutdown)
3639 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3640 spin_unlock_irqrestore(&np->lock, flags);
3641 }
3642
3643 nv_change_interrupt_mode(dev, tx_work + rx_work);
3644
3645 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3646 spin_lock_irqsave(&np->lock, flags);
3647 nv_link_irq(dev);
3648 spin_unlock_irqrestore(&np->lock, flags);
3649 }
3650 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3651 spin_lock_irqsave(&np->lock, flags);
3652 nv_linkchange(dev);
3653 spin_unlock_irqrestore(&np->lock, flags);
3654 np->link_timeout = jiffies + LINK_TIMEOUT;
3655 }
3656 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3657 spin_lock_irqsave(&np->lock, flags);
3658 if (!np->in_shutdown) {
3659 np->nic_poll_irq = np->irqmask;
3660 np->recover_error = 1;
3661 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3662 }
3663 spin_unlock_irqrestore(&np->lock, flags);
3664 napi_complete(napi);
3665 return rx_work;
3666 }
3667
3668 if (rx_work < budget) {
3669 /* re-enable interrupts
3670 (msix not enabled in napi) */
3671 napi_complete(napi);
3672
3673 writel(np->irqmask, base + NvRegIrqMask);
3674 }
3675 return rx_work;
3676 }
3677
3678 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3679 {
3680 struct net_device *dev = (struct net_device *) data;
3681 struct fe_priv *np = netdev_priv(dev);
3682 u8 __iomem *base = get_hwbase(dev);
3683 u32 events;
3684 int i;
3685 unsigned long flags;
3686
3687 for (i = 0;; i++) {
3688 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3689 writel(events, base + NvRegMSIXIrqStatus);
3690 netdev_dbg(dev, "rx irq events: %08x\n", events);
3691 if (!(events & np->irqmask))
3692 break;
3693
3694 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3695 if (unlikely(nv_alloc_rx_optimized(dev))) {
3696 spin_lock_irqsave(&np->lock, flags);
3697 if (!np->in_shutdown)
3698 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3699 spin_unlock_irqrestore(&np->lock, flags);
3700 }
3701 }
3702
3703 if (unlikely(i > max_interrupt_work)) {
3704 spin_lock_irqsave(&np->lock, flags);
3705 /* disable interrupts on the nic */
3706 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3707 pci_push(base);
3708
3709 if (!np->in_shutdown) {
3710 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3711 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3712 }
3713 spin_unlock_irqrestore(&np->lock, flags);
3714 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3715 __func__, i);
3716 break;
3717 }
3718 }
3719
3720 return IRQ_RETVAL(i);
3721 }
3722
3723 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3724 {
3725 struct net_device *dev = (struct net_device *) data;
3726 struct fe_priv *np = netdev_priv(dev);
3727 u8 __iomem *base = get_hwbase(dev);
3728 u32 events;
3729 int i;
3730 unsigned long flags;
3731
3732 for (i = 0;; i++) {
3733 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3734 writel(events, base + NvRegMSIXIrqStatus);
3735 netdev_dbg(dev, "irq events: %08x\n", events);
3736 if (!(events & np->irqmask))
3737 break;
3738
3739 /* check tx in case we reached max loop limit in tx isr */
3740 spin_lock_irqsave(&np->lock, flags);
3741 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3742 spin_unlock_irqrestore(&np->lock, flags);
3743
3744 if (events & NVREG_IRQ_LINK) {
3745 spin_lock_irqsave(&np->lock, flags);
3746 nv_link_irq(dev);
3747 spin_unlock_irqrestore(&np->lock, flags);
3748 }
3749 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3750 spin_lock_irqsave(&np->lock, flags);
3751 nv_linkchange(dev);
3752 spin_unlock_irqrestore(&np->lock, flags);
3753 np->link_timeout = jiffies + LINK_TIMEOUT;
3754 }
3755 if (events & NVREG_IRQ_RECOVER_ERROR) {
3756 spin_lock_irq(&np->lock);
3757 /* disable interrupts on the nic */
3758 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3759 pci_push(base);
3760
3761 if (!np->in_shutdown) {
3762 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3763 np->recover_error = 1;
3764 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3765 }
3766 spin_unlock_irq(&np->lock);
3767 break;
3768 }
3769 if (unlikely(i > max_interrupt_work)) {
3770 spin_lock_irqsave(&np->lock, flags);
3771 /* disable interrupts on the nic */
3772 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3773 pci_push(base);
3774
3775 if (!np->in_shutdown) {
3776 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3777 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3778 }
3779 spin_unlock_irqrestore(&np->lock, flags);
3780 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3781 __func__, i);
3782 break;
3783 }
3784
3785 }
3786
3787 return IRQ_RETVAL(i);
3788 }
3789
3790 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3791 {
3792 struct net_device *dev = (struct net_device *) data;
3793 struct fe_priv *np = netdev_priv(dev);
3794 u8 __iomem *base = get_hwbase(dev);
3795 u32 events;
3796
3797 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3798 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3799 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3800 } else {
3801 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3802 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3803 }
3804 pci_push(base);
3805 if (!(events & NVREG_IRQ_TIMER))
3806 return IRQ_RETVAL(0);
3807
3808 nv_msi_workaround(np);
3809
3810 spin_lock(&np->lock);
3811 np->intr_test = 1;
3812 spin_unlock(&np->lock);
3813
3814 return IRQ_RETVAL(1);
3815 }
3816
3817 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3818 {
3819 u8 __iomem *base = get_hwbase(dev);
3820 int i;
3821 u32 msixmap = 0;
3822
3823 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3824 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3825 * the remaining 8 interrupts.
3826 */
3827 for (i = 0; i < 8; i++) {
3828 if ((irqmask >> i) & 0x1)
3829 msixmap |= vector << (i << 2);
3830 }
3831 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3832
3833 msixmap = 0;
3834 for (i = 0; i < 8; i++) {
3835 if ((irqmask >> (i + 8)) & 0x1)
3836 msixmap |= vector << (i << 2);
3837 }
3838 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3839 }
3840
3841 static int nv_request_irq(struct net_device *dev, int intr_test)
3842 {
3843 struct fe_priv *np = get_nvpriv(dev);
3844 u8 __iomem *base = get_hwbase(dev);
3845 int ret = 1;
3846 int i;
3847 irqreturn_t (*handler)(int foo, void *data);
3848
3849 if (intr_test) {
3850 handler = nv_nic_irq_test;
3851 } else {
3852 if (nv_optimized(np))
3853 handler = nv_nic_irq_optimized;
3854 else
3855 handler = nv_nic_irq;
3856 }
3857
3858 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3859 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3860 np->msi_x_entry[i].entry = i;
3861 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3862 if (ret == 0) {
3863 np->msi_flags |= NV_MSI_X_ENABLED;
3864 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3865 /* Request irq for rx handling */
3866 sprintf(np->name_rx, "%s-rx", dev->name);
3867 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3868 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3869 netdev_info(dev,
3870 "request_irq failed for rx %d\n",
3871 ret);
3872 pci_disable_msix(np->pci_dev);
3873 np->msi_flags &= ~NV_MSI_X_ENABLED;
3874 goto out_err;
3875 }
3876 /* Request irq for tx handling */
3877 sprintf(np->name_tx, "%s-tx", dev->name);
3878 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3879 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3880 netdev_info(dev,
3881 "request_irq failed for tx %d\n",
3882 ret);
3883 pci_disable_msix(np->pci_dev);
3884 np->msi_flags &= ~NV_MSI_X_ENABLED;
3885 goto out_free_rx;
3886 }
3887 /* Request irq for link and timer handling */
3888 sprintf(np->name_other, "%s-other", dev->name);
3889 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3890 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3891 netdev_info(dev,
3892 "request_irq failed for link %d\n",
3893 ret);
3894 pci_disable_msix(np->pci_dev);
3895 np->msi_flags &= ~NV_MSI_X_ENABLED;
3896 goto out_free_tx;
3897 }
3898 /* map interrupts to their respective vector */
3899 writel(0, base + NvRegMSIXMap0);
3900 writel(0, base + NvRegMSIXMap1);
3901 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3902 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3903 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3904 } else {
3905 /* Request irq for all interrupts */
3906 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3907 netdev_info(dev,
3908 "request_irq failed %d\n",
3909 ret);
3910 pci_disable_msix(np->pci_dev);
3911 np->msi_flags &= ~NV_MSI_X_ENABLED;
3912 goto out_err;
3913 }
3914
3915 /* map interrupts to vector 0 */
3916 writel(0, base + NvRegMSIXMap0);
3917 writel(0, base + NvRegMSIXMap1);
3918 }
3919 netdev_info(dev, "MSI-X enabled\n");
3920 }
3921 }
3922 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3923 ret = pci_enable_msi(np->pci_dev);
3924 if (ret == 0) {
3925 np->msi_flags |= NV_MSI_ENABLED;
3926 dev->irq = np->pci_dev->irq;
3927 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3928 netdev_info(dev, "request_irq failed %d\n",
3929 ret);
3930 pci_disable_msi(np->pci_dev);
3931 np->msi_flags &= ~NV_MSI_ENABLED;
3932 dev->irq = np->pci_dev->irq;
3933 goto out_err;
3934 }
3935
3936 /* map interrupts to vector 0 */
3937 writel(0, base + NvRegMSIMap0);
3938 writel(0, base + NvRegMSIMap1);
3939 /* enable msi vector 0 */
3940 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3941 netdev_info(dev, "MSI enabled\n");
3942 }
3943 }
3944 if (ret != 0) {
3945 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3946 goto out_err;
3947
3948 }
3949
3950 return 0;
3951 out_free_tx:
3952 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3953 out_free_rx:
3954 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3955 out_err:
3956 return 1;
3957 }
3958
3959 static void nv_free_irq(struct net_device *dev)
3960 {
3961 struct fe_priv *np = get_nvpriv(dev);
3962 int i;
3963
3964 if (np->msi_flags & NV_MSI_X_ENABLED) {
3965 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3966 free_irq(np->msi_x_entry[i].vector, dev);
3967 pci_disable_msix(np->pci_dev);
3968 np->msi_flags &= ~NV_MSI_X_ENABLED;
3969 } else {
3970 free_irq(np->pci_dev->irq, dev);
3971 if (np->msi_flags & NV_MSI_ENABLED) {
3972 pci_disable_msi(np->pci_dev);
3973 np->msi_flags &= ~NV_MSI_ENABLED;
3974 }
3975 }
3976 }
3977
3978 static void nv_do_nic_poll(unsigned long data)
3979 {
3980 struct net_device *dev = (struct net_device *) data;
3981 struct fe_priv *np = netdev_priv(dev);
3982 u8 __iomem *base = get_hwbase(dev);
3983 u32 mask = 0;
3984
3985 /*
3986 * First disable irq(s) and then
3987 * reenable interrupts on the nic, we have to do this before calling
3988 * nv_nic_irq because that may decide to do otherwise
3989 */
3990
3991 if (!using_multi_irqs(dev)) {
3992 if (np->msi_flags & NV_MSI_X_ENABLED)
3993 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3994 else
3995 disable_irq_lockdep(np->pci_dev->irq);
3996 mask = np->irqmask;
3997 } else {
3998 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3999 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4000 mask |= NVREG_IRQ_RX_ALL;
4001 }
4002 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4003 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4004 mask |= NVREG_IRQ_TX_ALL;
4005 }
4006 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4007 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4008 mask |= NVREG_IRQ_OTHER;
4009 }
4010 }
4011 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4012
4013 if (np->recover_error) {
4014 np->recover_error = 0;
4015 netdev_info(dev, "MAC in recoverable error state\n");
4016 if (netif_running(dev)) {
4017 netif_tx_lock_bh(dev);
4018 netif_addr_lock(dev);
4019 spin_lock(&np->lock);
4020 /* stop engines */
4021 nv_stop_rxtx(dev);
4022 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4023 nv_mac_reset(dev);
4024 nv_txrx_reset(dev);
4025 /* drain rx queue */
4026 nv_drain_rxtx(dev);
4027 /* reinit driver view of the rx queue */
4028 set_bufsize(dev);
4029 if (nv_init_ring(dev)) {
4030 if (!np->in_shutdown)
4031 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4032 }
4033 /* reinit nic view of the rx queue */
4034 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4035 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4036 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4037 base + NvRegRingSizes);
4038 pci_push(base);
4039 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4040 pci_push(base);
4041 /* clear interrupts */
4042 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4043 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4044 else
4045 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4046
4047 /* restart rx engine */
4048 nv_start_rxtx(dev);
4049 spin_unlock(&np->lock);
4050 netif_addr_unlock(dev);
4051 netif_tx_unlock_bh(dev);
4052 }
4053 }
4054
4055 writel(mask, base + NvRegIrqMask);
4056 pci_push(base);
4057
4058 if (!using_multi_irqs(dev)) {
4059 np->nic_poll_irq = 0;
4060 if (nv_optimized(np))
4061 nv_nic_irq_optimized(0, dev);
4062 else
4063 nv_nic_irq(0, dev);
4064 if (np->msi_flags & NV_MSI_X_ENABLED)
4065 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4066 else
4067 enable_irq_lockdep(np->pci_dev->irq);
4068 } else {
4069 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4070 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4071 nv_nic_irq_rx(0, dev);
4072 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4073 }
4074 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4075 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4076 nv_nic_irq_tx(0, dev);
4077 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4078 }
4079 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4080 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4081 nv_nic_irq_other(0, dev);
4082 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4083 }
4084 }
4085
4086 }
4087
4088 #ifdef CONFIG_NET_POLL_CONTROLLER
4089 static void nv_poll_controller(struct net_device *dev)
4090 {
4091 nv_do_nic_poll((unsigned long) dev);
4092 }
4093 #endif
4094
4095 static void nv_do_stats_poll(unsigned long data)
4096 __acquires(&netdev_priv(dev)->hwstats_lock)
4097 __releases(&netdev_priv(dev)->hwstats_lock)
4098 {
4099 struct net_device *dev = (struct net_device *) data;
4100 struct fe_priv *np = netdev_priv(dev);
4101
4102 /* If lock is currently taken, the stats are being refreshed
4103 * and hence fresh enough */
4104 if (spin_trylock(&np->hwstats_lock)) {
4105 nv_update_stats(dev);
4106 spin_unlock(&np->hwstats_lock);
4107 }
4108
4109 if (!np->in_shutdown)
4110 mod_timer(&np->stats_poll,
4111 round_jiffies(jiffies + STATS_INTERVAL));
4112 }
4113
4114 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4115 {
4116 struct fe_priv *np = netdev_priv(dev);
4117 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4118 strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4119 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4120 }
4121
4122 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4123 {
4124 struct fe_priv *np = netdev_priv(dev);
4125 wolinfo->supported = WAKE_MAGIC;
4126
4127 spin_lock_irq(&np->lock);
4128 if (np->wolenabled)
4129 wolinfo->wolopts = WAKE_MAGIC;
4130 spin_unlock_irq(&np->lock);
4131 }
4132
4133 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4134 {
4135 struct fe_priv *np = netdev_priv(dev);
4136 u8 __iomem *base = get_hwbase(dev);
4137 u32 flags = 0;
4138
4139 if (wolinfo->wolopts == 0) {
4140 np->wolenabled = 0;
4141 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4142 np->wolenabled = 1;
4143 flags = NVREG_WAKEUPFLAGS_ENABLE;
4144 }
4145 if (netif_running(dev)) {
4146 spin_lock_irq(&np->lock);
4147 writel(flags, base + NvRegWakeUpFlags);
4148 spin_unlock_irq(&np->lock);
4149 }
4150 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4151 return 0;
4152 }
4153
4154 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4155 {
4156 struct fe_priv *np = netdev_priv(dev);
4157 u32 speed;
4158 int adv;
4159
4160 spin_lock_irq(&np->lock);
4161 ecmd->port = PORT_MII;
4162 if (!netif_running(dev)) {
4163 /* We do not track link speed / duplex setting if the
4164 * interface is disabled. Force a link check */
4165 if (nv_update_linkspeed(dev)) {
4166 if (!netif_carrier_ok(dev))
4167 netif_carrier_on(dev);
4168 } else {
4169 if (netif_carrier_ok(dev))
4170 netif_carrier_off(dev);
4171 }
4172 }
4173
4174 if (netif_carrier_ok(dev)) {
4175 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4176 case NVREG_LINKSPEED_10:
4177 speed = SPEED_10;
4178 break;
4179 case NVREG_LINKSPEED_100:
4180 speed = SPEED_100;
4181 break;
4182 case NVREG_LINKSPEED_1000:
4183 speed = SPEED_1000;
4184 break;
4185 default:
4186 speed = -1;
4187 break;
4188 }
4189 ecmd->duplex = DUPLEX_HALF;
4190 if (np->duplex)
4191 ecmd->duplex = DUPLEX_FULL;
4192 } else {
4193 speed = -1;
4194 ecmd->duplex = -1;
4195 }
4196 ethtool_cmd_speed_set(ecmd, speed);
4197 ecmd->autoneg = np->autoneg;
4198
4199 ecmd->advertising = ADVERTISED_MII;
4200 if (np->autoneg) {
4201 ecmd->advertising |= ADVERTISED_Autoneg;
4202 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4203 if (adv & ADVERTISE_10HALF)
4204 ecmd->advertising |= ADVERTISED_10baseT_Half;
4205 if (adv & ADVERTISE_10FULL)
4206 ecmd->advertising |= ADVERTISED_10baseT_Full;
4207 if (adv & ADVERTISE_100HALF)
4208 ecmd->advertising |= ADVERTISED_100baseT_Half;
4209 if (adv & ADVERTISE_100FULL)
4210 ecmd->advertising |= ADVERTISED_100baseT_Full;
4211 if (np->gigabit == PHY_GIGABIT) {
4212 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4213 if (adv & ADVERTISE_1000FULL)
4214 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4215 }
4216 }
4217 ecmd->supported = (SUPPORTED_Autoneg |
4218 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4219 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4220 SUPPORTED_MII);
4221 if (np->gigabit == PHY_GIGABIT)
4222 ecmd->supported |= SUPPORTED_1000baseT_Full;
4223
4224 ecmd->phy_address = np->phyaddr;
4225 ecmd->transceiver = XCVR_EXTERNAL;
4226
4227 /* ignore maxtxpkt, maxrxpkt for now */
4228 spin_unlock_irq(&np->lock);
4229 return 0;
4230 }
4231
4232 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4233 {
4234 struct fe_priv *np = netdev_priv(dev);
4235 u32 speed = ethtool_cmd_speed(ecmd);
4236
4237 if (ecmd->port != PORT_MII)
4238 return -EINVAL;
4239 if (ecmd->transceiver != XCVR_EXTERNAL)
4240 return -EINVAL;
4241 if (ecmd->phy_address != np->phyaddr) {
4242 /* TODO: support switching between multiple phys. Should be
4243 * trivial, but not enabled due to lack of test hardware. */
4244 return -EINVAL;
4245 }
4246 if (ecmd->autoneg == AUTONEG_ENABLE) {
4247 u32 mask;
4248
4249 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4250 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4251 if (np->gigabit == PHY_GIGABIT)
4252 mask |= ADVERTISED_1000baseT_Full;
4253
4254 if ((ecmd->advertising & mask) == 0)
4255 return -EINVAL;
4256
4257 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4258 /* Note: autonegotiation disable, speed 1000 intentionally
4259 * forbidden - no one should need that. */
4260
4261 if (speed != SPEED_10 && speed != SPEED_100)
4262 return -EINVAL;
4263 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4264 return -EINVAL;
4265 } else {
4266 return -EINVAL;
4267 }
4268
4269 netif_carrier_off(dev);
4270 if (netif_running(dev)) {
4271 unsigned long flags;
4272
4273 nv_disable_irq(dev);
4274 netif_tx_lock_bh(dev);
4275 netif_addr_lock(dev);
4276 /* with plain spinlock lockdep complains */
4277 spin_lock_irqsave(&np->lock, flags);
4278 /* stop engines */
4279 /* FIXME:
4280 * this can take some time, and interrupts are disabled
4281 * due to spin_lock_irqsave, but let's hope no daemon
4282 * is going to change the settings very often...
4283 * Worst case:
4284 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4285 * + some minor delays, which is up to a second approximately
4286 */
4287 nv_stop_rxtx(dev);
4288 spin_unlock_irqrestore(&np->lock, flags);
4289 netif_addr_unlock(dev);
4290 netif_tx_unlock_bh(dev);
4291 }
4292
4293 if (ecmd->autoneg == AUTONEG_ENABLE) {
4294 int adv, bmcr;
4295
4296 np->autoneg = 1;
4297
4298 /* advertise only what has been requested */
4299 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4300 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4301 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4302 adv |= ADVERTISE_10HALF;
4303 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4304 adv |= ADVERTISE_10FULL;
4305 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4306 adv |= ADVERTISE_100HALF;
4307 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4308 adv |= ADVERTISE_100FULL;
4309 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4310 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4311 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4312 adv |= ADVERTISE_PAUSE_ASYM;
4313 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4314
4315 if (np->gigabit == PHY_GIGABIT) {
4316 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4317 adv &= ~ADVERTISE_1000FULL;
4318 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4319 adv |= ADVERTISE_1000FULL;
4320 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4321 }
4322
4323 if (netif_running(dev))
4324 netdev_info(dev, "link down\n");
4325 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4326 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4327 bmcr |= BMCR_ANENABLE;
4328 /* reset the phy in order for settings to stick,
4329 * and cause autoneg to start */
4330 if (phy_reset(dev, bmcr)) {
4331 netdev_info(dev, "phy reset failed\n");
4332 return -EINVAL;
4333 }
4334 } else {
4335 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4336 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4337 }
4338 } else {
4339 int adv, bmcr;
4340
4341 np->autoneg = 0;
4342
4343 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4344 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4345 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4346 adv |= ADVERTISE_10HALF;
4347 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4348 adv |= ADVERTISE_10FULL;
4349 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4350 adv |= ADVERTISE_100HALF;
4351 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4352 adv |= ADVERTISE_100FULL;
4353 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4354 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4355 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4356 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4357 }
4358 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4359 adv |= ADVERTISE_PAUSE_ASYM;
4360 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4361 }
4362 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4363 np->fixed_mode = adv;
4364
4365 if (np->gigabit == PHY_GIGABIT) {
4366 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4367 adv &= ~ADVERTISE_1000FULL;
4368 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4369 }
4370
4371 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4372 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4373 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4374 bmcr |= BMCR_FULLDPLX;
4375 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4376 bmcr |= BMCR_SPEED100;
4377 if (np->phy_oui == PHY_OUI_MARVELL) {
4378 /* reset the phy in order for forced mode settings to stick */
4379 if (phy_reset(dev, bmcr)) {
4380 netdev_info(dev, "phy reset failed\n");
4381 return -EINVAL;
4382 }
4383 } else {
4384 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4385 if (netif_running(dev)) {
4386 /* Wait a bit and then reconfigure the nic. */
4387 udelay(10);
4388 nv_linkchange(dev);
4389 }
4390 }
4391 }
4392
4393 if (netif_running(dev)) {
4394 nv_start_rxtx(dev);
4395 nv_enable_irq(dev);
4396 }
4397
4398 return 0;
4399 }
4400
4401 #define FORCEDETH_REGS_VER 1
4402
4403 static int nv_get_regs_len(struct net_device *dev)
4404 {
4405 struct fe_priv *np = netdev_priv(dev);
4406 return np->register_size;
4407 }
4408
4409 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4410 {
4411 struct fe_priv *np = netdev_priv(dev);
4412 u8 __iomem *base = get_hwbase(dev);
4413 u32 *rbuf = buf;
4414 int i;
4415
4416 regs->version = FORCEDETH_REGS_VER;
4417 spin_lock_irq(&np->lock);
4418 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4419 rbuf[i] = readl(base + i*sizeof(u32));
4420 spin_unlock_irq(&np->lock);
4421 }
4422
4423 static int nv_nway_reset(struct net_device *dev)
4424 {
4425 struct fe_priv *np = netdev_priv(dev);
4426 int ret;
4427
4428 if (np->autoneg) {
4429 int bmcr;
4430
4431 netif_carrier_off(dev);
4432 if (netif_running(dev)) {
4433 nv_disable_irq(dev);
4434 netif_tx_lock_bh(dev);
4435 netif_addr_lock(dev);
4436 spin_lock(&np->lock);
4437 /* stop engines */
4438 nv_stop_rxtx(dev);
4439 spin_unlock(&np->lock);
4440 netif_addr_unlock(dev);
4441 netif_tx_unlock_bh(dev);
4442 netdev_info(dev, "link down\n");
4443 }
4444
4445 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4446 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4447 bmcr |= BMCR_ANENABLE;
4448 /* reset the phy in order for settings to stick*/
4449 if (phy_reset(dev, bmcr)) {
4450 netdev_info(dev, "phy reset failed\n");
4451 return -EINVAL;
4452 }
4453 } else {
4454 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4455 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4456 }
4457
4458 if (netif_running(dev)) {
4459 nv_start_rxtx(dev);
4460 nv_enable_irq(dev);
4461 }
4462 ret = 0;
4463 } else {
4464 ret = -EINVAL;
4465 }
4466
4467 return ret;
4468 }
4469
4470 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4471 {
4472 struct fe_priv *np = netdev_priv(dev);
4473
4474 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4475 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4476
4477 ring->rx_pending = np->rx_ring_size;
4478 ring->tx_pending = np->tx_ring_size;
4479 }
4480
4481 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4482 {
4483 struct fe_priv *np = netdev_priv(dev);
4484 u8 __iomem *base = get_hwbase(dev);
4485 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4486 dma_addr_t ring_addr;
4487
4488 if (ring->rx_pending < RX_RING_MIN ||
4489 ring->tx_pending < TX_RING_MIN ||
4490 ring->rx_mini_pending != 0 ||
4491 ring->rx_jumbo_pending != 0 ||
4492 (np->desc_ver == DESC_VER_1 &&
4493 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4494 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4495 (np->desc_ver != DESC_VER_1 &&
4496 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4497 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4498 return -EINVAL;
4499 }
4500
4501 /* allocate new rings */
4502 if (!nv_optimized(np)) {
4503 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4504 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4505 &ring_addr);
4506 } else {
4507 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4508 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4509 &ring_addr);
4510 }
4511 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4512 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4513 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4514 /* fall back to old rings */
4515 if (!nv_optimized(np)) {
4516 if (rxtx_ring)
4517 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4518 rxtx_ring, ring_addr);
4519 } else {
4520 if (rxtx_ring)
4521 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4522 rxtx_ring, ring_addr);
4523 }
4524
4525 kfree(rx_skbuff);
4526 kfree(tx_skbuff);
4527 goto exit;
4528 }
4529
4530 if (netif_running(dev)) {
4531 nv_disable_irq(dev);
4532 nv_napi_disable(dev);
4533 netif_tx_lock_bh(dev);
4534 netif_addr_lock(dev);
4535 spin_lock(&np->lock);
4536 /* stop engines */
4537 nv_stop_rxtx(dev);
4538 nv_txrx_reset(dev);
4539 /* drain queues */
4540 nv_drain_rxtx(dev);
4541 /* delete queues */
4542 free_rings(dev);
4543 }
4544
4545 /* set new values */
4546 np->rx_ring_size = ring->rx_pending;
4547 np->tx_ring_size = ring->tx_pending;
4548
4549 if (!nv_optimized(np)) {
4550 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4551 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4552 } else {
4553 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4554 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4555 }
4556 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4557 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4558 np->ring_addr = ring_addr;
4559
4560 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4561 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4562
4563 if (netif_running(dev)) {
4564 /* reinit driver view of the queues */
4565 set_bufsize(dev);
4566 if (nv_init_ring(dev)) {
4567 if (!np->in_shutdown)
4568 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4569 }
4570
4571 /* reinit nic view of the queues */
4572 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4573 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4574 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4575 base + NvRegRingSizes);
4576 pci_push(base);
4577 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4578 pci_push(base);
4579
4580 /* restart engines */
4581 nv_start_rxtx(dev);
4582 spin_unlock(&np->lock);
4583 netif_addr_unlock(dev);
4584 netif_tx_unlock_bh(dev);
4585 nv_napi_enable(dev);
4586 nv_enable_irq(dev);
4587 }
4588 return 0;
4589 exit:
4590 return -ENOMEM;
4591 }
4592
4593 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4594 {
4595 struct fe_priv *np = netdev_priv(dev);
4596
4597 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4598 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4599 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4600 }
4601
4602 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4603 {
4604 struct fe_priv *np = netdev_priv(dev);
4605 int adv, bmcr;
4606
4607 if ((!np->autoneg && np->duplex == 0) ||
4608 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4609 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4610 return -EINVAL;
4611 }
4612 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4613 netdev_info(dev, "hardware does not support tx pause frames\n");
4614 return -EINVAL;
4615 }
4616
4617 netif_carrier_off(dev);
4618 if (netif_running(dev)) {
4619 nv_disable_irq(dev);
4620 netif_tx_lock_bh(dev);
4621 netif_addr_lock(dev);
4622 spin_lock(&np->lock);
4623 /* stop engines */
4624 nv_stop_rxtx(dev);
4625 spin_unlock(&np->lock);
4626 netif_addr_unlock(dev);
4627 netif_tx_unlock_bh(dev);
4628 }
4629
4630 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4631 if (pause->rx_pause)
4632 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4633 if (pause->tx_pause)
4634 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4635
4636 if (np->autoneg && pause->autoneg) {
4637 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4638
4639 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4640 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4641 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4642 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4643 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4644 adv |= ADVERTISE_PAUSE_ASYM;
4645 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4646
4647 if (netif_running(dev))
4648 netdev_info(dev, "link down\n");
4649 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4650 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4651 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4652 } else {
4653 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4654 if (pause->rx_pause)
4655 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4656 if (pause->tx_pause)
4657 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4658
4659 if (!netif_running(dev))
4660 nv_update_linkspeed(dev);
4661 else
4662 nv_update_pause(dev, np->pause_flags);
4663 }
4664
4665 if (netif_running(dev)) {
4666 nv_start_rxtx(dev);
4667 nv_enable_irq(dev);
4668 }
4669 return 0;
4670 }
4671
4672 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4673 {
4674 struct fe_priv *np = netdev_priv(dev);
4675 unsigned long flags;
4676 u32 miicontrol;
4677 int err, retval = 0;
4678
4679 spin_lock_irqsave(&np->lock, flags);
4680 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4681 if (features & NETIF_F_LOOPBACK) {
4682 if (miicontrol & BMCR_LOOPBACK) {
4683 spin_unlock_irqrestore(&np->lock, flags);
4684 netdev_info(dev, "Loopback already enabled\n");
4685 return 0;
4686 }
4687 nv_disable_irq(dev);
4688 /* Turn on loopback mode */
4689 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4690 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4691 if (err) {
4692 retval = PHY_ERROR;
4693 spin_unlock_irqrestore(&np->lock, flags);
4694 phy_init(dev);
4695 } else {
4696 if (netif_running(dev)) {
4697 /* Force 1000 Mbps full-duplex */
4698 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4699 1);
4700 /* Force link up */
4701 netif_carrier_on(dev);
4702 }
4703 spin_unlock_irqrestore(&np->lock, flags);
4704 netdev_info(dev,
4705 "Internal PHY loopback mode enabled.\n");
4706 }
4707 } else {
4708 if (!(miicontrol & BMCR_LOOPBACK)) {
4709 spin_unlock_irqrestore(&np->lock, flags);
4710 netdev_info(dev, "Loopback already disabled\n");
4711 return 0;
4712 }
4713 nv_disable_irq(dev);
4714 /* Turn off loopback */
4715 spin_unlock_irqrestore(&np->lock, flags);
4716 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4717 phy_init(dev);
4718 }
4719 msleep(500);
4720 spin_lock_irqsave(&np->lock, flags);
4721 nv_enable_irq(dev);
4722 spin_unlock_irqrestore(&np->lock, flags);
4723
4724 return retval;
4725 }
4726
4727 static netdev_features_t nv_fix_features(struct net_device *dev,
4728 netdev_features_t features)
4729 {
4730 /* vlan is dependent on rx checksum offload */
4731 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4732 features |= NETIF_F_RXCSUM;
4733
4734 return features;
4735 }
4736
4737 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4738 {
4739 struct fe_priv *np = get_nvpriv(dev);
4740
4741 spin_lock_irq(&np->lock);
4742
4743 if (features & NETIF_F_HW_VLAN_RX)
4744 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4745 else
4746 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4747
4748 if (features & NETIF_F_HW_VLAN_TX)
4749 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4750 else
4751 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4752
4753 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4754
4755 spin_unlock_irq(&np->lock);
4756 }
4757
4758 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4759 {
4760 struct fe_priv *np = netdev_priv(dev);
4761 u8 __iomem *base = get_hwbase(dev);
4762 netdev_features_t changed = dev->features ^ features;
4763 int retval;
4764
4765 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4766 retval = nv_set_loopback(dev, features);
4767 if (retval != 0)
4768 return retval;
4769 }
4770
4771 if (changed & NETIF_F_RXCSUM) {
4772 spin_lock_irq(&np->lock);
4773
4774 if (features & NETIF_F_RXCSUM)
4775 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4776 else
4777 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4778
4779 if (netif_running(dev))
4780 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4781
4782 spin_unlock_irq(&np->lock);
4783 }
4784
4785 if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4786 nv_vlan_mode(dev, features);
4787
4788 return 0;
4789 }
4790
4791 static int nv_get_sset_count(struct net_device *dev, int sset)
4792 {
4793 struct fe_priv *np = netdev_priv(dev);
4794
4795 switch (sset) {
4796 case ETH_SS_TEST:
4797 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4798 return NV_TEST_COUNT_EXTENDED;
4799 else
4800 return NV_TEST_COUNT_BASE;
4801 case ETH_SS_STATS:
4802 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4803 return NV_DEV_STATISTICS_V3_COUNT;
4804 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4805 return NV_DEV_STATISTICS_V2_COUNT;
4806 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4807 return NV_DEV_STATISTICS_V1_COUNT;
4808 else
4809 return 0;
4810 default:
4811 return -EOPNOTSUPP;
4812 }
4813 }
4814
4815 static void nv_get_ethtool_stats(struct net_device *dev,
4816 struct ethtool_stats *estats, u64 *buffer)
4817 __acquires(&netdev_priv(dev)->hwstats_lock)
4818 __releases(&netdev_priv(dev)->hwstats_lock)
4819 {
4820 struct fe_priv *np = netdev_priv(dev);
4821
4822 spin_lock_bh(&np->hwstats_lock);
4823 nv_update_stats(dev);
4824 memcpy(buffer, &np->estats,
4825 nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4826 spin_unlock_bh(&np->hwstats_lock);
4827 }
4828
4829 static int nv_link_test(struct net_device *dev)
4830 {
4831 struct fe_priv *np = netdev_priv(dev);
4832 int mii_status;
4833
4834 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4835 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4836
4837 /* check phy link status */
4838 if (!(mii_status & BMSR_LSTATUS))
4839 return 0;
4840 else
4841 return 1;
4842 }
4843
4844 static int nv_register_test(struct net_device *dev)
4845 {
4846 u8 __iomem *base = get_hwbase(dev);
4847 int i = 0;
4848 u32 orig_read, new_read;
4849
4850 do {
4851 orig_read = readl(base + nv_registers_test[i].reg);
4852
4853 /* xor with mask to toggle bits */
4854 orig_read ^= nv_registers_test[i].mask;
4855
4856 writel(orig_read, base + nv_registers_test[i].reg);
4857
4858 new_read = readl(base + nv_registers_test[i].reg);
4859
4860 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4861 return 0;
4862
4863 /* restore original value */
4864 orig_read ^= nv_registers_test[i].mask;
4865 writel(orig_read, base + nv_registers_test[i].reg);
4866
4867 } while (nv_registers_test[++i].reg != 0);
4868
4869 return 1;
4870 }
4871
4872 static int nv_interrupt_test(struct net_device *dev)
4873 {
4874 struct fe_priv *np = netdev_priv(dev);
4875 u8 __iomem *base = get_hwbase(dev);
4876 int ret = 1;
4877 int testcnt;
4878 u32 save_msi_flags, save_poll_interval = 0;
4879
4880 if (netif_running(dev)) {
4881 /* free current irq */
4882 nv_free_irq(dev);
4883 save_poll_interval = readl(base+NvRegPollingInterval);
4884 }
4885
4886 /* flag to test interrupt handler */
4887 np->intr_test = 0;
4888
4889 /* setup test irq */
4890 save_msi_flags = np->msi_flags;
4891 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4892 np->msi_flags |= 0x001; /* setup 1 vector */
4893 if (nv_request_irq(dev, 1))
4894 return 0;
4895
4896 /* setup timer interrupt */
4897 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4898 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4899
4900 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4901
4902 /* wait for at least one interrupt */
4903 msleep(100);
4904
4905 spin_lock_irq(&np->lock);
4906
4907 /* flag should be set within ISR */
4908 testcnt = np->intr_test;
4909 if (!testcnt)
4910 ret = 2;
4911
4912 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4913 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4914 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4915 else
4916 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4917
4918 spin_unlock_irq(&np->lock);
4919
4920 nv_free_irq(dev);
4921
4922 np->msi_flags = save_msi_flags;
4923
4924 if (netif_running(dev)) {
4925 writel(save_poll_interval, base + NvRegPollingInterval);
4926 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4927 /* restore original irq */
4928 if (nv_request_irq(dev, 0))
4929 return 0;
4930 }
4931
4932 return ret;
4933 }
4934
4935 static int nv_loopback_test(struct net_device *dev)
4936 {
4937 struct fe_priv *np = netdev_priv(dev);
4938 u8 __iomem *base = get_hwbase(dev);
4939 struct sk_buff *tx_skb, *rx_skb;
4940 dma_addr_t test_dma_addr;
4941 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4942 u32 flags;
4943 int len, i, pkt_len;
4944 u8 *pkt_data;
4945 u32 filter_flags = 0;
4946 u32 misc1_flags = 0;
4947 int ret = 1;
4948
4949 if (netif_running(dev)) {
4950 nv_disable_irq(dev);
4951 filter_flags = readl(base + NvRegPacketFilterFlags);
4952 misc1_flags = readl(base + NvRegMisc1);
4953 } else {
4954 nv_txrx_reset(dev);
4955 }
4956
4957 /* reinit driver view of the rx queue */
4958 set_bufsize(dev);
4959 nv_init_ring(dev);
4960
4961 /* setup hardware for loopback */
4962 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4963 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4964
4965 /* reinit nic view of the rx queue */
4966 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4967 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4968 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4969 base + NvRegRingSizes);
4970 pci_push(base);
4971
4972 /* restart rx engine */
4973 nv_start_rxtx(dev);
4974
4975 /* setup packet for tx */
4976 pkt_len = ETH_DATA_LEN;
4977 tx_skb = dev_alloc_skb(pkt_len);
4978 if (!tx_skb) {
4979 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4980 ret = 0;
4981 goto out;
4982 }
4983 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4984 skb_tailroom(tx_skb),
4985 PCI_DMA_FROMDEVICE);
4986 pkt_data = skb_put(tx_skb, pkt_len);
4987 for (i = 0; i < pkt_len; i++)
4988 pkt_data[i] = (u8)(i & 0xff);
4989
4990 if (!nv_optimized(np)) {
4991 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4992 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4993 } else {
4994 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4995 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4996 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4997 }
4998 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4999 pci_push(get_hwbase(dev));
5000
5001 msleep(500);
5002
5003 /* check for rx of the packet */
5004 if (!nv_optimized(np)) {
5005 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5006 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5007
5008 } else {
5009 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5010 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5011 }
5012
5013 if (flags & NV_RX_AVAIL) {
5014 ret = 0;
5015 } else if (np->desc_ver == DESC_VER_1) {
5016 if (flags & NV_RX_ERROR)
5017 ret = 0;
5018 } else {
5019 if (flags & NV_RX2_ERROR)
5020 ret = 0;
5021 }
5022
5023 if (ret) {
5024 if (len != pkt_len) {
5025 ret = 0;
5026 } else {
5027 rx_skb = np->rx_skb[0].skb;
5028 for (i = 0; i < pkt_len; i++) {
5029 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5030 ret = 0;
5031 break;
5032 }
5033 }
5034 }
5035 }
5036
5037 pci_unmap_single(np->pci_dev, test_dma_addr,
5038 (skb_end_pointer(tx_skb) - tx_skb->data),
5039 PCI_DMA_TODEVICE);
5040 dev_kfree_skb_any(tx_skb);
5041 out:
5042 /* stop engines */
5043 nv_stop_rxtx(dev);
5044 nv_txrx_reset(dev);
5045 /* drain rx queue */
5046 nv_drain_rxtx(dev);
5047
5048 if (netif_running(dev)) {
5049 writel(misc1_flags, base + NvRegMisc1);
5050 writel(filter_flags, base + NvRegPacketFilterFlags);
5051 nv_enable_irq(dev);
5052 }
5053
5054 return ret;
5055 }
5056
5057 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5058 {
5059 struct fe_priv *np = netdev_priv(dev);
5060 u8 __iomem *base = get_hwbase(dev);
5061 int result;
5062 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5063
5064 if (!nv_link_test(dev)) {
5065 test->flags |= ETH_TEST_FL_FAILED;
5066 buffer[0] = 1;
5067 }
5068
5069 if (test->flags & ETH_TEST_FL_OFFLINE) {
5070 if (netif_running(dev)) {
5071 netif_stop_queue(dev);
5072 nv_napi_disable(dev);
5073 netif_tx_lock_bh(dev);
5074 netif_addr_lock(dev);
5075 spin_lock_irq(&np->lock);
5076 nv_disable_hw_interrupts(dev, np->irqmask);
5077 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5078 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5079 else
5080 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5081 /* stop engines */
5082 nv_stop_rxtx(dev);
5083 nv_txrx_reset(dev);
5084 /* drain rx queue */
5085 nv_drain_rxtx(dev);
5086 spin_unlock_irq(&np->lock);
5087 netif_addr_unlock(dev);
5088 netif_tx_unlock_bh(dev);
5089 }
5090
5091 if (!nv_register_test(dev)) {
5092 test->flags |= ETH_TEST_FL_FAILED;
5093 buffer[1] = 1;
5094 }
5095
5096 result = nv_interrupt_test(dev);
5097 if (result != 1) {
5098 test->flags |= ETH_TEST_FL_FAILED;
5099 buffer[2] = 1;
5100 }
5101 if (result == 0) {
5102 /* bail out */
5103 return;
5104 }
5105
5106 if (!nv_loopback_test(dev)) {
5107 test->flags |= ETH_TEST_FL_FAILED;
5108 buffer[3] = 1;
5109 }
5110
5111 if (netif_running(dev)) {
5112 /* reinit driver view of the rx queue */
5113 set_bufsize(dev);
5114 if (nv_init_ring(dev)) {
5115 if (!np->in_shutdown)
5116 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5117 }
5118 /* reinit nic view of the rx queue */
5119 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5120 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5121 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5122 base + NvRegRingSizes);
5123 pci_push(base);
5124 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5125 pci_push(base);
5126 /* restart rx engine */
5127 nv_start_rxtx(dev);
5128 netif_start_queue(dev);
5129 nv_napi_enable(dev);
5130 nv_enable_hw_interrupts(dev, np->irqmask);
5131 }
5132 }
5133 }
5134
5135 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5136 {
5137 switch (stringset) {
5138 case ETH_SS_STATS:
5139 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5140 break;
5141 case ETH_SS_TEST:
5142 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5143 break;
5144 }
5145 }
5146
5147 static const struct ethtool_ops ops = {
5148 .get_drvinfo = nv_get_drvinfo,
5149 .get_link = ethtool_op_get_link,
5150 .get_wol = nv_get_wol,
5151 .set_wol = nv_set_wol,
5152 .get_settings = nv_get_settings,
5153 .set_settings = nv_set_settings,
5154 .get_regs_len = nv_get_regs_len,
5155 .get_regs = nv_get_regs,
5156 .nway_reset = nv_nway_reset,
5157 .get_ringparam = nv_get_ringparam,
5158 .set_ringparam = nv_set_ringparam,
5159 .get_pauseparam = nv_get_pauseparam,
5160 .set_pauseparam = nv_set_pauseparam,
5161 .get_strings = nv_get_strings,
5162 .get_ethtool_stats = nv_get_ethtool_stats,
5163 .get_sset_count = nv_get_sset_count,
5164 .self_test = nv_self_test,
5165 };
5166
5167 /* The mgmt unit and driver use a semaphore to access the phy during init */
5168 static int nv_mgmt_acquire_sema(struct net_device *dev)
5169 {
5170 struct fe_priv *np = netdev_priv(dev);
5171 u8 __iomem *base = get_hwbase(dev);
5172 int i;
5173 u32 tx_ctrl, mgmt_sema;
5174
5175 for (i = 0; i < 10; i++) {
5176 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5177 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5178 break;
5179 msleep(500);
5180 }
5181
5182 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5183 return 0;
5184
5185 for (i = 0; i < 2; i++) {
5186 tx_ctrl = readl(base + NvRegTransmitterControl);
5187 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5188 writel(tx_ctrl, base + NvRegTransmitterControl);
5189
5190 /* verify that semaphore was acquired */
5191 tx_ctrl = readl(base + NvRegTransmitterControl);
5192 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5193 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5194 np->mgmt_sema = 1;
5195 return 1;
5196 } else
5197 udelay(50);
5198 }
5199
5200 return 0;
5201 }
5202
5203 static void nv_mgmt_release_sema(struct net_device *dev)
5204 {
5205 struct fe_priv *np = netdev_priv(dev);
5206 u8 __iomem *base = get_hwbase(dev);
5207 u32 tx_ctrl;
5208
5209 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5210 if (np->mgmt_sema) {
5211 tx_ctrl = readl(base + NvRegTransmitterControl);
5212 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5213 writel(tx_ctrl, base + NvRegTransmitterControl);
5214 }
5215 }
5216 }
5217
5218
5219 static int nv_mgmt_get_version(struct net_device *dev)
5220 {
5221 struct fe_priv *np = netdev_priv(dev);
5222 u8 __iomem *base = get_hwbase(dev);
5223 u32 data_ready = readl(base + NvRegTransmitterControl);
5224 u32 data_ready2 = 0;
5225 unsigned long start;
5226 int ready = 0;
5227
5228 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5229 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5230 start = jiffies;
5231 while (time_before(jiffies, start + 5*HZ)) {
5232 data_ready2 = readl(base + NvRegTransmitterControl);
5233 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5234 ready = 1;
5235 break;
5236 }
5237 schedule_timeout_uninterruptible(1);
5238 }
5239
5240 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5241 return 0;
5242
5243 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5244
5245 return 1;
5246 }
5247
5248 static int nv_open(struct net_device *dev)
5249 {
5250 struct fe_priv *np = netdev_priv(dev);
5251 u8 __iomem *base = get_hwbase(dev);
5252 int ret = 1;
5253 int oom, i;
5254 u32 low;
5255
5256 /* power up phy */
5257 mii_rw(dev, np->phyaddr, MII_BMCR,
5258 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5259
5260 nv_txrx_gate(dev, false);
5261 /* erase previous misconfiguration */
5262 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5263 nv_mac_reset(dev);
5264 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5265 writel(0, base + NvRegMulticastAddrB);
5266 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5267 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5268 writel(0, base + NvRegPacketFilterFlags);
5269
5270 writel(0, base + NvRegTransmitterControl);
5271 writel(0, base + NvRegReceiverControl);
5272
5273 writel(0, base + NvRegAdapterControl);
5274
5275 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5276 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5277
5278 /* initialize descriptor rings */
5279 set_bufsize(dev);
5280 oom = nv_init_ring(dev);
5281
5282 writel(0, base + NvRegLinkSpeed);
5283 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5284 nv_txrx_reset(dev);
5285 writel(0, base + NvRegUnknownSetupReg6);
5286
5287 np->in_shutdown = 0;
5288
5289 /* give hw rings */
5290 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5291 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5292 base + NvRegRingSizes);
5293
5294 writel(np->linkspeed, base + NvRegLinkSpeed);
5295 if (np->desc_ver == DESC_VER_1)
5296 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5297 else
5298 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5299 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5300 writel(np->vlanctl_bits, base + NvRegVlanControl);
5301 pci_push(base);
5302 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5303 if (reg_delay(dev, NvRegUnknownSetupReg5,
5304 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5305 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5306 netdev_info(dev,
5307 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5308
5309 writel(0, base + NvRegMIIMask);
5310 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5311 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5312
5313 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5314 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5315 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5316 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5317
5318 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5319
5320 get_random_bytes(&low, sizeof(low));
5321 low &= NVREG_SLOTTIME_MASK;
5322 if (np->desc_ver == DESC_VER_1) {
5323 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5324 } else {
5325 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5326 /* setup legacy backoff */
5327 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5328 } else {
5329 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5330 nv_gear_backoff_reseed(dev);
5331 }
5332 }
5333 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5334 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5335 if (poll_interval == -1) {
5336 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5337 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5338 else
5339 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5340 } else
5341 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5342 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5343 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5344 base + NvRegAdapterControl);
5345 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5346 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5347 if (np->wolenabled)
5348 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5349
5350 i = readl(base + NvRegPowerState);
5351 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5352 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5353
5354 pci_push(base);
5355 udelay(10);
5356 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5357
5358 nv_disable_hw_interrupts(dev, np->irqmask);
5359 pci_push(base);
5360 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5361 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5362 pci_push(base);
5363
5364 if (nv_request_irq(dev, 0))
5365 goto out_drain;
5366
5367 /* ask for interrupts */
5368 nv_enable_hw_interrupts(dev, np->irqmask);
5369
5370 spin_lock_irq(&np->lock);
5371 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5372 writel(0, base + NvRegMulticastAddrB);
5373 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5374 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5375 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5376 /* One manual link speed update: Interrupts are enabled, future link
5377 * speed changes cause interrupts and are handled by nv_link_irq().
5378 */
5379 {
5380 u32 miistat;
5381 miistat = readl(base + NvRegMIIStatus);
5382 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5383 }
5384 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5385 * to init hw */
5386 np->linkspeed = 0;
5387 ret = nv_update_linkspeed(dev);
5388 nv_start_rxtx(dev);
5389 netif_start_queue(dev);
5390 nv_napi_enable(dev);
5391
5392 if (ret) {
5393 netif_carrier_on(dev);
5394 } else {
5395 netdev_info(dev, "no link during initialization\n");
5396 netif_carrier_off(dev);
5397 }
5398 if (oom)
5399 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5400
5401 /* start statistics timer */
5402 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5403 mod_timer(&np->stats_poll,
5404 round_jiffies(jiffies + STATS_INTERVAL));
5405
5406 spin_unlock_irq(&np->lock);
5407
5408 /* If the loopback feature was set while the device was down, make sure
5409 * that it's set correctly now.
5410 */
5411 if (dev->features & NETIF_F_LOOPBACK)
5412 nv_set_loopback(dev, dev->features);
5413
5414 return 0;
5415 out_drain:
5416 nv_drain_rxtx(dev);
5417 return ret;
5418 }
5419
5420 static int nv_close(struct net_device *dev)
5421 {
5422 struct fe_priv *np = netdev_priv(dev);
5423 u8 __iomem *base;
5424
5425 spin_lock_irq(&np->lock);
5426 np->in_shutdown = 1;
5427 spin_unlock_irq(&np->lock);
5428 nv_napi_disable(dev);
5429 synchronize_irq(np->pci_dev->irq);
5430
5431 del_timer_sync(&np->oom_kick);
5432 del_timer_sync(&np->nic_poll);
5433 del_timer_sync(&np->stats_poll);
5434
5435 netif_stop_queue(dev);
5436 spin_lock_irq(&np->lock);
5437 nv_stop_rxtx(dev);
5438 nv_txrx_reset(dev);
5439
5440 /* disable interrupts on the nic or we will lock up */
5441 base = get_hwbase(dev);
5442 nv_disable_hw_interrupts(dev, np->irqmask);
5443 pci_push(base);
5444
5445 spin_unlock_irq(&np->lock);
5446
5447 nv_free_irq(dev);
5448
5449 nv_drain_rxtx(dev);
5450
5451 if (np->wolenabled || !phy_power_down) {
5452 nv_txrx_gate(dev, false);
5453 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5454 nv_start_rx(dev);
5455 } else {
5456 /* power down phy */
5457 mii_rw(dev, np->phyaddr, MII_BMCR,
5458 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5459 nv_txrx_gate(dev, true);
5460 }
5461
5462 /* FIXME: power down nic */
5463
5464 return 0;
5465 }
5466
5467 static const struct net_device_ops nv_netdev_ops = {
5468 .ndo_open = nv_open,
5469 .ndo_stop = nv_close,
5470 .ndo_get_stats64 = nv_get_stats64,
5471 .ndo_start_xmit = nv_start_xmit,
5472 .ndo_tx_timeout = nv_tx_timeout,
5473 .ndo_change_mtu = nv_change_mtu,
5474 .ndo_fix_features = nv_fix_features,
5475 .ndo_set_features = nv_set_features,
5476 .ndo_validate_addr = eth_validate_addr,
5477 .ndo_set_mac_address = nv_set_mac_address,
5478 .ndo_set_rx_mode = nv_set_multicast,
5479 #ifdef CONFIG_NET_POLL_CONTROLLER
5480 .ndo_poll_controller = nv_poll_controller,
5481 #endif
5482 };
5483
5484 static const struct net_device_ops nv_netdev_ops_optimized = {
5485 .ndo_open = nv_open,
5486 .ndo_stop = nv_close,
5487 .ndo_get_stats64 = nv_get_stats64,
5488 .ndo_start_xmit = nv_start_xmit_optimized,
5489 .ndo_tx_timeout = nv_tx_timeout,
5490 .ndo_change_mtu = nv_change_mtu,
5491 .ndo_fix_features = nv_fix_features,
5492 .ndo_set_features = nv_set_features,
5493 .ndo_validate_addr = eth_validate_addr,
5494 .ndo_set_mac_address = nv_set_mac_address,
5495 .ndo_set_rx_mode = nv_set_multicast,
5496 #ifdef CONFIG_NET_POLL_CONTROLLER
5497 .ndo_poll_controller = nv_poll_controller,
5498 #endif
5499 };
5500
5501 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5502 {
5503 struct net_device *dev;
5504 struct fe_priv *np;
5505 unsigned long addr;
5506 u8 __iomem *base;
5507 int err, i;
5508 u32 powerstate, txreg;
5509 u32 phystate_orig = 0, phystate;
5510 int phyinitialized = 0;
5511 static int printed_version;
5512
5513 if (!printed_version++)
5514 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5515 FORCEDETH_VERSION);
5516
5517 dev = alloc_etherdev(sizeof(struct fe_priv));
5518 err = -ENOMEM;
5519 if (!dev)
5520 goto out;
5521
5522 np = netdev_priv(dev);
5523 np->dev = dev;
5524 np->pci_dev = pci_dev;
5525 spin_lock_init(&np->lock);
5526 spin_lock_init(&np->hwstats_lock);
5527 SET_NETDEV_DEV(dev, &pci_dev->dev);
5528
5529 init_timer(&np->oom_kick);
5530 np->oom_kick.data = (unsigned long) dev;
5531 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5532 init_timer(&np->nic_poll);
5533 np->nic_poll.data = (unsigned long) dev;
5534 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5535 init_timer_deferrable(&np->stats_poll);
5536 np->stats_poll.data = (unsigned long) dev;
5537 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5538
5539 err = pci_enable_device(pci_dev);
5540 if (err)
5541 goto out_free;
5542
5543 pci_set_master(pci_dev);
5544
5545 err = pci_request_regions(pci_dev, DRV_NAME);
5546 if (err < 0)
5547 goto out_disable;
5548
5549 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5550 np->register_size = NV_PCI_REGSZ_VER3;
5551 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5552 np->register_size = NV_PCI_REGSZ_VER2;
5553 else
5554 np->register_size = NV_PCI_REGSZ_VER1;
5555
5556 err = -EINVAL;
5557 addr = 0;
5558 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5559 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5560 pci_resource_len(pci_dev, i) >= np->register_size) {
5561 addr = pci_resource_start(pci_dev, i);
5562 break;
5563 }
5564 }
5565 if (i == DEVICE_COUNT_RESOURCE) {
5566 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5567 goto out_relreg;
5568 }
5569
5570 /* copy of driver data */
5571 np->driver_data = id->driver_data;
5572 /* copy of device id */
5573 np->device_id = id->device;
5574
5575 /* handle different descriptor versions */
5576 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5577 /* packet format 3: supports 40-bit addressing */
5578 np->desc_ver = DESC_VER_3;
5579 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5580 if (dma_64bit) {
5581 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5582 dev_info(&pci_dev->dev,
5583 "64-bit DMA failed, using 32-bit addressing\n");
5584 else
5585 dev->features |= NETIF_F_HIGHDMA;
5586 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5587 dev_info(&pci_dev->dev,
5588 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5589 }
5590 }
5591 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5592 /* packet format 2: supports jumbo frames */
5593 np->desc_ver = DESC_VER_2;
5594 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5595 } else {
5596 /* original packet format */
5597 np->desc_ver = DESC_VER_1;
5598 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5599 }
5600
5601 np->pkt_limit = NV_PKTLIMIT_1;
5602 if (id->driver_data & DEV_HAS_LARGEDESC)
5603 np->pkt_limit = NV_PKTLIMIT_2;
5604
5605 if (id->driver_data & DEV_HAS_CHECKSUM) {
5606 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5607 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5608 NETIF_F_TSO | NETIF_F_RXCSUM;
5609 }
5610
5611 np->vlanctl_bits = 0;
5612 if (id->driver_data & DEV_HAS_VLAN) {
5613 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5614 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5615 }
5616
5617 dev->features |= dev->hw_features;
5618
5619 /* Add loopback capability to the device. */
5620 dev->hw_features |= NETIF_F_LOOPBACK;
5621
5622 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5623 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5624 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5625 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5626 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5627 }
5628
5629 err = -ENOMEM;
5630 np->base = ioremap(addr, np->register_size);
5631 if (!np->base)
5632 goto out_relreg;
5633 dev->base_addr = (unsigned long)np->base;
5634
5635 dev->irq = pci_dev->irq;
5636
5637 np->rx_ring_size = RX_RING_DEFAULT;
5638 np->tx_ring_size = TX_RING_DEFAULT;
5639
5640 if (!nv_optimized(np)) {
5641 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5642 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5643 &np->ring_addr);
5644 if (!np->rx_ring.orig)
5645 goto out_unmap;
5646 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5647 } else {
5648 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5649 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5650 &np->ring_addr);
5651 if (!np->rx_ring.ex)
5652 goto out_unmap;
5653 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5654 }
5655 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5656 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5657 if (!np->rx_skb || !np->tx_skb)
5658 goto out_freering;
5659
5660 if (!nv_optimized(np))
5661 dev->netdev_ops = &nv_netdev_ops;
5662 else
5663 dev->netdev_ops = &nv_netdev_ops_optimized;
5664
5665 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5666 SET_ETHTOOL_OPS(dev, &ops);
5667 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5668
5669 pci_set_drvdata(pci_dev, dev);
5670
5671 /* read the mac address */
5672 base = get_hwbase(dev);
5673 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5674 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5675
5676 /* check the workaround bit for correct mac address order */
5677 txreg = readl(base + NvRegTransmitPoll);
5678 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5679 /* mac address is already in correct order */
5680 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5681 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5682 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5683 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5684 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5685 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5686 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5687 /* mac address is already in correct order */
5688 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5689 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5690 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5691 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5692 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5693 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5694 /*
5695 * Set orig mac address back to the reversed version.
5696 * This flag will be cleared during low power transition.
5697 * Therefore, we should always put back the reversed address.
5698 */
5699 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5700 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5701 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5702 } else {
5703 /* need to reverse mac address to correct order */
5704 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5705 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5706 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5707 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5708 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5709 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5710 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5711 dev_dbg(&pci_dev->dev,
5712 "%s: set workaround bit for reversed mac addr\n",
5713 __func__);
5714 }
5715 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5716
5717 if (!is_valid_ether_addr(dev->perm_addr)) {
5718 /*
5719 * Bad mac address. At least one bios sets the mac address
5720 * to 01:23:45:67:89:ab
5721 */
5722 dev_err(&pci_dev->dev,
5723 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5724 dev->dev_addr);
5725 random_ether_addr(dev->dev_addr);
5726 dev_err(&pci_dev->dev,
5727 "Using random MAC address: %pM\n", dev->dev_addr);
5728 }
5729
5730 /* set mac address */
5731 nv_copy_mac_to_hw(dev);
5732
5733 /* disable WOL */
5734 writel(0, base + NvRegWakeUpFlags);
5735 np->wolenabled = 0;
5736 device_set_wakeup_enable(&pci_dev->dev, false);
5737
5738 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5739
5740 /* take phy and nic out of low power mode */
5741 powerstate = readl(base + NvRegPowerState2);
5742 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5743 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5744 pci_dev->revision >= 0xA3)
5745 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5746 writel(powerstate, base + NvRegPowerState2);
5747 }
5748
5749 if (np->desc_ver == DESC_VER_1)
5750 np->tx_flags = NV_TX_VALID;
5751 else
5752 np->tx_flags = NV_TX2_VALID;
5753
5754 np->msi_flags = 0;
5755 if ((id->driver_data & DEV_HAS_MSI) && msi)
5756 np->msi_flags |= NV_MSI_CAPABLE;
5757
5758 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5759 /* msix has had reported issues when modifying irqmask
5760 as in the case of napi, therefore, disable for now
5761 */
5762 #if 0
5763 np->msi_flags |= NV_MSI_X_CAPABLE;
5764 #endif
5765 }
5766
5767 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5768 np->irqmask = NVREG_IRQMASK_CPU;
5769 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5770 np->msi_flags |= 0x0001;
5771 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5772 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5773 /* start off in throughput mode */
5774 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5775 /* remove support for msix mode */
5776 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5777 } else {
5778 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5779 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5780 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5781 np->msi_flags |= 0x0003;
5782 }
5783
5784 if (id->driver_data & DEV_NEED_TIMERIRQ)
5785 np->irqmask |= NVREG_IRQ_TIMER;
5786 if (id->driver_data & DEV_NEED_LINKTIMER) {
5787 np->need_linktimer = 1;
5788 np->link_timeout = jiffies + LINK_TIMEOUT;
5789 } else {
5790 np->need_linktimer = 0;
5791 }
5792
5793 /* Limit the number of tx's outstanding for hw bug */
5794 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5795 np->tx_limit = 1;
5796 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5797 pci_dev->revision >= 0xA2)
5798 np->tx_limit = 0;
5799 }
5800
5801 /* clear phy state and temporarily halt phy interrupts */
5802 writel(0, base + NvRegMIIMask);
5803 phystate = readl(base + NvRegAdapterControl);
5804 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5805 phystate_orig = 1;
5806 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5807 writel(phystate, base + NvRegAdapterControl);
5808 }
5809 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5810
5811 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5812 /* management unit running on the mac? */
5813 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5814 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5815 nv_mgmt_acquire_sema(dev) &&
5816 nv_mgmt_get_version(dev)) {
5817 np->mac_in_use = 1;
5818 if (np->mgmt_version > 0)
5819 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5820 /* management unit setup the phy already? */
5821 if (np->mac_in_use &&
5822 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5823 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5824 /* phy is inited by mgmt unit */
5825 phyinitialized = 1;
5826 } else {
5827 /* we need to init the phy */
5828 }
5829 }
5830 }
5831
5832 /* find a suitable phy */
5833 for (i = 1; i <= 32; i++) {
5834 int id1, id2;
5835 int phyaddr = i & 0x1F;
5836
5837 spin_lock_irq(&np->lock);
5838 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5839 spin_unlock_irq(&np->lock);
5840 if (id1 < 0 || id1 == 0xffff)
5841 continue;
5842 spin_lock_irq(&np->lock);
5843 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5844 spin_unlock_irq(&np->lock);
5845 if (id2 < 0 || id2 == 0xffff)
5846 continue;
5847
5848 np->phy_model = id2 & PHYID2_MODEL_MASK;
5849 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5850 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5851 np->phyaddr = phyaddr;
5852 np->phy_oui = id1 | id2;
5853
5854 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5855 if (np->phy_oui == PHY_OUI_REALTEK2)
5856 np->phy_oui = PHY_OUI_REALTEK;
5857 /* Setup phy revision for Realtek */
5858 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5859 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5860
5861 break;
5862 }
5863 if (i == 33) {
5864 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5865 goto out_error;
5866 }
5867
5868 if (!phyinitialized) {
5869 /* reset it */
5870 phy_init(dev);
5871 } else {
5872 /* see if it is a gigabit phy */
5873 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5874 if (mii_status & PHY_GIGABIT)
5875 np->gigabit = PHY_GIGABIT;
5876 }
5877
5878 /* set default link speed settings */
5879 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5880 np->duplex = 0;
5881 np->autoneg = 1;
5882
5883 err = register_netdev(dev);
5884 if (err) {
5885 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5886 goto out_error;
5887 }
5888
5889 if (id->driver_data & DEV_HAS_VLAN)
5890 nv_vlan_mode(dev, dev->features);
5891
5892 netif_carrier_off(dev);
5893
5894 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5895 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5896
5897 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5898 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5899 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5900 "csum " : "",
5901 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5902 "vlan " : "",
5903 dev->features & (NETIF_F_LOOPBACK) ?
5904 "loopback " : "",
5905 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5906 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5907 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5908 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5909 np->need_linktimer ? "lnktim " : "",
5910 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5911 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5912 np->desc_ver);
5913
5914 return 0;
5915
5916 out_error:
5917 if (phystate_orig)
5918 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5919 pci_set_drvdata(pci_dev, NULL);
5920 out_freering:
5921 free_rings(dev);
5922 out_unmap:
5923 iounmap(get_hwbase(dev));
5924 out_relreg:
5925 pci_release_regions(pci_dev);
5926 out_disable:
5927 pci_disable_device(pci_dev);
5928 out_free:
5929 free_netdev(dev);
5930 out:
5931 return err;
5932 }
5933
5934 static void nv_restore_phy(struct net_device *dev)
5935 {
5936 struct fe_priv *np = netdev_priv(dev);
5937 u16 phy_reserved, mii_control;
5938
5939 if (np->phy_oui == PHY_OUI_REALTEK &&
5940 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5941 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5942 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5943 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5944 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5945 phy_reserved |= PHY_REALTEK_INIT8;
5946 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5947 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5948
5949 /* restart auto negotiation */
5950 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5951 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5952 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5953 }
5954 }
5955
5956 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5957 {
5958 struct net_device *dev = pci_get_drvdata(pci_dev);
5959 struct fe_priv *np = netdev_priv(dev);
5960 u8 __iomem *base = get_hwbase(dev);
5961
5962 /* special op: write back the misordered MAC address - otherwise
5963 * the next nv_probe would see a wrong address.
5964 */
5965 writel(np->orig_mac[0], base + NvRegMacAddrA);
5966 writel(np->orig_mac[1], base + NvRegMacAddrB);
5967 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5968 base + NvRegTransmitPoll);
5969 }
5970
5971 static void __devexit nv_remove(struct pci_dev *pci_dev)
5972 {
5973 struct net_device *dev = pci_get_drvdata(pci_dev);
5974
5975 unregister_netdev(dev);
5976
5977 nv_restore_mac_addr(pci_dev);
5978
5979 /* restore any phy related changes */
5980 nv_restore_phy(dev);
5981
5982 nv_mgmt_release_sema(dev);
5983
5984 /* free all structures */
5985 free_rings(dev);
5986 iounmap(get_hwbase(dev));
5987 pci_release_regions(pci_dev);
5988 pci_disable_device(pci_dev);
5989 free_netdev(dev);
5990 pci_set_drvdata(pci_dev, NULL);
5991 }
5992
5993 #ifdef CONFIG_PM_SLEEP
5994 static int nv_suspend(struct device *device)
5995 {
5996 struct pci_dev *pdev = to_pci_dev(device);
5997 struct net_device *dev = pci_get_drvdata(pdev);
5998 struct fe_priv *np = netdev_priv(dev);
5999 u8 __iomem *base = get_hwbase(dev);
6000 int i;
6001
6002 if (netif_running(dev)) {
6003 /* Gross. */
6004 nv_close(dev);
6005 }
6006 netif_device_detach(dev);
6007
6008 /* save non-pci configuration space */
6009 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6010 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6011
6012 return 0;
6013 }
6014
6015 static int nv_resume(struct device *device)
6016 {
6017 struct pci_dev *pdev = to_pci_dev(device);
6018 struct net_device *dev = pci_get_drvdata(pdev);
6019 struct fe_priv *np = netdev_priv(dev);
6020 u8 __iomem *base = get_hwbase(dev);
6021 int i, rc = 0;
6022
6023 /* restore non-pci configuration space */
6024 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6025 writel(np->saved_config_space[i], base+i*sizeof(u32));
6026
6027 if (np->driver_data & DEV_NEED_MSI_FIX)
6028 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6029
6030 /* restore phy state, including autoneg */
6031 phy_init(dev);
6032
6033 netif_device_attach(dev);
6034 if (netif_running(dev)) {
6035 rc = nv_open(dev);
6036 nv_set_multicast(dev);
6037 }
6038 return rc;
6039 }
6040
6041 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6042 #define NV_PM_OPS (&nv_pm_ops)
6043
6044 #else
6045 #define NV_PM_OPS NULL
6046 #endif /* CONFIG_PM_SLEEP */
6047
6048 #ifdef CONFIG_PM
6049 static void nv_shutdown(struct pci_dev *pdev)
6050 {
6051 struct net_device *dev = pci_get_drvdata(pdev);
6052 struct fe_priv *np = netdev_priv(dev);
6053
6054 if (netif_running(dev))
6055 nv_close(dev);
6056
6057 /*
6058 * Restore the MAC so a kernel started by kexec won't get confused.
6059 * If we really go for poweroff, we must not restore the MAC,
6060 * otherwise the MAC for WOL will be reversed at least on some boards.
6061 */
6062 if (system_state != SYSTEM_POWER_OFF)
6063 nv_restore_mac_addr(pdev);
6064
6065 pci_disable_device(pdev);
6066 /*
6067 * Apparently it is not possible to reinitialise from D3 hot,
6068 * only put the device into D3 if we really go for poweroff.
6069 */
6070 if (system_state == SYSTEM_POWER_OFF) {
6071 pci_wake_from_d3(pdev, np->wolenabled);
6072 pci_set_power_state(pdev, PCI_D3hot);
6073 }
6074 }
6075 #else
6076 #define nv_shutdown NULL
6077 #endif /* CONFIG_PM */
6078
6079 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6080 { /* nForce Ethernet Controller */
6081 PCI_DEVICE(0x10DE, 0x01C3),
6082 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6083 },
6084 { /* nForce2 Ethernet Controller */
6085 PCI_DEVICE(0x10DE, 0x0066),
6086 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6087 },
6088 { /* nForce3 Ethernet Controller */
6089 PCI_DEVICE(0x10DE, 0x00D6),
6090 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6091 },
6092 { /* nForce3 Ethernet Controller */
6093 PCI_DEVICE(0x10DE, 0x0086),
6094 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6095 },
6096 { /* nForce3 Ethernet Controller */
6097 PCI_DEVICE(0x10DE, 0x008C),
6098 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6099 },
6100 { /* nForce3 Ethernet Controller */
6101 PCI_DEVICE(0x10DE, 0x00E6),
6102 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6103 },
6104 { /* nForce3 Ethernet Controller */
6105 PCI_DEVICE(0x10DE, 0x00DF),
6106 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6107 },
6108 { /* CK804 Ethernet Controller */
6109 PCI_DEVICE(0x10DE, 0x0056),
6110 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6111 },
6112 { /* CK804 Ethernet Controller */
6113 PCI_DEVICE(0x10DE, 0x0057),
6114 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6115 },
6116 { /* MCP04 Ethernet Controller */
6117 PCI_DEVICE(0x10DE, 0x0037),
6118 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6119 },
6120 { /* MCP04 Ethernet Controller */
6121 PCI_DEVICE(0x10DE, 0x0038),
6122 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6123 },
6124 { /* MCP51 Ethernet Controller */
6125 PCI_DEVICE(0x10DE, 0x0268),
6126 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6127 },
6128 { /* MCP51 Ethernet Controller */
6129 PCI_DEVICE(0x10DE, 0x0269),
6130 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6131 },
6132 { /* MCP55 Ethernet Controller */
6133 PCI_DEVICE(0x10DE, 0x0372),
6134 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6135 },
6136 { /* MCP55 Ethernet Controller */
6137 PCI_DEVICE(0x10DE, 0x0373),
6138 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6139 },
6140 { /* MCP61 Ethernet Controller */
6141 PCI_DEVICE(0x10DE, 0x03E5),
6142 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6143 },
6144 { /* MCP61 Ethernet Controller */
6145 PCI_DEVICE(0x10DE, 0x03E6),
6146 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6147 },
6148 { /* MCP61 Ethernet Controller */
6149 PCI_DEVICE(0x10DE, 0x03EE),
6150 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6151 },
6152 { /* MCP61 Ethernet Controller */
6153 PCI_DEVICE(0x10DE, 0x03EF),
6154 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6155 },
6156 { /* MCP65 Ethernet Controller */
6157 PCI_DEVICE(0x10DE, 0x0450),
6158 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6159 },
6160 { /* MCP65 Ethernet Controller */
6161 PCI_DEVICE(0x10DE, 0x0451),
6162 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6163 },
6164 { /* MCP65 Ethernet Controller */
6165 PCI_DEVICE(0x10DE, 0x0452),
6166 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6167 },
6168 { /* MCP65 Ethernet Controller */
6169 PCI_DEVICE(0x10DE, 0x0453),
6170 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6171 },
6172 { /* MCP67 Ethernet Controller */
6173 PCI_DEVICE(0x10DE, 0x054C),
6174 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6175 },
6176 { /* MCP67 Ethernet Controller */
6177 PCI_DEVICE(0x10DE, 0x054D),
6178 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6179 },
6180 { /* MCP67 Ethernet Controller */
6181 PCI_DEVICE(0x10DE, 0x054E),
6182 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6183 },
6184 { /* MCP67 Ethernet Controller */
6185 PCI_DEVICE(0x10DE, 0x054F),
6186 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6187 },
6188 { /* MCP73 Ethernet Controller */
6189 PCI_DEVICE(0x10DE, 0x07DC),
6190 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6191 },
6192 { /* MCP73 Ethernet Controller */
6193 PCI_DEVICE(0x10DE, 0x07DD),
6194 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6195 },
6196 { /* MCP73 Ethernet Controller */
6197 PCI_DEVICE(0x10DE, 0x07DE),
6198 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6199 },
6200 { /* MCP73 Ethernet Controller */
6201 PCI_DEVICE(0x10DE, 0x07DF),
6202 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6203 },
6204 { /* MCP77 Ethernet Controller */
6205 PCI_DEVICE(0x10DE, 0x0760),
6206 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6207 },
6208 { /* MCP77 Ethernet Controller */
6209 PCI_DEVICE(0x10DE, 0x0761),
6210 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6211 },
6212 { /* MCP77 Ethernet Controller */
6213 PCI_DEVICE(0x10DE, 0x0762),
6214 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6215 },
6216 { /* MCP77 Ethernet Controller */
6217 PCI_DEVICE(0x10DE, 0x0763),
6218 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6219 },
6220 { /* MCP79 Ethernet Controller */
6221 PCI_DEVICE(0x10DE, 0x0AB0),
6222 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6223 },
6224 { /* MCP79 Ethernet Controller */
6225 PCI_DEVICE(0x10DE, 0x0AB1),
6226 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6227 },
6228 { /* MCP79 Ethernet Controller */
6229 PCI_DEVICE(0x10DE, 0x0AB2),
6230 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6231 },
6232 { /* MCP79 Ethernet Controller */
6233 PCI_DEVICE(0x10DE, 0x0AB3),
6234 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6235 },
6236 { /* MCP89 Ethernet Controller */
6237 PCI_DEVICE(0x10DE, 0x0D7D),
6238 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6239 },
6240 {0,},
6241 };
6242
6243 static struct pci_driver driver = {
6244 .name = DRV_NAME,
6245 .id_table = pci_tbl,
6246 .probe = nv_probe,
6247 .remove = __devexit_p(nv_remove),
6248 .shutdown = nv_shutdown,
6249 .driver.pm = NV_PM_OPS,
6250 };
6251
6252 static int __init init_nic(void)
6253 {
6254 return pci_register_driver(&driver);
6255 }
6256
6257 static void __exit exit_nic(void)
6258 {
6259 pci_unregister_driver(&driver);
6260 }
6261
6262 module_param(max_interrupt_work, int, 0);
6263 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6264 module_param(optimization_mode, int, 0);
6265 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6266 module_param(poll_interval, int, 0);
6267 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6268 module_param(msi, int, 0);
6269 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6270 module_param(msix, int, 0);
6271 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6272 module_param(dma_64bit, int, 0);
6273 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6274 module_param(phy_cross, int, 0);
6275 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6276 module_param(phy_power_down, int, 0);
6277 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6278 module_param(debug_tx_timeout, bool, 0);
6279 MODULE_PARM_DESC(debug_tx_timeout,
6280 "Dump tx related registers and ring when tx_timeout happens");
6281
6282 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6283 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6284 MODULE_LICENSE("GPL");
6285
6286 MODULE_DEVICE_TABLE(pci, pci_tbl);
6287
6288 module_init(init_nic);
6289 module_exit(exit_nic);
CJK support for tty framebuffer vt