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firewire: ohci: add a function for reading PHY registers
[linux-2.6/cjktty.git] / drivers / firewire / ohci.c
blob8ebccda94df9889e401514f406dbb6d54d43c955
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/byteorder.h>
42 #include <asm/page.h>
43 #include <asm/system.h>
44
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
47 #endif
48
49 #include "core.h"
50 #include "ohci.h"
51
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
65
66 struct descriptor {
67 __le16 req_count;
68 __le16 control;
69 __le32 data_address;
70 __le32 branch_address;
71 __le16 res_count;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
74
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
79
80 struct ar_buffer {
81 struct descriptor descriptor;
82 struct ar_buffer *next;
83 __le32 data[0];
84 };
85
86 struct ar_context {
87 struct fw_ohci *ohci;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
90 void *pointer;
91 u32 regs;
92 struct tasklet_struct tasklet;
93 };
94
95 struct context;
96
97 typedef int (*descriptor_callback_t)(struct context *ctx,
98 struct descriptor *d,
99 struct descriptor *last);
100
101 /*
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
104 */
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
108 size_t buffer_size;
109 size_t used;
110 struct descriptor buffer[0];
111 };
112
113 struct context {
114 struct fw_ohci *ohci;
115 u32 regs;
116 int total_allocation;
117
118 /*
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
121 * free buffers.
122 */
123 struct list_head buffer_list;
124
125 /*
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
128 */
129 struct descriptor_buffer *buffer_tail;
130
131 /*
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
134 */
135 struct descriptor *last;
136
137 /*
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
140 */
141 struct descriptor *prev;
142
143 descriptor_callback_t callback;
144
145 struct tasklet_struct tasklet;
146 };
147
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
154
155 struct iso_context {
156 struct fw_iso_context base;
157 struct context context;
158 int excess_bytes;
159 void *header;
160 size_t header_length;
161 };
162
163 #define CONFIG_ROM_SIZE 1024
164
165 struct fw_ohci {
166 struct fw_card card;
167
168 __iomem char *registers;
169 int node_id;
170 int generation;
171 int request_generation; /* for timestamping incoming requests */
172 unsigned quirks;
173
174 /*
175 * Spinlock for accessing fw_ohci data. Never call out of
176 * this driver with this lock held.
177 */
178 spinlock_t lock;
179
180 struct ar_context ar_request_ctx;
181 struct ar_context ar_response_ctx;
182 struct context at_request_ctx;
183 struct context at_response_ctx;
184
185 u32 it_context_mask;
186 struct iso_context *it_context_list;
187 u64 ir_context_channels;
188 u32 ir_context_mask;
189 struct iso_context *ir_context_list;
190
191 __be32 *config_rom;
192 dma_addr_t config_rom_bus;
193 __be32 *next_config_rom;
194 dma_addr_t next_config_rom_bus;
195 __be32 next_header;
196
197 __le32 *self_id_cpu;
198 dma_addr_t self_id_bus;
199 struct tasklet_struct bus_reset_tasklet;
200
201 u32 self_id_buffer[512];
202 };
203
204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
205 {
206 return container_of(card, struct fw_ohci, card);
207 }
208
209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
210 #define IR_CONTEXT_BUFFER_FILL 0x80000000
211 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
213 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
214 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
215
216 #define CONTEXT_RUN 0x8000
217 #define CONTEXT_WAKE 0x1000
218 #define CONTEXT_DEAD 0x0800
219 #define CONTEXT_ACTIVE 0x0400
220
221 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
222 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
223 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
224
225 #define OHCI1394_REGISTER_SIZE 0x800
226 #define OHCI_LOOP_COUNT 500
227 #define OHCI1394_PCI_HCI_Control 0x40
228 #define SELF_ID_BUF_SIZE 0x800
229 #define OHCI_TCODE_PHY_PACKET 0x0e
230 #define OHCI_VERSION_1_1 0x010010
231
232 static char ohci_driver_name[] = KBUILD_MODNAME;
233
234 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
235
236 #define QUIRK_CYCLE_TIMER 1
237 #define QUIRK_RESET_PACKET 2
238 #define QUIRK_BE_HEADERS 4
239
240 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
241 static const struct {
242 unsigned short vendor, device, flags;
243 } ohci_quirks[] = {
244 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
245 QUIRK_RESET_PACKET},
246 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
247 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
248 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
249 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
250 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
251 };
252
253 /* This overrides anything that was found in ohci_quirks[]. */
254 static int param_quirks;
255 module_param_named(quirks, param_quirks, int, 0644);
256 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
257 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
258 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
259 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
260 ")");
261
262 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
263
264 #define OHCI_PARAM_DEBUG_AT_AR 1
265 #define OHCI_PARAM_DEBUG_SELFIDS 2
266 #define OHCI_PARAM_DEBUG_IRQS 4
267 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
268
269 static int param_debug;
270 module_param_named(debug, param_debug, int, 0644);
271 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
272 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
273 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
274 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
275 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
276 ", or a combination, or all = -1)");
277
278 static void log_irqs(u32 evt)
279 {
280 if (likely(!(param_debug &
281 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
282 return;
283
284 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
285 !(evt & OHCI1394_busReset))
286 return;
287
288 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
289 evt & OHCI1394_selfIDComplete ? " selfID" : "",
290 evt & OHCI1394_RQPkt ? " AR_req" : "",
291 evt & OHCI1394_RSPkt ? " AR_resp" : "",
292 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
293 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
294 evt & OHCI1394_isochRx ? " IR" : "",
295 evt & OHCI1394_isochTx ? " IT" : "",
296 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
297 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
298 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
299 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
300 evt & OHCI1394_busReset ? " busReset" : "",
301 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
302 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
303 OHCI1394_respTxComplete | OHCI1394_isochRx |
304 OHCI1394_isochTx | OHCI1394_postedWriteErr |
305 OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
306 OHCI1394_regAccessFail | OHCI1394_busReset)
307 ? " ?" : "");
308 }
309
310 static const char *speed[] = {
311 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
312 };
313 static const char *power[] = {
314 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
315 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
316 };
317 static const char port[] = { '.', '-', 'p', 'c', };
318
319 static char _p(u32 *s, int shift)
320 {
321 return port[*s >> shift & 3];
322 }
323
324 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
325 {
326 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
327 return;
328
329 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
330 self_id_count, generation, node_id);
331
332 for (; self_id_count--; ++s)
333 if ((*s & 1 << 23) == 0)
334 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
335 "%s gc=%d %s %s%s%s\n",
336 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
337 speed[*s >> 14 & 3], *s >> 16 & 63,
338 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
339 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
340 else
341 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
342 *s, *s >> 24 & 63,
343 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
344 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
345 }
346
347 static const char *evts[] = {
348 [0x00] = "evt_no_status", [0x01] = "-reserved-",
349 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
350 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
351 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
352 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
353 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
354 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
355 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
356 [0x10] = "-reserved-", [0x11] = "ack_complete",
357 [0x12] = "ack_pending ", [0x13] = "-reserved-",
358 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
359 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
360 [0x18] = "-reserved-", [0x19] = "-reserved-",
361 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
362 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
363 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
364 [0x20] = "pending/cancelled",
365 };
366 static const char *tcodes[] = {
367 [0x0] = "QW req", [0x1] = "BW req",
368 [0x2] = "W resp", [0x3] = "-reserved-",
369 [0x4] = "QR req", [0x5] = "BR req",
370 [0x6] = "QR resp", [0x7] = "BR resp",
371 [0x8] = "cycle start", [0x9] = "Lk req",
372 [0xa] = "async stream packet", [0xb] = "Lk resp",
373 [0xc] = "-reserved-", [0xd] = "-reserved-",
374 [0xe] = "link internal", [0xf] = "-reserved-",
375 };
376 static const char *phys[] = {
377 [0x0] = "phy config packet", [0x1] = "link-on packet",
378 [0x2] = "self-id packet", [0x3] = "-reserved-",
379 };
380
381 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
382 {
383 int tcode = header[0] >> 4 & 0xf;
384 char specific[12];
385
386 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
387 return;
388
389 if (unlikely(evt >= ARRAY_SIZE(evts)))
390 evt = 0x1f;
391
392 if (evt == OHCI1394_evt_bus_reset) {
393 fw_notify("A%c evt_bus_reset, generation %d\n",
394 dir, (header[2] >> 16) & 0xff);
395 return;
396 }
397
398 if (header[0] == ~header[1]) {
399 fw_notify("A%c %s, %s, %08x\n",
400 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
401 return;
402 }
403
404 switch (tcode) {
405 case 0x0: case 0x6: case 0x8:
406 snprintf(specific, sizeof(specific), " = %08x",
407 be32_to_cpu((__force __be32)header[3]));
408 break;
409 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
410 snprintf(specific, sizeof(specific), " %x,%x",
411 header[3] >> 16, header[3] & 0xffff);
412 break;
413 default:
414 specific[0] = '\0';
415 }
416
417 switch (tcode) {
418 case 0xe: case 0xa:
419 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
420 break;
421 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
422 fw_notify("A%c spd %x tl %02x, "
423 "%04x -> %04x, %s, "
424 "%s, %04x%08x%s\n",
425 dir, speed, header[0] >> 10 & 0x3f,
426 header[1] >> 16, header[0] >> 16, evts[evt],
427 tcodes[tcode], header[1] & 0xffff, header[2], specific);
428 break;
429 default:
430 fw_notify("A%c spd %x tl %02x, "
431 "%04x -> %04x, %s, "
432 "%s%s\n",
433 dir, speed, header[0] >> 10 & 0x3f,
434 header[1] >> 16, header[0] >> 16, evts[evt],
435 tcodes[tcode], specific);
436 }
437 }
438
439 #else
440
441 #define log_irqs(evt)
442 #define log_selfids(node_id, generation, self_id_count, sid)
443 #define log_ar_at_event(dir, speed, header, evt)
444
445 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
446
447 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
448 {
449 writel(data, ohci->registers + offset);
450 }
451
452 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
453 {
454 return readl(ohci->registers + offset);
455 }
456
457 static inline void flush_writes(const struct fw_ohci *ohci)
458 {
459 /* Do a dummy read to flush writes. */
460 reg_read(ohci, OHCI1394_Version);
461 }
462
463 static int read_phy_reg(struct fw_card *card, int addr, u32 *value)
464 {
465 struct fw_ohci *ohci = fw_ohci(card);
466 u32 val;
467
468 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
469 flush_writes(ohci);
470 msleep(2);
471 val = reg_read(ohci, OHCI1394_PhyControl);
472 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
473 fw_error("failed to read phy reg bits\n");
474 return -EBUSY;
475 }
476
477 *value = OHCI1394_PhyControl_ReadData(val);
478
479 return 0;
480 }
481
482 static int ohci_update_phy_reg(struct fw_card *card, int addr,
483 int clear_bits, int set_bits)
484 {
485 struct fw_ohci *ohci = fw_ohci(card);
486 u32 old;
487 int err;
488
489 err = read_phy_reg(card, addr, &old);
490 if (err < 0)
491 return err;
492
493 old = (old & ~clear_bits) | set_bits;
494 reg_write(ohci, OHCI1394_PhyControl,
495 OHCI1394_PhyControl_Write(addr, old));
496
497 return 0;
498 }
499
500 static int ar_context_add_page(struct ar_context *ctx)
501 {
502 struct device *dev = ctx->ohci->card.device;
503 struct ar_buffer *ab;
504 dma_addr_t uninitialized_var(ab_bus);
505 size_t offset;
506
507 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
508 if (ab == NULL)
509 return -ENOMEM;
510
511 ab->next = NULL;
512 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
513 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
514 DESCRIPTOR_STATUS |
515 DESCRIPTOR_BRANCH_ALWAYS);
516 offset = offsetof(struct ar_buffer, data);
517 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
518 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
519 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
520 ab->descriptor.branch_address = 0;
521
522 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
523 ctx->last_buffer->next = ab;
524 ctx->last_buffer = ab;
525
526 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
527 flush_writes(ctx->ohci);
528
529 return 0;
530 }
531
532 static void ar_context_release(struct ar_context *ctx)
533 {
534 struct ar_buffer *ab, *ab_next;
535 size_t offset;
536 dma_addr_t ab_bus;
537
538 for (ab = ctx->current_buffer; ab; ab = ab_next) {
539 ab_next = ab->next;
540 offset = offsetof(struct ar_buffer, data);
541 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
542 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
543 ab, ab_bus);
544 }
545 }
546
547 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
548 #define cond_le32_to_cpu(v) \
549 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
550 #else
551 #define cond_le32_to_cpu(v) le32_to_cpu(v)
552 #endif
553
554 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
555 {
556 struct fw_ohci *ohci = ctx->ohci;
557 struct fw_packet p;
558 u32 status, length, tcode;
559 int evt;
560
561 p.header[0] = cond_le32_to_cpu(buffer[0]);
562 p.header[1] = cond_le32_to_cpu(buffer[1]);
563 p.header[2] = cond_le32_to_cpu(buffer[2]);
564
565 tcode = (p.header[0] >> 4) & 0x0f;
566 switch (tcode) {
567 case TCODE_WRITE_QUADLET_REQUEST:
568 case TCODE_READ_QUADLET_RESPONSE:
569 p.header[3] = (__force __u32) buffer[3];
570 p.header_length = 16;
571 p.payload_length = 0;
572 break;
573
574 case TCODE_READ_BLOCK_REQUEST :
575 p.header[3] = cond_le32_to_cpu(buffer[3]);
576 p.header_length = 16;
577 p.payload_length = 0;
578 break;
579
580 case TCODE_WRITE_BLOCK_REQUEST:
581 case TCODE_READ_BLOCK_RESPONSE:
582 case TCODE_LOCK_REQUEST:
583 case TCODE_LOCK_RESPONSE:
584 p.header[3] = cond_le32_to_cpu(buffer[3]);
585 p.header_length = 16;
586 p.payload_length = p.header[3] >> 16;
587 break;
588
589 case TCODE_WRITE_RESPONSE:
590 case TCODE_READ_QUADLET_REQUEST:
591 case OHCI_TCODE_PHY_PACKET:
592 p.header_length = 12;
593 p.payload_length = 0;
594 break;
595
596 default:
597 /* FIXME: Stop context, discard everything, and restart? */
598 p.header_length = 0;
599 p.payload_length = 0;
600 }
601
602 p.payload = (void *) buffer + p.header_length;
603
604 /* FIXME: What to do about evt_* errors? */
605 length = (p.header_length + p.payload_length + 3) / 4;
606 status = cond_le32_to_cpu(buffer[length]);
607 evt = (status >> 16) & 0x1f;
608
609 p.ack = evt - 16;
610 p.speed = (status >> 21) & 0x7;
611 p.timestamp = status & 0xffff;
612 p.generation = ohci->request_generation;
613
614 log_ar_at_event('R', p.speed, p.header, evt);
615
616 /*
617 * The OHCI bus reset handler synthesizes a phy packet with
618 * the new generation number when a bus reset happens (see
619 * section 8.4.2.3). This helps us determine when a request
620 * was received and make sure we send the response in the same
621 * generation. We only need this for requests; for responses
622 * we use the unique tlabel for finding the matching
623 * request.
624 *
625 * Alas some chips sometimes emit bus reset packets with a
626 * wrong generation. We set the correct generation for these
627 * at a slightly incorrect time (in bus_reset_tasklet).
628 */
629 if (evt == OHCI1394_evt_bus_reset) {
630 if (!(ohci->quirks & QUIRK_RESET_PACKET))
631 ohci->request_generation = (p.header[2] >> 16) & 0xff;
632 } else if (ctx == &ohci->ar_request_ctx) {
633 fw_core_handle_request(&ohci->card, &p);
634 } else {
635 fw_core_handle_response(&ohci->card, &p);
636 }
637
638 return buffer + length + 1;
639 }
640
641 static void ar_context_tasklet(unsigned long data)
642 {
643 struct ar_context *ctx = (struct ar_context *)data;
644 struct fw_ohci *ohci = ctx->ohci;
645 struct ar_buffer *ab;
646 struct descriptor *d;
647 void *buffer, *end;
648
649 ab = ctx->current_buffer;
650 d = &ab->descriptor;
651
652 if (d->res_count == 0) {
653 size_t size, rest, offset;
654 dma_addr_t start_bus;
655 void *start;
656
657 /*
658 * This descriptor is finished and we may have a
659 * packet split across this and the next buffer. We
660 * reuse the page for reassembling the split packet.
661 */
662
663 offset = offsetof(struct ar_buffer, data);
664 start = buffer = ab;
665 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
666
667 ab = ab->next;
668 d = &ab->descriptor;
669 size = buffer + PAGE_SIZE - ctx->pointer;
670 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
671 memmove(buffer, ctx->pointer, size);
672 memcpy(buffer + size, ab->data, rest);
673 ctx->current_buffer = ab;
674 ctx->pointer = (void *) ab->data + rest;
675 end = buffer + size + rest;
676
677 while (buffer < end)
678 buffer = handle_ar_packet(ctx, buffer);
679
680 dma_free_coherent(ohci->card.device, PAGE_SIZE,
681 start, start_bus);
682 ar_context_add_page(ctx);
683 } else {
684 buffer = ctx->pointer;
685 ctx->pointer = end =
686 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
687
688 while (buffer < end)
689 buffer = handle_ar_packet(ctx, buffer);
690 }
691 }
692
693 static int ar_context_init(struct ar_context *ctx,
694 struct fw_ohci *ohci, u32 regs)
695 {
696 struct ar_buffer ab;
697
698 ctx->regs = regs;
699 ctx->ohci = ohci;
700 ctx->last_buffer = &ab;
701 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
702
703 ar_context_add_page(ctx);
704 ar_context_add_page(ctx);
705 ctx->current_buffer = ab.next;
706 ctx->pointer = ctx->current_buffer->data;
707
708 return 0;
709 }
710
711 static void ar_context_run(struct ar_context *ctx)
712 {
713 struct ar_buffer *ab = ctx->current_buffer;
714 dma_addr_t ab_bus;
715 size_t offset;
716
717 offset = offsetof(struct ar_buffer, data);
718 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
719
720 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
721 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
722 flush_writes(ctx->ohci);
723 }
724
725 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
726 {
727 int b, key;
728
729 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
730 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
731
732 /* figure out which descriptor the branch address goes in */
733 if (z == 2 && (b == 3 || key == 2))
734 return d;
735 else
736 return d + z - 1;
737 }
738
739 static void context_tasklet(unsigned long data)
740 {
741 struct context *ctx = (struct context *) data;
742 struct descriptor *d, *last;
743 u32 address;
744 int z;
745 struct descriptor_buffer *desc;
746
747 desc = list_entry(ctx->buffer_list.next,
748 struct descriptor_buffer, list);
749 last = ctx->last;
750 while (last->branch_address != 0) {
751 struct descriptor_buffer *old_desc = desc;
752 address = le32_to_cpu(last->branch_address);
753 z = address & 0xf;
754 address &= ~0xf;
755
756 /* If the branch address points to a buffer outside of the
757 * current buffer, advance to the next buffer. */
758 if (address < desc->buffer_bus ||
759 address >= desc->buffer_bus + desc->used)
760 desc = list_entry(desc->list.next,
761 struct descriptor_buffer, list);
762 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
763 last = find_branch_descriptor(d, z);
764
765 if (!ctx->callback(ctx, d, last))
766 break;
767
768 if (old_desc != desc) {
769 /* If we've advanced to the next buffer, move the
770 * previous buffer to the free list. */
771 unsigned long flags;
772 old_desc->used = 0;
773 spin_lock_irqsave(&ctx->ohci->lock, flags);
774 list_move_tail(&old_desc->list, &ctx->buffer_list);
775 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
776 }
777 ctx->last = last;
778 }
779 }
780
781 /*
782 * Allocate a new buffer and add it to the list of free buffers for this
783 * context. Must be called with ohci->lock held.
784 */
785 static int context_add_buffer(struct context *ctx)
786 {
787 struct descriptor_buffer *desc;
788 dma_addr_t uninitialized_var(bus_addr);
789 int offset;
790
791 /*
792 * 16MB of descriptors should be far more than enough for any DMA
793 * program. This will catch run-away userspace or DoS attacks.
794 */
795 if (ctx->total_allocation >= 16*1024*1024)
796 return -ENOMEM;
797
798 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
799 &bus_addr, GFP_ATOMIC);
800 if (!desc)
801 return -ENOMEM;
802
803 offset = (void *)&desc->buffer - (void *)desc;
804 desc->buffer_size = PAGE_SIZE - offset;
805 desc->buffer_bus = bus_addr + offset;
806 desc->used = 0;
807
808 list_add_tail(&desc->list, &ctx->buffer_list);
809 ctx->total_allocation += PAGE_SIZE;
810
811 return 0;
812 }
813
814 static int context_init(struct context *ctx, struct fw_ohci *ohci,
815 u32 regs, descriptor_callback_t callback)
816 {
817 ctx->ohci = ohci;
818 ctx->regs = regs;
819 ctx->total_allocation = 0;
820
821 INIT_LIST_HEAD(&ctx->buffer_list);
822 if (context_add_buffer(ctx) < 0)
823 return -ENOMEM;
824
825 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
826 struct descriptor_buffer, list);
827
828 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
829 ctx->callback = callback;
830
831 /*
832 * We put a dummy descriptor in the buffer that has a NULL
833 * branch address and looks like it's been sent. That way we
834 * have a descriptor to append DMA programs to.
835 */
836 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
837 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
838 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
839 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
840 ctx->last = ctx->buffer_tail->buffer;
841 ctx->prev = ctx->buffer_tail->buffer;
842
843 return 0;
844 }
845
846 static void context_release(struct context *ctx)
847 {
848 struct fw_card *card = &ctx->ohci->card;
849 struct descriptor_buffer *desc, *tmp;
850
851 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
852 dma_free_coherent(card->device, PAGE_SIZE, desc,
853 desc->buffer_bus -
854 ((void *)&desc->buffer - (void *)desc));
855 }
856
857 /* Must be called with ohci->lock held */
858 static struct descriptor *context_get_descriptors(struct context *ctx,
859 int z, dma_addr_t *d_bus)
860 {
861 struct descriptor *d = NULL;
862 struct descriptor_buffer *desc = ctx->buffer_tail;
863
864 if (z * sizeof(*d) > desc->buffer_size)
865 return NULL;
866
867 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
868 /* No room for the descriptor in this buffer, so advance to the
869 * next one. */
870
871 if (desc->list.next == &ctx->buffer_list) {
872 /* If there is no free buffer next in the list,
873 * allocate one. */
874 if (context_add_buffer(ctx) < 0)
875 return NULL;
876 }
877 desc = list_entry(desc->list.next,
878 struct descriptor_buffer, list);
879 ctx->buffer_tail = desc;
880 }
881
882 d = desc->buffer + desc->used / sizeof(*d);
883 memset(d, 0, z * sizeof(*d));
884 *d_bus = desc->buffer_bus + desc->used;
885
886 return d;
887 }
888
889 static void context_run(struct context *ctx, u32 extra)
890 {
891 struct fw_ohci *ohci = ctx->ohci;
892
893 reg_write(ohci, COMMAND_PTR(ctx->regs),
894 le32_to_cpu(ctx->last->branch_address));
895 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
896 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
897 flush_writes(ohci);
898 }
899
900 static void context_append(struct context *ctx,
901 struct descriptor *d, int z, int extra)
902 {
903 dma_addr_t d_bus;
904 struct descriptor_buffer *desc = ctx->buffer_tail;
905
906 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
907
908 desc->used += (z + extra) * sizeof(*d);
909 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
910 ctx->prev = find_branch_descriptor(d, z);
911
912 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
913 flush_writes(ctx->ohci);
914 }
915
916 static void context_stop(struct context *ctx)
917 {
918 u32 reg;
919 int i;
920
921 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
922 flush_writes(ctx->ohci);
923
924 for (i = 0; i < 10; i++) {
925 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
926 if ((reg & CONTEXT_ACTIVE) == 0)
927 return;
928
929 mdelay(1);
930 }
931 fw_error("Error: DMA context still active (0x%08x)\n", reg);
932 }
933
934 struct driver_data {
935 struct fw_packet *packet;
936 };
937
938 /*
939 * This function apppends a packet to the DMA queue for transmission.
940 * Must always be called with the ochi->lock held to ensure proper
941 * generation handling and locking around packet queue manipulation.
942 */
943 static int at_context_queue_packet(struct context *ctx,
944 struct fw_packet *packet)
945 {
946 struct fw_ohci *ohci = ctx->ohci;
947 dma_addr_t d_bus, uninitialized_var(payload_bus);
948 struct driver_data *driver_data;
949 struct descriptor *d, *last;
950 __le32 *header;
951 int z, tcode;
952 u32 reg;
953
954 d = context_get_descriptors(ctx, 4, &d_bus);
955 if (d == NULL) {
956 packet->ack = RCODE_SEND_ERROR;
957 return -1;
958 }
959
960 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
961 d[0].res_count = cpu_to_le16(packet->timestamp);
962
963 /*
964 * The DMA format for asyncronous link packets is different
965 * from the IEEE1394 layout, so shift the fields around
966 * accordingly. If header_length is 8, it's a PHY packet, to
967 * which we need to prepend an extra quadlet.
968 */
969
970 header = (__le32 *) &d[1];
971 switch (packet->header_length) {
972 case 16:
973 case 12:
974 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
975 (packet->speed << 16));
976 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
977 (packet->header[0] & 0xffff0000));
978 header[2] = cpu_to_le32(packet->header[2]);
979
980 tcode = (packet->header[0] >> 4) & 0x0f;
981 if (TCODE_IS_BLOCK_PACKET(tcode))
982 header[3] = cpu_to_le32(packet->header[3]);
983 else
984 header[3] = (__force __le32) packet->header[3];
985
986 d[0].req_count = cpu_to_le16(packet->header_length);
987 break;
988
989 case 8:
990 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
991 (packet->speed << 16));
992 header[1] = cpu_to_le32(packet->header[0]);
993 header[2] = cpu_to_le32(packet->header[1]);
994 d[0].req_count = cpu_to_le16(12);
995 break;
996
997 case 4:
998 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
999 (packet->speed << 16));
1000 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1001 d[0].req_count = cpu_to_le16(8);
1002 break;
1003
1004 default:
1005 /* BUG(); */
1006 packet->ack = RCODE_SEND_ERROR;
1007 return -1;
1008 }
1009
1010 driver_data = (struct driver_data *) &d[3];
1011 driver_data->packet = packet;
1012 packet->driver_data = driver_data;
1013
1014 if (packet->payload_length > 0) {
1015 payload_bus =
1016 dma_map_single(ohci->card.device, packet->payload,
1017 packet->payload_length, DMA_TO_DEVICE);
1018 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1019 packet->ack = RCODE_SEND_ERROR;
1020 return -1;
1021 }
1022 packet->payload_bus = payload_bus;
1023 packet->payload_mapped = true;
1024
1025 d[2].req_count = cpu_to_le16(packet->payload_length);
1026 d[2].data_address = cpu_to_le32(payload_bus);
1027 last = &d[2];
1028 z = 3;
1029 } else {
1030 last = &d[0];
1031 z = 2;
1032 }
1033
1034 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1035 DESCRIPTOR_IRQ_ALWAYS |
1036 DESCRIPTOR_BRANCH_ALWAYS);
1037
1038 /*
1039 * If the controller and packet generations don't match, we need to
1040 * bail out and try again. If IntEvent.busReset is set, the AT context
1041 * is halted, so appending to the context and trying to run it is
1042 * futile. Most controllers do the right thing and just flush the AT
1043 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1044 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1045 * up stalling out. So we just bail out in software and try again
1046 * later, and everyone is happy.
1047 * FIXME: Document how the locking works.
1048 */
1049 if (ohci->generation != packet->generation ||
1050 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1051 if (packet->payload_mapped)
1052 dma_unmap_single(ohci->card.device, payload_bus,
1053 packet->payload_length, DMA_TO_DEVICE);
1054 packet->ack = RCODE_GENERATION;
1055 return -1;
1056 }
1057
1058 context_append(ctx, d, z, 4 - z);
1059
1060 /* If the context isn't already running, start it up. */
1061 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1062 if ((reg & CONTEXT_RUN) == 0)
1063 context_run(ctx, 0);
1064
1065 return 0;
1066 }
1067
1068 static int handle_at_packet(struct context *context,
1069 struct descriptor *d,
1070 struct descriptor *last)
1071 {
1072 struct driver_data *driver_data;
1073 struct fw_packet *packet;
1074 struct fw_ohci *ohci = context->ohci;
1075 int evt;
1076
1077 if (last->transfer_status == 0)
1078 /* This descriptor isn't done yet, stop iteration. */
1079 return 0;
1080
1081 driver_data = (struct driver_data *) &d[3];
1082 packet = driver_data->packet;
1083 if (packet == NULL)
1084 /* This packet was cancelled, just continue. */
1085 return 1;
1086
1087 if (packet->payload_mapped)
1088 dma_unmap_single(ohci->card.device, packet->payload_bus,
1089 packet->payload_length, DMA_TO_DEVICE);
1090
1091 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1092 packet->timestamp = le16_to_cpu(last->res_count);
1093
1094 log_ar_at_event('T', packet->speed, packet->header, evt);
1095
1096 switch (evt) {
1097 case OHCI1394_evt_timeout:
1098 /* Async response transmit timed out. */
1099 packet->ack = RCODE_CANCELLED;
1100 break;
1101
1102 case OHCI1394_evt_flushed:
1103 /*
1104 * The packet was flushed should give same error as
1105 * when we try to use a stale generation count.
1106 */
1107 packet->ack = RCODE_GENERATION;
1108 break;
1109
1110 case OHCI1394_evt_missing_ack:
1111 /*
1112 * Using a valid (current) generation count, but the
1113 * node is not on the bus or not sending acks.
1114 */
1115 packet->ack = RCODE_NO_ACK;
1116 break;
1117
1118 case ACK_COMPLETE + 0x10:
1119 case ACK_PENDING + 0x10:
1120 case ACK_BUSY_X + 0x10:
1121 case ACK_BUSY_A + 0x10:
1122 case ACK_BUSY_B + 0x10:
1123 case ACK_DATA_ERROR + 0x10:
1124 case ACK_TYPE_ERROR + 0x10:
1125 packet->ack = evt - 0x10;
1126 break;
1127
1128 default:
1129 packet->ack = RCODE_SEND_ERROR;
1130 break;
1131 }
1132
1133 packet->callback(packet, &ohci->card, packet->ack);
1134
1135 return 1;
1136 }
1137
1138 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1139 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1140 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1141 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1142 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1143
1144 static void handle_local_rom(struct fw_ohci *ohci,
1145 struct fw_packet *packet, u32 csr)
1146 {
1147 struct fw_packet response;
1148 int tcode, length, i;
1149
1150 tcode = HEADER_GET_TCODE(packet->header[0]);
1151 if (TCODE_IS_BLOCK_PACKET(tcode))
1152 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1153 else
1154 length = 4;
1155
1156 i = csr - CSR_CONFIG_ROM;
1157 if (i + length > CONFIG_ROM_SIZE) {
1158 fw_fill_response(&response, packet->header,
1159 RCODE_ADDRESS_ERROR, NULL, 0);
1160 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1161 fw_fill_response(&response, packet->header,
1162 RCODE_TYPE_ERROR, NULL, 0);
1163 } else {
1164 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1165 (void *) ohci->config_rom + i, length);
1166 }
1167
1168 fw_core_handle_response(&ohci->card, &response);
1169 }
1170
1171 static void handle_local_lock(struct fw_ohci *ohci,
1172 struct fw_packet *packet, u32 csr)
1173 {
1174 struct fw_packet response;
1175 int tcode, length, ext_tcode, sel;
1176 __be32 *payload, lock_old;
1177 u32 lock_arg, lock_data;
1178
1179 tcode = HEADER_GET_TCODE(packet->header[0]);
1180 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1181 payload = packet->payload;
1182 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1183
1184 if (tcode == TCODE_LOCK_REQUEST &&
1185 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1186 lock_arg = be32_to_cpu(payload[0]);
1187 lock_data = be32_to_cpu(payload[1]);
1188 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1189 lock_arg = 0;
1190 lock_data = 0;
1191 } else {
1192 fw_fill_response(&response, packet->header,
1193 RCODE_TYPE_ERROR, NULL, 0);
1194 goto out;
1195 }
1196
1197 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1198 reg_write(ohci, OHCI1394_CSRData, lock_data);
1199 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1200 reg_write(ohci, OHCI1394_CSRControl, sel);
1201
1202 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1203 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1204 else
1205 fw_notify("swap not done yet\n");
1206
1207 fw_fill_response(&response, packet->header,
1208 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1209 out:
1210 fw_core_handle_response(&ohci->card, &response);
1211 }
1212
1213 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1214 {
1215 u64 offset;
1216 u32 csr;
1217
1218 if (ctx == &ctx->ohci->at_request_ctx) {
1219 packet->ack = ACK_PENDING;
1220 packet->callback(packet, &ctx->ohci->card, packet->ack);
1221 }
1222
1223 offset =
1224 ((unsigned long long)
1225 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1226 packet->header[2];
1227 csr = offset - CSR_REGISTER_BASE;
1228
1229 /* Handle config rom reads. */
1230 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1231 handle_local_rom(ctx->ohci, packet, csr);
1232 else switch (csr) {
1233 case CSR_BUS_MANAGER_ID:
1234 case CSR_BANDWIDTH_AVAILABLE:
1235 case CSR_CHANNELS_AVAILABLE_HI:
1236 case CSR_CHANNELS_AVAILABLE_LO:
1237 handle_local_lock(ctx->ohci, packet, csr);
1238 break;
1239 default:
1240 if (ctx == &ctx->ohci->at_request_ctx)
1241 fw_core_handle_request(&ctx->ohci->card, packet);
1242 else
1243 fw_core_handle_response(&ctx->ohci->card, packet);
1244 break;
1245 }
1246
1247 if (ctx == &ctx->ohci->at_response_ctx) {
1248 packet->ack = ACK_COMPLETE;
1249 packet->callback(packet, &ctx->ohci->card, packet->ack);
1250 }
1251 }
1252
1253 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1254 {
1255 unsigned long flags;
1256 int ret;
1257
1258 spin_lock_irqsave(&ctx->ohci->lock, flags);
1259
1260 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1261 ctx->ohci->generation == packet->generation) {
1262 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1263 handle_local_request(ctx, packet);
1264 return;
1265 }
1266
1267 ret = at_context_queue_packet(ctx, packet);
1268 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1269
1270 if (ret < 0)
1271 packet->callback(packet, &ctx->ohci->card, packet->ack);
1272
1273 }
1274
1275 static void bus_reset_tasklet(unsigned long data)
1276 {
1277 struct fw_ohci *ohci = (struct fw_ohci *)data;
1278 int self_id_count, i, j, reg;
1279 int generation, new_generation;
1280 unsigned long flags;
1281 void *free_rom = NULL;
1282 dma_addr_t free_rom_bus = 0;
1283
1284 reg = reg_read(ohci, OHCI1394_NodeID);
1285 if (!(reg & OHCI1394_NodeID_idValid)) {
1286 fw_notify("node ID not valid, new bus reset in progress\n");
1287 return;
1288 }
1289 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1290 fw_notify("malconfigured bus\n");
1291 return;
1292 }
1293 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1294 OHCI1394_NodeID_nodeNumber);
1295
1296 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1297 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1298 fw_notify("inconsistent self IDs\n");
1299 return;
1300 }
1301 /*
1302 * The count in the SelfIDCount register is the number of
1303 * bytes in the self ID receive buffer. Since we also receive
1304 * the inverted quadlets and a header quadlet, we shift one
1305 * bit extra to get the actual number of self IDs.
1306 */
1307 self_id_count = (reg >> 3) & 0xff;
1308 if (self_id_count == 0 || self_id_count > 252) {
1309 fw_notify("inconsistent self IDs\n");
1310 return;
1311 }
1312 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1313 rmb();
1314
1315 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1316 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1317 fw_notify("inconsistent self IDs\n");
1318 return;
1319 }
1320 ohci->self_id_buffer[j] =
1321 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1322 }
1323 rmb();
1324
1325 /*
1326 * Check the consistency of the self IDs we just read. The
1327 * problem we face is that a new bus reset can start while we
1328 * read out the self IDs from the DMA buffer. If this happens,
1329 * the DMA buffer will be overwritten with new self IDs and we
1330 * will read out inconsistent data. The OHCI specification
1331 * (section 11.2) recommends a technique similar to
1332 * linux/seqlock.h, where we remember the generation of the
1333 * self IDs in the buffer before reading them out and compare
1334 * it to the current generation after reading them out. If
1335 * the two generations match we know we have a consistent set
1336 * of self IDs.
1337 */
1338
1339 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1340 if (new_generation != generation) {
1341 fw_notify("recursive bus reset detected, "
1342 "discarding self ids\n");
1343 return;
1344 }
1345
1346 /* FIXME: Document how the locking works. */
1347 spin_lock_irqsave(&ohci->lock, flags);
1348
1349 ohci->generation = generation;
1350 context_stop(&ohci->at_request_ctx);
1351 context_stop(&ohci->at_response_ctx);
1352 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1353
1354 if (ohci->quirks & QUIRK_RESET_PACKET)
1355 ohci->request_generation = generation;
1356
1357 /*
1358 * This next bit is unrelated to the AT context stuff but we
1359 * have to do it under the spinlock also. If a new config rom
1360 * was set up before this reset, the old one is now no longer
1361 * in use and we can free it. Update the config rom pointers
1362 * to point to the current config rom and clear the
1363 * next_config_rom pointer so a new udpate can take place.
1364 */
1365
1366 if (ohci->next_config_rom != NULL) {
1367 if (ohci->next_config_rom != ohci->config_rom) {
1368 free_rom = ohci->config_rom;
1369 free_rom_bus = ohci->config_rom_bus;
1370 }
1371 ohci->config_rom = ohci->next_config_rom;
1372 ohci->config_rom_bus = ohci->next_config_rom_bus;
1373 ohci->next_config_rom = NULL;
1374
1375 /*
1376 * Restore config_rom image and manually update
1377 * config_rom registers. Writing the header quadlet
1378 * will indicate that the config rom is ready, so we
1379 * do that last.
1380 */
1381 reg_write(ohci, OHCI1394_BusOptions,
1382 be32_to_cpu(ohci->config_rom[2]));
1383 ohci->config_rom[0] = ohci->next_header;
1384 reg_write(ohci, OHCI1394_ConfigROMhdr,
1385 be32_to_cpu(ohci->next_header));
1386 }
1387
1388 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1389 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1390 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1391 #endif
1392
1393 spin_unlock_irqrestore(&ohci->lock, flags);
1394
1395 if (free_rom)
1396 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1397 free_rom, free_rom_bus);
1398
1399 log_selfids(ohci->node_id, generation,
1400 self_id_count, ohci->self_id_buffer);
1401
1402 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1403 self_id_count, ohci->self_id_buffer);
1404 }
1405
1406 static irqreturn_t irq_handler(int irq, void *data)
1407 {
1408 struct fw_ohci *ohci = data;
1409 u32 event, iso_event;
1410 int i;
1411
1412 event = reg_read(ohci, OHCI1394_IntEventClear);
1413
1414 if (!event || !~event)
1415 return IRQ_NONE;
1416
1417 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1418 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1419 log_irqs(event);
1420
1421 if (event & OHCI1394_selfIDComplete)
1422 tasklet_schedule(&ohci->bus_reset_tasklet);
1423
1424 if (event & OHCI1394_RQPkt)
1425 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1426
1427 if (event & OHCI1394_RSPkt)
1428 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1429
1430 if (event & OHCI1394_reqTxComplete)
1431 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1432
1433 if (event & OHCI1394_respTxComplete)
1434 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1435
1436 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1437 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1438
1439 while (iso_event) {
1440 i = ffs(iso_event) - 1;
1441 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1442 iso_event &= ~(1 << i);
1443 }
1444
1445 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1446 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1447
1448 while (iso_event) {
1449 i = ffs(iso_event) - 1;
1450 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1451 iso_event &= ~(1 << i);
1452 }
1453
1454 if (unlikely(event & OHCI1394_regAccessFail))
1455 fw_error("Register access failure - "
1456 "please notify linux1394-devel@lists.sf.net\n");
1457
1458 if (unlikely(event & OHCI1394_postedWriteErr))
1459 fw_error("PCI posted write error\n");
1460
1461 if (unlikely(event & OHCI1394_cycleTooLong)) {
1462 if (printk_ratelimit())
1463 fw_notify("isochronous cycle too long\n");
1464 reg_write(ohci, OHCI1394_LinkControlSet,
1465 OHCI1394_LinkControl_cycleMaster);
1466 }
1467
1468 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1469 /*
1470 * We need to clear this event bit in order to make
1471 * cycleMatch isochronous I/O work. In theory we should
1472 * stop active cycleMatch iso contexts now and restart
1473 * them at least two cycles later. (FIXME?)
1474 */
1475 if (printk_ratelimit())
1476 fw_notify("isochronous cycle inconsistent\n");
1477 }
1478
1479 return IRQ_HANDLED;
1480 }
1481
1482 static int software_reset(struct fw_ohci *ohci)
1483 {
1484 int i;
1485
1486 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1487
1488 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1489 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1490 OHCI1394_HCControl_softReset) == 0)
1491 return 0;
1492 msleep(1);
1493 }
1494
1495 return -EBUSY;
1496 }
1497
1498 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1499 {
1500 size_t size = length * 4;
1501
1502 memcpy(dest, src, size);
1503 if (size < CONFIG_ROM_SIZE)
1504 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1505 }
1506
1507 static int ohci_enable(struct fw_card *card,
1508 const __be32 *config_rom, size_t length)
1509 {
1510 struct fw_ohci *ohci = fw_ohci(card);
1511 struct pci_dev *dev = to_pci_dev(card->device);
1512 u32 lps;
1513 int i;
1514
1515 if (software_reset(ohci)) {
1516 fw_error("Failed to reset ohci card.\n");
1517 return -EBUSY;
1518 }
1519
1520 /*
1521 * Now enable LPS, which we need in order to start accessing
1522 * most of the registers. In fact, on some cards (ALI M5251),
1523 * accessing registers in the SClk domain without LPS enabled
1524 * will lock up the machine. Wait 50msec to make sure we have
1525 * full link enabled. However, with some cards (well, at least
1526 * a JMicron PCIe card), we have to try again sometimes.
1527 */
1528 reg_write(ohci, OHCI1394_HCControlSet,
1529 OHCI1394_HCControl_LPS |
1530 OHCI1394_HCControl_postedWriteEnable);
1531 flush_writes(ohci);
1532
1533 for (lps = 0, i = 0; !lps && i < 3; i++) {
1534 msleep(50);
1535 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1536 OHCI1394_HCControl_LPS;
1537 }
1538
1539 if (!lps) {
1540 fw_error("Failed to set Link Power Status\n");
1541 return -EIO;
1542 }
1543
1544 reg_write(ohci, OHCI1394_HCControlClear,
1545 OHCI1394_HCControl_noByteSwapData);
1546
1547 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1548 reg_write(ohci, OHCI1394_LinkControlClear,
1549 OHCI1394_LinkControl_rcvPhyPkt);
1550 reg_write(ohci, OHCI1394_LinkControlSet,
1551 OHCI1394_LinkControl_rcvSelfID |
1552 OHCI1394_LinkControl_cycleTimerEnable |
1553 OHCI1394_LinkControl_cycleMaster);
1554
1555 reg_write(ohci, OHCI1394_ATRetries,
1556 OHCI1394_MAX_AT_REQ_RETRIES |
1557 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1558 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1559
1560 ar_context_run(&ohci->ar_request_ctx);
1561 ar_context_run(&ohci->ar_response_ctx);
1562
1563 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1564 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1565 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1566 reg_write(ohci, OHCI1394_IntMaskSet,
1567 OHCI1394_selfIDComplete |
1568 OHCI1394_RQPkt | OHCI1394_RSPkt |
1569 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1570 OHCI1394_isochRx | OHCI1394_isochTx |
1571 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1572 OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
1573 OHCI1394_masterIntEnable);
1574 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1575 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1576
1577 /* Activate link_on bit and contender bit in our self ID packets.*/
1578 if (ohci_update_phy_reg(card, 4, 0,
1579 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1580 return -EIO;
1581
1582 /*
1583 * When the link is not yet enabled, the atomic config rom
1584 * update mechanism described below in ohci_set_config_rom()
1585 * is not active. We have to update ConfigRomHeader and
1586 * BusOptions manually, and the write to ConfigROMmap takes
1587 * effect immediately. We tie this to the enabling of the
1588 * link, so we have a valid config rom before enabling - the
1589 * OHCI requires that ConfigROMhdr and BusOptions have valid
1590 * values before enabling.
1591 *
1592 * However, when the ConfigROMmap is written, some controllers
1593 * always read back quadlets 0 and 2 from the config rom to
1594 * the ConfigRomHeader and BusOptions registers on bus reset.
1595 * They shouldn't do that in this initial case where the link
1596 * isn't enabled. This means we have to use the same
1597 * workaround here, setting the bus header to 0 and then write
1598 * the right values in the bus reset tasklet.
1599 */
1600
1601 if (config_rom) {
1602 ohci->next_config_rom =
1603 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1604 &ohci->next_config_rom_bus,
1605 GFP_KERNEL);
1606 if (ohci->next_config_rom == NULL)
1607 return -ENOMEM;
1608
1609 copy_config_rom(ohci->next_config_rom, config_rom, length);
1610 } else {
1611 /*
1612 * In the suspend case, config_rom is NULL, which
1613 * means that we just reuse the old config rom.
1614 */
1615 ohci->next_config_rom = ohci->config_rom;
1616 ohci->next_config_rom_bus = ohci->config_rom_bus;
1617 }
1618
1619 ohci->next_header = ohci->next_config_rom[0];
1620 ohci->next_config_rom[0] = 0;
1621 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1622 reg_write(ohci, OHCI1394_BusOptions,
1623 be32_to_cpu(ohci->next_config_rom[2]));
1624 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1625
1626 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1627
1628 if (request_irq(dev->irq, irq_handler,
1629 IRQF_SHARED, ohci_driver_name, ohci)) {
1630 fw_error("Failed to allocate shared interrupt %d.\n",
1631 dev->irq);
1632 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1633 ohci->config_rom, ohci->config_rom_bus);
1634 return -EIO;
1635 }
1636
1637 reg_write(ohci, OHCI1394_HCControlSet,
1638 OHCI1394_HCControl_linkEnable |
1639 OHCI1394_HCControl_BIBimageValid);
1640 flush_writes(ohci);
1641
1642 /*
1643 * We are ready to go, initiate bus reset to finish the
1644 * initialization.
1645 */
1646
1647 fw_core_initiate_bus_reset(&ohci->card, 1);
1648
1649 return 0;
1650 }
1651
1652 static int ohci_set_config_rom(struct fw_card *card,
1653 const __be32 *config_rom, size_t length)
1654 {
1655 struct fw_ohci *ohci;
1656 unsigned long flags;
1657 int ret = -EBUSY;
1658 __be32 *next_config_rom;
1659 dma_addr_t uninitialized_var(next_config_rom_bus);
1660
1661 ohci = fw_ohci(card);
1662
1663 /*
1664 * When the OHCI controller is enabled, the config rom update
1665 * mechanism is a bit tricky, but easy enough to use. See
1666 * section 5.5.6 in the OHCI specification.
1667 *
1668 * The OHCI controller caches the new config rom address in a
1669 * shadow register (ConfigROMmapNext) and needs a bus reset
1670 * for the changes to take place. When the bus reset is
1671 * detected, the controller loads the new values for the
1672 * ConfigRomHeader and BusOptions registers from the specified
1673 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1674 * shadow register. All automatically and atomically.
1675 *
1676 * Now, there's a twist to this story. The automatic load of
1677 * ConfigRomHeader and BusOptions doesn't honor the
1678 * noByteSwapData bit, so with a be32 config rom, the
1679 * controller will load be32 values in to these registers
1680 * during the atomic update, even on litte endian
1681 * architectures. The workaround we use is to put a 0 in the
1682 * header quadlet; 0 is endian agnostic and means that the
1683 * config rom isn't ready yet. In the bus reset tasklet we
1684 * then set up the real values for the two registers.
1685 *
1686 * We use ohci->lock to avoid racing with the code that sets
1687 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1688 */
1689
1690 next_config_rom =
1691 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1692 &next_config_rom_bus, GFP_KERNEL);
1693 if (next_config_rom == NULL)
1694 return -ENOMEM;
1695
1696 spin_lock_irqsave(&ohci->lock, flags);
1697
1698 if (ohci->next_config_rom == NULL) {
1699 ohci->next_config_rom = next_config_rom;
1700 ohci->next_config_rom_bus = next_config_rom_bus;
1701
1702 copy_config_rom(ohci->next_config_rom, config_rom, length);
1703
1704 ohci->next_header = config_rom[0];
1705 ohci->next_config_rom[0] = 0;
1706
1707 reg_write(ohci, OHCI1394_ConfigROMmap,
1708 ohci->next_config_rom_bus);
1709 ret = 0;
1710 }
1711
1712 spin_unlock_irqrestore(&ohci->lock, flags);
1713
1714 /*
1715 * Now initiate a bus reset to have the changes take
1716 * effect. We clean up the old config rom memory and DMA
1717 * mappings in the bus reset tasklet, since the OHCI
1718 * controller could need to access it before the bus reset
1719 * takes effect.
1720 */
1721 if (ret == 0)
1722 fw_core_initiate_bus_reset(&ohci->card, 1);
1723 else
1724 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1725 next_config_rom, next_config_rom_bus);
1726
1727 return ret;
1728 }
1729
1730 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1731 {
1732 struct fw_ohci *ohci = fw_ohci(card);
1733
1734 at_context_transmit(&ohci->at_request_ctx, packet);
1735 }
1736
1737 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1738 {
1739 struct fw_ohci *ohci = fw_ohci(card);
1740
1741 at_context_transmit(&ohci->at_response_ctx, packet);
1742 }
1743
1744 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1745 {
1746 struct fw_ohci *ohci = fw_ohci(card);
1747 struct context *ctx = &ohci->at_request_ctx;
1748 struct driver_data *driver_data = packet->driver_data;
1749 int ret = -ENOENT;
1750
1751 tasklet_disable(&ctx->tasklet);
1752
1753 if (packet->ack != 0)
1754 goto out;
1755
1756 if (packet->payload_mapped)
1757 dma_unmap_single(ohci->card.device, packet->payload_bus,
1758 packet->payload_length, DMA_TO_DEVICE);
1759
1760 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1761 driver_data->packet = NULL;
1762 packet->ack = RCODE_CANCELLED;
1763 packet->callback(packet, &ohci->card, packet->ack);
1764 ret = 0;
1765 out:
1766 tasklet_enable(&ctx->tasklet);
1767
1768 return ret;
1769 }
1770
1771 static int ohci_enable_phys_dma(struct fw_card *card,
1772 int node_id, int generation)
1773 {
1774 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1775 return 0;
1776 #else
1777 struct fw_ohci *ohci = fw_ohci(card);
1778 unsigned long flags;
1779 int n, ret = 0;
1780
1781 /*
1782 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1783 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1784 */
1785
1786 spin_lock_irqsave(&ohci->lock, flags);
1787
1788 if (ohci->generation != generation) {
1789 ret = -ESTALE;
1790 goto out;
1791 }
1792
1793 /*
1794 * Note, if the node ID contains a non-local bus ID, physical DMA is
1795 * enabled for _all_ nodes on remote buses.
1796 */
1797
1798 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1799 if (n < 32)
1800 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1801 else
1802 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1803
1804 flush_writes(ohci);
1805 out:
1806 spin_unlock_irqrestore(&ohci->lock, flags);
1807
1808 return ret;
1809 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1810 }
1811
1812 static u32 cycle_timer_ticks(u32 cycle_timer)
1813 {
1814 u32 ticks;
1815
1816 ticks = cycle_timer & 0xfff;
1817 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1818 ticks += (3072 * 8000) * (cycle_timer >> 25);
1819
1820 return ticks;
1821 }
1822
1823 /*
1824 * Some controllers exhibit one or more of the following bugs when updating the
1825 * iso cycle timer register:
1826 * - When the lowest six bits are wrapping around to zero, a read that happens
1827 * at the same time will return garbage in the lowest ten bits.
1828 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1829 * not incremented for about 60 ns.
1830 * - Occasionally, the entire register reads zero.
1831 *
1832 * To catch these, we read the register three times and ensure that the
1833 * difference between each two consecutive reads is approximately the same, i.e.
1834 * less than twice the other. Furthermore, any negative difference indicates an
1835 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1836 * execute, so we have enough precision to compute the ratio of the differences.)
1837 */
1838 static u32 ohci_get_cycle_time(struct fw_card *card)
1839 {
1840 struct fw_ohci *ohci = fw_ohci(card);
1841 u32 c0, c1, c2;
1842 u32 t0, t1, t2;
1843 s32 diff01, diff12;
1844 int i;
1845
1846 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1847
1848 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1849 i = 0;
1850 c1 = c2;
1851 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1852 do {
1853 c0 = c1;
1854 c1 = c2;
1855 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1856 t0 = cycle_timer_ticks(c0);
1857 t1 = cycle_timer_ticks(c1);
1858 t2 = cycle_timer_ticks(c2);
1859 diff01 = t1 - t0;
1860 diff12 = t2 - t1;
1861 } while ((diff01 <= 0 || diff12 <= 0 ||
1862 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1863 && i++ < 20);
1864 }
1865
1866 return c2;
1867 }
1868
1869 static void copy_iso_headers(struct iso_context *ctx, void *p)
1870 {
1871 int i = ctx->header_length;
1872
1873 if (i + ctx->base.header_size > PAGE_SIZE)
1874 return;
1875
1876 /*
1877 * The iso header is byteswapped to little endian by
1878 * the controller, but the remaining header quadlets
1879 * are big endian. We want to present all the headers
1880 * as big endian, so we have to swap the first quadlet.
1881 */
1882 if (ctx->base.header_size > 0)
1883 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1884 if (ctx->base.header_size > 4)
1885 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1886 if (ctx->base.header_size > 8)
1887 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1888 ctx->header_length += ctx->base.header_size;
1889 }
1890
1891 static int handle_ir_packet_per_buffer(struct context *context,
1892 struct descriptor *d,
1893 struct descriptor *last)
1894 {
1895 struct iso_context *ctx =
1896 container_of(context, struct iso_context, context);
1897 struct descriptor *pd;
1898 __le32 *ir_header;
1899 void *p;
1900
1901 for (pd = d; pd <= last; pd++) {
1902 if (pd->transfer_status)
1903 break;
1904 }
1905 if (pd > last)
1906 /* Descriptor(s) not done yet, stop iteration */
1907 return 0;
1908
1909 p = last + 1;
1910 copy_iso_headers(ctx, p);
1911
1912 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1913 ir_header = (__le32 *) p;
1914 ctx->base.callback(&ctx->base,
1915 le32_to_cpu(ir_header[0]) & 0xffff,
1916 ctx->header_length, ctx->header,
1917 ctx->base.callback_data);
1918 ctx->header_length = 0;
1919 }
1920
1921 return 1;
1922 }
1923
1924 static int handle_it_packet(struct context *context,
1925 struct descriptor *d,
1926 struct descriptor *last)
1927 {
1928 struct iso_context *ctx =
1929 container_of(context, struct iso_context, context);
1930 int i;
1931 struct descriptor *pd;
1932
1933 for (pd = d; pd <= last; pd++)
1934 if (pd->transfer_status)
1935 break;
1936 if (pd > last)
1937 /* Descriptor(s) not done yet, stop iteration */
1938 return 0;
1939
1940 i = ctx->header_length;
1941 if (i + 4 < PAGE_SIZE) {
1942 /* Present this value as big-endian to match the receive code */
1943 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1944 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1945 le16_to_cpu(pd->res_count));
1946 ctx->header_length += 4;
1947 }
1948 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1949 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1950 ctx->header_length, ctx->header,
1951 ctx->base.callback_data);
1952 ctx->header_length = 0;
1953 }
1954 return 1;
1955 }
1956
1957 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1958 int type, int channel, size_t header_size)
1959 {
1960 struct fw_ohci *ohci = fw_ohci(card);
1961 struct iso_context *ctx, *list;
1962 descriptor_callback_t callback;
1963 u64 *channels, dont_care = ~0ULL;
1964 u32 *mask, regs;
1965 unsigned long flags;
1966 int index, ret = -ENOMEM;
1967
1968 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1969 channels = &dont_care;
1970 mask = &ohci->it_context_mask;
1971 list = ohci->it_context_list;
1972 callback = handle_it_packet;
1973 } else {
1974 channels = &ohci->ir_context_channels;
1975 mask = &ohci->ir_context_mask;
1976 list = ohci->ir_context_list;
1977 callback = handle_ir_packet_per_buffer;
1978 }
1979
1980 spin_lock_irqsave(&ohci->lock, flags);
1981 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1982 if (index >= 0) {
1983 *channels &= ~(1ULL << channel);
1984 *mask &= ~(1 << index);
1985 }
1986 spin_unlock_irqrestore(&ohci->lock, flags);
1987
1988 if (index < 0)
1989 return ERR_PTR(-EBUSY);
1990
1991 if (type == FW_ISO_CONTEXT_TRANSMIT)
1992 regs = OHCI1394_IsoXmitContextBase(index);
1993 else
1994 regs = OHCI1394_IsoRcvContextBase(index);
1995
1996 ctx = &list[index];
1997 memset(ctx, 0, sizeof(*ctx));
1998 ctx->header_length = 0;
1999 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2000 if (ctx->header == NULL)
2001 goto out;
2002
2003 ret = context_init(&ctx->context, ohci, regs, callback);
2004 if (ret < 0)
2005 goto out_with_header;
2006
2007 return &ctx->base;
2008
2009 out_with_header:
2010 free_page((unsigned long)ctx->header);
2011 out:
2012 spin_lock_irqsave(&ohci->lock, flags);
2013 *mask |= 1 << index;
2014 spin_unlock_irqrestore(&ohci->lock, flags);
2015
2016 return ERR_PTR(ret);
2017 }
2018
2019 static int ohci_start_iso(struct fw_iso_context *base,
2020 s32 cycle, u32 sync, u32 tags)
2021 {
2022 struct iso_context *ctx = container_of(base, struct iso_context, base);
2023 struct fw_ohci *ohci = ctx->context.ohci;
2024 u32 control, match;
2025 int index;
2026
2027 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2028 index = ctx - ohci->it_context_list;
2029 match = 0;
2030 if (cycle >= 0)
2031 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2032 (cycle & 0x7fff) << 16;
2033
2034 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2035 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2036 context_run(&ctx->context, match);
2037 } else {
2038 index = ctx - ohci->ir_context_list;
2039 control = IR_CONTEXT_ISOCH_HEADER;
2040 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2041 if (cycle >= 0) {
2042 match |= (cycle & 0x07fff) << 12;
2043 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2044 }
2045
2046 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2047 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2048 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2049 context_run(&ctx->context, control);
2050 }
2051
2052 return 0;
2053 }
2054
2055 static int ohci_stop_iso(struct fw_iso_context *base)
2056 {
2057 struct fw_ohci *ohci = fw_ohci(base->card);
2058 struct iso_context *ctx = container_of(base, struct iso_context, base);
2059 int index;
2060
2061 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2062 index = ctx - ohci->it_context_list;
2063 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2064 } else {
2065 index = ctx - ohci->ir_context_list;
2066 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2067 }
2068 flush_writes(ohci);
2069 context_stop(&ctx->context);
2070
2071 return 0;
2072 }
2073
2074 static void ohci_free_iso_context(struct fw_iso_context *base)
2075 {
2076 struct fw_ohci *ohci = fw_ohci(base->card);
2077 struct iso_context *ctx = container_of(base, struct iso_context, base);
2078 unsigned long flags;
2079 int index;
2080
2081 ohci_stop_iso(base);
2082 context_release(&ctx->context);
2083 free_page((unsigned long)ctx->header);
2084
2085 spin_lock_irqsave(&ohci->lock, flags);
2086
2087 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2088 index = ctx - ohci->it_context_list;
2089 ohci->it_context_mask |= 1 << index;
2090 } else {
2091 index = ctx - ohci->ir_context_list;
2092 ohci->ir_context_mask |= 1 << index;
2093 ohci->ir_context_channels |= 1ULL << base->channel;
2094 }
2095
2096 spin_unlock_irqrestore(&ohci->lock, flags);
2097 }
2098
2099 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2100 struct fw_iso_packet *packet,
2101 struct fw_iso_buffer *buffer,
2102 unsigned long payload)
2103 {
2104 struct iso_context *ctx = container_of(base, struct iso_context, base);
2105 struct descriptor *d, *last, *pd;
2106 struct fw_iso_packet *p;
2107 __le32 *header;
2108 dma_addr_t d_bus, page_bus;
2109 u32 z, header_z, payload_z, irq;
2110 u32 payload_index, payload_end_index, next_page_index;
2111 int page, end_page, i, length, offset;
2112
2113 p = packet;
2114 payload_index = payload;
2115
2116 if (p->skip)
2117 z = 1;
2118 else
2119 z = 2;
2120 if (p->header_length > 0)
2121 z++;
2122
2123 /* Determine the first page the payload isn't contained in. */
2124 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2125 if (p->payload_length > 0)
2126 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2127 else
2128 payload_z = 0;
2129
2130 z += payload_z;
2131
2132 /* Get header size in number of descriptors. */
2133 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2134
2135 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2136 if (d == NULL)
2137 return -ENOMEM;
2138
2139 if (!p->skip) {
2140 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2141 d[0].req_count = cpu_to_le16(8);
2142 /*
2143 * Link the skip address to this descriptor itself. This causes
2144 * a context to skip a cycle whenever lost cycles or FIFO
2145 * overruns occur, without dropping the data. The application
2146 * should then decide whether this is an error condition or not.
2147 * FIXME: Make the context's cycle-lost behaviour configurable?
2148 */
2149 d[0].branch_address = cpu_to_le32(d_bus | z);
2150
2151 header = (__le32 *) &d[1];
2152 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2153 IT_HEADER_TAG(p->tag) |
2154 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2155 IT_HEADER_CHANNEL(ctx->base.channel) |
2156 IT_HEADER_SPEED(ctx->base.speed));
2157 header[1] =
2158 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2159 p->payload_length));
2160 }
2161
2162 if (p->header_length > 0) {
2163 d[2].req_count = cpu_to_le16(p->header_length);
2164 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2165 memcpy(&d[z], p->header, p->header_length);
2166 }
2167
2168 pd = d + z - payload_z;
2169 payload_end_index = payload_index + p->payload_length;
2170 for (i = 0; i < payload_z; i++) {
2171 page = payload_index >> PAGE_SHIFT;
2172 offset = payload_index & ~PAGE_MASK;
2173 next_page_index = (page + 1) << PAGE_SHIFT;
2174 length =
2175 min(next_page_index, payload_end_index) - payload_index;
2176 pd[i].req_count = cpu_to_le16(length);
2177
2178 page_bus = page_private(buffer->pages[page]);
2179 pd[i].data_address = cpu_to_le32(page_bus + offset);
2180
2181 payload_index += length;
2182 }
2183
2184 if (p->interrupt)
2185 irq = DESCRIPTOR_IRQ_ALWAYS;
2186 else
2187 irq = DESCRIPTOR_NO_IRQ;
2188
2189 last = z == 2 ? d : d + z - 1;
2190 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2191 DESCRIPTOR_STATUS |
2192 DESCRIPTOR_BRANCH_ALWAYS |
2193 irq);
2194
2195 context_append(&ctx->context, d, z, header_z);
2196
2197 return 0;
2198 }
2199
2200 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2201 struct fw_iso_packet *packet,
2202 struct fw_iso_buffer *buffer,
2203 unsigned long payload)
2204 {
2205 struct iso_context *ctx = container_of(base, struct iso_context, base);
2206 struct descriptor *d, *pd;
2207 struct fw_iso_packet *p = packet;
2208 dma_addr_t d_bus, page_bus;
2209 u32 z, header_z, rest;
2210 int i, j, length;
2211 int page, offset, packet_count, header_size, payload_per_buffer;
2212
2213 /*
2214 * The OHCI controller puts the isochronous header and trailer in the
2215 * buffer, so we need at least 8 bytes.
2216 */
2217 packet_count = p->header_length / ctx->base.header_size;
2218 header_size = max(ctx->base.header_size, (size_t)8);
2219
2220 /* Get header size in number of descriptors. */
2221 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2222 page = payload >> PAGE_SHIFT;
2223 offset = payload & ~PAGE_MASK;
2224 payload_per_buffer = p->payload_length / packet_count;
2225
2226 for (i = 0; i < packet_count; i++) {
2227 /* d points to the header descriptor */
2228 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2229 d = context_get_descriptors(&ctx->context,
2230 z + header_z, &d_bus);
2231 if (d == NULL)
2232 return -ENOMEM;
2233
2234 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2235 DESCRIPTOR_INPUT_MORE);
2236 if (p->skip && i == 0)
2237 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2238 d->req_count = cpu_to_le16(header_size);
2239 d->res_count = d->req_count;
2240 d->transfer_status = 0;
2241 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2242
2243 rest = payload_per_buffer;
2244 pd = d;
2245 for (j = 1; j < z; j++) {
2246 pd++;
2247 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2248 DESCRIPTOR_INPUT_MORE);
2249
2250 if (offset + rest < PAGE_SIZE)
2251 length = rest;
2252 else
2253 length = PAGE_SIZE - offset;
2254 pd->req_count = cpu_to_le16(length);
2255 pd->res_count = pd->req_count;
2256 pd->transfer_status = 0;
2257
2258 page_bus = page_private(buffer->pages[page]);
2259 pd->data_address = cpu_to_le32(page_bus + offset);
2260
2261 offset = (offset + length) & ~PAGE_MASK;
2262 rest -= length;
2263 if (offset == 0)
2264 page++;
2265 }
2266 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2267 DESCRIPTOR_INPUT_LAST |
2268 DESCRIPTOR_BRANCH_ALWAYS);
2269 if (p->interrupt && i == packet_count - 1)
2270 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2271
2272 context_append(&ctx->context, d, z, header_z);
2273 }
2274
2275 return 0;
2276 }
2277
2278 static int ohci_queue_iso(struct fw_iso_context *base,
2279 struct fw_iso_packet *packet,
2280 struct fw_iso_buffer *buffer,
2281 unsigned long payload)
2282 {
2283 struct iso_context *ctx = container_of(base, struct iso_context, base);
2284 unsigned long flags;
2285 int ret;
2286
2287 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2288 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2289 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2290 else
2291 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2292 buffer, payload);
2293 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2294
2295 return ret;
2296 }
2297
2298 static const struct fw_card_driver ohci_driver = {
2299 .enable = ohci_enable,
2300 .update_phy_reg = ohci_update_phy_reg,
2301 .set_config_rom = ohci_set_config_rom,
2302 .send_request = ohci_send_request,
2303 .send_response = ohci_send_response,
2304 .cancel_packet = ohci_cancel_packet,
2305 .enable_phys_dma = ohci_enable_phys_dma,
2306 .get_cycle_time = ohci_get_cycle_time,
2307
2308 .allocate_iso_context = ohci_allocate_iso_context,
2309 .free_iso_context = ohci_free_iso_context,
2310 .queue_iso = ohci_queue_iso,
2311 .start_iso = ohci_start_iso,
2312 .stop_iso = ohci_stop_iso,
2313 };
2314
2315 #ifdef CONFIG_PPC_PMAC
2316 static void ohci_pmac_on(struct pci_dev *dev)
2317 {
2318 if (machine_is(powermac)) {
2319 struct device_node *ofn = pci_device_to_OF_node(dev);
2320
2321 if (ofn) {
2322 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2323 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2324 }
2325 }
2326 }
2327
2328 static void ohci_pmac_off(struct pci_dev *dev)
2329 {
2330 if (machine_is(powermac)) {
2331 struct device_node *ofn = pci_device_to_OF_node(dev);
2332
2333 if (ofn) {
2334 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2335 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2336 }
2337 }
2338 }
2339 #else
2340 #define ohci_pmac_on(dev)
2341 #define ohci_pmac_off(dev)
2342 #endif /* CONFIG_PPC_PMAC */
2343
2344 static int __devinit pci_probe(struct pci_dev *dev,
2345 const struct pci_device_id *ent)
2346 {
2347 struct fw_ohci *ohci;
2348 u32 bus_options, max_receive, link_speed, version;
2349 u64 guid;
2350 int i, err, n_ir, n_it;
2351 size_t size;
2352
2353 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2354 if (ohci == NULL) {
2355 err = -ENOMEM;
2356 goto fail;
2357 }
2358
2359 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2360
2361 ohci_pmac_on(dev);
2362
2363 err = pci_enable_device(dev);
2364 if (err) {
2365 fw_error("Failed to enable OHCI hardware\n");
2366 goto fail_free;
2367 }
2368
2369 pci_set_master(dev);
2370 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2371 pci_set_drvdata(dev, ohci);
2372
2373 spin_lock_init(&ohci->lock);
2374
2375 tasklet_init(&ohci->bus_reset_tasklet,
2376 bus_reset_tasklet, (unsigned long)ohci);
2377
2378 err = pci_request_region(dev, 0, ohci_driver_name);
2379 if (err) {
2380 fw_error("MMIO resource unavailable\n");
2381 goto fail_disable;
2382 }
2383
2384 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2385 if (ohci->registers == NULL) {
2386 fw_error("Failed to remap registers\n");
2387 err = -ENXIO;
2388 goto fail_iomem;
2389 }
2390
2391 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2392 if (ohci_quirks[i].vendor == dev->vendor &&
2393 (ohci_quirks[i].device == dev->device ||
2394 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2395 ohci->quirks = ohci_quirks[i].flags;
2396 break;
2397 }
2398 if (param_quirks)
2399 ohci->quirks = param_quirks;
2400
2401 ar_context_init(&ohci->ar_request_ctx, ohci,
2402 OHCI1394_AsReqRcvContextControlSet);
2403
2404 ar_context_init(&ohci->ar_response_ctx, ohci,
2405 OHCI1394_AsRspRcvContextControlSet);
2406
2407 context_init(&ohci->at_request_ctx, ohci,
2408 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2409
2410 context_init(&ohci->at_response_ctx, ohci,
2411 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2412
2413 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2414 ohci->ir_context_channels = ~0ULL;
2415 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2416 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2417 n_ir = hweight32(ohci->ir_context_mask);
2418 size = sizeof(struct iso_context) * n_ir;
2419 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2420
2421 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2422 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2423 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2424 n_it = hweight32(ohci->it_context_mask);
2425 size = sizeof(struct iso_context) * n_it;
2426 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2427
2428 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2429 err = -ENOMEM;
2430 goto fail_contexts;
2431 }
2432
2433 /* self-id dma buffer allocation */
2434 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2435 SELF_ID_BUF_SIZE,
2436 &ohci->self_id_bus,
2437 GFP_KERNEL);
2438 if (ohci->self_id_cpu == NULL) {
2439 err = -ENOMEM;
2440 goto fail_contexts;
2441 }
2442
2443 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2444 max_receive = (bus_options >> 12) & 0xf;
2445 link_speed = bus_options & 0x7;
2446 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2447 reg_read(ohci, OHCI1394_GUIDLo);
2448
2449 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2450 if (err)
2451 goto fail_self_id;
2452
2453 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2454 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2455 "%d IR + %d IT contexts, quirks 0x%x\n",
2456 dev_name(&dev->dev), version >> 16, version & 0xff,
2457 n_ir, n_it, ohci->quirks);
2458
2459 return 0;
2460
2461 fail_self_id:
2462 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2463 ohci->self_id_cpu, ohci->self_id_bus);
2464 fail_contexts:
2465 kfree(ohci->ir_context_list);
2466 kfree(ohci->it_context_list);
2467 context_release(&ohci->at_response_ctx);
2468 context_release(&ohci->at_request_ctx);
2469 ar_context_release(&ohci->ar_response_ctx);
2470 ar_context_release(&ohci->ar_request_ctx);
2471 pci_iounmap(dev, ohci->registers);
2472 fail_iomem:
2473 pci_release_region(dev, 0);
2474 fail_disable:
2475 pci_disable_device(dev);
2476 fail_free:
2477 kfree(&ohci->card);
2478 ohci_pmac_off(dev);
2479 fail:
2480 if (err == -ENOMEM)
2481 fw_error("Out of memory\n");
2482
2483 return err;
2484 }
2485
2486 static void pci_remove(struct pci_dev *dev)
2487 {
2488 struct fw_ohci *ohci;
2489
2490 ohci = pci_get_drvdata(dev);
2491 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2492 flush_writes(ohci);
2493 fw_core_remove_card(&ohci->card);
2494
2495 /*
2496 * FIXME: Fail all pending packets here, now that the upper
2497 * layers can't queue any more.
2498 */
2499
2500 software_reset(ohci);
2501 free_irq(dev->irq, ohci);
2502
2503 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2504 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2505 ohci->next_config_rom, ohci->next_config_rom_bus);
2506 if (ohci->config_rom)
2507 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2508 ohci->config_rom, ohci->config_rom_bus);
2509 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2510 ohci->self_id_cpu, ohci->self_id_bus);
2511 ar_context_release(&ohci->ar_request_ctx);
2512 ar_context_release(&ohci->ar_response_ctx);
2513 context_release(&ohci->at_request_ctx);
2514 context_release(&ohci->at_response_ctx);
2515 kfree(ohci->it_context_list);
2516 kfree(ohci->ir_context_list);
2517 pci_iounmap(dev, ohci->registers);
2518 pci_release_region(dev, 0);
2519 pci_disable_device(dev);
2520 kfree(&ohci->card);
2521 ohci_pmac_off(dev);
2522
2523 fw_notify("Removed fw-ohci device.\n");
2524 }
2525
2526 #ifdef CONFIG_PM
2527 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2528 {
2529 struct fw_ohci *ohci = pci_get_drvdata(dev);
2530 int err;
2531
2532 software_reset(ohci);
2533 free_irq(dev->irq, ohci);
2534 err = pci_save_state(dev);
2535 if (err) {
2536 fw_error("pci_save_state failed\n");
2537 return err;
2538 }
2539 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2540 if (err)
2541 fw_error("pci_set_power_state failed with %d\n", err);
2542 ohci_pmac_off(dev);
2543
2544 return 0;
2545 }
2546
2547 static int pci_resume(struct pci_dev *dev)
2548 {
2549 struct fw_ohci *ohci = pci_get_drvdata(dev);
2550 int err;
2551
2552 ohci_pmac_on(dev);
2553 pci_set_power_state(dev, PCI_D0);
2554 pci_restore_state(dev);
2555 err = pci_enable_device(dev);
2556 if (err) {
2557 fw_error("pci_enable_device failed\n");
2558 return err;
2559 }
2560
2561 return ohci_enable(&ohci->card, NULL, 0);
2562 }
2563 #endif
2564
2565 static const struct pci_device_id pci_table[] = {
2566 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2567 { }
2568 };
2569
2570 MODULE_DEVICE_TABLE(pci, pci_table);
2571
2572 static struct pci_driver fw_ohci_pci_driver = {
2573 .name = ohci_driver_name,
2574 .id_table = pci_table,
2575 .probe = pci_probe,
2576 .remove = pci_remove,
2577 #ifdef CONFIG_PM
2578 .resume = pci_resume,
2579 .suspend = pci_suspend,
2580 #endif
2581 };
2582
2583 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2584 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2585 MODULE_LICENSE("GPL");
2586
2587 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2588 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2589 MODULE_ALIAS("ohci1394");
2590 #endif
2591
2592 static int __init fw_ohci_init(void)
2593 {
2594 return pci_register_driver(&fw_ohci_pci_driver);
2595 }
2596
2597 static void __exit fw_ohci_cleanup(void)
2598 {
2599 pci_unregister_driver(&fw_ohci_pci_driver);
2600 }
2601
2602 module_init(fw_ohci_init);
2603 module_exit(fw_ohci_cleanup);
CJK support for tty framebuffer vt