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e1000e: conditionally restart autoneg on 82577/8/9 when setting LPLU state
[linux-2.6/cjktty.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
blob6a6e6f6d9e73c72a74a613971a07d71dc0331670
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
57 */
58
59 #include "e1000.h"
60
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
67
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
77
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
80
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
90
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
92
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
102
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
111
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
113
114 #define E1000_ICH_RAR_ENTRIES 7
115
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
121
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
127
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
129
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
135
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
138
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
143
144 /* EMI Registers */
145 #define I82579_EMI_ADDR 0x10
146 #define I82579_EMI_DATA 0x11
147 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
148 #define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */
149 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
150
151 /* Strapping Option Register - RO */
152 #define E1000_STRAP 0x0000C
153 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
154 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
155
156 /* OEM Bits Phy Register */
157 #define HV_OEM_BITS PHY_REG(768, 25)
158 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
159 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
160 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
161
162 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
163 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
164
165 /* KMRN Mode Control */
166 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
167 #define HV_KMRN_MDIO_SLOW 0x0400
168
169 /* KMRN FIFO Control and Status */
170 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
171 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
172 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
173
174 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
175 /* Offset 04h HSFSTS */
176 union ich8_hws_flash_status {
177 struct ich8_hsfsts {
178 u16 flcdone :1; /* bit 0 Flash Cycle Done */
179 u16 flcerr :1; /* bit 1 Flash Cycle Error */
180 u16 dael :1; /* bit 2 Direct Access error Log */
181 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
182 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
183 u16 reserved1 :2; /* bit 13:6 Reserved */
184 u16 reserved2 :6; /* bit 13:6 Reserved */
185 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
186 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
187 } hsf_status;
188 u16 regval;
189 };
190
191 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
192 /* Offset 06h FLCTL */
193 union ich8_hws_flash_ctrl {
194 struct ich8_hsflctl {
195 u16 flcgo :1; /* 0 Flash Cycle Go */
196 u16 flcycle :2; /* 2:1 Flash Cycle */
197 u16 reserved :5; /* 7:3 Reserved */
198 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
199 u16 flockdn :6; /* 15:10 Reserved */
200 } hsf_ctrl;
201 u16 regval;
202 };
203
204 /* ICH Flash Region Access Permissions */
205 union ich8_hws_flash_regacc {
206 struct ich8_flracc {
207 u32 grra :8; /* 0:7 GbE region Read Access */
208 u32 grwa :8; /* 8:15 GbE region Write Access */
209 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
210 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
211 } hsf_flregacc;
212 u16 regval;
213 };
214
215 /* ICH Flash Protected Region */
216 union ich8_flash_protected_range {
217 struct ich8_pr {
218 u32 base:13; /* 0:12 Protected Range Base */
219 u32 reserved1:2; /* 13:14 Reserved */
220 u32 rpe:1; /* 15 Read Protection Enable */
221 u32 limit:13; /* 16:28 Protected Range Limit */
222 u32 reserved2:2; /* 29:30 Reserved */
223 u32 wpe:1; /* 31 Write Protection Enable */
224 } range;
225 u32 regval;
226 };
227
228 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
229 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
230 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
231 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
232 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
233 u32 offset, u8 byte);
234 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
235 u8 *data);
236 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
237 u16 *data);
238 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
239 u8 size, u16 *data);
240 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
241 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
242 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
243 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
244 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
245 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
246 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
247 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
248 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
249 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
250 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
251 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
252 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
253 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
254 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
255 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
256 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
257 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
258 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
259 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
260
261 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
262 {
263 return readw(hw->flash_address + reg);
264 }
265
266 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
267 {
268 return readl(hw->flash_address + reg);
269 }
270
271 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
272 {
273 writew(val, hw->flash_address + reg);
274 }
275
276 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
277 {
278 writel(val, hw->flash_address + reg);
279 }
280
281 #define er16flash(reg) __er16flash(hw, (reg))
282 #define er32flash(reg) __er32flash(hw, (reg))
283 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
284 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
285
286 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
287 {
288 u32 ctrl;
289
290 ctrl = er32(CTRL);
291 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
292 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
293 ew32(CTRL, ctrl);
294 e1e_flush();
295 udelay(10);
296 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
297 ew32(CTRL, ctrl);
298 }
299
300 /**
301 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
302 * @hw: pointer to the HW structure
303 *
304 * Initialize family-specific PHY parameters and function pointers.
305 **/
306 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
307 {
308 struct e1000_phy_info *phy = &hw->phy;
309 s32 ret_val = 0;
310
311 phy->addr = 1;
312 phy->reset_delay_us = 100;
313
314 phy->ops.set_page = e1000_set_page_igp;
315 phy->ops.read_reg = e1000_read_phy_reg_hv;
316 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
317 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
318 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
319 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
320 phy->ops.write_reg = e1000_write_phy_reg_hv;
321 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
322 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
323 phy->ops.power_up = e1000_power_up_phy_copper;
324 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
325 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
326
327 if (!e1000_check_reset_block(hw)) {
328 u32 fwsm = er32(FWSM);
329
330 /*
331 * The MAC-PHY interconnect may still be in SMBus mode after
332 * Sx->S0. If resetting the PHY is not blocked, toggle the
333 * LANPHYPC Value bit to force the interconnect to PCIe mode.
334 */
335 e1000_toggle_lanphypc_value_ich8lan(hw);
336 msleep(50);
337
338 /*
339 * Gate automatic PHY configuration by hardware on
340 * non-managed 82579
341 */
342 if ((hw->mac.type == e1000_pch2lan) &&
343 !(fwsm & E1000_ICH_FWSM_FW_VALID))
344 e1000_gate_hw_phy_config_ich8lan(hw, true);
345
346 /*
347 * Reset the PHY before any access to it. Doing so, ensures
348 * that the PHY is in a known good state before we read/write
349 * PHY registers. The generic reset is sufficient here,
350 * because we haven't determined the PHY type yet.
351 */
352 ret_val = e1000e_phy_hw_reset_generic(hw);
353 if (ret_val)
354 goto out;
355
356 /* Ungate automatic PHY configuration on non-managed 82579 */
357 if ((hw->mac.type == e1000_pch2lan) &&
358 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
359 usleep_range(10000, 20000);
360 e1000_gate_hw_phy_config_ich8lan(hw, false);
361 }
362 }
363
364 phy->id = e1000_phy_unknown;
365 switch (hw->mac.type) {
366 default:
367 ret_val = e1000e_get_phy_id(hw);
368 if (ret_val)
369 goto out;
370 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
371 break;
372 /* fall-through */
373 case e1000_pch2lan:
374 /*
375 * In case the PHY needs to be in mdio slow mode,
376 * set slow mode and try to get the PHY id again.
377 */
378 ret_val = e1000_set_mdio_slow_mode_hv(hw);
379 if (ret_val)
380 goto out;
381 ret_val = e1000e_get_phy_id(hw);
382 if (ret_val)
383 goto out;
384 break;
385 }
386 phy->type = e1000e_get_phy_type_from_id(phy->id);
387
388 switch (phy->type) {
389 case e1000_phy_82577:
390 case e1000_phy_82579:
391 phy->ops.check_polarity = e1000_check_polarity_82577;
392 phy->ops.force_speed_duplex =
393 e1000_phy_force_speed_duplex_82577;
394 phy->ops.get_cable_length = e1000_get_cable_length_82577;
395 phy->ops.get_info = e1000_get_phy_info_82577;
396 phy->ops.commit = e1000e_phy_sw_reset;
397 break;
398 case e1000_phy_82578:
399 phy->ops.check_polarity = e1000_check_polarity_m88;
400 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
401 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
402 phy->ops.get_info = e1000e_get_phy_info_m88;
403 break;
404 default:
405 ret_val = -E1000_ERR_PHY;
406 break;
407 }
408
409 out:
410 return ret_val;
411 }
412
413 /**
414 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
415 * @hw: pointer to the HW structure
416 *
417 * Initialize family-specific PHY parameters and function pointers.
418 **/
419 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
420 {
421 struct e1000_phy_info *phy = &hw->phy;
422 s32 ret_val;
423 u16 i = 0;
424
425 phy->addr = 1;
426 phy->reset_delay_us = 100;
427
428 phy->ops.power_up = e1000_power_up_phy_copper;
429 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
430
431 /*
432 * We may need to do this twice - once for IGP and if that fails,
433 * we'll set BM func pointers and try again
434 */
435 ret_val = e1000e_determine_phy_address(hw);
436 if (ret_val) {
437 phy->ops.write_reg = e1000e_write_phy_reg_bm;
438 phy->ops.read_reg = e1000e_read_phy_reg_bm;
439 ret_val = e1000e_determine_phy_address(hw);
440 if (ret_val) {
441 e_dbg("Cannot determine PHY addr. Erroring out\n");
442 return ret_val;
443 }
444 }
445
446 phy->id = 0;
447 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
448 (i++ < 100)) {
449 usleep_range(1000, 2000);
450 ret_val = e1000e_get_phy_id(hw);
451 if (ret_val)
452 return ret_val;
453 }
454
455 /* Verify phy id */
456 switch (phy->id) {
457 case IGP03E1000_E_PHY_ID:
458 phy->type = e1000_phy_igp_3;
459 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
460 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
461 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
462 phy->ops.get_info = e1000e_get_phy_info_igp;
463 phy->ops.check_polarity = e1000_check_polarity_igp;
464 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
465 break;
466 case IFE_E_PHY_ID:
467 case IFE_PLUS_E_PHY_ID:
468 case IFE_C_E_PHY_ID:
469 phy->type = e1000_phy_ife;
470 phy->autoneg_mask = E1000_ALL_NOT_GIG;
471 phy->ops.get_info = e1000_get_phy_info_ife;
472 phy->ops.check_polarity = e1000_check_polarity_ife;
473 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
474 break;
475 case BME1000_E_PHY_ID:
476 phy->type = e1000_phy_bm;
477 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
478 phy->ops.read_reg = e1000e_read_phy_reg_bm;
479 phy->ops.write_reg = e1000e_write_phy_reg_bm;
480 phy->ops.commit = e1000e_phy_sw_reset;
481 phy->ops.get_info = e1000e_get_phy_info_m88;
482 phy->ops.check_polarity = e1000_check_polarity_m88;
483 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
484 break;
485 default:
486 return -E1000_ERR_PHY;
487 break;
488 }
489
490 return 0;
491 }
492
493 /**
494 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
495 * @hw: pointer to the HW structure
496 *
497 * Initialize family-specific NVM parameters and function
498 * pointers.
499 **/
500 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
501 {
502 struct e1000_nvm_info *nvm = &hw->nvm;
503 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
504 u32 gfpreg, sector_base_addr, sector_end_addr;
505 u16 i;
506
507 /* Can't read flash registers if the register set isn't mapped. */
508 if (!hw->flash_address) {
509 e_dbg("ERROR: Flash registers not mapped\n");
510 return -E1000_ERR_CONFIG;
511 }
512
513 nvm->type = e1000_nvm_flash_sw;
514
515 gfpreg = er32flash(ICH_FLASH_GFPREG);
516
517 /*
518 * sector_X_addr is a "sector"-aligned address (4096 bytes)
519 * Add 1 to sector_end_addr since this sector is included in
520 * the overall size.
521 */
522 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
523 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
524
525 /* flash_base_addr is byte-aligned */
526 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
527
528 /*
529 * find total size of the NVM, then cut in half since the total
530 * size represents two separate NVM banks.
531 */
532 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
533 << FLASH_SECTOR_ADDR_SHIFT;
534 nvm->flash_bank_size /= 2;
535 /* Adjust to word count */
536 nvm->flash_bank_size /= sizeof(u16);
537
538 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
539
540 /* Clear shadow ram */
541 for (i = 0; i < nvm->word_size; i++) {
542 dev_spec->shadow_ram[i].modified = false;
543 dev_spec->shadow_ram[i].value = 0xFFFF;
544 }
545
546 return 0;
547 }
548
549 /**
550 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
551 * @hw: pointer to the HW structure
552 *
553 * Initialize family-specific MAC parameters and function
554 * pointers.
555 **/
556 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
557 {
558 struct e1000_hw *hw = &adapter->hw;
559 struct e1000_mac_info *mac = &hw->mac;
560
561 /* Set media type function pointer */
562 hw->phy.media_type = e1000_media_type_copper;
563
564 /* Set mta register count */
565 mac->mta_reg_count = 32;
566 /* Set rar entry count */
567 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
568 if (mac->type == e1000_ich8lan)
569 mac->rar_entry_count--;
570 /* FWSM register */
571 mac->has_fwsm = true;
572 /* ARC subsystem not supported */
573 mac->arc_subsystem_valid = false;
574 /* Adaptive IFS supported */
575 mac->adaptive_ifs = true;
576
577 /* LED operations */
578 switch (mac->type) {
579 case e1000_ich8lan:
580 case e1000_ich9lan:
581 case e1000_ich10lan:
582 /* check management mode */
583 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
584 /* ID LED init */
585 mac->ops.id_led_init = e1000e_id_led_init;
586 /* blink LED */
587 mac->ops.blink_led = e1000e_blink_led_generic;
588 /* setup LED */
589 mac->ops.setup_led = e1000e_setup_led_generic;
590 /* cleanup LED */
591 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
592 /* turn on/off LED */
593 mac->ops.led_on = e1000_led_on_ich8lan;
594 mac->ops.led_off = e1000_led_off_ich8lan;
595 break;
596 case e1000_pchlan:
597 case e1000_pch2lan:
598 /* check management mode */
599 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
600 /* ID LED init */
601 mac->ops.id_led_init = e1000_id_led_init_pchlan;
602 /* setup LED */
603 mac->ops.setup_led = e1000_setup_led_pchlan;
604 /* cleanup LED */
605 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
606 /* turn on/off LED */
607 mac->ops.led_on = e1000_led_on_pchlan;
608 mac->ops.led_off = e1000_led_off_pchlan;
609 break;
610 default:
611 break;
612 }
613
614 /* Enable PCS Lock-loss workaround for ICH8 */
615 if (mac->type == e1000_ich8lan)
616 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
617
618 /* Gate automatic PHY configuration by hardware on managed 82579 */
619 if ((mac->type == e1000_pch2lan) &&
620 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
621 e1000_gate_hw_phy_config_ich8lan(hw, true);
622
623 return 0;
624 }
625
626 /**
627 * e1000_set_eee_pchlan - Enable/disable EEE support
628 * @hw: pointer to the HW structure
629 *
630 * Enable/disable EEE based on setting in dev_spec structure. The bits in
631 * the LPI Control register will remain set only if/when link is up.
632 **/
633 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
634 {
635 s32 ret_val = 0;
636 u16 phy_reg;
637
638 if (hw->phy.type != e1000_phy_82579)
639 goto out;
640
641 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
642 if (ret_val)
643 goto out;
644
645 if (hw->dev_spec.ich8lan.eee_disable)
646 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
647 else
648 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
649
650 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
651 out:
652 return ret_val;
653 }
654
655 /**
656 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
657 * @hw: pointer to the HW structure
658 *
659 * Checks to see of the link status of the hardware has changed. If a
660 * change in link status has been detected, then we read the PHY registers
661 * to get the current speed/duplex if link exists.
662 **/
663 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
664 {
665 struct e1000_mac_info *mac = &hw->mac;
666 s32 ret_val;
667 bool link;
668 u16 phy_reg;
669
670 /*
671 * We only want to go out to the PHY registers to see if Auto-Neg
672 * has completed and/or if our link status has changed. The
673 * get_link_status flag is set upon receiving a Link Status
674 * Change or Rx Sequence Error interrupt.
675 */
676 if (!mac->get_link_status) {
677 ret_val = 0;
678 goto out;
679 }
680
681 /*
682 * First we want to see if the MII Status Register reports
683 * link. If so, then we want to get the current speed/duplex
684 * of the PHY.
685 */
686 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
687 if (ret_val)
688 goto out;
689
690 if (hw->mac.type == e1000_pchlan) {
691 ret_val = e1000_k1_gig_workaround_hv(hw, link);
692 if (ret_val)
693 goto out;
694 }
695
696 if (!link)
697 goto out; /* No link detected */
698
699 mac->get_link_status = false;
700
701 switch (hw->mac.type) {
702 case e1000_pch2lan:
703 ret_val = e1000_k1_workaround_lv(hw);
704 if (ret_val)
705 goto out;
706 /* fall-thru */
707 case e1000_pchlan:
708 if (hw->phy.type == e1000_phy_82578) {
709 ret_val = e1000_link_stall_workaround_hv(hw);
710 if (ret_val)
711 goto out;
712 }
713
714 /*
715 * Workaround for PCHx parts in half-duplex:
716 * Set the number of preambles removed from the packet
717 * when it is passed from the PHY to the MAC to prevent
718 * the MAC from misinterpreting the packet type.
719 */
720 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
721 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
722
723 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
724 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
725
726 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
727 break;
728 default:
729 break;
730 }
731
732 /*
733 * Check if there was DownShift, must be checked
734 * immediately after link-up
735 */
736 e1000e_check_downshift(hw);
737
738 /* Enable/Disable EEE after link up */
739 ret_val = e1000_set_eee_pchlan(hw);
740 if (ret_val)
741 goto out;
742
743 /*
744 * If we are forcing speed/duplex, then we simply return since
745 * we have already determined whether we have link or not.
746 */
747 if (!mac->autoneg) {
748 ret_val = -E1000_ERR_CONFIG;
749 goto out;
750 }
751
752 /*
753 * Auto-Neg is enabled. Auto Speed Detection takes care
754 * of MAC speed/duplex configuration. So we only need to
755 * configure Collision Distance in the MAC.
756 */
757 e1000e_config_collision_dist(hw);
758
759 /*
760 * Configure Flow Control now that Auto-Neg has completed.
761 * First, we need to restore the desired flow control
762 * settings because we may have had to re-autoneg with a
763 * different link partner.
764 */
765 ret_val = e1000e_config_fc_after_link_up(hw);
766 if (ret_val)
767 e_dbg("Error configuring flow control\n");
768
769 out:
770 return ret_val;
771 }
772
773 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
774 {
775 struct e1000_hw *hw = &adapter->hw;
776 s32 rc;
777
778 rc = e1000_init_mac_params_ich8lan(adapter);
779 if (rc)
780 return rc;
781
782 rc = e1000_init_nvm_params_ich8lan(hw);
783 if (rc)
784 return rc;
785
786 switch (hw->mac.type) {
787 case e1000_ich8lan:
788 case e1000_ich9lan:
789 case e1000_ich10lan:
790 rc = e1000_init_phy_params_ich8lan(hw);
791 break;
792 case e1000_pchlan:
793 case e1000_pch2lan:
794 rc = e1000_init_phy_params_pchlan(hw);
795 break;
796 default:
797 break;
798 }
799 if (rc)
800 return rc;
801
802 /*
803 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
804 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
805 */
806 if ((adapter->hw.phy.type == e1000_phy_ife) ||
807 ((adapter->hw.mac.type >= e1000_pch2lan) &&
808 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
809 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
810 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
811
812 hw->mac.ops.blink_led = NULL;
813 }
814
815 if ((adapter->hw.mac.type == e1000_ich8lan) &&
816 (adapter->hw.phy.type != e1000_phy_ife))
817 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
818
819 /* Enable workaround for 82579 w/ ME enabled */
820 if ((adapter->hw.mac.type == e1000_pch2lan) &&
821 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
822 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
823
824 /* Disable EEE by default until IEEE802.3az spec is finalized */
825 if (adapter->flags2 & FLAG2_HAS_EEE)
826 adapter->hw.dev_spec.ich8lan.eee_disable = true;
827
828 return 0;
829 }
830
831 static DEFINE_MUTEX(nvm_mutex);
832
833 /**
834 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
835 * @hw: pointer to the HW structure
836 *
837 * Acquires the mutex for performing NVM operations.
838 **/
839 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
840 {
841 mutex_lock(&nvm_mutex);
842
843 return 0;
844 }
845
846 /**
847 * e1000_release_nvm_ich8lan - Release NVM mutex
848 * @hw: pointer to the HW structure
849 *
850 * Releases the mutex used while performing NVM operations.
851 **/
852 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
853 {
854 mutex_unlock(&nvm_mutex);
855 }
856
857 /**
858 * e1000_acquire_swflag_ich8lan - Acquire software control flag
859 * @hw: pointer to the HW structure
860 *
861 * Acquires the software control flag for performing PHY and select
862 * MAC CSR accesses.
863 **/
864 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
865 {
866 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
867 s32 ret_val = 0;
868
869 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
870 &hw->adapter->state)) {
871 e_dbg("contention for Phy access\n");
872 return -E1000_ERR_PHY;
873 }
874
875 while (timeout) {
876 extcnf_ctrl = er32(EXTCNF_CTRL);
877 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
878 break;
879
880 mdelay(1);
881 timeout--;
882 }
883
884 if (!timeout) {
885 e_dbg("SW has already locked the resource.\n");
886 ret_val = -E1000_ERR_CONFIG;
887 goto out;
888 }
889
890 timeout = SW_FLAG_TIMEOUT;
891
892 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
893 ew32(EXTCNF_CTRL, extcnf_ctrl);
894
895 while (timeout) {
896 extcnf_ctrl = er32(EXTCNF_CTRL);
897 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
898 break;
899
900 mdelay(1);
901 timeout--;
902 }
903
904 if (!timeout) {
905 e_dbg("Failed to acquire the semaphore, FW or HW has it: "
906 "FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
907 er32(FWSM), extcnf_ctrl);
908 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
909 ew32(EXTCNF_CTRL, extcnf_ctrl);
910 ret_val = -E1000_ERR_CONFIG;
911 goto out;
912 }
913
914 out:
915 if (ret_val)
916 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
917
918 return ret_val;
919 }
920
921 /**
922 * e1000_release_swflag_ich8lan - Release software control flag
923 * @hw: pointer to the HW structure
924 *
925 * Releases the software control flag for performing PHY and select
926 * MAC CSR accesses.
927 **/
928 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
929 {
930 u32 extcnf_ctrl;
931
932 extcnf_ctrl = er32(EXTCNF_CTRL);
933
934 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
935 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
936 ew32(EXTCNF_CTRL, extcnf_ctrl);
937 } else {
938 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
939 }
940
941 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
942 }
943
944 /**
945 * e1000_check_mng_mode_ich8lan - Checks management mode
946 * @hw: pointer to the HW structure
947 *
948 * This checks if the adapter has any manageability enabled.
949 * This is a function pointer entry point only called by read/write
950 * routines for the PHY and NVM parts.
951 **/
952 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
953 {
954 u32 fwsm;
955
956 fwsm = er32(FWSM);
957 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
958 ((fwsm & E1000_FWSM_MODE_MASK) ==
959 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
960 }
961
962 /**
963 * e1000_check_mng_mode_pchlan - Checks management mode
964 * @hw: pointer to the HW structure
965 *
966 * This checks if the adapter has iAMT enabled.
967 * This is a function pointer entry point only called by read/write
968 * routines for the PHY and NVM parts.
969 **/
970 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
971 {
972 u32 fwsm;
973
974 fwsm = er32(FWSM);
975 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
976 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
977 }
978
979 /**
980 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
981 * @hw: pointer to the HW structure
982 *
983 * Checks if firmware is blocking the reset of the PHY.
984 * This is a function pointer entry point only called by
985 * reset routines.
986 **/
987 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
988 {
989 u32 fwsm;
990
991 fwsm = er32(FWSM);
992
993 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
994 }
995
996 /**
997 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
998 * @hw: pointer to the HW structure
999 *
1000 * Assumes semaphore already acquired.
1001 *
1002 **/
1003 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1004 {
1005 u16 phy_data;
1006 u32 strap = er32(STRAP);
1007 s32 ret_val = 0;
1008
1009 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1010
1011 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1012 if (ret_val)
1013 goto out;
1014
1015 phy_data &= ~HV_SMB_ADDR_MASK;
1016 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1017 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1018 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1019
1020 out:
1021 return ret_val;
1022 }
1023
1024 /**
1025 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1026 * @hw: pointer to the HW structure
1027 *
1028 * SW should configure the LCD from the NVM extended configuration region
1029 * as a workaround for certain parts.
1030 **/
1031 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1032 {
1033 struct e1000_phy_info *phy = &hw->phy;
1034 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1035 s32 ret_val = 0;
1036 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1037
1038 /*
1039 * Initialize the PHY from the NVM on ICH platforms. This
1040 * is needed due to an issue where the NVM configuration is
1041 * not properly autoloaded after power transitions.
1042 * Therefore, after each PHY reset, we will load the
1043 * configuration data out of the NVM manually.
1044 */
1045 switch (hw->mac.type) {
1046 case e1000_ich8lan:
1047 if (phy->type != e1000_phy_igp_3)
1048 return ret_val;
1049
1050 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1051 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1052 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1053 break;
1054 }
1055 /* Fall-thru */
1056 case e1000_pchlan:
1057 case e1000_pch2lan:
1058 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1059 break;
1060 default:
1061 return ret_val;
1062 }
1063
1064 ret_val = hw->phy.ops.acquire(hw);
1065 if (ret_val)
1066 return ret_val;
1067
1068 data = er32(FEXTNVM);
1069 if (!(data & sw_cfg_mask))
1070 goto out;
1071
1072 /*
1073 * Make sure HW does not configure LCD from PHY
1074 * extended configuration before SW configuration
1075 */
1076 data = er32(EXTCNF_CTRL);
1077 if (!(hw->mac.type == e1000_pch2lan)) {
1078 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1079 goto out;
1080 }
1081
1082 cnf_size = er32(EXTCNF_SIZE);
1083 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1084 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1085 if (!cnf_size)
1086 goto out;
1087
1088 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1089 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1090
1091 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1092 (hw->mac.type == e1000_pchlan)) ||
1093 (hw->mac.type == e1000_pch2lan)) {
1094 /*
1095 * HW configures the SMBus address and LEDs when the
1096 * OEM and LCD Write Enable bits are set in the NVM.
1097 * When both NVM bits are cleared, SW will configure
1098 * them instead.
1099 */
1100 ret_val = e1000_write_smbus_addr(hw);
1101 if (ret_val)
1102 goto out;
1103
1104 data = er32(LEDCTL);
1105 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1106 (u16)data);
1107 if (ret_val)
1108 goto out;
1109 }
1110
1111 /* Configure LCD from extended configuration region. */
1112
1113 /* cnf_base_addr is in DWORD */
1114 word_addr = (u16)(cnf_base_addr << 1);
1115
1116 for (i = 0; i < cnf_size; i++) {
1117 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1118 &reg_data);
1119 if (ret_val)
1120 goto out;
1121
1122 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1123 1, &reg_addr);
1124 if (ret_val)
1125 goto out;
1126
1127 /* Save off the PHY page for future writes. */
1128 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1129 phy_page = reg_data;
1130 continue;
1131 }
1132
1133 reg_addr &= PHY_REG_MASK;
1134 reg_addr |= phy_page;
1135
1136 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1137 reg_data);
1138 if (ret_val)
1139 goto out;
1140 }
1141
1142 out:
1143 hw->phy.ops.release(hw);
1144 return ret_val;
1145 }
1146
1147 /**
1148 * e1000_k1_gig_workaround_hv - K1 Si workaround
1149 * @hw: pointer to the HW structure
1150 * @link: link up bool flag
1151 *
1152 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1153 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1154 * If link is down, the function will restore the default K1 setting located
1155 * in the NVM.
1156 **/
1157 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1158 {
1159 s32 ret_val = 0;
1160 u16 status_reg = 0;
1161 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1162
1163 if (hw->mac.type != e1000_pchlan)
1164 goto out;
1165
1166 /* Wrap the whole flow with the sw flag */
1167 ret_val = hw->phy.ops.acquire(hw);
1168 if (ret_val)
1169 goto out;
1170
1171 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1172 if (link) {
1173 if (hw->phy.type == e1000_phy_82578) {
1174 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1175 &status_reg);
1176 if (ret_val)
1177 goto release;
1178
1179 status_reg &= BM_CS_STATUS_LINK_UP |
1180 BM_CS_STATUS_RESOLVED |
1181 BM_CS_STATUS_SPEED_MASK;
1182
1183 if (status_reg == (BM_CS_STATUS_LINK_UP |
1184 BM_CS_STATUS_RESOLVED |
1185 BM_CS_STATUS_SPEED_1000))
1186 k1_enable = false;
1187 }
1188
1189 if (hw->phy.type == e1000_phy_82577) {
1190 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1191 &status_reg);
1192 if (ret_val)
1193 goto release;
1194
1195 status_reg &= HV_M_STATUS_LINK_UP |
1196 HV_M_STATUS_AUTONEG_COMPLETE |
1197 HV_M_STATUS_SPEED_MASK;
1198
1199 if (status_reg == (HV_M_STATUS_LINK_UP |
1200 HV_M_STATUS_AUTONEG_COMPLETE |
1201 HV_M_STATUS_SPEED_1000))
1202 k1_enable = false;
1203 }
1204
1205 /* Link stall fix for link up */
1206 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1207 0x0100);
1208 if (ret_val)
1209 goto release;
1210
1211 } else {
1212 /* Link stall fix for link down */
1213 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1214 0x4100);
1215 if (ret_val)
1216 goto release;
1217 }
1218
1219 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1220
1221 release:
1222 hw->phy.ops.release(hw);
1223 out:
1224 return ret_val;
1225 }
1226
1227 /**
1228 * e1000_configure_k1_ich8lan - Configure K1 power state
1229 * @hw: pointer to the HW structure
1230 * @enable: K1 state to configure
1231 *
1232 * Configure the K1 power state based on the provided parameter.
1233 * Assumes semaphore already acquired.
1234 *
1235 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1236 **/
1237 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1238 {
1239 s32 ret_val = 0;
1240 u32 ctrl_reg = 0;
1241 u32 ctrl_ext = 0;
1242 u32 reg = 0;
1243 u16 kmrn_reg = 0;
1244
1245 ret_val = e1000e_read_kmrn_reg_locked(hw,
1246 E1000_KMRNCTRLSTA_K1_CONFIG,
1247 &kmrn_reg);
1248 if (ret_val)
1249 goto out;
1250
1251 if (k1_enable)
1252 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1253 else
1254 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1255
1256 ret_val = e1000e_write_kmrn_reg_locked(hw,
1257 E1000_KMRNCTRLSTA_K1_CONFIG,
1258 kmrn_reg);
1259 if (ret_val)
1260 goto out;
1261
1262 udelay(20);
1263 ctrl_ext = er32(CTRL_EXT);
1264 ctrl_reg = er32(CTRL);
1265
1266 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1267 reg |= E1000_CTRL_FRCSPD;
1268 ew32(CTRL, reg);
1269
1270 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1271 e1e_flush();
1272 udelay(20);
1273 ew32(CTRL, ctrl_reg);
1274 ew32(CTRL_EXT, ctrl_ext);
1275 e1e_flush();
1276 udelay(20);
1277
1278 out:
1279 return ret_val;
1280 }
1281
1282 /**
1283 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1284 * @hw: pointer to the HW structure
1285 * @d0_state: boolean if entering d0 or d3 device state
1286 *
1287 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1288 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1289 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1290 **/
1291 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1292 {
1293 s32 ret_val = 0;
1294 u32 mac_reg;
1295 u16 oem_reg;
1296
1297 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1298 return ret_val;
1299
1300 ret_val = hw->phy.ops.acquire(hw);
1301 if (ret_val)
1302 return ret_val;
1303
1304 if (!(hw->mac.type == e1000_pch2lan)) {
1305 mac_reg = er32(EXTCNF_CTRL);
1306 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1307 goto out;
1308 }
1309
1310 mac_reg = er32(FEXTNVM);
1311 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1312 goto out;
1313
1314 mac_reg = er32(PHY_CTRL);
1315
1316 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1317 if (ret_val)
1318 goto out;
1319
1320 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1321
1322 if (d0_state) {
1323 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1324 oem_reg |= HV_OEM_BITS_GBE_DIS;
1325
1326 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1327 oem_reg |= HV_OEM_BITS_LPLU;
1328
1329 /* Set Restart auto-neg to activate the bits */
1330 if (!e1000_check_reset_block(hw))
1331 oem_reg |= HV_OEM_BITS_RESTART_AN;
1332 } else {
1333 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1334 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1335 oem_reg |= HV_OEM_BITS_GBE_DIS;
1336
1337 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1338 E1000_PHY_CTRL_NOND0A_LPLU))
1339 oem_reg |= HV_OEM_BITS_LPLU;
1340 }
1341
1342 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1343
1344 out:
1345 hw->phy.ops.release(hw);
1346
1347 return ret_val;
1348 }
1349
1350
1351 /**
1352 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1353 * @hw: pointer to the HW structure
1354 **/
1355 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1356 {
1357 s32 ret_val;
1358 u16 data;
1359
1360 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1361 if (ret_val)
1362 return ret_val;
1363
1364 data |= HV_KMRN_MDIO_SLOW;
1365
1366 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1367
1368 return ret_val;
1369 }
1370
1371 /**
1372 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1373 * done after every PHY reset.
1374 **/
1375 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1376 {
1377 s32 ret_val = 0;
1378 u16 phy_data;
1379
1380 if (hw->mac.type != e1000_pchlan)
1381 return ret_val;
1382
1383 /* Set MDIO slow mode before any other MDIO access */
1384 if (hw->phy.type == e1000_phy_82577) {
1385 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1386 if (ret_val)
1387 goto out;
1388 }
1389
1390 if (((hw->phy.type == e1000_phy_82577) &&
1391 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1392 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1393 /* Disable generation of early preamble */
1394 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1395 if (ret_val)
1396 return ret_val;
1397
1398 /* Preamble tuning for SSC */
1399 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1400 if (ret_val)
1401 return ret_val;
1402 }
1403
1404 if (hw->phy.type == e1000_phy_82578) {
1405 /*
1406 * Return registers to default by doing a soft reset then
1407 * writing 0x3140 to the control register.
1408 */
1409 if (hw->phy.revision < 2) {
1410 e1000e_phy_sw_reset(hw);
1411 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1412 }
1413 }
1414
1415 /* Select page 0 */
1416 ret_val = hw->phy.ops.acquire(hw);
1417 if (ret_val)
1418 return ret_val;
1419
1420 hw->phy.addr = 1;
1421 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1422 hw->phy.ops.release(hw);
1423 if (ret_val)
1424 goto out;
1425
1426 /*
1427 * Configure the K1 Si workaround during phy reset assuming there is
1428 * link so that it disables K1 if link is in 1Gbps.
1429 */
1430 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1431 if (ret_val)
1432 goto out;
1433
1434 /* Workaround for link disconnects on a busy hub in half duplex */
1435 ret_val = hw->phy.ops.acquire(hw);
1436 if (ret_val)
1437 goto out;
1438 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1439 if (ret_val)
1440 goto release;
1441 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1442 phy_data & 0x00FF);
1443 release:
1444 hw->phy.ops.release(hw);
1445 out:
1446 return ret_val;
1447 }
1448
1449 /**
1450 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1451 * @hw: pointer to the HW structure
1452 **/
1453 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1454 {
1455 u32 mac_reg;
1456 u16 i, phy_reg = 0;
1457 s32 ret_val;
1458
1459 ret_val = hw->phy.ops.acquire(hw);
1460 if (ret_val)
1461 return;
1462 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1463 if (ret_val)
1464 goto release;
1465
1466 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1467 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1468 mac_reg = er32(RAL(i));
1469 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1470 (u16)(mac_reg & 0xFFFF));
1471 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1472 (u16)((mac_reg >> 16) & 0xFFFF));
1473
1474 mac_reg = er32(RAH(i));
1475 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1476 (u16)(mac_reg & 0xFFFF));
1477 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1478 (u16)((mac_reg & E1000_RAH_AV)
1479 >> 16));
1480 }
1481
1482 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1483
1484 release:
1485 hw->phy.ops.release(hw);
1486 }
1487
1488 /**
1489 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1490 * with 82579 PHY
1491 * @hw: pointer to the HW structure
1492 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1493 **/
1494 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1495 {
1496 s32 ret_val = 0;
1497 u16 phy_reg, data;
1498 u32 mac_reg;
1499 u16 i;
1500
1501 if (hw->mac.type != e1000_pch2lan)
1502 goto out;
1503
1504 /* disable Rx path while enabling/disabling workaround */
1505 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1506 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1507 if (ret_val)
1508 goto out;
1509
1510 if (enable) {
1511 /*
1512 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1513 * SHRAL/H) and initial CRC values to the MAC
1514 */
1515 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1516 u8 mac_addr[ETH_ALEN] = {0};
1517 u32 addr_high, addr_low;
1518
1519 addr_high = er32(RAH(i));
1520 if (!(addr_high & E1000_RAH_AV))
1521 continue;
1522 addr_low = er32(RAL(i));
1523 mac_addr[0] = (addr_low & 0xFF);
1524 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1525 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1526 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1527 mac_addr[4] = (addr_high & 0xFF);
1528 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1529
1530 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1531 }
1532
1533 /* Write Rx addresses to the PHY */
1534 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1535
1536 /* Enable jumbo frame workaround in the MAC */
1537 mac_reg = er32(FFLT_DBG);
1538 mac_reg &= ~(1 << 14);
1539 mac_reg |= (7 << 15);
1540 ew32(FFLT_DBG, mac_reg);
1541
1542 mac_reg = er32(RCTL);
1543 mac_reg |= E1000_RCTL_SECRC;
1544 ew32(RCTL, mac_reg);
1545
1546 ret_val = e1000e_read_kmrn_reg(hw,
1547 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1548 &data);
1549 if (ret_val)
1550 goto out;
1551 ret_val = e1000e_write_kmrn_reg(hw,
1552 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1553 data | (1 << 0));
1554 if (ret_val)
1555 goto out;
1556 ret_val = e1000e_read_kmrn_reg(hw,
1557 E1000_KMRNCTRLSTA_HD_CTRL,
1558 &data);
1559 if (ret_val)
1560 goto out;
1561 data &= ~(0xF << 8);
1562 data |= (0xB << 8);
1563 ret_val = e1000e_write_kmrn_reg(hw,
1564 E1000_KMRNCTRLSTA_HD_CTRL,
1565 data);
1566 if (ret_val)
1567 goto out;
1568
1569 /* Enable jumbo frame workaround in the PHY */
1570 e1e_rphy(hw, PHY_REG(769, 23), &data);
1571 data &= ~(0x7F << 5);
1572 data |= (0x37 << 5);
1573 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1574 if (ret_val)
1575 goto out;
1576 e1e_rphy(hw, PHY_REG(769, 16), &data);
1577 data &= ~(1 << 13);
1578 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1579 if (ret_val)
1580 goto out;
1581 e1e_rphy(hw, PHY_REG(776, 20), &data);
1582 data &= ~(0x3FF << 2);
1583 data |= (0x1A << 2);
1584 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1585 if (ret_val)
1586 goto out;
1587 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1588 if (ret_val)
1589 goto out;
1590 e1e_rphy(hw, HV_PM_CTRL, &data);
1591 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1592 if (ret_val)
1593 goto out;
1594 } else {
1595 /* Write MAC register values back to h/w defaults */
1596 mac_reg = er32(FFLT_DBG);
1597 mac_reg &= ~(0xF << 14);
1598 ew32(FFLT_DBG, mac_reg);
1599
1600 mac_reg = er32(RCTL);
1601 mac_reg &= ~E1000_RCTL_SECRC;
1602 ew32(RCTL, mac_reg);
1603
1604 ret_val = e1000e_read_kmrn_reg(hw,
1605 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1606 &data);
1607 if (ret_val)
1608 goto out;
1609 ret_val = e1000e_write_kmrn_reg(hw,
1610 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1611 data & ~(1 << 0));
1612 if (ret_val)
1613 goto out;
1614 ret_val = e1000e_read_kmrn_reg(hw,
1615 E1000_KMRNCTRLSTA_HD_CTRL,
1616 &data);
1617 if (ret_val)
1618 goto out;
1619 data &= ~(0xF << 8);
1620 data |= (0xB << 8);
1621 ret_val = e1000e_write_kmrn_reg(hw,
1622 E1000_KMRNCTRLSTA_HD_CTRL,
1623 data);
1624 if (ret_val)
1625 goto out;
1626
1627 /* Write PHY register values back to h/w defaults */
1628 e1e_rphy(hw, PHY_REG(769, 23), &data);
1629 data &= ~(0x7F << 5);
1630 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1631 if (ret_val)
1632 goto out;
1633 e1e_rphy(hw, PHY_REG(769, 16), &data);
1634 data |= (1 << 13);
1635 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1636 if (ret_val)
1637 goto out;
1638 e1e_rphy(hw, PHY_REG(776, 20), &data);
1639 data &= ~(0x3FF << 2);
1640 data |= (0x8 << 2);
1641 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1642 if (ret_val)
1643 goto out;
1644 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1645 if (ret_val)
1646 goto out;
1647 e1e_rphy(hw, HV_PM_CTRL, &data);
1648 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1649 if (ret_val)
1650 goto out;
1651 }
1652
1653 /* re-enable Rx path after enabling/disabling workaround */
1654 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1655
1656 out:
1657 return ret_val;
1658 }
1659
1660 /**
1661 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1662 * done after every PHY reset.
1663 **/
1664 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1665 {
1666 s32 ret_val = 0;
1667
1668 if (hw->mac.type != e1000_pch2lan)
1669 goto out;
1670
1671 /* Set MDIO slow mode before any other MDIO access */
1672 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1673
1674 ret_val = hw->phy.ops.acquire(hw);
1675 if (ret_val)
1676 goto out;
1677 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1678 I82579_MSE_THRESHOLD);
1679 if (ret_val)
1680 goto release;
1681 /* set MSE higher to enable link to stay up when noise is high */
1682 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);
1683 if (ret_val)
1684 goto release;
1685 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1686 I82579_MSE_LINK_DOWN);
1687 if (ret_val)
1688 goto release;
1689 /* drop link after 5 times MSE threshold was reached */
1690 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);
1691 release:
1692 hw->phy.ops.release(hw);
1693
1694 out:
1695 return ret_val;
1696 }
1697
1698 /**
1699 * e1000_k1_gig_workaround_lv - K1 Si workaround
1700 * @hw: pointer to the HW structure
1701 *
1702 * Workaround to set the K1 beacon duration for 82579 parts
1703 **/
1704 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1705 {
1706 s32 ret_val = 0;
1707 u16 status_reg = 0;
1708 u32 mac_reg;
1709 u16 phy_reg;
1710
1711 if (hw->mac.type != e1000_pch2lan)
1712 goto out;
1713
1714 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1715 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1716 if (ret_val)
1717 goto out;
1718
1719 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1720 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1721 mac_reg = er32(FEXTNVM4);
1722 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1723
1724 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1725 if (ret_val)
1726 goto out;
1727
1728 if (status_reg & HV_M_STATUS_SPEED_1000) {
1729 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1730 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1731 } else {
1732 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1733 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1734 }
1735 ew32(FEXTNVM4, mac_reg);
1736 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1737 }
1738
1739 out:
1740 return ret_val;
1741 }
1742
1743 /**
1744 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1745 * @hw: pointer to the HW structure
1746 * @gate: boolean set to true to gate, false to ungate
1747 *
1748 * Gate/ungate the automatic PHY configuration via hardware; perform
1749 * the configuration via software instead.
1750 **/
1751 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1752 {
1753 u32 extcnf_ctrl;
1754
1755 if (hw->mac.type != e1000_pch2lan)
1756 return;
1757
1758 extcnf_ctrl = er32(EXTCNF_CTRL);
1759
1760 if (gate)
1761 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1762 else
1763 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1764
1765 ew32(EXTCNF_CTRL, extcnf_ctrl);
1766 return;
1767 }
1768
1769 /**
1770 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1771 * @hw: pointer to the HW structure
1772 *
1773 * Check the appropriate indication the MAC has finished configuring the
1774 * PHY after a software reset.
1775 **/
1776 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1777 {
1778 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1779
1780 /* Wait for basic configuration completes before proceeding */
1781 do {
1782 data = er32(STATUS);
1783 data &= E1000_STATUS_LAN_INIT_DONE;
1784 udelay(100);
1785 } while ((!data) && --loop);
1786
1787 /*
1788 * If basic configuration is incomplete before the above loop
1789 * count reaches 0, loading the configuration from NVM will
1790 * leave the PHY in a bad state possibly resulting in no link.
1791 */
1792 if (loop == 0)
1793 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1794
1795 /* Clear the Init Done bit for the next init event */
1796 data = er32(STATUS);
1797 data &= ~E1000_STATUS_LAN_INIT_DONE;
1798 ew32(STATUS, data);
1799 }
1800
1801 /**
1802 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1803 * @hw: pointer to the HW structure
1804 **/
1805 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1806 {
1807 s32 ret_val = 0;
1808 u16 reg;
1809
1810 if (e1000_check_reset_block(hw))
1811 goto out;
1812
1813 /* Allow time for h/w to get to quiescent state after reset */
1814 usleep_range(10000, 20000);
1815
1816 /* Perform any necessary post-reset workarounds */
1817 switch (hw->mac.type) {
1818 case e1000_pchlan:
1819 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1820 if (ret_val)
1821 goto out;
1822 break;
1823 case e1000_pch2lan:
1824 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1825 if (ret_val)
1826 goto out;
1827 break;
1828 default:
1829 break;
1830 }
1831
1832 /* Clear the host wakeup bit after lcd reset */
1833 if (hw->mac.type >= e1000_pchlan) {
1834 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1835 reg &= ~BM_WUC_HOST_WU_BIT;
1836 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1837 }
1838
1839 /* Configure the LCD with the extended configuration region in NVM */
1840 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1841 if (ret_val)
1842 goto out;
1843
1844 /* Configure the LCD with the OEM bits in NVM */
1845 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1846
1847 if (hw->mac.type == e1000_pch2lan) {
1848 /* Ungate automatic PHY configuration on non-managed 82579 */
1849 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1850 usleep_range(10000, 20000);
1851 e1000_gate_hw_phy_config_ich8lan(hw, false);
1852 }
1853
1854 /* Set EEE LPI Update Timer to 200usec */
1855 ret_val = hw->phy.ops.acquire(hw);
1856 if (ret_val)
1857 goto out;
1858 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1859 I82579_LPI_UPDATE_TIMER);
1860 if (ret_val)
1861 goto release;
1862 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1863 0x1387);
1864 release:
1865 hw->phy.ops.release(hw);
1866 }
1867
1868 out:
1869 return ret_val;
1870 }
1871
1872 /**
1873 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1874 * @hw: pointer to the HW structure
1875 *
1876 * Resets the PHY
1877 * This is a function pointer entry point called by drivers
1878 * or other shared routines.
1879 **/
1880 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1881 {
1882 s32 ret_val = 0;
1883
1884 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1885 if ((hw->mac.type == e1000_pch2lan) &&
1886 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1887 e1000_gate_hw_phy_config_ich8lan(hw, true);
1888
1889 ret_val = e1000e_phy_hw_reset_generic(hw);
1890 if (ret_val)
1891 goto out;
1892
1893 ret_val = e1000_post_phy_reset_ich8lan(hw);
1894
1895 out:
1896 return ret_val;
1897 }
1898
1899 /**
1900 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1901 * @hw: pointer to the HW structure
1902 * @active: true to enable LPLU, false to disable
1903 *
1904 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1905 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1906 * the phy speed. This function will manually set the LPLU bit and restart
1907 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1908 * since it configures the same bit.
1909 **/
1910 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1911 {
1912 s32 ret_val = 0;
1913 u16 oem_reg;
1914
1915 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1916 if (ret_val)
1917 goto out;
1918
1919 if (active)
1920 oem_reg |= HV_OEM_BITS_LPLU;
1921 else
1922 oem_reg &= ~HV_OEM_BITS_LPLU;
1923
1924 if (!e1000_check_reset_block(hw))
1925 oem_reg |= HV_OEM_BITS_RESTART_AN;
1926
1927 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1928
1929 out:
1930 return ret_val;
1931 }
1932
1933 /**
1934 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1935 * @hw: pointer to the HW structure
1936 * @active: true to enable LPLU, false to disable
1937 *
1938 * Sets the LPLU D0 state according to the active flag. When
1939 * activating LPLU this function also disables smart speed
1940 * and vice versa. LPLU will not be activated unless the
1941 * device autonegotiation advertisement meets standards of
1942 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1943 * This is a function pointer entry point only called by
1944 * PHY setup routines.
1945 **/
1946 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1947 {
1948 struct e1000_phy_info *phy = &hw->phy;
1949 u32 phy_ctrl;
1950 s32 ret_val = 0;
1951 u16 data;
1952
1953 if (phy->type == e1000_phy_ife)
1954 return ret_val;
1955
1956 phy_ctrl = er32(PHY_CTRL);
1957
1958 if (active) {
1959 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1960 ew32(PHY_CTRL, phy_ctrl);
1961
1962 if (phy->type != e1000_phy_igp_3)
1963 return 0;
1964
1965 /*
1966 * Call gig speed drop workaround on LPLU before accessing
1967 * any PHY registers
1968 */
1969 if (hw->mac.type == e1000_ich8lan)
1970 e1000e_gig_downshift_workaround_ich8lan(hw);
1971
1972 /* When LPLU is enabled, we should disable SmartSpeed */
1973 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1974 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1975 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1976 if (ret_val)
1977 return ret_val;
1978 } else {
1979 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1980 ew32(PHY_CTRL, phy_ctrl);
1981
1982 if (phy->type != e1000_phy_igp_3)
1983 return 0;
1984
1985 /*
1986 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1987 * during Dx states where the power conservation is most
1988 * important. During driver activity we should enable
1989 * SmartSpeed, so performance is maintained.
1990 */
1991 if (phy->smart_speed == e1000_smart_speed_on) {
1992 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1993 &data);
1994 if (ret_val)
1995 return ret_val;
1996
1997 data |= IGP01E1000_PSCFR_SMART_SPEED;
1998 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1999 data);
2000 if (ret_val)
2001 return ret_val;
2002 } else if (phy->smart_speed == e1000_smart_speed_off) {
2003 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2004 &data);
2005 if (ret_val)
2006 return ret_val;
2007
2008 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2009 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2010 data);
2011 if (ret_val)
2012 return ret_val;
2013 }
2014 }
2015
2016 return 0;
2017 }
2018
2019 /**
2020 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2021 * @hw: pointer to the HW structure
2022 * @active: true to enable LPLU, false to disable
2023 *
2024 * Sets the LPLU D3 state according to the active flag. When
2025 * activating LPLU this function also disables smart speed
2026 * and vice versa. LPLU will not be activated unless the
2027 * device autonegotiation advertisement meets standards of
2028 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2029 * This is a function pointer entry point only called by
2030 * PHY setup routines.
2031 **/
2032 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2033 {
2034 struct e1000_phy_info *phy = &hw->phy;
2035 u32 phy_ctrl;
2036 s32 ret_val;
2037 u16 data;
2038
2039 phy_ctrl = er32(PHY_CTRL);
2040
2041 if (!active) {
2042 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2043 ew32(PHY_CTRL, phy_ctrl);
2044
2045 if (phy->type != e1000_phy_igp_3)
2046 return 0;
2047
2048 /*
2049 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2050 * during Dx states where the power conservation is most
2051 * important. During driver activity we should enable
2052 * SmartSpeed, so performance is maintained.
2053 */
2054 if (phy->smart_speed == e1000_smart_speed_on) {
2055 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2056 &data);
2057 if (ret_val)
2058 return ret_val;
2059
2060 data |= IGP01E1000_PSCFR_SMART_SPEED;
2061 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2062 data);
2063 if (ret_val)
2064 return ret_val;
2065 } else if (phy->smart_speed == e1000_smart_speed_off) {
2066 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2067 &data);
2068 if (ret_val)
2069 return ret_val;
2070
2071 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2072 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2073 data);
2074 if (ret_val)
2075 return ret_val;
2076 }
2077 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2078 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2079 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2080 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2081 ew32(PHY_CTRL, phy_ctrl);
2082
2083 if (phy->type != e1000_phy_igp_3)
2084 return 0;
2085
2086 /*
2087 * Call gig speed drop workaround on LPLU before accessing
2088 * any PHY registers
2089 */
2090 if (hw->mac.type == e1000_ich8lan)
2091 e1000e_gig_downshift_workaround_ich8lan(hw);
2092
2093 /* When LPLU is enabled, we should disable SmartSpeed */
2094 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2095 if (ret_val)
2096 return ret_val;
2097
2098 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2099 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2100 }
2101
2102 return 0;
2103 }
2104
2105 /**
2106 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2107 * @hw: pointer to the HW structure
2108 * @bank: pointer to the variable that returns the active bank
2109 *
2110 * Reads signature byte from the NVM using the flash access registers.
2111 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2112 **/
2113 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2114 {
2115 u32 eecd;
2116 struct e1000_nvm_info *nvm = &hw->nvm;
2117 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2118 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2119 u8 sig_byte = 0;
2120 s32 ret_val = 0;
2121
2122 switch (hw->mac.type) {
2123 case e1000_ich8lan:
2124 case e1000_ich9lan:
2125 eecd = er32(EECD);
2126 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2127 E1000_EECD_SEC1VAL_VALID_MASK) {
2128 if (eecd & E1000_EECD_SEC1VAL)
2129 *bank = 1;
2130 else
2131 *bank = 0;
2132
2133 return 0;
2134 }
2135 e_dbg("Unable to determine valid NVM bank via EEC - "
2136 "reading flash signature\n");
2137 /* fall-thru */
2138 default:
2139 /* set bank to 0 in case flash read fails */
2140 *bank = 0;
2141
2142 /* Check bank 0 */
2143 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2144 &sig_byte);
2145 if (ret_val)
2146 return ret_val;
2147 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2148 E1000_ICH_NVM_SIG_VALUE) {
2149 *bank = 0;
2150 return 0;
2151 }
2152
2153 /* Check bank 1 */
2154 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2155 bank1_offset,
2156 &sig_byte);
2157 if (ret_val)
2158 return ret_val;
2159 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2160 E1000_ICH_NVM_SIG_VALUE) {
2161 *bank = 1;
2162 return 0;
2163 }
2164
2165 e_dbg("ERROR: No valid NVM bank present\n");
2166 return -E1000_ERR_NVM;
2167 }
2168
2169 return 0;
2170 }
2171
2172 /**
2173 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2174 * @hw: pointer to the HW structure
2175 * @offset: The offset (in bytes) of the word(s) to read.
2176 * @words: Size of data to read in words
2177 * @data: Pointer to the word(s) to read at offset.
2178 *
2179 * Reads a word(s) from the NVM using the flash access registers.
2180 **/
2181 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2182 u16 *data)
2183 {
2184 struct e1000_nvm_info *nvm = &hw->nvm;
2185 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2186 u32 act_offset;
2187 s32 ret_val = 0;
2188 u32 bank = 0;
2189 u16 i, word;
2190
2191 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2192 (words == 0)) {
2193 e_dbg("nvm parameter(s) out of bounds\n");
2194 ret_val = -E1000_ERR_NVM;
2195 goto out;
2196 }
2197
2198 nvm->ops.acquire(hw);
2199
2200 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2201 if (ret_val) {
2202 e_dbg("Could not detect valid bank, assuming bank 0\n");
2203 bank = 0;
2204 }
2205
2206 act_offset = (bank) ? nvm->flash_bank_size : 0;
2207 act_offset += offset;
2208
2209 ret_val = 0;
2210 for (i = 0; i < words; i++) {
2211 if (dev_spec->shadow_ram[offset+i].modified) {
2212 data[i] = dev_spec->shadow_ram[offset+i].value;
2213 } else {
2214 ret_val = e1000_read_flash_word_ich8lan(hw,
2215 act_offset + i,
2216 &word);
2217 if (ret_val)
2218 break;
2219 data[i] = word;
2220 }
2221 }
2222
2223 nvm->ops.release(hw);
2224
2225 out:
2226 if (ret_val)
2227 e_dbg("NVM read error: %d\n", ret_val);
2228
2229 return ret_val;
2230 }
2231
2232 /**
2233 * e1000_flash_cycle_init_ich8lan - Initialize flash
2234 * @hw: pointer to the HW structure
2235 *
2236 * This function does initial flash setup so that a new read/write/erase cycle
2237 * can be started.
2238 **/
2239 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2240 {
2241 union ich8_hws_flash_status hsfsts;
2242 s32 ret_val = -E1000_ERR_NVM;
2243
2244 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2245
2246 /* Check if the flash descriptor is valid */
2247 if (hsfsts.hsf_status.fldesvalid == 0) {
2248 e_dbg("Flash descriptor invalid. "
2249 "SW Sequencing must be used.\n");
2250 return -E1000_ERR_NVM;
2251 }
2252
2253 /* Clear FCERR and DAEL in hw status by writing 1 */
2254 hsfsts.hsf_status.flcerr = 1;
2255 hsfsts.hsf_status.dael = 1;
2256
2257 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2258
2259 /*
2260 * Either we should have a hardware SPI cycle in progress
2261 * bit to check against, in order to start a new cycle or
2262 * FDONE bit should be changed in the hardware so that it
2263 * is 1 after hardware reset, which can then be used as an
2264 * indication whether a cycle is in progress or has been
2265 * completed.
2266 */
2267
2268 if (hsfsts.hsf_status.flcinprog == 0) {
2269 /*
2270 * There is no cycle running at present,
2271 * so we can start a cycle.
2272 * Begin by setting Flash Cycle Done.
2273 */
2274 hsfsts.hsf_status.flcdone = 1;
2275 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2276 ret_val = 0;
2277 } else {
2278 s32 i = 0;
2279
2280 /*
2281 * Otherwise poll for sometime so the current
2282 * cycle has a chance to end before giving up.
2283 */
2284 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2285 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2286 if (hsfsts.hsf_status.flcinprog == 0) {
2287 ret_val = 0;
2288 break;
2289 }
2290 udelay(1);
2291 }
2292 if (ret_val == 0) {
2293 /*
2294 * Successful in waiting for previous cycle to timeout,
2295 * now set the Flash Cycle Done.
2296 */
2297 hsfsts.hsf_status.flcdone = 1;
2298 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2299 } else {
2300 e_dbg("Flash controller busy, cannot get access\n");
2301 }
2302 }
2303
2304 return ret_val;
2305 }
2306
2307 /**
2308 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2309 * @hw: pointer to the HW structure
2310 * @timeout: maximum time to wait for completion
2311 *
2312 * This function starts a flash cycle and waits for its completion.
2313 **/
2314 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2315 {
2316 union ich8_hws_flash_ctrl hsflctl;
2317 union ich8_hws_flash_status hsfsts;
2318 s32 ret_val = -E1000_ERR_NVM;
2319 u32 i = 0;
2320
2321 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2322 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2323 hsflctl.hsf_ctrl.flcgo = 1;
2324 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2325
2326 /* wait till FDONE bit is set to 1 */
2327 do {
2328 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2329 if (hsfsts.hsf_status.flcdone == 1)
2330 break;
2331 udelay(1);
2332 } while (i++ < timeout);
2333
2334 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2335 return 0;
2336
2337 return ret_val;
2338 }
2339
2340 /**
2341 * e1000_read_flash_word_ich8lan - Read word from flash
2342 * @hw: pointer to the HW structure
2343 * @offset: offset to data location
2344 * @data: pointer to the location for storing the data
2345 *
2346 * Reads the flash word at offset into data. Offset is converted
2347 * to bytes before read.
2348 **/
2349 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2350 u16 *data)
2351 {
2352 /* Must convert offset into bytes. */
2353 offset <<= 1;
2354
2355 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2356 }
2357
2358 /**
2359 * e1000_read_flash_byte_ich8lan - Read byte from flash
2360 * @hw: pointer to the HW structure
2361 * @offset: The offset of the byte to read.
2362 * @data: Pointer to a byte to store the value read.
2363 *
2364 * Reads a single byte from the NVM using the flash access registers.
2365 **/
2366 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2367 u8 *data)
2368 {
2369 s32 ret_val;
2370 u16 word = 0;
2371
2372 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2373 if (ret_val)
2374 return ret_val;
2375
2376 *data = (u8)word;
2377
2378 return 0;
2379 }
2380
2381 /**
2382 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2383 * @hw: pointer to the HW structure
2384 * @offset: The offset (in bytes) of the byte or word to read.
2385 * @size: Size of data to read, 1=byte 2=word
2386 * @data: Pointer to the word to store the value read.
2387 *
2388 * Reads a byte or word from the NVM using the flash access registers.
2389 **/
2390 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2391 u8 size, u16 *data)
2392 {
2393 union ich8_hws_flash_status hsfsts;
2394 union ich8_hws_flash_ctrl hsflctl;
2395 u32 flash_linear_addr;
2396 u32 flash_data = 0;
2397 s32 ret_val = -E1000_ERR_NVM;
2398 u8 count = 0;
2399
2400 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2401 return -E1000_ERR_NVM;
2402
2403 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2404 hw->nvm.flash_base_addr;
2405
2406 do {
2407 udelay(1);
2408 /* Steps */
2409 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2410 if (ret_val != 0)
2411 break;
2412
2413 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2414 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2415 hsflctl.hsf_ctrl.fldbcount = size - 1;
2416 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2417 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2418
2419 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2420
2421 ret_val = e1000_flash_cycle_ich8lan(hw,
2422 ICH_FLASH_READ_COMMAND_TIMEOUT);
2423
2424 /*
2425 * Check if FCERR is set to 1, if set to 1, clear it
2426 * and try the whole sequence a few more times, else
2427 * read in (shift in) the Flash Data0, the order is
2428 * least significant byte first msb to lsb
2429 */
2430 if (ret_val == 0) {
2431 flash_data = er32flash(ICH_FLASH_FDATA0);
2432 if (size == 1)
2433 *data = (u8)(flash_data & 0x000000FF);
2434 else if (size == 2)
2435 *data = (u16)(flash_data & 0x0000FFFF);
2436 break;
2437 } else {
2438 /*
2439 * If we've gotten here, then things are probably
2440 * completely hosed, but if the error condition is
2441 * detected, it won't hurt to give it another try...
2442 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2443 */
2444 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2445 if (hsfsts.hsf_status.flcerr == 1) {
2446 /* Repeat for some time before giving up. */
2447 continue;
2448 } else if (hsfsts.hsf_status.flcdone == 0) {
2449 e_dbg("Timeout error - flash cycle "
2450 "did not complete.\n");
2451 break;
2452 }
2453 }
2454 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2455
2456 return ret_val;
2457 }
2458
2459 /**
2460 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2461 * @hw: pointer to the HW structure
2462 * @offset: The offset (in bytes) of the word(s) to write.
2463 * @words: Size of data to write in words
2464 * @data: Pointer to the word(s) to write at offset.
2465 *
2466 * Writes a byte or word to the NVM using the flash access registers.
2467 **/
2468 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2469 u16 *data)
2470 {
2471 struct e1000_nvm_info *nvm = &hw->nvm;
2472 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2473 u16 i;
2474
2475 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2476 (words == 0)) {
2477 e_dbg("nvm parameter(s) out of bounds\n");
2478 return -E1000_ERR_NVM;
2479 }
2480
2481 nvm->ops.acquire(hw);
2482
2483 for (i = 0; i < words; i++) {
2484 dev_spec->shadow_ram[offset+i].modified = true;
2485 dev_spec->shadow_ram[offset+i].value = data[i];
2486 }
2487
2488 nvm->ops.release(hw);
2489
2490 return 0;
2491 }
2492
2493 /**
2494 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2495 * @hw: pointer to the HW structure
2496 *
2497 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2498 * which writes the checksum to the shadow ram. The changes in the shadow
2499 * ram are then committed to the EEPROM by processing each bank at a time
2500 * checking for the modified bit and writing only the pending changes.
2501 * After a successful commit, the shadow ram is cleared and is ready for
2502 * future writes.
2503 **/
2504 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2505 {
2506 struct e1000_nvm_info *nvm = &hw->nvm;
2507 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2508 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2509 s32 ret_val;
2510 u16 data;
2511
2512 ret_val = e1000e_update_nvm_checksum_generic(hw);
2513 if (ret_val)
2514 goto out;
2515
2516 if (nvm->type != e1000_nvm_flash_sw)
2517 goto out;
2518
2519 nvm->ops.acquire(hw);
2520
2521 /*
2522 * We're writing to the opposite bank so if we're on bank 1,
2523 * write to bank 0 etc. We also need to erase the segment that
2524 * is going to be written
2525 */
2526 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2527 if (ret_val) {
2528 e_dbg("Could not detect valid bank, assuming bank 0\n");
2529 bank = 0;
2530 }
2531
2532 if (bank == 0) {
2533 new_bank_offset = nvm->flash_bank_size;
2534 old_bank_offset = 0;
2535 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2536 if (ret_val)
2537 goto release;
2538 } else {
2539 old_bank_offset = nvm->flash_bank_size;
2540 new_bank_offset = 0;
2541 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2542 if (ret_val)
2543 goto release;
2544 }
2545
2546 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2547 /*
2548 * Determine whether to write the value stored
2549 * in the other NVM bank or a modified value stored
2550 * in the shadow RAM
2551 */
2552 if (dev_spec->shadow_ram[i].modified) {
2553 data = dev_spec->shadow_ram[i].value;
2554 } else {
2555 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2556 old_bank_offset,
2557 &data);
2558 if (ret_val)
2559 break;
2560 }
2561
2562 /*
2563 * If the word is 0x13, then make sure the signature bits
2564 * (15:14) are 11b until the commit has completed.
2565 * This will allow us to write 10b which indicates the
2566 * signature is valid. We want to do this after the write
2567 * has completed so that we don't mark the segment valid
2568 * while the write is still in progress
2569 */
2570 if (i == E1000_ICH_NVM_SIG_WORD)
2571 data |= E1000_ICH_NVM_SIG_MASK;
2572
2573 /* Convert offset to bytes. */
2574 act_offset = (i + new_bank_offset) << 1;
2575
2576 udelay(100);
2577 /* Write the bytes to the new bank. */
2578 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2579 act_offset,
2580 (u8)data);
2581 if (ret_val)
2582 break;
2583
2584 udelay(100);
2585 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2586 act_offset + 1,
2587 (u8)(data >> 8));
2588 if (ret_val)
2589 break;
2590 }
2591
2592 /*
2593 * Don't bother writing the segment valid bits if sector
2594 * programming failed.
2595 */
2596 if (ret_val) {
2597 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2598 e_dbg("Flash commit failed.\n");
2599 goto release;
2600 }
2601
2602 /*
2603 * Finally validate the new segment by setting bit 15:14
2604 * to 10b in word 0x13 , this can be done without an
2605 * erase as well since these bits are 11 to start with
2606 * and we need to change bit 14 to 0b
2607 */
2608 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2609 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2610 if (ret_val)
2611 goto release;
2612
2613 data &= 0xBFFF;
2614 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2615 act_offset * 2 + 1,
2616 (u8)(data >> 8));
2617 if (ret_val)
2618 goto release;
2619
2620 /*
2621 * And invalidate the previously valid segment by setting
2622 * its signature word (0x13) high_byte to 0b. This can be
2623 * done without an erase because flash erase sets all bits
2624 * to 1's. We can write 1's to 0's without an erase
2625 */
2626 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2627 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2628 if (ret_val)
2629 goto release;
2630
2631 /* Great! Everything worked, we can now clear the cached entries. */
2632 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2633 dev_spec->shadow_ram[i].modified = false;
2634 dev_spec->shadow_ram[i].value = 0xFFFF;
2635 }
2636
2637 release:
2638 nvm->ops.release(hw);
2639
2640 /*
2641 * Reload the EEPROM, or else modifications will not appear
2642 * until after the next adapter reset.
2643 */
2644 if (!ret_val) {
2645 e1000e_reload_nvm(hw);
2646 usleep_range(10000, 20000);
2647 }
2648
2649 out:
2650 if (ret_val)
2651 e_dbg("NVM update error: %d\n", ret_val);
2652
2653 return ret_val;
2654 }
2655
2656 /**
2657 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2658 * @hw: pointer to the HW structure
2659 *
2660 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2661 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2662 * calculated, in which case we need to calculate the checksum and set bit 6.
2663 **/
2664 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2665 {
2666 s32 ret_val;
2667 u16 data;
2668
2669 /*
2670 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2671 * needs to be fixed. This bit is an indication that the NVM
2672 * was prepared by OEM software and did not calculate the
2673 * checksum...a likely scenario.
2674 */
2675 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2676 if (ret_val)
2677 return ret_val;
2678
2679 if ((data & 0x40) == 0) {
2680 data |= 0x40;
2681 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2682 if (ret_val)
2683 return ret_val;
2684 ret_val = e1000e_update_nvm_checksum(hw);
2685 if (ret_val)
2686 return ret_val;
2687 }
2688
2689 return e1000e_validate_nvm_checksum_generic(hw);
2690 }
2691
2692 /**
2693 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2694 * @hw: pointer to the HW structure
2695 *
2696 * To prevent malicious write/erase of the NVM, set it to be read-only
2697 * so that the hardware ignores all write/erase cycles of the NVM via
2698 * the flash control registers. The shadow-ram copy of the NVM will
2699 * still be updated, however any updates to this copy will not stick
2700 * across driver reloads.
2701 **/
2702 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2703 {
2704 struct e1000_nvm_info *nvm = &hw->nvm;
2705 union ich8_flash_protected_range pr0;
2706 union ich8_hws_flash_status hsfsts;
2707 u32 gfpreg;
2708
2709 nvm->ops.acquire(hw);
2710
2711 gfpreg = er32flash(ICH_FLASH_GFPREG);
2712
2713 /* Write-protect GbE Sector of NVM */
2714 pr0.regval = er32flash(ICH_FLASH_PR0);
2715 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2716 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2717 pr0.range.wpe = true;
2718 ew32flash(ICH_FLASH_PR0, pr0.regval);
2719
2720 /*
2721 * Lock down a subset of GbE Flash Control Registers, e.g.
2722 * PR0 to prevent the write-protection from being lifted.
2723 * Once FLOCKDN is set, the registers protected by it cannot
2724 * be written until FLOCKDN is cleared by a hardware reset.
2725 */
2726 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2727 hsfsts.hsf_status.flockdn = true;
2728 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2729
2730 nvm->ops.release(hw);
2731 }
2732
2733 /**
2734 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2735 * @hw: pointer to the HW structure
2736 * @offset: The offset (in bytes) of the byte/word to read.
2737 * @size: Size of data to read, 1=byte 2=word
2738 * @data: The byte(s) to write to the NVM.
2739 *
2740 * Writes one/two bytes to the NVM using the flash access registers.
2741 **/
2742 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2743 u8 size, u16 data)
2744 {
2745 union ich8_hws_flash_status hsfsts;
2746 union ich8_hws_flash_ctrl hsflctl;
2747 u32 flash_linear_addr;
2748 u32 flash_data = 0;
2749 s32 ret_val;
2750 u8 count = 0;
2751
2752 if (size < 1 || size > 2 || data > size * 0xff ||
2753 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2754 return -E1000_ERR_NVM;
2755
2756 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2757 hw->nvm.flash_base_addr;
2758
2759 do {
2760 udelay(1);
2761 /* Steps */
2762 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2763 if (ret_val)
2764 break;
2765
2766 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2767 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2768 hsflctl.hsf_ctrl.fldbcount = size -1;
2769 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2770 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2771
2772 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2773
2774 if (size == 1)
2775 flash_data = (u32)data & 0x00FF;
2776 else
2777 flash_data = (u32)data;
2778
2779 ew32flash(ICH_FLASH_FDATA0, flash_data);
2780
2781 /*
2782 * check if FCERR is set to 1 , if set to 1, clear it
2783 * and try the whole sequence a few more times else done
2784 */
2785 ret_val = e1000_flash_cycle_ich8lan(hw,
2786 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2787 if (!ret_val)
2788 break;
2789
2790 /*
2791 * If we're here, then things are most likely
2792 * completely hosed, but if the error condition
2793 * is detected, it won't hurt to give it another
2794 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2795 */
2796 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2797 if (hsfsts.hsf_status.flcerr == 1)
2798 /* Repeat for some time before giving up. */
2799 continue;
2800 if (hsfsts.hsf_status.flcdone == 0) {
2801 e_dbg("Timeout error - flash cycle "
2802 "did not complete.");
2803 break;
2804 }
2805 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2806
2807 return ret_val;
2808 }
2809
2810 /**
2811 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2812 * @hw: pointer to the HW structure
2813 * @offset: The index of the byte to read.
2814 * @data: The byte to write to the NVM.
2815 *
2816 * Writes a single byte to the NVM using the flash access registers.
2817 **/
2818 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2819 u8 data)
2820 {
2821 u16 word = (u16)data;
2822
2823 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2824 }
2825
2826 /**
2827 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2828 * @hw: pointer to the HW structure
2829 * @offset: The offset of the byte to write.
2830 * @byte: The byte to write to the NVM.
2831 *
2832 * Writes a single byte to the NVM using the flash access registers.
2833 * Goes through a retry algorithm before giving up.
2834 **/
2835 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2836 u32 offset, u8 byte)
2837 {
2838 s32 ret_val;
2839 u16 program_retries;
2840
2841 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2842 if (!ret_val)
2843 return ret_val;
2844
2845 for (program_retries = 0; program_retries < 100; program_retries++) {
2846 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2847 udelay(100);
2848 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2849 if (!ret_val)
2850 break;
2851 }
2852 if (program_retries == 100)
2853 return -E1000_ERR_NVM;
2854
2855 return 0;
2856 }
2857
2858 /**
2859 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2860 * @hw: pointer to the HW structure
2861 * @bank: 0 for first bank, 1 for second bank, etc.
2862 *
2863 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2864 * bank N is 4096 * N + flash_reg_addr.
2865 **/
2866 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2867 {
2868 struct e1000_nvm_info *nvm = &hw->nvm;
2869 union ich8_hws_flash_status hsfsts;
2870 union ich8_hws_flash_ctrl hsflctl;
2871 u32 flash_linear_addr;
2872 /* bank size is in 16bit words - adjust to bytes */
2873 u32 flash_bank_size = nvm->flash_bank_size * 2;
2874 s32 ret_val;
2875 s32 count = 0;
2876 s32 j, iteration, sector_size;
2877
2878 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2879
2880 /*
2881 * Determine HW Sector size: Read BERASE bits of hw flash status
2882 * register
2883 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2884 * consecutive sectors. The start index for the nth Hw sector
2885 * can be calculated as = bank * 4096 + n * 256
2886 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2887 * The start index for the nth Hw sector can be calculated
2888 * as = bank * 4096
2889 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2890 * (ich9 only, otherwise error condition)
2891 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2892 */
2893 switch (hsfsts.hsf_status.berasesz) {
2894 case 0:
2895 /* Hw sector size 256 */
2896 sector_size = ICH_FLASH_SEG_SIZE_256;
2897 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2898 break;
2899 case 1:
2900 sector_size = ICH_FLASH_SEG_SIZE_4K;
2901 iteration = 1;
2902 break;
2903 case 2:
2904 sector_size = ICH_FLASH_SEG_SIZE_8K;
2905 iteration = 1;
2906 break;
2907 case 3:
2908 sector_size = ICH_FLASH_SEG_SIZE_64K;
2909 iteration = 1;
2910 break;
2911 default:
2912 return -E1000_ERR_NVM;
2913 }
2914
2915 /* Start with the base address, then add the sector offset. */
2916 flash_linear_addr = hw->nvm.flash_base_addr;
2917 flash_linear_addr += (bank) ? flash_bank_size : 0;
2918
2919 for (j = 0; j < iteration ; j++) {
2920 do {
2921 /* Steps */
2922 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2923 if (ret_val)
2924 return ret_val;
2925
2926 /*
2927 * Write a value 11 (block Erase) in Flash
2928 * Cycle field in hw flash control
2929 */
2930 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2931 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2932 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2933
2934 /*
2935 * Write the last 24 bits of an index within the
2936 * block into Flash Linear address field in Flash
2937 * Address.
2938 */
2939 flash_linear_addr += (j * sector_size);
2940 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2941
2942 ret_val = e1000_flash_cycle_ich8lan(hw,
2943 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2944 if (ret_val == 0)
2945 break;
2946
2947 /*
2948 * Check if FCERR is set to 1. If 1,
2949 * clear it and try the whole sequence
2950 * a few more times else Done
2951 */
2952 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2953 if (hsfsts.hsf_status.flcerr == 1)
2954 /* repeat for some time before giving up */
2955 continue;
2956 else if (hsfsts.hsf_status.flcdone == 0)
2957 return ret_val;
2958 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2959 }
2960
2961 return 0;
2962 }
2963
2964 /**
2965 * e1000_valid_led_default_ich8lan - Set the default LED settings
2966 * @hw: pointer to the HW structure
2967 * @data: Pointer to the LED settings
2968 *
2969 * Reads the LED default settings from the NVM to data. If the NVM LED
2970 * settings is all 0's or F's, set the LED default to a valid LED default
2971 * setting.
2972 **/
2973 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2974 {
2975 s32 ret_val;
2976
2977 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2978 if (ret_val) {
2979 e_dbg("NVM Read Error\n");
2980 return ret_val;
2981 }
2982
2983 if (*data == ID_LED_RESERVED_0000 ||
2984 *data == ID_LED_RESERVED_FFFF)
2985 *data = ID_LED_DEFAULT_ICH8LAN;
2986
2987 return 0;
2988 }
2989
2990 /**
2991 * e1000_id_led_init_pchlan - store LED configurations
2992 * @hw: pointer to the HW structure
2993 *
2994 * PCH does not control LEDs via the LEDCTL register, rather it uses
2995 * the PHY LED configuration register.
2996 *
2997 * PCH also does not have an "always on" or "always off" mode which
2998 * complicates the ID feature. Instead of using the "on" mode to indicate
2999 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
3000 * use "link_up" mode. The LEDs will still ID on request if there is no
3001 * link based on logic in e1000_led_[on|off]_pchlan().
3002 **/
3003 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3004 {
3005 struct e1000_mac_info *mac = &hw->mac;
3006 s32 ret_val;
3007 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3008 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3009 u16 data, i, temp, shift;
3010
3011 /* Get default ID LED modes */
3012 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3013 if (ret_val)
3014 goto out;
3015
3016 mac->ledctl_default = er32(LEDCTL);
3017 mac->ledctl_mode1 = mac->ledctl_default;
3018 mac->ledctl_mode2 = mac->ledctl_default;
3019
3020 for (i = 0; i < 4; i++) {
3021 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3022 shift = (i * 5);
3023 switch (temp) {
3024 case ID_LED_ON1_DEF2:
3025 case ID_LED_ON1_ON2:
3026 case ID_LED_ON1_OFF2:
3027 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3028 mac->ledctl_mode1 |= (ledctl_on << shift);
3029 break;
3030 case ID_LED_OFF1_DEF2:
3031 case ID_LED_OFF1_ON2:
3032 case ID_LED_OFF1_OFF2:
3033 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3034 mac->ledctl_mode1 |= (ledctl_off << shift);
3035 break;
3036 default:
3037 /* Do nothing */
3038 break;
3039 }
3040 switch (temp) {
3041 case ID_LED_DEF1_ON2:
3042 case ID_LED_ON1_ON2:
3043 case ID_LED_OFF1_ON2:
3044 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3045 mac->ledctl_mode2 |= (ledctl_on << shift);
3046 break;
3047 case ID_LED_DEF1_OFF2:
3048 case ID_LED_ON1_OFF2:
3049 case ID_LED_OFF1_OFF2:
3050 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3051 mac->ledctl_mode2 |= (ledctl_off << shift);
3052 break;
3053 default:
3054 /* Do nothing */
3055 break;
3056 }
3057 }
3058
3059 out:
3060 return ret_val;
3061 }
3062
3063 /**
3064 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3065 * @hw: pointer to the HW structure
3066 *
3067 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3068 * register, so the the bus width is hard coded.
3069 **/
3070 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3071 {
3072 struct e1000_bus_info *bus = &hw->bus;
3073 s32 ret_val;
3074
3075 ret_val = e1000e_get_bus_info_pcie(hw);
3076
3077 /*
3078 * ICH devices are "PCI Express"-ish. They have
3079 * a configuration space, but do not contain
3080 * PCI Express Capability registers, so bus width
3081 * must be hardcoded.
3082 */
3083 if (bus->width == e1000_bus_width_unknown)
3084 bus->width = e1000_bus_width_pcie_x1;
3085
3086 return ret_val;
3087 }
3088
3089 /**
3090 * e1000_reset_hw_ich8lan - Reset the hardware
3091 * @hw: pointer to the HW structure
3092 *
3093 * Does a full reset of the hardware which includes a reset of the PHY and
3094 * MAC.
3095 **/
3096 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3097 {
3098 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3099 u16 reg;
3100 u32 ctrl, kab;
3101 s32 ret_val;
3102
3103 /*
3104 * Prevent the PCI-E bus from sticking if there is no TLP connection
3105 * on the last TLP read/write transaction when MAC is reset.
3106 */
3107 ret_val = e1000e_disable_pcie_master(hw);
3108 if (ret_val)
3109 e_dbg("PCI-E Master disable polling has failed.\n");
3110
3111 e_dbg("Masking off all interrupts\n");
3112 ew32(IMC, 0xffffffff);
3113
3114 /*
3115 * Disable the Transmit and Receive units. Then delay to allow
3116 * any pending transactions to complete before we hit the MAC
3117 * with the global reset.
3118 */
3119 ew32(RCTL, 0);
3120 ew32(TCTL, E1000_TCTL_PSP);
3121 e1e_flush();
3122
3123 usleep_range(10000, 20000);
3124
3125 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3126 if (hw->mac.type == e1000_ich8lan) {
3127 /* Set Tx and Rx buffer allocation to 8k apiece. */
3128 ew32(PBA, E1000_PBA_8K);
3129 /* Set Packet Buffer Size to 16k. */
3130 ew32(PBS, E1000_PBS_16K);
3131 }
3132
3133 if (hw->mac.type == e1000_pchlan) {
3134 /* Save the NVM K1 bit setting*/
3135 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3136 if (ret_val)
3137 return ret_val;
3138
3139 if (reg & E1000_NVM_K1_ENABLE)
3140 dev_spec->nvm_k1_enabled = true;
3141 else
3142 dev_spec->nvm_k1_enabled = false;
3143 }
3144
3145 ctrl = er32(CTRL);
3146
3147 if (!e1000_check_reset_block(hw)) {
3148 /*
3149 * Full-chip reset requires MAC and PHY reset at the same
3150 * time to make sure the interface between MAC and the
3151 * external PHY is reset.
3152 */
3153 ctrl |= E1000_CTRL_PHY_RST;
3154
3155 /*
3156 * Gate automatic PHY configuration by hardware on
3157 * non-managed 82579
3158 */
3159 if ((hw->mac.type == e1000_pch2lan) &&
3160 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3161 e1000_gate_hw_phy_config_ich8lan(hw, true);
3162 }
3163 ret_val = e1000_acquire_swflag_ich8lan(hw);
3164 e_dbg("Issuing a global reset to ich8lan\n");
3165 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3166 /* cannot issue a flush here because it hangs the hardware */
3167 msleep(20);
3168
3169 if (!ret_val)
3170 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3171
3172 if (ctrl & E1000_CTRL_PHY_RST) {
3173 ret_val = hw->phy.ops.get_cfg_done(hw);
3174 if (ret_val)
3175 goto out;
3176
3177 ret_val = e1000_post_phy_reset_ich8lan(hw);
3178 if (ret_val)
3179 goto out;
3180 }
3181
3182 /*
3183 * For PCH, this write will make sure that any noise
3184 * will be detected as a CRC error and be dropped rather than show up
3185 * as a bad packet to the DMA engine.
3186 */
3187 if (hw->mac.type == e1000_pchlan)
3188 ew32(CRC_OFFSET, 0x65656565);
3189
3190 ew32(IMC, 0xffffffff);
3191 er32(ICR);
3192
3193 kab = er32(KABGTXD);
3194 kab |= E1000_KABGTXD_BGSQLBIAS;
3195 ew32(KABGTXD, kab);
3196
3197 out:
3198 return ret_val;
3199 }
3200
3201 /**
3202 * e1000_init_hw_ich8lan - Initialize the hardware
3203 * @hw: pointer to the HW structure
3204 *
3205 * Prepares the hardware for transmit and receive by doing the following:
3206 * - initialize hardware bits
3207 * - initialize LED identification
3208 * - setup receive address registers
3209 * - setup flow control
3210 * - setup transmit descriptors
3211 * - clear statistics
3212 **/
3213 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3214 {
3215 struct e1000_mac_info *mac = &hw->mac;
3216 u32 ctrl_ext, txdctl, snoop;
3217 s32 ret_val;
3218 u16 i;
3219
3220 e1000_initialize_hw_bits_ich8lan(hw);
3221
3222 /* Initialize identification LED */
3223 ret_val = mac->ops.id_led_init(hw);
3224 if (ret_val)
3225 e_dbg("Error initializing identification LED\n");
3226 /* This is not fatal and we should not stop init due to this */
3227
3228 /* Setup the receive address. */
3229 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3230
3231 /* Zero out the Multicast HASH table */
3232 e_dbg("Zeroing the MTA\n");
3233 for (i = 0; i < mac->mta_reg_count; i++)
3234 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3235
3236 /*
3237 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3238 * the ME. Disable wakeup by clearing the host wakeup bit.
3239 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3240 */
3241 if (hw->phy.type == e1000_phy_82578) {
3242 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3243 i &= ~BM_WUC_HOST_WU_BIT;
3244 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3245 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3246 if (ret_val)
3247 return ret_val;
3248 }
3249
3250 /* Setup link and flow control */
3251 ret_val = e1000_setup_link_ich8lan(hw);
3252
3253 /* Set the transmit descriptor write-back policy for both queues */
3254 txdctl = er32(TXDCTL(0));
3255 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3256 E1000_TXDCTL_FULL_TX_DESC_WB;
3257 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3258 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3259 ew32(TXDCTL(0), txdctl);
3260 txdctl = er32(TXDCTL(1));
3261 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3262 E1000_TXDCTL_FULL_TX_DESC_WB;
3263 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3264 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3265 ew32(TXDCTL(1), txdctl);
3266
3267 /*
3268 * ICH8 has opposite polarity of no_snoop bits.
3269 * By default, we should use snoop behavior.
3270 */
3271 if (mac->type == e1000_ich8lan)
3272 snoop = PCIE_ICH8_SNOOP_ALL;
3273 else
3274 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3275 e1000e_set_pcie_no_snoop(hw, snoop);
3276
3277 ctrl_ext = er32(CTRL_EXT);
3278 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3279 ew32(CTRL_EXT, ctrl_ext);
3280
3281 /*
3282 * Clear all of the statistics registers (clear on read). It is
3283 * important that we do this after we have tried to establish link
3284 * because the symbol error count will increment wildly if there
3285 * is no link.
3286 */
3287 e1000_clear_hw_cntrs_ich8lan(hw);
3288
3289 return 0;
3290 }
3291 /**
3292 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3293 * @hw: pointer to the HW structure
3294 *
3295 * Sets/Clears required hardware bits necessary for correctly setting up the
3296 * hardware for transmit and receive.
3297 **/
3298 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3299 {
3300 u32 reg;
3301
3302 /* Extended Device Control */
3303 reg = er32(CTRL_EXT);
3304 reg |= (1 << 22);
3305 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3306 if (hw->mac.type >= e1000_pchlan)
3307 reg |= E1000_CTRL_EXT_PHYPDEN;
3308 ew32(CTRL_EXT, reg);
3309
3310 /* Transmit Descriptor Control 0 */
3311 reg = er32(TXDCTL(0));
3312 reg |= (1 << 22);
3313 ew32(TXDCTL(0), reg);
3314
3315 /* Transmit Descriptor Control 1 */
3316 reg = er32(TXDCTL(1));
3317 reg |= (1 << 22);
3318 ew32(TXDCTL(1), reg);
3319
3320 /* Transmit Arbitration Control 0 */
3321 reg = er32(TARC(0));
3322 if (hw->mac.type == e1000_ich8lan)
3323 reg |= (1 << 28) | (1 << 29);
3324 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3325 ew32(TARC(0), reg);
3326
3327 /* Transmit Arbitration Control 1 */
3328 reg = er32(TARC(1));
3329 if (er32(TCTL) & E1000_TCTL_MULR)
3330 reg &= ~(1 << 28);
3331 else
3332 reg |= (1 << 28);
3333 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3334 ew32(TARC(1), reg);
3335
3336 /* Device Status */
3337 if (hw->mac.type == e1000_ich8lan) {
3338 reg = er32(STATUS);
3339 reg &= ~(1 << 31);
3340 ew32(STATUS, reg);
3341 }
3342
3343 /*
3344 * work-around descriptor data corruption issue during nfs v2 udp
3345 * traffic, just disable the nfs filtering capability
3346 */
3347 reg = er32(RFCTL);
3348 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3349 ew32(RFCTL, reg);
3350 }
3351
3352 /**
3353 * e1000_setup_link_ich8lan - Setup flow control and link settings
3354 * @hw: pointer to the HW structure
3355 *
3356 * Determines which flow control settings to use, then configures flow
3357 * control. Calls the appropriate media-specific link configuration
3358 * function. Assuming the adapter has a valid link partner, a valid link
3359 * should be established. Assumes the hardware has previously been reset
3360 * and the transmitter and receiver are not enabled.
3361 **/
3362 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3363 {
3364 s32 ret_val;
3365
3366 if (e1000_check_reset_block(hw))
3367 return 0;
3368
3369 /*
3370 * ICH parts do not have a word in the NVM to determine
3371 * the default flow control setting, so we explicitly
3372 * set it to full.
3373 */
3374 if (hw->fc.requested_mode == e1000_fc_default) {
3375 /* Workaround h/w hang when Tx flow control enabled */
3376 if (hw->mac.type == e1000_pchlan)
3377 hw->fc.requested_mode = e1000_fc_rx_pause;
3378 else
3379 hw->fc.requested_mode = e1000_fc_full;
3380 }
3381
3382 /*
3383 * Save off the requested flow control mode for use later. Depending
3384 * on the link partner's capabilities, we may or may not use this mode.
3385 */
3386 hw->fc.current_mode = hw->fc.requested_mode;
3387
3388 e_dbg("After fix-ups FlowControl is now = %x\n",
3389 hw->fc.current_mode);
3390
3391 /* Continue to configure the copper link. */
3392 ret_val = e1000_setup_copper_link_ich8lan(hw);
3393 if (ret_val)
3394 return ret_val;
3395
3396 ew32(FCTTV, hw->fc.pause_time);
3397 if ((hw->phy.type == e1000_phy_82578) ||
3398 (hw->phy.type == e1000_phy_82579) ||
3399 (hw->phy.type == e1000_phy_82577)) {
3400 ew32(FCRTV_PCH, hw->fc.refresh_time);
3401
3402 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3403 hw->fc.pause_time);
3404 if (ret_val)
3405 return ret_val;
3406 }
3407
3408 return e1000e_set_fc_watermarks(hw);
3409 }
3410
3411 /**
3412 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3413 * @hw: pointer to the HW structure
3414 *
3415 * Configures the kumeran interface to the PHY to wait the appropriate time
3416 * when polling the PHY, then call the generic setup_copper_link to finish
3417 * configuring the copper link.
3418 **/
3419 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3420 {
3421 u32 ctrl;
3422 s32 ret_val;
3423 u16 reg_data;
3424
3425 ctrl = er32(CTRL);
3426 ctrl |= E1000_CTRL_SLU;
3427 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3428 ew32(CTRL, ctrl);
3429
3430 /*
3431 * Set the mac to wait the maximum time between each iteration
3432 * and increase the max iterations when polling the phy;
3433 * this fixes erroneous timeouts at 10Mbps.
3434 */
3435 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3436 if (ret_val)
3437 return ret_val;
3438 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3439 &reg_data);
3440 if (ret_val)
3441 return ret_val;
3442 reg_data |= 0x3F;
3443 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3444 reg_data);
3445 if (ret_val)
3446 return ret_val;
3447
3448 switch (hw->phy.type) {
3449 case e1000_phy_igp_3:
3450 ret_val = e1000e_copper_link_setup_igp(hw);
3451 if (ret_val)
3452 return ret_val;
3453 break;
3454 case e1000_phy_bm:
3455 case e1000_phy_82578:
3456 ret_val = e1000e_copper_link_setup_m88(hw);
3457 if (ret_val)
3458 return ret_val;
3459 break;
3460 case e1000_phy_82577:
3461 case e1000_phy_82579:
3462 ret_val = e1000_copper_link_setup_82577(hw);
3463 if (ret_val)
3464 return ret_val;
3465 break;
3466 case e1000_phy_ife:
3467 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3468 if (ret_val)
3469 return ret_val;
3470
3471 reg_data &= ~IFE_PMC_AUTO_MDIX;
3472
3473 switch (hw->phy.mdix) {
3474 case 1:
3475 reg_data &= ~IFE_PMC_FORCE_MDIX;
3476 break;
3477 case 2:
3478 reg_data |= IFE_PMC_FORCE_MDIX;
3479 break;
3480 case 0:
3481 default:
3482 reg_data |= IFE_PMC_AUTO_MDIX;
3483 break;
3484 }
3485 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3486 if (ret_val)
3487 return ret_val;
3488 break;
3489 default:
3490 break;
3491 }
3492 return e1000e_setup_copper_link(hw);
3493 }
3494
3495 /**
3496 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3497 * @hw: pointer to the HW structure
3498 * @speed: pointer to store current link speed
3499 * @duplex: pointer to store the current link duplex
3500 *
3501 * Calls the generic get_speed_and_duplex to retrieve the current link
3502 * information and then calls the Kumeran lock loss workaround for links at
3503 * gigabit speeds.
3504 **/
3505 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3506 u16 *duplex)
3507 {
3508 s32 ret_val;
3509
3510 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3511 if (ret_val)
3512 return ret_val;
3513
3514 if ((hw->mac.type == e1000_ich8lan) &&
3515 (hw->phy.type == e1000_phy_igp_3) &&
3516 (*speed == SPEED_1000)) {
3517 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3518 }
3519
3520 return ret_val;
3521 }
3522
3523 /**
3524 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3525 * @hw: pointer to the HW structure
3526 *
3527 * Work-around for 82566 Kumeran PCS lock loss:
3528 * On link status change (i.e. PCI reset, speed change) and link is up and
3529 * speed is gigabit-
3530 * 0) if workaround is optionally disabled do nothing
3531 * 1) wait 1ms for Kumeran link to come up
3532 * 2) check Kumeran Diagnostic register PCS lock loss bit
3533 * 3) if not set the link is locked (all is good), otherwise...
3534 * 4) reset the PHY
3535 * 5) repeat up to 10 times
3536 * Note: this is only called for IGP3 copper when speed is 1gb.
3537 **/
3538 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3539 {
3540 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3541 u32 phy_ctrl;
3542 s32 ret_val;
3543 u16 i, data;
3544 bool link;
3545
3546 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3547 return 0;
3548
3549 /*
3550 * Make sure link is up before proceeding. If not just return.
3551 * Attempting this while link is negotiating fouled up link
3552 * stability
3553 */
3554 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3555 if (!link)
3556 return 0;
3557
3558 for (i = 0; i < 10; i++) {
3559 /* read once to clear */
3560 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3561 if (ret_val)
3562 return ret_val;
3563 /* and again to get new status */
3564 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3565 if (ret_val)
3566 return ret_val;
3567
3568 /* check for PCS lock */
3569 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3570 return 0;
3571
3572 /* Issue PHY reset */
3573 e1000_phy_hw_reset(hw);
3574 mdelay(5);
3575 }
3576 /* Disable GigE link negotiation */
3577 phy_ctrl = er32(PHY_CTRL);
3578 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3579 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3580 ew32(PHY_CTRL, phy_ctrl);
3581
3582 /*
3583 * Call gig speed drop workaround on Gig disable before accessing
3584 * any PHY registers
3585 */
3586 e1000e_gig_downshift_workaround_ich8lan(hw);
3587
3588 /* unable to acquire PCS lock */
3589 return -E1000_ERR_PHY;
3590 }
3591
3592 /**
3593 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3594 * @hw: pointer to the HW structure
3595 * @state: boolean value used to set the current Kumeran workaround state
3596 *
3597 * If ICH8, set the current Kumeran workaround state (enabled - true
3598 * /disabled - false).
3599 **/
3600 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3601 bool state)
3602 {
3603 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3604
3605 if (hw->mac.type != e1000_ich8lan) {
3606 e_dbg("Workaround applies to ICH8 only.\n");
3607 return;
3608 }
3609
3610 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3611 }
3612
3613 /**
3614 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3615 * @hw: pointer to the HW structure
3616 *
3617 * Workaround for 82566 power-down on D3 entry:
3618 * 1) disable gigabit link
3619 * 2) write VR power-down enable
3620 * 3) read it back
3621 * Continue if successful, else issue LCD reset and repeat
3622 **/
3623 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3624 {
3625 u32 reg;
3626 u16 data;
3627 u8 retry = 0;
3628
3629 if (hw->phy.type != e1000_phy_igp_3)
3630 return;
3631
3632 /* Try the workaround twice (if needed) */
3633 do {
3634 /* Disable link */
3635 reg = er32(PHY_CTRL);
3636 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3637 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3638 ew32(PHY_CTRL, reg);
3639
3640 /*
3641 * Call gig speed drop workaround on Gig disable before
3642 * accessing any PHY registers
3643 */
3644 if (hw->mac.type == e1000_ich8lan)
3645 e1000e_gig_downshift_workaround_ich8lan(hw);
3646
3647 /* Write VR power-down enable */
3648 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3649 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3650 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3651
3652 /* Read it back and test */
3653 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3654 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3655 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3656 break;
3657
3658 /* Issue PHY reset and repeat at most one more time */
3659 reg = er32(CTRL);
3660 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3661 retry++;
3662 } while (retry);
3663 }
3664
3665 /**
3666 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3667 * @hw: pointer to the HW structure
3668 *
3669 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3670 * LPLU, Gig disable, MDIC PHY reset):
3671 * 1) Set Kumeran Near-end loopback
3672 * 2) Clear Kumeran Near-end loopback
3673 * Should only be called for ICH8[m] devices with any 1G Phy.
3674 **/
3675 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3676 {
3677 s32 ret_val;
3678 u16 reg_data;
3679
3680 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3681 return;
3682
3683 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3684 &reg_data);
3685 if (ret_val)
3686 return;
3687 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3688 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3689 reg_data);
3690 if (ret_val)
3691 return;
3692 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3693 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3694 reg_data);
3695 }
3696
3697 /**
3698 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3699 * @hw: pointer to the HW structure
3700 *
3701 * During S0 to Sx transition, it is possible the link remains at gig
3702 * instead of negotiating to a lower speed. Before going to Sx, set
3703 * 'Gig Disable' to force link speed negotiation to a lower speed based on
3704 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
3705 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3706 * needs to be written.
3707 **/
3708 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3709 {
3710 u32 phy_ctrl;
3711 s32 ret_val;
3712
3713 phy_ctrl = er32(PHY_CTRL);
3714 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
3715 ew32(PHY_CTRL, phy_ctrl);
3716
3717 if (hw->mac.type == e1000_ich8lan)
3718 e1000e_gig_downshift_workaround_ich8lan(hw);
3719
3720 if (hw->mac.type >= e1000_pchlan) {
3721 e1000_oem_bits_config_ich8lan(hw, false);
3722 e1000_phy_hw_reset_ich8lan(hw);
3723 ret_val = hw->phy.ops.acquire(hw);
3724 if (ret_val)
3725 return;
3726 e1000_write_smbus_addr(hw);
3727 hw->phy.ops.release(hw);
3728 }
3729 }
3730
3731 /**
3732 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3733 * @hw: pointer to the HW structure
3734 *
3735 * During Sx to S0 transitions on non-managed devices or managed devices
3736 * on which PHY resets are not blocked, if the PHY registers cannot be
3737 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
3738 * the PHY.
3739 **/
3740 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3741 {
3742 u16 phy_id1, phy_id2;
3743 s32 ret_val;
3744
3745 if ((hw->mac.type != e1000_pch2lan) || e1000_check_reset_block(hw))
3746 return;
3747
3748 ret_val = hw->phy.ops.acquire(hw);
3749 if (ret_val) {
3750 e_dbg("Failed to acquire PHY semaphore in resume\n");
3751 return;
3752 }
3753
3754 /* Test access to the PHY registers by reading the ID regs */
3755 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3756 if (ret_val)
3757 goto release;
3758 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3759 if (ret_val)
3760 goto release;
3761
3762 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3763 (u32)(phy_id2 & PHY_REVISION_MASK)))
3764 goto release;
3765
3766 e1000_toggle_lanphypc_value_ich8lan(hw);
3767
3768 hw->phy.ops.release(hw);
3769 msleep(50);
3770 e1000_phy_hw_reset(hw);
3771 msleep(50);
3772 return;
3773
3774 release:
3775 hw->phy.ops.release(hw);
3776
3777 return;
3778 }
3779
3780 /**
3781 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3782 * @hw: pointer to the HW structure
3783 *
3784 * Return the LED back to the default configuration.
3785 **/
3786 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3787 {
3788 if (hw->phy.type == e1000_phy_ife)
3789 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3790
3791 ew32(LEDCTL, hw->mac.ledctl_default);
3792 return 0;
3793 }
3794
3795 /**
3796 * e1000_led_on_ich8lan - Turn LEDs on
3797 * @hw: pointer to the HW structure
3798 *
3799 * Turn on the LEDs.
3800 **/
3801 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3802 {
3803 if (hw->phy.type == e1000_phy_ife)
3804 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3805 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3806
3807 ew32(LEDCTL, hw->mac.ledctl_mode2);
3808 return 0;
3809 }
3810
3811 /**
3812 * e1000_led_off_ich8lan - Turn LEDs off
3813 * @hw: pointer to the HW structure
3814 *
3815 * Turn off the LEDs.
3816 **/
3817 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3818 {
3819 if (hw->phy.type == e1000_phy_ife)
3820 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3821 (IFE_PSCL_PROBE_MODE |
3822 IFE_PSCL_PROBE_LEDS_OFF));
3823
3824 ew32(LEDCTL, hw->mac.ledctl_mode1);
3825 return 0;
3826 }
3827
3828 /**
3829 * e1000_setup_led_pchlan - Configures SW controllable LED
3830 * @hw: pointer to the HW structure
3831 *
3832 * This prepares the SW controllable LED for use.
3833 **/
3834 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3835 {
3836 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3837 }
3838
3839 /**
3840 * e1000_cleanup_led_pchlan - Restore the default LED operation
3841 * @hw: pointer to the HW structure
3842 *
3843 * Return the LED back to the default configuration.
3844 **/
3845 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3846 {
3847 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3848 }
3849
3850 /**
3851 * e1000_led_on_pchlan - Turn LEDs on
3852 * @hw: pointer to the HW structure
3853 *
3854 * Turn on the LEDs.
3855 **/
3856 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3857 {
3858 u16 data = (u16)hw->mac.ledctl_mode2;
3859 u32 i, led;
3860
3861 /*
3862 * If no link, then turn LED on by setting the invert bit
3863 * for each LED that's mode is "link_up" in ledctl_mode2.
3864 */
3865 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3866 for (i = 0; i < 3; i++) {
3867 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3868 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3869 E1000_LEDCTL_MODE_LINK_UP)
3870 continue;
3871 if (led & E1000_PHY_LED0_IVRT)
3872 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3873 else
3874 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3875 }
3876 }
3877
3878 return e1e_wphy(hw, HV_LED_CONFIG, data);
3879 }
3880
3881 /**
3882 * e1000_led_off_pchlan - Turn LEDs off
3883 * @hw: pointer to the HW structure
3884 *
3885 * Turn off the LEDs.
3886 **/
3887 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3888 {
3889 u16 data = (u16)hw->mac.ledctl_mode1;
3890 u32 i, led;
3891
3892 /*
3893 * If no link, then turn LED off by clearing the invert bit
3894 * for each LED that's mode is "link_up" in ledctl_mode1.
3895 */
3896 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3897 for (i = 0; i < 3; i++) {
3898 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3899 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3900 E1000_LEDCTL_MODE_LINK_UP)
3901 continue;
3902 if (led & E1000_PHY_LED0_IVRT)
3903 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3904 else
3905 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3906 }
3907 }
3908
3909 return e1e_wphy(hw, HV_LED_CONFIG, data);
3910 }
3911
3912 /**
3913 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3914 * @hw: pointer to the HW structure
3915 *
3916 * Read appropriate register for the config done bit for completion status
3917 * and configure the PHY through s/w for EEPROM-less parts.
3918 *
3919 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3920 * config done bit, so only an error is logged and continues. If we were
3921 * to return with error, EEPROM-less silicon would not be able to be reset
3922 * or change link.
3923 **/
3924 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3925 {
3926 s32 ret_val = 0;
3927 u32 bank = 0;
3928 u32 status;
3929
3930 e1000e_get_cfg_done(hw);
3931
3932 /* Wait for indication from h/w that it has completed basic config */
3933 if (hw->mac.type >= e1000_ich10lan) {
3934 e1000_lan_init_done_ich8lan(hw);
3935 } else {
3936 ret_val = e1000e_get_auto_rd_done(hw);
3937 if (ret_val) {
3938 /*
3939 * When auto config read does not complete, do not
3940 * return with an error. This can happen in situations
3941 * where there is no eeprom and prevents getting link.
3942 */
3943 e_dbg("Auto Read Done did not complete\n");
3944 ret_val = 0;
3945 }
3946 }
3947
3948 /* Clear PHY Reset Asserted bit */
3949 status = er32(STATUS);
3950 if (status & E1000_STATUS_PHYRA)
3951 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3952 else
3953 e_dbg("PHY Reset Asserted not set - needs delay\n");
3954
3955 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3956 if (hw->mac.type <= e1000_ich9lan) {
3957 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3958 (hw->phy.type == e1000_phy_igp_3)) {
3959 e1000e_phy_init_script_igp3(hw);
3960 }
3961 } else {
3962 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3963 /* Maybe we should do a basic PHY config */
3964 e_dbg("EEPROM not present\n");
3965 ret_val = -E1000_ERR_CONFIG;
3966 }
3967 }
3968
3969 return ret_val;
3970 }
3971
3972 /**
3973 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3974 * @hw: pointer to the HW structure
3975 *
3976 * In the case of a PHY power down to save power, or to turn off link during a
3977 * driver unload, or wake on lan is not enabled, remove the link.
3978 **/
3979 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3980 {
3981 /* If the management interface is not enabled, then power down */
3982 if (!(hw->mac.ops.check_mng_mode(hw) ||
3983 hw->phy.ops.check_reset_block(hw)))
3984 e1000_power_down_phy_copper(hw);
3985 }
3986
3987 /**
3988 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3989 * @hw: pointer to the HW structure
3990 *
3991 * Clears hardware counters specific to the silicon family and calls
3992 * clear_hw_cntrs_generic to clear all general purpose counters.
3993 **/
3994 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3995 {
3996 u16 phy_data;
3997 s32 ret_val;
3998
3999 e1000e_clear_hw_cntrs_base(hw);
4000
4001 er32(ALGNERRC);
4002 er32(RXERRC);
4003 er32(TNCRS);
4004 er32(CEXTERR);
4005 er32(TSCTC);
4006 er32(TSCTFC);
4007
4008 er32(MGTPRC);
4009 er32(MGTPDC);
4010 er32(MGTPTC);
4011
4012 er32(IAC);
4013 er32(ICRXOC);
4014
4015 /* Clear PHY statistics registers */
4016 if ((hw->phy.type == e1000_phy_82578) ||
4017 (hw->phy.type == e1000_phy_82579) ||
4018 (hw->phy.type == e1000_phy_82577)) {
4019 ret_val = hw->phy.ops.acquire(hw);
4020 if (ret_val)
4021 return;
4022 ret_val = hw->phy.ops.set_page(hw,
4023 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4024 if (ret_val)
4025 goto release;
4026 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4027 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4028 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4029 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4030 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4031 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4032 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4033 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4034 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4035 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4036 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4037 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4038 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4039 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4040 release:
4041 hw->phy.ops.release(hw);
4042 }
4043 }
4044
4045 static const struct e1000_mac_operations ich8_mac_ops = {
4046 .id_led_init = e1000e_id_led_init,
4047 /* check_mng_mode dependent on mac type */
4048 .check_for_link = e1000_check_for_copper_link_ich8lan,
4049 /* cleanup_led dependent on mac type */
4050 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4051 .get_bus_info = e1000_get_bus_info_ich8lan,
4052 .set_lan_id = e1000_set_lan_id_single_port,
4053 .get_link_up_info = e1000_get_link_up_info_ich8lan,
4054 /* led_on dependent on mac type */
4055 /* led_off dependent on mac type */
4056 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
4057 .reset_hw = e1000_reset_hw_ich8lan,
4058 .init_hw = e1000_init_hw_ich8lan,
4059 .setup_link = e1000_setup_link_ich8lan,
4060 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4061 /* id_led_init dependent on mac type */
4062 };
4063
4064 static const struct e1000_phy_operations ich8_phy_ops = {
4065 .acquire = e1000_acquire_swflag_ich8lan,
4066 .check_reset_block = e1000_check_reset_block_ich8lan,
4067 .commit = NULL,
4068 .get_cfg_done = e1000_get_cfg_done_ich8lan,
4069 .get_cable_length = e1000e_get_cable_length_igp_2,
4070 .read_reg = e1000e_read_phy_reg_igp,
4071 .release = e1000_release_swflag_ich8lan,
4072 .reset = e1000_phy_hw_reset_ich8lan,
4073 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4074 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
4075 .write_reg = e1000e_write_phy_reg_igp,
4076 };
4077
4078 static const struct e1000_nvm_operations ich8_nvm_ops = {
4079 .acquire = e1000_acquire_nvm_ich8lan,
4080 .read = e1000_read_nvm_ich8lan,
4081 .release = e1000_release_nvm_ich8lan,
4082 .update = e1000_update_nvm_checksum_ich8lan,
4083 .valid_led_default = e1000_valid_led_default_ich8lan,
4084 .validate = e1000_validate_nvm_checksum_ich8lan,
4085 .write = e1000_write_nvm_ich8lan,
4086 };
4087
4088 const struct e1000_info e1000_ich8_info = {
4089 .mac = e1000_ich8lan,
4090 .flags = FLAG_HAS_WOL
4091 | FLAG_IS_ICH
4092 | FLAG_HAS_CTRLEXT_ON_LOAD
4093 | FLAG_HAS_AMT
4094 | FLAG_HAS_FLASH
4095 | FLAG_APME_IN_WUC,
4096 .pba = 8,
4097 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
4098 .get_variants = e1000_get_variants_ich8lan,
4099 .mac_ops = &ich8_mac_ops,
4100 .phy_ops = &ich8_phy_ops,
4101 .nvm_ops = &ich8_nvm_ops,
4102 };
4103
4104 const struct e1000_info e1000_ich9_info = {
4105 .mac = e1000_ich9lan,
4106 .flags = FLAG_HAS_JUMBO_FRAMES
4107 | FLAG_IS_ICH
4108 | FLAG_HAS_WOL
4109 | FLAG_HAS_CTRLEXT_ON_LOAD
4110 | FLAG_HAS_AMT
4111 | FLAG_HAS_FLASH
4112 | FLAG_APME_IN_WUC,
4113 .pba = 18,
4114 .max_hw_frame_size = DEFAULT_JUMBO,
4115 .get_variants = e1000_get_variants_ich8lan,
4116 .mac_ops = &ich8_mac_ops,
4117 .phy_ops = &ich8_phy_ops,
4118 .nvm_ops = &ich8_nvm_ops,
4119 };
4120
4121 const struct e1000_info e1000_ich10_info = {
4122 .mac = e1000_ich10lan,
4123 .flags = FLAG_HAS_JUMBO_FRAMES
4124 | FLAG_IS_ICH
4125 | FLAG_HAS_WOL
4126 | FLAG_HAS_CTRLEXT_ON_LOAD
4127 | FLAG_HAS_AMT
4128 | FLAG_HAS_FLASH
4129 | FLAG_APME_IN_WUC,
4130 .pba = 18,
4131 .max_hw_frame_size = DEFAULT_JUMBO,
4132 .get_variants = e1000_get_variants_ich8lan,
4133 .mac_ops = &ich8_mac_ops,
4134 .phy_ops = &ich8_phy_ops,
4135 .nvm_ops = &ich8_nvm_ops,
4136 };
4137
4138 const struct e1000_info e1000_pch_info = {
4139 .mac = e1000_pchlan,
4140 .flags = FLAG_IS_ICH
4141 | FLAG_HAS_WOL
4142 | FLAG_HAS_CTRLEXT_ON_LOAD
4143 | FLAG_HAS_AMT
4144 | FLAG_HAS_FLASH
4145 | FLAG_HAS_JUMBO_FRAMES
4146 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4147 | FLAG_APME_IN_WUC,
4148 .flags2 = FLAG2_HAS_PHY_STATS,
4149 .pba = 26,
4150 .max_hw_frame_size = 4096,
4151 .get_variants = e1000_get_variants_ich8lan,
4152 .mac_ops = &ich8_mac_ops,
4153 .phy_ops = &ich8_phy_ops,
4154 .nvm_ops = &ich8_nvm_ops,
4155 };
4156
4157 const struct e1000_info e1000_pch2_info = {
4158 .mac = e1000_pch2lan,
4159 .flags = FLAG_IS_ICH
4160 | FLAG_HAS_WOL
4161 | FLAG_HAS_CTRLEXT_ON_LOAD
4162 | FLAG_HAS_AMT
4163 | FLAG_HAS_FLASH
4164 | FLAG_HAS_JUMBO_FRAMES
4165 | FLAG_APME_IN_WUC,
4166 .flags2 = FLAG2_HAS_PHY_STATS
4167 | FLAG2_HAS_EEE,
4168 .pba = 26,
4169 .max_hw_frame_size = DEFAULT_JUMBO,
4170 .get_variants = e1000_get_variants_ich8lan,
4171 .mac_ops = &ich8_mac_ops,
4172 .phy_ops = &ich8_phy_ops,
4173 .nvm_ops = &ich8_nvm_ops,
4174 };
CJK support for tty framebuffer vt