include/asm-sparc64/pbm.h

   1 /* pbm.h: UltraSparc PCI controller software state.
   2  *
   3  * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #ifndef __SPARC64_PBM_H
   7 #define __SPARC64_PBM_H
   8
   9 #include <linux/types.h>
  10 #include <linux/pci.h>
  11 #include <linux/ioport.h>
  12 #include <linux/spinlock.h>
  13 #include <linux/msi.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/page.h>
  17 #include <asm/oplib.h>
  18 #include <asm/prom.h>
  19 #include <asm/of_device.h>
  20 #include <asm/iommu.h>
  21
  22 /* The abstraction used here is that there are PCI controllers,
  23  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
  24  * underneath.  Each PCI bus module uses an IOMMU (shared by both
  25  * PBMs of a controller, or per-PBM), and if a streaming buffer
  26  * is present, each PCI bus module has it's own. (ie. the IOMMU
  27  * might be shared between PBMs, the STC is never shared)
  28  * Furthermore, each PCI bus module controls it's own autonomous
  29  * PCI bus.
  30  */
  31
  32 extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
  33
  34 #define PCI_STC_FLUSHFLAG_INIT(STC) \
  35         (*((STC)->strbuf_flushflag) = 0UL)
  36 #define PCI_STC_FLUSHFLAG_SET(STC) \
  37         (*((STC)->strbuf_flushflag) != 0UL)
  38
  39 /* There can be quite a few ranges and interrupt maps on a PCI
  40  * segment.  Thus...
  41  */
  42 #define PROM_PCIRNG_MAX         64
  43 #define PROM_PCIIMAP_MAX        64
  44
  45 struct pci_controller_info;
  46
  47 struct pci_pbm_info {
  48         /* PCI controller we sit under. */
  49         struct pci_controller_info      *parent;
  50
  51         /* Physical address base of controller registers. */
  52         unsigned long                   controller_regs;
  53
  54         /* Physical address base of PBM registers. */
  55         unsigned long                   pbm_regs;
  56
  57         /* Physical address of DMA sync register, if any.  */
  58         unsigned long                   sync_reg;
  59
  60         /* Opaque 32-bit system bus Port ID. */
  61         u32                             portid;
  62
  63         /* Opaque 32-bit handle used for hypervisor calls.  */
  64         u32                             devhandle;
  65
  66         /* Chipset version information. */
  67         int                             chip_type;
  68 #define PBM_CHIP_TYPE_SABRE             1
  69 #define PBM_CHIP_TYPE_PSYCHO            2
  70 #define PBM_CHIP_TYPE_SCHIZO            3
  71 #define PBM_CHIP_TYPE_SCHIZO_PLUS       4
  72 #define PBM_CHIP_TYPE_TOMATILLO         5
  73         int                             chip_version;
  74         int                             chip_revision;
  75
  76         /* Name used for top-level resources. */
  77         char                            *name;
  78
  79         /* OBP specific information. */
  80         struct device_node              *prom_node;
  81         u64                             ino_bitmap;
  82
  83         /* PBM I/O and Memory space resources. */
  84         struct resource                 io_space;
  85         struct resource                 mem_space;
  86
  87         /* Base of PCI Config space, can be per-PBM or shared. */
  88         unsigned long                   config_space;
  89
  90         /* State of 66MHz capabilities on this PBM. */
  91         int                             is_66mhz_capable;
  92         int                             all_devs_66mhz;
  93
  94 #ifdef CONFIG_PCI_MSI
  95         /* MSI info.  */
  96         u32                             msiq_num;
  97         u32                             msiq_ent_count;
  98         u32                             msiq_first;
  99         u32                             msiq_first_devino;
 100         u32                             msi_num;
 101         u32                             msi_first;
 102         u32                             msi_data_mask;
 103         u32                             msix_data_width;
 104         u64                             msi32_start;
 105         u64                             msi64_start;
 106         u32                             msi32_len;
 107         u32                             msi64_len;
 108         void                            *msi_queues;
 109         unsigned long                   *msi_bitmap;
 110 #endif /* !(CONFIG_PCI_MSI) */
 111
 112         /* This PBM's streaming buffer. */
 113         struct strbuf                   stc;
 114
 115         /* IOMMU state, potentially shared by both PBM segments. */
 116         struct iommu                    *iommu;
 117
 118         /* Now things for the actual PCI bus probes. */
 119         unsigned int                    pci_first_busno;
 120         unsigned int                    pci_last_busno;
 121         struct pci_bus                  *pci_bus;
 122 };
 123
 124 struct pci_controller_info {
 125         /* List of all PCI controllers. */
 126         struct pci_controller_info      *next;
 127
 128         /* Each controller gets a unique index, used mostly for
 129          * error logging purposes.
 130          */
 131         int                             index;
 132
 133         /* The PCI bus modules controlled by us. */
 134         struct pci_pbm_info             pbm_A;
 135         struct pci_pbm_info             pbm_B;
 136
 137         /* Operations which are controller specific. */
 138         void (*scan_bus)(struct pci_controller_info *);
 139
 140 #ifdef CONFIG_PCI_MSI
 141         int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
 142                              struct msi_desc *entry);
 143         void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
 144 #endif
 145
 146         /* Now things for the actual PCI bus probes. */
 147         struct pci_ops                  *pci_ops;
 148         unsigned int                    pci_first_busno;
 149         unsigned int                    pci_last_busno;
 150 };
 151
 152 #endif /* !(__SPARC64_PBM_H) */