2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
38 #include <asm/proto.h>
39 #include <asm/timex.h>
44 int apic_runs_main_timer
;
45 int apic_calibrate_pmtmr __initdata
;
47 int disable_apic_timer __initdata
;
49 static struct resource
*ioapic_resources
;
50 static struct resource lapic_resource
= {
52 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
56 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
57 * IPIs in place of local APIC timers
59 static cpumask_t timer_interrupt_broadcast_ipi_mask
;
61 /* Using APIC to generate smp_local_timer_interrupt? */
62 int using_apic_timer __read_mostly
= 0;
64 static void apic_pm_activate(void);
66 void enable_NMI_through_LVT0 (void * dummy
)
70 v
= APIC_DM_NMI
; /* unmask and set to NMI */
71 apic_write(APIC_LVT0
, v
);
76 unsigned int v
, maxlvt
;
78 v
= apic_read(APIC_LVR
);
79 maxlvt
= GET_APIC_MAXLVT(v
);
84 * 'what should we do if we get a hw irq event on an illegal vector'.
85 * each architecture has to answer this themselves.
87 void ack_bad_irq(unsigned int irq
)
89 printk("unexpected IRQ trap at vector %02x\n", irq
);
91 * Currently unexpected vectors happen only on SMP and APIC.
92 * We _must_ ack these because every local APIC has only N
93 * irq slots per priority level, and a 'hanging, unacked' IRQ
94 * holds up an irq slot - in excessive cases (when multiple
95 * unexpected vectors occur) that might lock up the APIC
97 * But don't ack when the APIC is disabled. -AK
103 void clear_local_APIC(void)
108 maxlvt
= get_maxlvt();
111 * Masking an LVT entry can trigger a local APIC error
112 * if the vector is zero. Mask LVTERR first to prevent this.
115 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
116 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
119 * Careful: we have to set masks only first to deassert
120 * any level-triggered sources.
122 v
= apic_read(APIC_LVTT
);
123 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
124 v
= apic_read(APIC_LVT0
);
125 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
126 v
= apic_read(APIC_LVT1
);
127 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
129 v
= apic_read(APIC_LVTPC
);
130 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
134 * Clean APIC state for other OSs:
136 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
137 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
138 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
140 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
142 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
143 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
144 apic_write(APIC_ESR
, 0);
148 void disconnect_bsp_APIC(int virt_wire_setup
)
150 /* Go back to Virtual Wire compatibility mode */
153 /* For the spurious interrupt use vector F, and enable it */
154 value
= apic_read(APIC_SPIV
);
155 value
&= ~APIC_VECTOR_MASK
;
156 value
|= APIC_SPIV_APIC_ENABLED
;
158 apic_write(APIC_SPIV
, value
);
160 if (!virt_wire_setup
) {
161 /* For LVT0 make it edge triggered, active high, external and enabled */
162 value
= apic_read(APIC_LVT0
);
163 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
164 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
165 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
166 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
167 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
168 apic_write(APIC_LVT0
, value
);
171 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
174 /* For LVT1 make it edge triggered, active high, nmi and enabled */
175 value
= apic_read(APIC_LVT1
);
176 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
177 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
178 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
179 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
180 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
181 apic_write(APIC_LVT1
, value
);
184 void disable_local_APIC(void)
191 * Disable APIC (implies clearing of registers
194 value
= apic_read(APIC_SPIV
);
195 value
&= ~APIC_SPIV_APIC_ENABLED
;
196 apic_write(APIC_SPIV
, value
);
200 * This is to verify that we're looking at a real local APIC.
201 * Check these against your board if the CPUs aren't getting
202 * started for no apparent reason.
204 int __init
verify_local_APIC(void)
206 unsigned int reg0
, reg1
;
209 * The version register is read-only in a real APIC.
211 reg0
= apic_read(APIC_LVR
);
212 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
213 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
214 reg1
= apic_read(APIC_LVR
);
215 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
218 * The two version reads above should print the same
219 * numbers. If the second one is different, then we
220 * poke at a non-APIC.
226 * Check if the version looks reasonably.
228 reg1
= GET_APIC_VERSION(reg0
);
229 if (reg1
== 0x00 || reg1
== 0xff)
232 if (reg1
< 0x02 || reg1
== 0xff)
236 * The ID register is read/write in a real APIC.
238 reg0
= apic_read(APIC_ID
);
239 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
240 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
241 reg1
= apic_read(APIC_ID
);
242 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
243 apic_write(APIC_ID
, reg0
);
244 if (reg1
!= (reg0
^ APIC_ID_MASK
))
248 * The next two are just to see if we have sane values.
249 * They're only really relevant if we're in Virtual Wire
250 * compatibility mode, but most boxes are anymore.
252 reg0
= apic_read(APIC_LVT0
);
253 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
254 reg1
= apic_read(APIC_LVT1
);
255 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
260 void __init
sync_Arb_IDs(void)
262 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
263 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
264 if (ver
>= 0x14) /* P4 or higher */
270 apic_wait_icr_idle();
272 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
273 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
278 * An initial setup of the virtual wire mode.
280 void __init
init_bsp_APIC(void)
285 * Don't do the setup now if we have a SMP BIOS as the
286 * through-I/O-APIC virtual wire mode might be active.
288 if (smp_found_config
|| !cpu_has_apic
)
291 value
= apic_read(APIC_LVR
);
294 * Do not trust the local APIC being empty at bootup.
301 value
= apic_read(APIC_SPIV
);
302 value
&= ~APIC_VECTOR_MASK
;
303 value
|= APIC_SPIV_APIC_ENABLED
;
304 value
|= APIC_SPIV_FOCUS_DISABLED
;
305 value
|= SPURIOUS_APIC_VECTOR
;
306 apic_write(APIC_SPIV
, value
);
309 * Set up the virtual wire mode.
311 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
313 apic_write(APIC_LVT1
, value
);
316 void __cpuinit
setup_local_APIC (void)
318 unsigned int value
, maxlvt
;
321 value
= apic_read(APIC_LVR
);
323 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
326 * Double-check whether this APIC is really registered.
327 * This is meaningless in clustered apic mode, so we skip it.
329 if (!apic_id_registered())
333 * Intel recommends to set DFR, LDR and TPR before enabling
334 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
335 * document number 292116). So here it goes...
340 * Set Task Priority to 'accept all'. We never change this
343 value
= apic_read(APIC_TASKPRI
);
344 value
&= ~APIC_TPRI_MASK
;
345 apic_write(APIC_TASKPRI
, value
);
348 * After a crash, we no longer service the interrupts and a pending
349 * interrupt from previous kernel might still have ISR bit set.
351 * Most probably by now CPU has serviced that pending interrupt and
352 * it might not have done the ack_APIC_irq() because it thought,
353 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
354 * does not clear the ISR bit and cpu thinks it has already serivced
355 * the interrupt. Hence a vector might get locked. It was noticed
356 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
358 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
359 value
= apic_read(APIC_ISR
+ i
*0x10);
360 for (j
= 31; j
>= 0; j
--) {
367 * Now that we are all set up, enable the APIC
369 value
= apic_read(APIC_SPIV
);
370 value
&= ~APIC_VECTOR_MASK
;
374 value
|= APIC_SPIV_APIC_ENABLED
;
376 /* We always use processor focus */
379 * Set spurious IRQ vector
381 value
|= SPURIOUS_APIC_VECTOR
;
382 apic_write(APIC_SPIV
, value
);
387 * set up through-local-APIC on the BP's LINT0. This is not
388 * strictly necessary in pure symmetric-IO mode, but sometimes
389 * we delegate interrupts to the 8259A.
392 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
394 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
395 if (!smp_processor_id() && !value
) {
396 value
= APIC_DM_EXTINT
;
397 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", smp_processor_id());
399 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
400 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", smp_processor_id());
402 apic_write(APIC_LVT0
, value
);
405 * only the BP should see the LINT1 NMI signal, obviously.
407 if (!smp_processor_id())
410 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
411 apic_write(APIC_LVT1
, value
);
415 maxlvt
= get_maxlvt();
416 oldvalue
= apic_read(APIC_ESR
);
417 value
= ERROR_APIC_VECTOR
; // enables sending errors
418 apic_write(APIC_LVTERR
, value
);
420 * spec says clear errors after enabling vector.
423 apic_write(APIC_ESR
, 0);
424 value
= apic_read(APIC_ESR
);
425 if (value
!= oldvalue
)
426 apic_printk(APIC_VERBOSE
,
427 "ESR value after enabling vector: %08x, after %08x\n",
431 nmi_watchdog_default();
432 setup_apic_nmi_watchdog(NULL
);
439 /* 'active' is true if the local APIC was enabled by us and
440 not the BIOS; this signifies that we are also responsible
441 for disabling it before entering apm/acpi suspend */
443 /* r/w apic fields */
444 unsigned int apic_id
;
445 unsigned int apic_taskpri
;
446 unsigned int apic_ldr
;
447 unsigned int apic_dfr
;
448 unsigned int apic_spiv
;
449 unsigned int apic_lvtt
;
450 unsigned int apic_lvtpc
;
451 unsigned int apic_lvt0
;
452 unsigned int apic_lvt1
;
453 unsigned int apic_lvterr
;
454 unsigned int apic_tmict
;
455 unsigned int apic_tdcr
;
456 unsigned int apic_thmr
;
459 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
463 if (!apic_pm_state
.active
)
466 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
467 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
468 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
469 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
470 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
471 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
472 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
473 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
474 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
475 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
476 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
477 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
478 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
479 local_irq_save(flags
);
480 disable_local_APIC();
481 local_irq_restore(flags
);
485 static int lapic_resume(struct sys_device
*dev
)
490 if (!apic_pm_state
.active
)
493 local_irq_save(flags
);
494 rdmsr(MSR_IA32_APICBASE
, l
, h
);
495 l
&= ~MSR_IA32_APICBASE_BASE
;
496 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
497 wrmsr(MSR_IA32_APICBASE
, l
, h
);
498 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
499 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
500 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
501 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
502 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
503 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
504 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
505 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
506 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
507 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
508 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
509 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
510 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
511 apic_write(APIC_ESR
, 0);
513 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
514 apic_write(APIC_ESR
, 0);
516 local_irq_restore(flags
);
520 static struct sysdev_class lapic_sysclass
= {
521 set_kset_name("lapic"),
522 .resume
= lapic_resume
,
523 .suspend
= lapic_suspend
,
526 static struct sys_device device_lapic
= {
528 .cls
= &lapic_sysclass
,
531 static void __cpuinit
apic_pm_activate(void)
533 apic_pm_state
.active
= 1;
536 static int __init
init_lapic_sysfs(void)
541 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
542 error
= sysdev_class_register(&lapic_sysclass
);
544 error
= sysdev_register(&device_lapic
);
547 device_initcall(init_lapic_sysfs
);
549 #else /* CONFIG_PM */
551 static void apic_pm_activate(void) { }
553 #endif /* CONFIG_PM */
555 static int __init
apic_set_verbosity(char *str
)
558 skip_ioapic_setup
= 0;
562 if (strcmp("debug", str
) == 0)
563 apic_verbosity
= APIC_DEBUG
;
564 else if (strcmp("verbose", str
) == 0)
565 apic_verbosity
= APIC_VERBOSE
;
567 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
568 " use apic=verbose or apic=debug\n", str
);
574 early_param("apic", apic_set_verbosity
);
577 * Detect and enable local APICs on non-SMP boards.
578 * Original code written by Keir Fraser.
579 * On AMD64 we trust the BIOS - if it says no APIC it is likely
580 * not correctly set up (usually the APIC timer won't work etc.)
583 static int __init
detect_init_APIC (void)
586 printk(KERN_INFO
"No local APIC present\n");
590 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
595 #ifdef CONFIG_X86_IO_APIC
596 static struct resource
* __init
ioapic_setup_resources(void)
598 #define IOAPIC_RESOURCE_NAME_SIZE 11
600 struct resource
*res
;
607 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
610 mem
= alloc_bootmem(n
);
615 mem
+= sizeof(struct resource
) * nr_ioapics
;
617 for (i
= 0; i
< nr_ioapics
; i
++) {
619 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
620 sprintf(mem
, "IOAPIC %u", i
);
621 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
625 ioapic_resources
= res
;
630 static int __init
ioapic_insert_resources(void)
633 struct resource
*r
= ioapic_resources
;
636 printk("IO APIC resources could be not be allocated.\n");
640 for (i
= 0; i
< nr_ioapics
; i
++) {
641 insert_resource(&iomem_resource
, r
);
648 /* Insert the IO APIC resources after PCI initialization has occured to handle
649 * IO APICS that are mapped in on a BAR in PCI space. */
650 late_initcall(ioapic_insert_resources
);
653 void __init
init_apic_mappings(void)
655 unsigned long apic_phys
;
658 * If no local APIC can be found then set up a fake all
659 * zeroes page to simulate the local APIC and another
660 * one for the IO-APIC.
662 if (!smp_found_config
&& detect_init_APIC()) {
663 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
664 apic_phys
= __pa(apic_phys
);
666 apic_phys
= mp_lapic_addr
;
668 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
670 apic_printk(APIC_VERBOSE
,"mapped APIC to %16lx (%16lx)\n", APIC_BASE
, apic_phys
);
672 /* Put local APIC into the resource map. */
673 lapic_resource
.start
= apic_phys
;
674 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
675 insert_resource(&iomem_resource
, &lapic_resource
);
678 * Fetch the APIC ID of the BSP in case we have a
679 * default configuration (or the MP table is broken).
681 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
684 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
686 struct resource
*ioapic_res
;
688 ioapic_res
= ioapic_setup_resources();
689 for (i
= 0; i
< nr_ioapics
; i
++) {
690 if (smp_found_config
) {
691 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
693 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
694 ioapic_phys
= __pa(ioapic_phys
);
696 set_fixmap_nocache(idx
, ioapic_phys
);
697 apic_printk(APIC_VERBOSE
,"mapped IOAPIC to %016lx (%016lx)\n",
698 __fix_to_virt(idx
), ioapic_phys
);
701 if (ioapic_res
!= NULL
) {
702 ioapic_res
->start
= ioapic_phys
;
703 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
711 * This function sets up the local APIC timer, with a timeout of
712 * 'clocks' APIC bus clock. During calibration we actually call
713 * this function twice on the boot CPU, once with a bogus timeout
714 * value, second time for real. The other (noncalibrating) CPUs
715 * call this function only once, with the real, calibrated value.
717 * We do reads before writes even if unnecessary, to get around the
718 * P5 APIC double write bug.
721 #define APIC_DIVISOR 16
723 static void __setup_APIC_LVTT(unsigned int clocks
)
725 unsigned int lvtt_value
, tmp_value
, ver
;
726 int cpu
= smp_processor_id();
728 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
729 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
731 if (cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
))
732 lvtt_value
|= APIC_LVT_MASKED
;
734 apic_write(APIC_LVTT
, lvtt_value
);
739 tmp_value
= apic_read(APIC_TDCR
);
740 apic_write(APIC_TDCR
, (tmp_value
741 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
744 apic_write(APIC_TMICT
, clocks
/APIC_DIVISOR
);
747 static void setup_APIC_timer(unsigned int clocks
)
751 local_irq_save(flags
);
753 /* wait for irq slice */
754 if (vxtime
.hpet_address
&& hpet_use_timer
) {
755 int trigger
= hpet_readl(HPET_T0_CMP
);
756 while (hpet_readl(HPET_COUNTER
) >= trigger
)
758 while (hpet_readl(HPET_COUNTER
) < trigger
)
764 c2
|= inb_p(0x40) << 8;
769 c2
|= inb_p(0x40) << 8;
770 } while (c2
- c1
< 300);
772 __setup_APIC_LVTT(clocks
);
773 /* Turn off PIT interrupt if we use APIC timer as main timer.
774 Only works with the PM timer right now
775 TBD fix it for HPET too. */
776 if (vxtime
.mode
== VXTIME_PMTMR
&&
777 smp_processor_id() == boot_cpu_id
&&
778 apic_runs_main_timer
== 1 &&
779 !cpu_isset(boot_cpu_id
, timer_interrupt_broadcast_ipi_mask
)) {
780 stop_timer_interrupt();
781 apic_runs_main_timer
++;
783 local_irq_restore(flags
);
787 * In this function we calibrate APIC bus clocks to the external
788 * timer. Unfortunately we cannot use jiffies and the timer irq
789 * to calibrate, since some later bootup code depends on getting
790 * the first irq? Ugh.
792 * We want to do the calibration only once since we
793 * want to have local timer irqs syncron. CPUs connected
794 * by the same APIC bus have the very same bus frequency.
795 * And we want to have irqs off anyways, no accidental
799 #define TICK_COUNT 100000000
801 static int __init
calibrate_APIC_clock(void)
803 int apic
, apic_start
, tsc
, tsc_start
;
806 * Put whatever arbitrary (but long enough) timeout
807 * value into the APIC clock, we just want to get the
808 * counter running for calibration.
810 __setup_APIC_LVTT(1000000000);
812 apic_start
= apic_read(APIC_TMCCT
);
813 #ifdef CONFIG_X86_PM_TIMER
814 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
815 pmtimer_wait(5000); /* 5ms wait */
816 apic
= apic_read(APIC_TMCCT
);
817 result
= (apic_start
- apic
) * 1000L / 5;
824 apic
= apic_read(APIC_TMCCT
);
826 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
827 (apic
- apic_start
) < TICK_COUNT
);
829 result
= (apic_start
- apic
) * 1000L * cpu_khz
/
832 printk("result %d\n", result
);
835 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
836 result
/ 1000 / 1000, result
/ 1000 % 1000);
838 return result
* APIC_DIVISOR
/ HZ
;
841 static unsigned int calibration_result
;
843 void __init
setup_boot_APIC_clock (void)
845 if (disable_apic_timer
) {
846 printk(KERN_INFO
"Disabling APIC timer\n");
850 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
851 using_apic_timer
= 1;
855 calibration_result
= calibrate_APIC_clock();
857 * Now set up the timer for real.
859 setup_APIC_timer(calibration_result
);
864 void __cpuinit
setup_secondary_APIC_clock(void)
866 local_irq_disable(); /* FIXME: Do we need this? --RR */
867 setup_APIC_timer(calibration_result
);
871 void disable_APIC_timer(void)
873 if (using_apic_timer
) {
876 v
= apic_read(APIC_LVTT
);
878 * When an illegal vector value (0-15) is written to an LVT
879 * entry and delivery mode is Fixed, the APIC may signal an
880 * illegal vector error, with out regard to whether the mask
881 * bit is set or whether an interrupt is actually seen on input.
883 * Boot sequence might call this function when the LVTT has
884 * '0' vector value. So make sure vector field is set to
887 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
888 apic_write(APIC_LVTT
, v
);
892 void enable_APIC_timer(void)
894 int cpu
= smp_processor_id();
896 if (using_apic_timer
&&
897 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
900 v
= apic_read(APIC_LVTT
);
901 apic_write(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
905 void switch_APIC_timer_to_ipi(void *cpumask
)
907 cpumask_t mask
= *(cpumask_t
*)cpumask
;
908 int cpu
= smp_processor_id();
910 if (cpu_isset(cpu
, mask
) &&
911 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
912 disable_APIC_timer();
913 cpu_set(cpu
, timer_interrupt_broadcast_ipi_mask
);
916 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
918 void smp_send_timer_broadcast_ipi(void)
922 cpus_and(mask
, cpu_online_map
, timer_interrupt_broadcast_ipi_mask
);
923 if (!cpus_empty(mask
)) {
924 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
928 void switch_ipi_to_APIC_timer(void *cpumask
)
930 cpumask_t mask
= *(cpumask_t
*)cpumask
;
931 int cpu
= smp_processor_id();
933 if (cpu_isset(cpu
, mask
) &&
934 cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
935 cpu_clear(cpu
, timer_interrupt_broadcast_ipi_mask
);
939 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
941 int setup_profiling_timer(unsigned int multiplier
)
946 void setup_APIC_extened_lvt(unsigned char lvt_off
, unsigned char vector
,
947 unsigned char msg_type
, unsigned char mask
)
949 unsigned long reg
= (lvt_off
<< 4) + K8_APIC_EXT_LVT_BASE
;
950 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
957 * Local timer interrupt handler. It does both profiling and
958 * process statistics/rescheduling.
960 * We do profiling in every local tick, statistics/rescheduling
961 * happen only every 'profiling multiplier' ticks. The default
962 * multiplier is 1 and it can be changed by writing the new multiplier
963 * value into /proc/profile.
966 void smp_local_timer_interrupt(void)
968 profile_tick(CPU_PROFILING
);
970 update_process_times(user_mode(get_irq_regs()));
972 if (apic_runs_main_timer
> 1 && smp_processor_id() == boot_cpu_id
)
973 main_timer_handler();
975 * We take the 'long' return path, and there every subsystem
976 * grabs the appropriate locks (kernel lock/ irq lock).
978 * We might want to decouple profiling from the 'long path',
979 * and do the profiling totally in assembly.
981 * Currently this isn't too much of an issue (performance wise),
982 * we can take more than 100K local irqs per second on a 100 MHz P5.
987 * Local APIC timer interrupt. This is the most natural way for doing
988 * local interrupts, but local timer interrupts can be emulated by
989 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
991 * [ if a single-CPU system runs an SMP kernel then we call the local
992 * interrupt as well. Thus we cannot inline the local irq ... ]
994 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
996 struct pt_regs
*old_regs
= set_irq_regs(regs
);
999 * the NMI deadlock-detector uses this.
1001 add_pda(apic_timer_irqs
, 1);
1004 * NOTE! We'd better ACK the irq immediately,
1005 * because timer handling can be slow.
1009 * update_process_times() expects us to have done irq_enter().
1010 * Besides, if we don't timer interrupts ignore the global
1011 * interrupt lock, which is the WrongThing (tm) to do.
1015 smp_local_timer_interrupt();
1017 set_irq_regs(old_regs
);
1021 * apic_is_clustered_box() -- Check if we can expect good TSC
1023 * Thus far, the major user of this is IBM's Summit2 series:
1025 * Clustered boxes may have unsynced TSC problems if they are
1026 * multi-chassis. Use available data to take a good guess.
1027 * If in doubt, go HPET.
1029 __cpuinit
int apic_is_clustered_box(void)
1031 int i
, clusters
, zeros
;
1033 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1035 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1037 for (i
= 0; i
< NR_CPUS
; i
++) {
1038 id
= bios_cpu_apicid
[i
];
1039 if (id
!= BAD_APICID
)
1040 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1043 /* Problem: Partially populated chassis may not have CPUs in some of
1044 * the APIC clusters they have been allocated. Only present CPUs have
1045 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1046 * clusters are allocated sequentially, count zeros only if they are
1051 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1052 if (test_bit(i
, clustermap
)) {
1053 clusters
+= 1 + zeros
;
1060 * If clusters > 2, then should be multi-chassis.
1061 * May have to revisit this when multi-core + hyperthreaded CPUs come
1062 * out, but AFAIK this will work even for them.
1064 return (clusters
> 2);
1068 * This interrupt should _never_ happen with our APIC/SMP architecture
1070 asmlinkage
void smp_spurious_interrupt(void)
1076 * Check if this really is a spurious interrupt and ACK it
1077 * if it is a vectored one. Just in case...
1078 * Spurious interrupts should not be ACKed.
1080 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1081 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1085 static unsigned long last_warning
;
1086 static unsigned long skipped
;
1088 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1089 if (time_before(last_warning
+30*HZ
,jiffies
)) {
1090 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, %ld skipped.\n",
1091 smp_processor_id(), skipped
);
1092 last_warning
= jiffies
;
1102 * This interrupt should never happen with our APIC/SMP architecture
1105 asmlinkage
void smp_error_interrupt(void)
1111 /* First tickle the hardware, only then report what went on. -- REW */
1112 v
= apic_read(APIC_ESR
);
1113 apic_write(APIC_ESR
, 0);
1114 v1
= apic_read(APIC_ESR
);
1116 atomic_inc(&irq_err_count
);
1118 /* Here is what the APIC error bits mean:
1121 2: Send accept error
1122 3: Receive accept error
1124 5: Send illegal vector
1125 6: Received illegal vector
1126 7: Illegal register address
1128 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1129 smp_processor_id(), v
, v1
);
1136 * This initializes the IO-APIC and APIC hardware if this is
1139 int __init
APIC_init_uniprocessor (void)
1142 printk(KERN_INFO
"Apic disabled\n");
1145 if (!cpu_has_apic
) {
1147 printk(KERN_INFO
"Apic disabled by BIOS\n");
1151 verify_local_APIC();
1153 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1154 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
1158 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1162 setup_boot_APIC_clock();
1163 check_nmi_watchdog();
1167 static __init
int setup_disableapic(char *str
)
1170 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1173 early_param("disableapic", setup_disableapic
);
1175 /* same as disableapic, for compatibility */
1176 static __init
int setup_nolapic(char *str
)
1178 return setup_disableapic(str
);
1180 early_param("nolapic", setup_nolapic
);
1182 static __init
int setup_noapictimer(char *str
)
1184 if (str
[0] != ' ' && str
[0] != 0)
1186 disable_apic_timer
= 1;
1190 static __init
int setup_apicmaintimer(char *str
)
1192 apic_runs_main_timer
= 1;
1196 __setup("apicmaintimer", setup_apicmaintimer
);
1198 static __init
int setup_noapicmaintimer(char *str
)
1200 apic_runs_main_timer
= -1;
1203 __setup("noapicmaintimer", setup_noapicmaintimer
);
1205 static __init
int setup_apicpmtimer(char *s
)
1207 apic_calibrate_pmtmr
= 1;
1209 return setup_apicmaintimer(NULL
);
1211 __setup("apicpmtimer", setup_apicpmtimer
);
1213 __setup("noapictimer", setup_noapictimer
);