2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.98"
72 #define DRV_MODULE_RELDATE "February 25, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
134 #define TG3_RAW_IP_ALIGN 2
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139 #define TG3_NUM_TEST 6
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
145 static char version
[] __devinitdata
=
146 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION
);
152 MODULE_FIRMWARE(FIRMWARE_TG3
);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
157 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug
, int, 0);
159 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
161 static struct pci_device_id tg3_pci_tbl
[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5785
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57720
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
237 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
239 static const struct {
240 const char string
[ETH_GSTRING_LEN
];
241 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
274 { "tx_flow_control" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
307 { "rx_threshold_hit" },
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
320 static const struct {
321 const char string
[ETH_GSTRING_LEN
];
322 } ethtool_test_keys
[TG3_NUM_TEST
] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
331 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
333 writel(val
, tp
->regs
+ off
);
336 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
338 return (readl(tp
->regs
+ off
));
341 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
343 writel(val
, tp
->aperegs
+ off
);
346 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
348 return (readl(tp
->aperegs
+ off
));
351 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
355 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
356 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
357 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
358 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
361 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
363 writel(val
, tp
->regs
+ off
);
364 readl(tp
->regs
+ off
);
367 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
372 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
373 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
374 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
375 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
379 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
383 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
384 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
385 TG3_64BIT_REG_LOW
, val
);
388 if (off
== (MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
)) {
389 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
390 TG3_64BIT_REG_LOW
, val
);
394 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
395 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
396 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
397 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
402 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
404 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
405 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
409 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
414 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
415 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
416 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
417 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
426 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
428 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
429 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
430 /* Non-posted methods */
431 tp
->write32(tp
, off
, val
);
434 tg3_write32(tp
, off
, val
);
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
446 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
448 tp
->write32_mbox(tp
, off
, val
);
449 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
450 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
451 tp
->read32_mbox(tp
, off
);
454 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
456 void __iomem
*mbox
= tp
->regs
+ off
;
458 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
460 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
464 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
466 return (readl(tp
->regs
+ off
+ GRCMBOX_BASE
));
469 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
471 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
485 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
489 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
490 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
493 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
494 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
495 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
496 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
502 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
507 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
510 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
514 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
515 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
520 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
521 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
522 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
523 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
529 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
534 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
537 static void tg3_ape_lock_init(struct tg3
*tp
)
541 /* Make sure the driver hasn't any stale locks. */
542 for (i
= 0; i
< 8; i
++)
543 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
544 APE_LOCK_GRANT_DRIVER
);
547 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
553 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
557 case TG3_APE_LOCK_GRC
:
558 case TG3_APE_LOCK_MEM
:
566 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i
= 0; i
< 100; i
++) {
570 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
571 if (status
== APE_LOCK_GRANT_DRIVER
)
576 if (status
!= APE_LOCK_GRANT_DRIVER
) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
579 APE_LOCK_GRANT_DRIVER
);
587 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
591 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
595 case TG3_APE_LOCK_GRC
:
596 case TG3_APE_LOCK_MEM
:
603 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
606 static void tg3_disable_ints(struct tg3
*tp
)
608 tw32(TG3PCI_MISC_HOST_CTRL
,
609 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
613 static inline void tg3_cond_int(struct tg3
*tp
)
615 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
616 (tp
->hw_status
->status
& SD_STATUS_UPDATED
))
617 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
619 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
620 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
623 static void tg3_enable_ints(struct tg3
*tp
)
628 tw32(TG3PCI_MISC_HOST_CTRL
,
629 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
631 (tp
->last_tag
<< 24));
632 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
634 (tp
->last_tag
<< 24));
638 static inline unsigned int tg3_has_work(struct tg3
*tp
)
640 struct tg3_hw_status
*sblk
= tp
->hw_status
;
641 unsigned int work_exists
= 0;
643 /* check for phy events */
644 if (!(tp
->tg3_flags
&
645 (TG3_FLAG_USE_LINKCHG_REG
|
646 TG3_FLAG_POLL_SERDES
))) {
647 if (sblk
->status
& SD_STATUS_LINK_CHG
)
650 /* check for RX/TX work to do */
651 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
||
652 sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
663 static void tg3_restart_ints(struct tg3
*tp
)
665 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
673 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
675 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
676 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
679 static inline void tg3_netif_stop(struct tg3
*tp
)
681 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
682 napi_disable(&tp
->napi
);
683 netif_tx_disable(tp
->dev
);
686 static inline void tg3_netif_start(struct tg3
*tp
)
688 netif_wake_queue(tp
->dev
);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
693 napi_enable(&tp
->napi
);
694 tp
->hw_status
->status
|= SD_STATUS_UPDATED
;
698 static void tg3_switch_clocks(struct tg3
*tp
)
700 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
703 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
704 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
707 orig_clock_ctrl
= clock_ctrl
;
708 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
709 CLOCK_CTRL_CLKRUN_OENABLE
|
711 tp
->pci_clock_ctrl
= clock_ctrl
;
713 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
714 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
716 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
718 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
721 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
723 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
724 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
727 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
730 #define PHY_BUSY_LOOPS 5000
732 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
738 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
740 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
746 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
747 MI_COM_PHY_ADDR_MASK
);
748 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
749 MI_COM_REG_ADDR_MASK
);
750 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
752 tw32_f(MAC_MI_COM
, frame_val
);
754 loops
= PHY_BUSY_LOOPS
;
757 frame_val
= tr32(MAC_MI_COM
);
759 if ((frame_val
& MI_COM_BUSY
) == 0) {
761 frame_val
= tr32(MAC_MI_COM
);
769 *val
= frame_val
& MI_COM_DATA_MASK
;
773 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
774 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
781 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
787 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
&&
788 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
791 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
793 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
797 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
798 MI_COM_PHY_ADDR_MASK
);
799 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
800 MI_COM_REG_ADDR_MASK
);
801 frame_val
|= (val
& MI_COM_DATA_MASK
);
802 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
804 tw32_f(MAC_MI_COM
, frame_val
);
806 loops
= PHY_BUSY_LOOPS
;
809 frame_val
= tr32(MAC_MI_COM
);
810 if ((frame_val
& MI_COM_BUSY
) == 0) {
812 frame_val
= tr32(MAC_MI_COM
);
822 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
823 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
830 static int tg3_bmcr_reset(struct tg3
*tp
)
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
838 phy_control
= BMCR_RESET
;
839 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
845 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
849 if ((phy_control
& BMCR_RESET
) == 0) {
861 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
863 struct tg3
*tp
= bp
->priv
;
866 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
869 if (tg3_readphy(tp
, reg
, &val
))
875 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
877 struct tg3
*tp
= bp
->priv
;
879 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
882 if (tg3_writephy(tp
, reg
, val
))
888 static int tg3_mdio_reset(struct mii_bus
*bp
)
893 static void tg3_mdio_config_5785(struct tg3
*tp
)
896 struct phy_device
*phydev
;
898 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
899 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
900 case TG3_PHY_ID_BCM50610
:
901 val
= MAC_PHYCFG2_50610_LED_MODES
;
903 case TG3_PHY_ID_BCMAC131
:
904 val
= MAC_PHYCFG2_AC131_LED_MODES
;
906 case TG3_PHY_ID_RTL8211C
:
907 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
909 case TG3_PHY_ID_RTL8201E
:
910 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
916 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
917 tw32(MAC_PHYCFG2
, val
);
919 val
= tr32(MAC_PHYCFG1
);
920 val
&= ~MAC_PHYCFG1_RGMII_INT
;
921 tw32(MAC_PHYCFG1
, val
);
926 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
))
927 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
928 MAC_PHYCFG2_FMODE_MASK_MASK
|
929 MAC_PHYCFG2_GMODE_MASK_MASK
|
930 MAC_PHYCFG2_ACT_MASK_MASK
|
931 MAC_PHYCFG2_QUAL_MASK_MASK
|
932 MAC_PHYCFG2_INBAND_ENABLE
;
934 tw32(MAC_PHYCFG2
, val
);
936 val
= tr32(MAC_PHYCFG1
) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC
|
937 MAC_PHYCFG1_RGMII_SND_STAT_EN
);
938 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
) {
939 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
940 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
941 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
942 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
944 tw32(MAC_PHYCFG1
, val
| MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
);
946 val
= tr32(MAC_EXT_RGMII_MODE
);
947 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
948 MAC_RGMII_MODE_RX_QUALITY
|
949 MAC_RGMII_MODE_RX_ACTIVITY
|
950 MAC_RGMII_MODE_RX_ENG_DET
|
951 MAC_RGMII_MODE_TX_ENABLE
|
952 MAC_RGMII_MODE_TX_LOWPWR
|
953 MAC_RGMII_MODE_TX_RESET
);
954 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
955 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
956 val
|= MAC_RGMII_MODE_RX_INT_B
|
957 MAC_RGMII_MODE_RX_QUALITY
|
958 MAC_RGMII_MODE_RX_ACTIVITY
|
959 MAC_RGMII_MODE_RX_ENG_DET
;
960 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
961 val
|= MAC_RGMII_MODE_TX_ENABLE
|
962 MAC_RGMII_MODE_TX_LOWPWR
|
963 MAC_RGMII_MODE_TX_RESET
;
965 tw32(MAC_EXT_RGMII_MODE
, val
);
968 static void tg3_mdio_start(struct tg3
*tp
)
970 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
971 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
972 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
973 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
976 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
977 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
980 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
981 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
982 tg3_mdio_config_5785(tp
);
985 static void tg3_mdio_stop(struct tg3
*tp
)
987 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
988 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
989 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_PAUSED
;
990 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
994 static int tg3_mdio_init(struct tg3
*tp
)
998 struct phy_device
*phydev
;
1002 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1003 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1006 tp
->mdio_bus
= mdiobus_alloc();
1007 if (tp
->mdio_bus
== NULL
)
1010 tp
->mdio_bus
->name
= "tg3 mdio bus";
1011 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1012 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1013 tp
->mdio_bus
->priv
= tp
;
1014 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1015 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1016 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1017 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1018 tp
->mdio_bus
->phy_mask
= ~(1 << PHY_ADDR
);
1019 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1021 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1022 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1029 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1032 i
= mdiobus_register(tp
->mdio_bus
);
1034 printk(KERN_WARNING
"%s: mdiobus_reg failed (0x%x)\n",
1036 mdiobus_free(tp
->mdio_bus
);
1040 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1042 if (!phydev
|| !phydev
->drv
) {
1043 printk(KERN_WARNING
"%s: No PHY devices\n", tp
->dev
->name
);
1044 mdiobus_unregister(tp
->mdio_bus
);
1045 mdiobus_free(tp
->mdio_bus
);
1049 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1050 case TG3_PHY_ID_BCM57780
:
1051 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1053 case TG3_PHY_ID_BCM50610
:
1054 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)
1055 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1056 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1057 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1058 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1059 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1061 case TG3_PHY_ID_RTL8211C
:
1062 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1064 case TG3_PHY_ID_RTL8201E
:
1065 case TG3_PHY_ID_BCMAC131
:
1066 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1070 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1073 tg3_mdio_config_5785(tp
);
1078 static void tg3_mdio_fini(struct tg3
*tp
)
1080 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1081 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1082 mdiobus_unregister(tp
->mdio_bus
);
1083 mdiobus_free(tp
->mdio_bus
);
1084 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1093 val
= tr32(GRC_RX_CPU_EVENT
);
1094 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1095 tw32_f(GRC_RX_CPU_EVENT
, val
);
1097 tp
->last_event_jiffies
= jiffies
;
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1106 unsigned int delay_cnt
;
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1113 if (time_remain
< 0)
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt
= jiffies_to_usecs(time_remain
);
1118 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1119 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1120 delay_cnt
= (delay_cnt
>> 3) + 1;
1122 for (i
= 0; i
< delay_cnt
; i
++) {
1123 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3
*tp
)
1135 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1136 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1139 tg3_wait_for_event_ack(tp
);
1141 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1143 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1146 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1148 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1149 val
|= (reg
& 0xffff);
1150 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1153 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1155 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1156 val
|= (reg
& 0xffff);
1157 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1160 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1161 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1163 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1164 val
|= (reg
& 0xffff);
1166 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1168 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1172 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1174 tg3_generate_fw_event(tp
);
1177 static void tg3_link_report(struct tg3
*tp
)
1179 if (!netif_carrier_ok(tp
->dev
)) {
1180 if (netif_msg_link(tp
))
1181 printk(KERN_INFO PFX
"%s: Link is down.\n",
1183 tg3_ump_link_report(tp
);
1184 } else if (netif_msg_link(tp
)) {
1185 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1187 (tp
->link_config
.active_speed
== SPEED_1000
?
1189 (tp
->link_config
.active_speed
== SPEED_100
?
1191 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1197 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1199 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1201 tg3_ump_link_report(tp
);
1205 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1209 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1210 miireg
= ADVERTISE_PAUSE_CAP
;
1211 else if (flow_ctrl
& FLOW_CTRL_TX
)
1212 miireg
= ADVERTISE_PAUSE_ASYM
;
1213 else if (flow_ctrl
& FLOW_CTRL_RX
)
1214 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1221 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1225 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1226 miireg
= ADVERTISE_1000XPAUSE
;
1227 else if (flow_ctrl
& FLOW_CTRL_TX
)
1228 miireg
= ADVERTISE_1000XPSE_ASYM
;
1229 else if (flow_ctrl
& FLOW_CTRL_RX
)
1230 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1237 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1241 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1242 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1243 if (rmtadv
& LPA_1000XPAUSE
)
1244 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1245 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1248 if (rmtadv
& LPA_1000XPAUSE
)
1249 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1251 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1252 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1259 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1263 u32 old_rx_mode
= tp
->rx_mode
;
1264 u32 old_tx_mode
= tp
->tx_mode
;
1266 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1267 autoneg
= tp
->mdio_bus
->phy_map
[PHY_ADDR
]->autoneg
;
1269 autoneg
= tp
->link_config
.autoneg
;
1271 if (autoneg
== AUTONEG_ENABLE
&&
1272 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1273 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1274 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1276 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1278 flowctrl
= tp
->link_config
.flowctrl
;
1280 tp
->link_config
.active_flowctrl
= flowctrl
;
1282 if (flowctrl
& FLOW_CTRL_RX
)
1283 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1285 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1287 if (old_rx_mode
!= tp
->rx_mode
)
1288 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1290 if (flowctrl
& FLOW_CTRL_TX
)
1291 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1293 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1295 if (old_tx_mode
!= tp
->tx_mode
)
1296 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1299 static void tg3_adjust_link(struct net_device
*dev
)
1301 u8 oldflowctrl
, linkmesg
= 0;
1302 u32 mac_mode
, lcl_adv
, rmt_adv
;
1303 struct tg3
*tp
= netdev_priv(dev
);
1304 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1306 spin_lock(&tp
->lock
);
1308 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1309 MAC_MODE_HALF_DUPLEX
);
1311 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1317 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1318 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1320 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1322 if (phydev
->duplex
== DUPLEX_HALF
)
1323 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1325 lcl_adv
= tg3_advert_flowctrl_1000T(
1326 tp
->link_config
.flowctrl
);
1329 rmt_adv
= LPA_PAUSE_CAP
;
1330 if (phydev
->asym_pause
)
1331 rmt_adv
|= LPA_PAUSE_ASYM
;
1334 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1336 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1338 if (mac_mode
!= tp
->mac_mode
) {
1339 tp
->mac_mode
= mac_mode
;
1340 tw32_f(MAC_MODE
, tp
->mac_mode
);
1344 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1345 if (phydev
->speed
== SPEED_10
)
1347 MAC_MI_STAT_10MBPS_MODE
|
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1350 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1353 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1354 tw32(MAC_TX_LENGTHS
,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1356 (6 << TX_LENGTHS_IPG_SHIFT
) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1359 tw32(MAC_TX_LENGTHS
,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1361 (6 << TX_LENGTHS_IPG_SHIFT
) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1364 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1365 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1366 phydev
->speed
!= tp
->link_config
.active_speed
||
1367 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1368 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1371 tp
->link_config
.active_speed
= phydev
->speed
;
1372 tp
->link_config
.active_duplex
= phydev
->duplex
;
1374 spin_unlock(&tp
->lock
);
1377 tg3_link_report(tp
);
1380 static int tg3_phy_init(struct tg3
*tp
)
1382 struct phy_device
*phydev
;
1384 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1387 /* Bring the PHY back to a known state. */
1390 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1392 /* Attach the MAC to the PHY. */
1393 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1394 phydev
->dev_flags
, phydev
->interface
);
1395 if (IS_ERR(phydev
)) {
1396 printk(KERN_ERR
"%s: Could not attach to PHY\n", tp
->dev
->name
);
1397 return PTR_ERR(phydev
);
1400 /* Mask with MAC supported features. */
1401 switch (phydev
->interface
) {
1402 case PHY_INTERFACE_MODE_GMII
:
1403 case PHY_INTERFACE_MODE_RGMII
:
1404 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1405 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1407 SUPPORTED_Asym_Pause
);
1411 case PHY_INTERFACE_MODE_MII
:
1412 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1414 SUPPORTED_Asym_Pause
);
1417 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1421 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1423 phydev
->advertising
= phydev
->supported
;
1428 static void tg3_phy_start(struct tg3
*tp
)
1430 struct phy_device
*phydev
;
1432 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1435 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1437 if (tp
->link_config
.phy_is_low_power
) {
1438 tp
->link_config
.phy_is_low_power
= 0;
1439 phydev
->speed
= tp
->link_config
.orig_speed
;
1440 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1441 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1442 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1447 phy_start_aneg(phydev
);
1450 static void tg3_phy_stop(struct tg3
*tp
)
1452 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1455 phy_stop(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1458 static void tg3_phy_fini(struct tg3
*tp
)
1460 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1461 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1462 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1466 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1468 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1469 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1472 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1476 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1477 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
1480 reg
= MII_TG3_MISC_SHDW_WREN
|
1481 MII_TG3_MISC_SHDW_SCR5_SEL
|
1482 MII_TG3_MISC_SHDW_SCR5_LPED
|
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1484 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1485 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1486 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1487 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1489 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1492 reg
= MII_TG3_MISC_SHDW_WREN
|
1493 MII_TG3_MISC_SHDW_APD_SEL
|
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1496 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1498 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1501 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1505 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1506 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1509 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1512 if (!tg3_readphy(tp
, MII_TG3_EPHY_TEST
, &ephy
)) {
1513 tg3_writephy(tp
, MII_TG3_EPHY_TEST
,
1514 ephy
| MII_TG3_EPHY_SHADOW_EN
);
1515 if (!tg3_readphy(tp
, MII_TG3_EPHYTST_MISCCTRL
, &phy
)) {
1517 phy
|= MII_TG3_EPHYTST_MISCCTRL_MDIX
;
1519 phy
&= ~MII_TG3_EPHYTST_MISCCTRL_MDIX
;
1520 tg3_writephy(tp
, MII_TG3_EPHYTST_MISCCTRL
, phy
);
1522 tg3_writephy(tp
, MII_TG3_EPHY_TEST
, ephy
);
1525 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1526 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1527 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1528 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1530 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1532 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1533 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1534 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1539 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1543 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1546 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1547 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1548 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1549 (val
| (1 << 15) | (1 << 4)));
1552 static void tg3_phy_apply_otp(struct tg3
*tp
)
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1564 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1565 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1567 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1568 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1569 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1571 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1572 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1573 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1575 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1576 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1577 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1579 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1580 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1582 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1583 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1585 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1586 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1587 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1589 /* Turn off SM_DSP clock. */
1590 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1591 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1592 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1595 static int tg3_wait_macro_done(struct tg3
*tp
)
1602 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1603 if ((tmp32
& 0x1000) == 0)
1613 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1615 static const u32 test_pat
[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1623 for (chan
= 0; chan
< 4; chan
++) {
1626 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1627 (chan
* 0x2000) | 0x0200);
1628 tg3_writephy(tp
, 0x16, 0x0002);
1630 for (i
= 0; i
< 6; i
++)
1631 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1634 tg3_writephy(tp
, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp
)) {
1640 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1641 (chan
* 0x2000) | 0x0200);
1642 tg3_writephy(tp
, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp
)) {
1648 tg3_writephy(tp
, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp
)) {
1654 for (i
= 0; i
< 6; i
+= 2) {
1657 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1658 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1659 tg3_wait_macro_done(tp
)) {
1665 if (low
!= test_pat
[chan
][i
] ||
1666 high
!= test_pat
[chan
][i
+1]) {
1667 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1668 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1669 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1679 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1683 for (chan
= 0; chan
< 4; chan
++) {
1686 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1687 (chan
* 0x2000) | 0x0200);
1688 tg3_writephy(tp
, 0x16, 0x0002);
1689 for (i
= 0; i
< 6; i
++)
1690 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1691 tg3_writephy(tp
, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp
))
1699 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1701 u32 reg32
, phy9_orig
;
1702 int retries
, do_phy_reset
, err
;
1708 err
= tg3_bmcr_reset(tp
);
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1719 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp
, MII_BMCR
,
1723 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1729 tg3_writephy(tp
, MII_TG3_CTRL
,
1730 (MII_TG3_CTRL_AS_MASTER
|
1731 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1738 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1740 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1743 } while (--retries
);
1745 err
= tg3_phy_reset_chanpat(tp
);
1749 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1750 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1752 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1753 tg3_writephy(tp
, 0x16, 0x0000);
1755 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1756 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1761 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1764 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1766 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1768 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1775 /* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1778 static int tg3_phy_reset(struct tg3
*tp
)
1784 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1787 val
= tr32(GRC_MISC_CFG
);
1788 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1791 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1792 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1796 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1797 netif_carrier_off(tp
->dev
);
1798 tg3_link_report(tp
);
1801 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1802 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1803 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1804 err
= tg3_phy_reset_5703_4_5(tp
);
1811 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1812 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1813 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1814 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1816 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1819 err
= tg3_bmcr_reset(tp
);
1823 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1826 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1827 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1829 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1832 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1833 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1836 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1837 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1839 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1845 tg3_phy_apply_otp(tp
);
1847 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1848 tg3_phy_toggle_apd(tp
, true);
1850 tg3_phy_toggle_apd(tp
, false);
1853 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1854 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1855 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1856 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1857 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1858 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1859 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1861 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1862 tg3_writephy(tp
, 0x1c, 0x8d68);
1863 tg3_writephy(tp
, 0x1c, 0x8d68);
1865 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1866 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1867 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1868 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1869 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1870 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1871 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1872 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1873 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1875 else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
1876 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1877 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1878 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
1879 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1880 tg3_writephy(tp
, MII_TG3_TEST1
,
1881 MII_TG3_TEST1_TRIM_EN
| 0x4);
1883 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1884 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1891 } else if (tp
->tg3_flags2
& TG3_FLG2_JUMBO_CAPABLE
) {
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1896 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
1897 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1903 if (tp
->tg3_flags2
& TG3_FLG2_JUMBO_CAPABLE
) {
1906 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
1907 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1908 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
1911 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1912 /* adjust output voltage */
1913 tg3_writephy(tp
, MII_TG3_EPHY_PTEST
, 0x12);
1916 tg3_phy_toggle_automdix(tp
, 1);
1917 tg3_phy_set_wirespeed(tp
);
1921 static void tg3_frob_aux_power(struct tg3
*tp
)
1923 struct tg3
*tp_peer
= tp
;
1925 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0)
1928 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
1929 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
1930 struct net_device
*dev_peer
;
1932 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
1933 /* remove_one() may have been run on the peer. */
1937 tp_peer
= netdev_priv(dev_peer
);
1940 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1941 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
1942 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1943 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
1944 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1945 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1946 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1947 (GRC_LCLCTRL_GPIO_OE0
|
1948 GRC_LCLCTRL_GPIO_OE1
|
1949 GRC_LCLCTRL_GPIO_OE2
|
1950 GRC_LCLCTRL_GPIO_OUTPUT0
|
1951 GRC_LCLCTRL_GPIO_OUTPUT1
),
1953 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
1956 GRC_LCLCTRL_GPIO_OE1
|
1957 GRC_LCLCTRL_GPIO_OE2
|
1958 GRC_LCLCTRL_GPIO_OUTPUT0
|
1959 GRC_LCLCTRL_GPIO_OUTPUT1
|
1961 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1963 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
1964 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1966 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
1967 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1970 u32 grc_local_ctrl
= 0;
1972 if (tp_peer
!= tp
&&
1973 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
1979 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
1980 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1981 grc_local_ctrl
, 100);
1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2
= tp
->nic_sram_data_cfg
&
1986 NIC_SRAM_DATA_CFG_NO_GPIO2
;
1988 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
1989 GRC_LCLCTRL_GPIO_OE1
|
1990 GRC_LCLCTRL_GPIO_OE2
|
1991 GRC_LCLCTRL_GPIO_OUTPUT1
|
1992 GRC_LCLCTRL_GPIO_OUTPUT2
;
1994 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
1995 GRC_LCLCTRL_GPIO_OUTPUT2
);
1997 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1998 grc_local_ctrl
, 100);
2000 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2002 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2003 grc_local_ctrl
, 100);
2006 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2007 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2008 grc_local_ctrl
, 100);
2012 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2013 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2014 if (tp_peer
!= tp
&&
2015 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2018 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2019 (GRC_LCLCTRL_GPIO_OE1
|
2020 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2022 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2023 GRC_LCLCTRL_GPIO_OE1
, 100);
2025 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2026 (GRC_LCLCTRL_GPIO_OE1
|
2027 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2032 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2034 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2036 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
) {
2037 if (speed
!= SPEED_10
)
2039 } else if (speed
== SPEED_10
)
2045 static int tg3_setup_phy(struct tg3
*, int);
2047 #define RESET_KIND_SHUTDOWN 0
2048 #define RESET_KIND_INIT 1
2049 #define RESET_KIND_SUSPEND 2
2051 static void tg3_write_sig_post_reset(struct tg3
*, int);
2052 static int tg3_halt_cpu(struct tg3
*, u32
);
2054 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2058 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2059 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2060 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2061 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2064 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2065 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2066 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2071 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2073 val
= tr32(GRC_MISC_CFG
);
2074 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2077 } else if (do_low_power
) {
2078 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2079 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2081 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2082 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2083 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2085 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2088 /* The PHY should not be powered down on some chips because
2091 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2092 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2093 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2094 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2097 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2098 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2099 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2100 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2101 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2102 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2105 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2108 /* tp->lock is held. */
2109 static int tg3_nvram_lock(struct tg3
*tp
)
2111 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2114 if (tp
->nvram_lock_cnt
== 0) {
2115 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2116 for (i
= 0; i
< 8000; i
++) {
2117 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2122 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2126 tp
->nvram_lock_cnt
++;
2131 /* tp->lock is held. */
2132 static void tg3_nvram_unlock(struct tg3
*tp
)
2134 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2135 if (tp
->nvram_lock_cnt
> 0)
2136 tp
->nvram_lock_cnt
--;
2137 if (tp
->nvram_lock_cnt
== 0)
2138 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2142 /* tp->lock is held. */
2143 static void tg3_enable_nvram_access(struct tg3
*tp
)
2145 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2146 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2147 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2149 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2153 /* tp->lock is held. */
2154 static void tg3_disable_nvram_access(struct tg3
*tp
)
2156 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2157 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2158 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2160 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2164 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2165 u32 offset
, u32
*val
)
2170 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2173 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2174 EEPROM_ADDR_DEVID_MASK
|
2176 tw32(GRC_EEPROM_ADDR
,
2178 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2179 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2180 EEPROM_ADDR_ADDR_MASK
) |
2181 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2183 for (i
= 0; i
< 1000; i
++) {
2184 tmp
= tr32(GRC_EEPROM_ADDR
);
2186 if (tmp
& EEPROM_ADDR_COMPLETE
)
2190 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2193 tmp
= tr32(GRC_EEPROM_DATA
);
2196 * The data will always be opposite the native endian
2197 * format. Perform a blind byteswap to compensate.
2204 #define NVRAM_CMD_TIMEOUT 10000
2206 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2210 tw32(NVRAM_CMD
, nvram_cmd
);
2211 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2213 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2219 if (i
== NVRAM_CMD_TIMEOUT
)
2225 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2227 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2228 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2229 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2230 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2231 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2233 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2234 ATMEL_AT45DB0X1B_PAGE_POS
) +
2235 (addr
% tp
->nvram_pagesize
);
2240 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2242 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2243 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2244 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2245 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2246 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2248 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2249 tp
->nvram_pagesize
) +
2250 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2255 /* NOTE: Data read in from NVRAM is byteswapped according to
2256 * the byteswapping settings for all other register accesses.
2257 * tg3 devices are BE devices, so on a BE machine, the data
2258 * returned will be exactly as it is seen in NVRAM. On a LE
2259 * machine, the 32-bit value will be byteswapped.
2261 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2265 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2266 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2268 offset
= tg3_nvram_phys_addr(tp
, offset
);
2270 if (offset
> NVRAM_ADDR_MSK
)
2273 ret
= tg3_nvram_lock(tp
);
2277 tg3_enable_nvram_access(tp
);
2279 tw32(NVRAM_ADDR
, offset
);
2280 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2281 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2284 *val
= tr32(NVRAM_RDDATA
);
2286 tg3_disable_nvram_access(tp
);
2288 tg3_nvram_unlock(tp
);
2293 /* Ensures NVRAM data is in bytestream format. */
2294 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2297 int res
= tg3_nvram_read(tp
, offset
, &v
);
2299 *val
= cpu_to_be32(v
);
2303 /* tp->lock is held. */
2304 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2306 u32 addr_high
, addr_low
;
2309 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2310 tp
->dev
->dev_addr
[1]);
2311 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2312 (tp
->dev
->dev_addr
[3] << 16) |
2313 (tp
->dev
->dev_addr
[4] << 8) |
2314 (tp
->dev
->dev_addr
[5] << 0));
2315 for (i
= 0; i
< 4; i
++) {
2316 if (i
== 1 && skip_mac_1
)
2318 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2319 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2322 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2323 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2324 for (i
= 0; i
< 12; i
++) {
2325 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2326 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2330 addr_high
= (tp
->dev
->dev_addr
[0] +
2331 tp
->dev
->dev_addr
[1] +
2332 tp
->dev
->dev_addr
[2] +
2333 tp
->dev
->dev_addr
[3] +
2334 tp
->dev
->dev_addr
[4] +
2335 tp
->dev
->dev_addr
[5]) &
2336 TX_BACKOFF_SEED_MASK
;
2337 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2340 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2343 bool device_should_wake
, do_low_power
;
2345 /* Make sure register accesses (indirect or otherwise)
2346 * will function correctly.
2348 pci_write_config_dword(tp
->pdev
,
2349 TG3PCI_MISC_HOST_CTRL
,
2350 tp
->misc_host_ctrl
);
2354 pci_enable_wake(tp
->pdev
, state
, false);
2355 pci_set_power_state(tp
->pdev
, PCI_D0
);
2357 /* Switch out of Vaux if it is a NIC */
2358 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2359 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2369 printk(KERN_ERR PFX
"%s: Invalid power state (D%d) requested\n",
2370 tp
->dev
->name
, state
);
2374 /* Restore the CLKREQ setting. */
2375 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2378 pci_read_config_word(tp
->pdev
,
2379 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2381 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2382 pci_write_config_word(tp
->pdev
,
2383 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2387 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2388 tw32(TG3PCI_MISC_HOST_CTRL
,
2389 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2391 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2392 device_may_wakeup(&tp
->pdev
->dev
) &&
2393 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2395 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2396 do_low_power
= false;
2397 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2398 !tp
->link_config
.phy_is_low_power
) {
2399 struct phy_device
*phydev
;
2400 u32 phyid
, advertising
;
2402 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
2404 tp
->link_config
.phy_is_low_power
= 1;
2406 tp
->link_config
.orig_speed
= phydev
->speed
;
2407 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2408 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2409 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2411 advertising
= ADVERTISED_TP
|
2413 ADVERTISED_Autoneg
|
2414 ADVERTISED_10baseT_Half
;
2416 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2417 device_should_wake
) {
2418 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2420 ADVERTISED_100baseT_Half
|
2421 ADVERTISED_100baseT_Full
|
2422 ADVERTISED_10baseT_Full
;
2424 advertising
|= ADVERTISED_10baseT_Full
;
2427 phydev
->advertising
= advertising
;
2429 phy_start_aneg(phydev
);
2431 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2432 if (phyid
!= TG3_PHY_ID_BCMAC131
) {
2433 phyid
&= TG3_PHY_OUI_MASK
;
2434 if (phyid
== TG3_PHY_OUI_1
||
2435 phyid
== TG3_PHY_OUI_2
||
2436 phyid
== TG3_PHY_OUI_3
)
2437 do_low_power
= true;
2441 do_low_power
= true;
2443 if (tp
->link_config
.phy_is_low_power
== 0) {
2444 tp
->link_config
.phy_is_low_power
= 1;
2445 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2446 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2447 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2450 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2451 tp
->link_config
.speed
= SPEED_10
;
2452 tp
->link_config
.duplex
= DUPLEX_HALF
;
2453 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2454 tg3_setup_phy(tp
, 0);
2458 __tg3_set_mac_addr(tp
, 0);
2460 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2463 val
= tr32(GRC_VCPU_EXT_CTRL
);
2464 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2465 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2469 for (i
= 0; i
< 200; i
++) {
2470 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2471 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2476 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2477 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2478 WOL_DRV_STATE_SHUTDOWN
|
2482 if (device_should_wake
) {
2485 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2487 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2491 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2492 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2494 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2496 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2497 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2499 u32 speed
= (tp
->tg3_flags
&
2500 TG3_FLAG_WOL_SPEED_100MB
) ?
2501 SPEED_100
: SPEED_10
;
2502 if (tg3_5700_link_polarity(tp
, speed
))
2503 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2505 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2508 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2511 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2512 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2514 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2515 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2516 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2517 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2518 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2519 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2521 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2522 mac_mode
|= tp
->mac_mode
&
2523 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2524 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2525 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2528 tw32_f(MAC_MODE
, mac_mode
);
2531 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2535 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2536 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2537 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2540 base_val
= tp
->pci_clock_ctrl
;
2541 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2542 CLOCK_CTRL_TXCLK_DISABLE
);
2544 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2545 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2546 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2547 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2548 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2550 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2551 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2552 u32 newbits1
, newbits2
;
2554 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2555 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2556 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2557 CLOCK_CTRL_TXCLK_DISABLE
|
2559 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2560 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2561 newbits1
= CLOCK_CTRL_625_CORE
;
2562 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2564 newbits1
= CLOCK_CTRL_ALTCLK
;
2565 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2568 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2571 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2574 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2577 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2578 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2579 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2580 CLOCK_CTRL_TXCLK_DISABLE
|
2581 CLOCK_CTRL_44MHZ_CORE
);
2583 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2586 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2587 tp
->pci_clock_ctrl
| newbits3
, 40);
2591 if (!(device_should_wake
) &&
2592 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2593 tg3_power_down_phy(tp
, do_low_power
);
2595 tg3_frob_aux_power(tp
);
2597 /* Workaround for unstable PLL clock */
2598 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2599 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2600 u32 val
= tr32(0x7d00);
2602 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2604 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2607 err
= tg3_nvram_lock(tp
);
2608 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2610 tg3_nvram_unlock(tp
);
2614 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2616 if (device_should_wake
)
2617 pci_enable_wake(tp
->pdev
, state
, true);
2619 /* Finally, set the new power state. */
2620 pci_set_power_state(tp
->pdev
, state
);
2625 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2627 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2628 case MII_TG3_AUX_STAT_10HALF
:
2630 *duplex
= DUPLEX_HALF
;
2633 case MII_TG3_AUX_STAT_10FULL
:
2635 *duplex
= DUPLEX_FULL
;
2638 case MII_TG3_AUX_STAT_100HALF
:
2640 *duplex
= DUPLEX_HALF
;
2643 case MII_TG3_AUX_STAT_100FULL
:
2645 *duplex
= DUPLEX_FULL
;
2648 case MII_TG3_AUX_STAT_1000HALF
:
2649 *speed
= SPEED_1000
;
2650 *duplex
= DUPLEX_HALF
;
2653 case MII_TG3_AUX_STAT_1000FULL
:
2654 *speed
= SPEED_1000
;
2655 *duplex
= DUPLEX_FULL
;
2659 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2660 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2662 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2666 *speed
= SPEED_INVALID
;
2667 *duplex
= DUPLEX_INVALID
;
2672 static void tg3_phy_copper_begin(struct tg3
*tp
)
2677 if (tp
->link_config
.phy_is_low_power
) {
2678 /* Entering low power mode. Disable gigabit and
2679 * 100baseT advertisements.
2681 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2683 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2684 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2685 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2686 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2688 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2689 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2690 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2691 tp
->link_config
.advertising
&=
2692 ~(ADVERTISED_1000baseT_Half
|
2693 ADVERTISED_1000baseT_Full
);
2695 new_adv
= ADVERTISE_CSMA
;
2696 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2697 new_adv
|= ADVERTISE_10HALF
;
2698 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2699 new_adv
|= ADVERTISE_10FULL
;
2700 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2701 new_adv
|= ADVERTISE_100HALF
;
2702 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2703 new_adv
|= ADVERTISE_100FULL
;
2705 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2707 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2709 if (tp
->link_config
.advertising
&
2710 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2712 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2713 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2714 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2715 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2716 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2717 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2718 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2719 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2720 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2721 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2723 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2726 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2727 new_adv
|= ADVERTISE_CSMA
;
2729 /* Asking for a specific link mode. */
2730 if (tp
->link_config
.speed
== SPEED_1000
) {
2731 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2733 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2734 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2736 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2737 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2738 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2739 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2740 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2742 if (tp
->link_config
.speed
== SPEED_100
) {
2743 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2744 new_adv
|= ADVERTISE_100FULL
;
2746 new_adv
|= ADVERTISE_100HALF
;
2748 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2749 new_adv
|= ADVERTISE_10FULL
;
2751 new_adv
|= ADVERTISE_10HALF
;
2753 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2758 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2761 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2762 tp
->link_config
.speed
!= SPEED_INVALID
) {
2763 u32 bmcr
, orig_bmcr
;
2765 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2766 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2769 switch (tp
->link_config
.speed
) {
2775 bmcr
|= BMCR_SPEED100
;
2779 bmcr
|= TG3_BMCR_SPEED1000
;
2783 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2784 bmcr
|= BMCR_FULLDPLX
;
2786 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2787 (bmcr
!= orig_bmcr
)) {
2788 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2789 for (i
= 0; i
< 1500; i
++) {
2793 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2794 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2796 if (!(tmp
& BMSR_LSTATUS
)) {
2801 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2805 tg3_writephy(tp
, MII_BMCR
,
2806 BMCR_ANENABLE
| BMCR_ANRESTART
);
2810 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2814 /* Turn off tap power management. */
2815 /* Set Extended packet length bit */
2816 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2818 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2819 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2821 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2822 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2824 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2825 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2827 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2828 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2830 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2831 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2838 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2840 u32 adv_reg
, all_mask
= 0;
2842 if (mask
& ADVERTISED_10baseT_Half
)
2843 all_mask
|= ADVERTISE_10HALF
;
2844 if (mask
& ADVERTISED_10baseT_Full
)
2845 all_mask
|= ADVERTISE_10FULL
;
2846 if (mask
& ADVERTISED_100baseT_Half
)
2847 all_mask
|= ADVERTISE_100HALF
;
2848 if (mask
& ADVERTISED_100baseT_Full
)
2849 all_mask
|= ADVERTISE_100FULL
;
2851 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2854 if ((adv_reg
& all_mask
) != all_mask
)
2856 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
2860 if (mask
& ADVERTISED_1000baseT_Half
)
2861 all_mask
|= ADVERTISE_1000HALF
;
2862 if (mask
& ADVERTISED_1000baseT_Full
)
2863 all_mask
|= ADVERTISE_1000FULL
;
2865 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2868 if ((tg3_ctrl
& all_mask
) != all_mask
)
2874 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2878 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2881 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2882 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2884 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2885 if (curadv
!= reqadv
)
2888 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2889 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2891 /* Reprogram the advertisement register, even if it
2892 * does not affect the current link. If the link
2893 * gets renegotiated in the future, we can save an
2894 * additional renegotiation cycle by advertising
2895 * it correctly in the first place.
2897 if (curadv
!= reqadv
) {
2898 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
2899 ADVERTISE_PAUSE_ASYM
);
2900 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
2907 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
2909 int current_link_up
;
2911 u32 lcl_adv
, rmt_adv
;
2919 (MAC_STATUS_SYNC_CHANGED
|
2920 MAC_STATUS_CFG_CHANGED
|
2921 MAC_STATUS_MI_COMPLETION
|
2922 MAC_STATUS_LNKSTATE_CHANGED
));
2925 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
2927 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
2931 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
2933 /* Some third-party PHYs need to be reset on link going
2936 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2937 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2938 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
2939 netif_carrier_ok(tp
->dev
)) {
2940 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2941 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2942 !(bmsr
& BMSR_LSTATUS
))
2948 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
2949 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2950 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
2951 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
2954 if (!(bmsr
& BMSR_LSTATUS
)) {
2955 err
= tg3_init_5401phy_dsp(tp
);
2959 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2960 for (i
= 0; i
< 1000; i
++) {
2962 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2963 (bmsr
& BMSR_LSTATUS
)) {
2969 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
2970 !(bmsr
& BMSR_LSTATUS
) &&
2971 tp
->link_config
.active_speed
== SPEED_1000
) {
2972 err
= tg3_phy_reset(tp
);
2974 err
= tg3_init_5401phy_dsp(tp
);
2979 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2980 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
2981 /* 5701 {A0,B0} CRC bug workaround */
2982 tg3_writephy(tp
, 0x15, 0x0a75);
2983 tg3_writephy(tp
, 0x1c, 0x8c68);
2984 tg3_writephy(tp
, 0x1c, 0x8d68);
2985 tg3_writephy(tp
, 0x1c, 0x8c68);
2988 /* Clear pending interrupts... */
2989 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
2990 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
2992 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
2993 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
2994 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
)
2995 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
2997 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2998 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2999 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3000 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3001 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3003 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3006 current_link_up
= 0;
3007 current_speed
= SPEED_INVALID
;
3008 current_duplex
= DUPLEX_INVALID
;
3010 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3013 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3014 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3015 if (!(val
& (1 << 10))) {
3017 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3023 for (i
= 0; i
< 100; i
++) {
3024 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3025 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3026 (bmsr
& BMSR_LSTATUS
))
3031 if (bmsr
& BMSR_LSTATUS
) {
3034 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3035 for (i
= 0; i
< 2000; i
++) {
3037 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3042 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3047 for (i
= 0; i
< 200; i
++) {
3048 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3049 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3051 if (bmcr
&& bmcr
!= 0x7fff)
3059 tp
->link_config
.active_speed
= current_speed
;
3060 tp
->link_config
.active_duplex
= current_duplex
;
3062 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3063 if ((bmcr
& BMCR_ANENABLE
) &&
3064 tg3_copper_is_advertising_all(tp
,
3065 tp
->link_config
.advertising
)) {
3066 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3068 current_link_up
= 1;
3071 if (!(bmcr
& BMCR_ANENABLE
) &&
3072 tp
->link_config
.speed
== current_speed
&&
3073 tp
->link_config
.duplex
== current_duplex
&&
3074 tp
->link_config
.flowctrl
==
3075 tp
->link_config
.active_flowctrl
) {
3076 current_link_up
= 1;
3080 if (current_link_up
== 1 &&
3081 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3082 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3086 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3089 tg3_phy_copper_begin(tp
);
3091 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3092 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3093 (tmp
& BMSR_LSTATUS
))
3094 current_link_up
= 1;
3097 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3098 if (current_link_up
== 1) {
3099 if (tp
->link_config
.active_speed
== SPEED_100
||
3100 tp
->link_config
.active_speed
== SPEED_10
)
3101 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3103 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3105 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3107 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3108 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3109 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3111 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3112 if (current_link_up
== 1 &&
3113 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3114 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3116 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3119 /* ??? Without this setting Netgear GA302T PHY does not
3120 * ??? send/receive packets...
3122 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
3123 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3124 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3125 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3129 tw32_f(MAC_MODE
, tp
->mac_mode
);
3132 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3133 /* Polled via timer. */
3134 tw32_f(MAC_EVENT
, 0);
3136 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3140 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3141 current_link_up
== 1 &&
3142 tp
->link_config
.active_speed
== SPEED_1000
&&
3143 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3144 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3147 (MAC_STATUS_SYNC_CHANGED
|
3148 MAC_STATUS_CFG_CHANGED
));
3151 NIC_SRAM_FIRMWARE_MBOX
,
3152 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3155 /* Prevent send BD corruption. */
3156 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3157 u16 oldlnkctl
, newlnkctl
;
3159 pci_read_config_word(tp
->pdev
,
3160 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3162 if (tp
->link_config
.active_speed
== SPEED_100
||
3163 tp
->link_config
.active_speed
== SPEED_10
)
3164 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3166 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3167 if (newlnkctl
!= oldlnkctl
)
3168 pci_write_config_word(tp
->pdev
,
3169 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3173 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3174 if (current_link_up
)
3175 netif_carrier_on(tp
->dev
);
3177 netif_carrier_off(tp
->dev
);
3178 tg3_link_report(tp
);
3184 struct tg3_fiber_aneginfo
{
3186 #define ANEG_STATE_UNKNOWN 0
3187 #define ANEG_STATE_AN_ENABLE 1
3188 #define ANEG_STATE_RESTART_INIT 2
3189 #define ANEG_STATE_RESTART 3
3190 #define ANEG_STATE_DISABLE_LINK_OK 4
3191 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3192 #define ANEG_STATE_ABILITY_DETECT 6
3193 #define ANEG_STATE_ACK_DETECT_INIT 7
3194 #define ANEG_STATE_ACK_DETECT 8
3195 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3196 #define ANEG_STATE_COMPLETE_ACK 10
3197 #define ANEG_STATE_IDLE_DETECT_INIT 11
3198 #define ANEG_STATE_IDLE_DETECT 12
3199 #define ANEG_STATE_LINK_OK 13
3200 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3201 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3204 #define MR_AN_ENABLE 0x00000001
3205 #define MR_RESTART_AN 0x00000002
3206 #define MR_AN_COMPLETE 0x00000004
3207 #define MR_PAGE_RX 0x00000008
3208 #define MR_NP_LOADED 0x00000010
3209 #define MR_TOGGLE_TX 0x00000020
3210 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3211 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3212 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3213 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3214 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3215 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3216 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3217 #define MR_TOGGLE_RX 0x00002000
3218 #define MR_NP_RX 0x00004000
3220 #define MR_LINK_OK 0x80000000
3222 unsigned long link_time
, cur_time
;
3224 u32 ability_match_cfg
;
3225 int ability_match_count
;
3227 char ability_match
, idle_match
, ack_match
;
3229 u32 txconfig
, rxconfig
;
3230 #define ANEG_CFG_NP 0x00000080
3231 #define ANEG_CFG_ACK 0x00000040
3232 #define ANEG_CFG_RF2 0x00000020
3233 #define ANEG_CFG_RF1 0x00000010
3234 #define ANEG_CFG_PS2 0x00000001
3235 #define ANEG_CFG_PS1 0x00008000
3236 #define ANEG_CFG_HD 0x00004000
3237 #define ANEG_CFG_FD 0x00002000
3238 #define ANEG_CFG_INVAL 0x00001f06
3243 #define ANEG_TIMER_ENAB 2
3244 #define ANEG_FAILED -1
3246 #define ANEG_STATE_SETTLE_TIME 10000
3248 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3249 struct tg3_fiber_aneginfo
*ap
)
3252 unsigned long delta
;
3256 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3260 ap
->ability_match_cfg
= 0;
3261 ap
->ability_match_count
= 0;
3262 ap
->ability_match
= 0;
3268 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3269 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3271 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3272 ap
->ability_match_cfg
= rx_cfg_reg
;
3273 ap
->ability_match
= 0;
3274 ap
->ability_match_count
= 0;
3276 if (++ap
->ability_match_count
> 1) {
3277 ap
->ability_match
= 1;
3278 ap
->ability_match_cfg
= rx_cfg_reg
;
3281 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3289 ap
->ability_match_cfg
= 0;
3290 ap
->ability_match_count
= 0;
3291 ap
->ability_match
= 0;
3297 ap
->rxconfig
= rx_cfg_reg
;
3301 case ANEG_STATE_UNKNOWN
:
3302 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3303 ap
->state
= ANEG_STATE_AN_ENABLE
;
3306 case ANEG_STATE_AN_ENABLE
:
3307 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3308 if (ap
->flags
& MR_AN_ENABLE
) {
3311 ap
->ability_match_cfg
= 0;
3312 ap
->ability_match_count
= 0;
3313 ap
->ability_match
= 0;
3317 ap
->state
= ANEG_STATE_RESTART_INIT
;
3319 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3323 case ANEG_STATE_RESTART_INIT
:
3324 ap
->link_time
= ap
->cur_time
;
3325 ap
->flags
&= ~(MR_NP_LOADED
);
3327 tw32(MAC_TX_AUTO_NEG
, 0);
3328 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3329 tw32_f(MAC_MODE
, tp
->mac_mode
);
3332 ret
= ANEG_TIMER_ENAB
;
3333 ap
->state
= ANEG_STATE_RESTART
;
3336 case ANEG_STATE_RESTART
:
3337 delta
= ap
->cur_time
- ap
->link_time
;
3338 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3339 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3341 ret
= ANEG_TIMER_ENAB
;
3345 case ANEG_STATE_DISABLE_LINK_OK
:
3349 case ANEG_STATE_ABILITY_DETECT_INIT
:
3350 ap
->flags
&= ~(MR_TOGGLE_TX
);
3351 ap
->txconfig
= ANEG_CFG_FD
;
3352 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3353 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3354 ap
->txconfig
|= ANEG_CFG_PS1
;
3355 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3356 ap
->txconfig
|= ANEG_CFG_PS2
;
3357 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3358 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3359 tw32_f(MAC_MODE
, tp
->mac_mode
);
3362 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3365 case ANEG_STATE_ABILITY_DETECT
:
3366 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
3367 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3371 case ANEG_STATE_ACK_DETECT_INIT
:
3372 ap
->txconfig
|= ANEG_CFG_ACK
;
3373 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3374 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3375 tw32_f(MAC_MODE
, tp
->mac_mode
);
3378 ap
->state
= ANEG_STATE_ACK_DETECT
;
3381 case ANEG_STATE_ACK_DETECT
:
3382 if (ap
->ack_match
!= 0) {
3383 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3384 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3385 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3387 ap
->state
= ANEG_STATE_AN_ENABLE
;
3389 } else if (ap
->ability_match
!= 0 &&
3390 ap
->rxconfig
== 0) {
3391 ap
->state
= ANEG_STATE_AN_ENABLE
;
3395 case ANEG_STATE_COMPLETE_ACK_INIT
:
3396 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3400 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3401 MR_LP_ADV_HALF_DUPLEX
|
3402 MR_LP_ADV_SYM_PAUSE
|
3403 MR_LP_ADV_ASYM_PAUSE
|
3404 MR_LP_ADV_REMOTE_FAULT1
|
3405 MR_LP_ADV_REMOTE_FAULT2
|
3406 MR_LP_ADV_NEXT_PAGE
|
3409 if (ap
->rxconfig
& ANEG_CFG_FD
)
3410 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3411 if (ap
->rxconfig
& ANEG_CFG_HD
)
3412 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3413 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3414 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3415 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3416 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3417 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3418 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3419 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3420 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3421 if (ap
->rxconfig
& ANEG_CFG_NP
)
3422 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3424 ap
->link_time
= ap
->cur_time
;
3426 ap
->flags
^= (MR_TOGGLE_TX
);
3427 if (ap
->rxconfig
& 0x0008)
3428 ap
->flags
|= MR_TOGGLE_RX
;
3429 if (ap
->rxconfig
& ANEG_CFG_NP
)
3430 ap
->flags
|= MR_NP_RX
;
3431 ap
->flags
|= MR_PAGE_RX
;
3433 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3434 ret
= ANEG_TIMER_ENAB
;
3437 case ANEG_STATE_COMPLETE_ACK
:
3438 if (ap
->ability_match
!= 0 &&
3439 ap
->rxconfig
== 0) {
3440 ap
->state
= ANEG_STATE_AN_ENABLE
;
3443 delta
= ap
->cur_time
- ap
->link_time
;
3444 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3445 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3446 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3448 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3449 !(ap
->flags
& MR_NP_RX
)) {
3450 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3458 case ANEG_STATE_IDLE_DETECT_INIT
:
3459 ap
->link_time
= ap
->cur_time
;
3460 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3461 tw32_f(MAC_MODE
, tp
->mac_mode
);
3464 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3465 ret
= ANEG_TIMER_ENAB
;
3468 case ANEG_STATE_IDLE_DETECT
:
3469 if (ap
->ability_match
!= 0 &&
3470 ap
->rxconfig
== 0) {
3471 ap
->state
= ANEG_STATE_AN_ENABLE
;
3474 delta
= ap
->cur_time
- ap
->link_time
;
3475 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3476 /* XXX another gem from the Broadcom driver :( */
3477 ap
->state
= ANEG_STATE_LINK_OK
;
3481 case ANEG_STATE_LINK_OK
:
3482 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3486 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3487 /* ??? unimplemented */
3490 case ANEG_STATE_NEXT_PAGE_WAIT
:
3491 /* ??? unimplemented */
3502 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3505 struct tg3_fiber_aneginfo aninfo
;
3506 int status
= ANEG_FAILED
;
3510 tw32_f(MAC_TX_AUTO_NEG
, 0);
3512 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3513 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3516 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3519 memset(&aninfo
, 0, sizeof(aninfo
));
3520 aninfo
.flags
|= MR_AN_ENABLE
;
3521 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3522 aninfo
.cur_time
= 0;
3524 while (++tick
< 195000) {
3525 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3526 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3532 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3533 tw32_f(MAC_MODE
, tp
->mac_mode
);
3536 *txflags
= aninfo
.txconfig
;
3537 *rxflags
= aninfo
.flags
;
3539 if (status
== ANEG_DONE
&&
3540 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3541 MR_LP_ADV_FULL_DUPLEX
)))
3547 static void tg3_init_bcm8002(struct tg3
*tp
)
3549 u32 mac_status
= tr32(MAC_STATUS
);
3552 /* Reset when initting first time or we have a link. */
3553 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3554 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3557 /* Set PLL lock range. */
3558 tg3_writephy(tp
, 0x16, 0x8007);
3561 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3563 /* Wait for reset to complete. */
3564 /* XXX schedule_timeout() ... */
3565 for (i
= 0; i
< 500; i
++)
3568 /* Config mode; select PMA/Ch 1 regs. */
3569 tg3_writephy(tp
, 0x10, 0x8411);
3571 /* Enable auto-lock and comdet, select txclk for tx. */
3572 tg3_writephy(tp
, 0x11, 0x0a10);
3574 tg3_writephy(tp
, 0x18, 0x00a0);
3575 tg3_writephy(tp
, 0x16, 0x41ff);
3577 /* Assert and deassert POR. */
3578 tg3_writephy(tp
, 0x13, 0x0400);
3580 tg3_writephy(tp
, 0x13, 0x0000);
3582 tg3_writephy(tp
, 0x11, 0x0a50);
3584 tg3_writephy(tp
, 0x11, 0x0a10);
3586 /* Wait for signal to stabilize */
3587 /* XXX schedule_timeout() ... */
3588 for (i
= 0; i
< 15000; i
++)
3591 /* Deselect the channel register so we can read the PHYID
3594 tg3_writephy(tp
, 0x10, 0x8011);
3597 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3600 u32 sg_dig_ctrl
, sg_dig_status
;
3601 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3602 int workaround
, port_a
;
3603 int current_link_up
;
3606 expected_sg_dig_ctrl
= 0;
3609 current_link_up
= 0;
3611 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3612 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3614 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3617 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3618 /* preserve bits 20-23 for voltage regulator */
3619 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3622 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3624 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3625 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3627 u32 val
= serdes_cfg
;
3633 tw32_f(MAC_SERDES_CFG
, val
);
3636 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3638 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3639 tg3_setup_flow_control(tp
, 0, 0);
3640 current_link_up
= 1;
3645 /* Want auto-negotiation. */
3646 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3648 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3649 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3650 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3651 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3652 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3654 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3655 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3656 tp
->serdes_counter
&&
3657 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3658 MAC_STATUS_RCVD_CFG
)) ==
3659 MAC_STATUS_PCS_SYNCED
)) {
3660 tp
->serdes_counter
--;
3661 current_link_up
= 1;
3666 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3667 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3669 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3671 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3672 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3673 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3674 MAC_STATUS_SIGNAL_DET
)) {
3675 sg_dig_status
= tr32(SG_DIG_STATUS
);
3676 mac_status
= tr32(MAC_STATUS
);
3678 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3679 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3680 u32 local_adv
= 0, remote_adv
= 0;
3682 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3683 local_adv
|= ADVERTISE_1000XPAUSE
;
3684 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3685 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3687 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3688 remote_adv
|= LPA_1000XPAUSE
;
3689 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3690 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3692 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3693 current_link_up
= 1;
3694 tp
->serdes_counter
= 0;
3695 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3696 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3697 if (tp
->serdes_counter
)
3698 tp
->serdes_counter
--;
3701 u32 val
= serdes_cfg
;
3708 tw32_f(MAC_SERDES_CFG
, val
);
3711 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3714 /* Link parallel detection - link is up */
3715 /* only if we have PCS_SYNC and not */
3716 /* receiving config code words */
3717 mac_status
= tr32(MAC_STATUS
);
3718 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3719 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3720 tg3_setup_flow_control(tp
, 0, 0);
3721 current_link_up
= 1;
3723 TG3_FLG2_PARALLEL_DETECT
;
3724 tp
->serdes_counter
=
3725 SERDES_PARALLEL_DET_TIMEOUT
;
3727 goto restart_autoneg
;
3731 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3732 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3736 return current_link_up
;
3739 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3741 int current_link_up
= 0;
3743 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3746 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3747 u32 txflags
, rxflags
;
3750 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3751 u32 local_adv
= 0, remote_adv
= 0;
3753 if (txflags
& ANEG_CFG_PS1
)
3754 local_adv
|= ADVERTISE_1000XPAUSE
;
3755 if (txflags
& ANEG_CFG_PS2
)
3756 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3758 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3759 remote_adv
|= LPA_1000XPAUSE
;
3760 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3761 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3763 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3765 current_link_up
= 1;
3767 for (i
= 0; i
< 30; i
++) {
3770 (MAC_STATUS_SYNC_CHANGED
|
3771 MAC_STATUS_CFG_CHANGED
));
3773 if ((tr32(MAC_STATUS
) &
3774 (MAC_STATUS_SYNC_CHANGED
|
3775 MAC_STATUS_CFG_CHANGED
)) == 0)
3779 mac_status
= tr32(MAC_STATUS
);
3780 if (current_link_up
== 0 &&
3781 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3782 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3783 current_link_up
= 1;
3785 tg3_setup_flow_control(tp
, 0, 0);
3787 /* Forcing 1000FD link up. */
3788 current_link_up
= 1;
3790 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3793 tw32_f(MAC_MODE
, tp
->mac_mode
);
3798 return current_link_up
;
3801 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3804 u16 orig_active_speed
;
3805 u8 orig_active_duplex
;
3807 int current_link_up
;
3810 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3811 orig_active_speed
= tp
->link_config
.active_speed
;
3812 orig_active_duplex
= tp
->link_config
.active_duplex
;
3814 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3815 netif_carrier_ok(tp
->dev
) &&
3816 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3817 mac_status
= tr32(MAC_STATUS
);
3818 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3819 MAC_STATUS_SIGNAL_DET
|
3820 MAC_STATUS_CFG_CHANGED
|
3821 MAC_STATUS_RCVD_CFG
);
3822 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3823 MAC_STATUS_SIGNAL_DET
)) {
3824 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3825 MAC_STATUS_CFG_CHANGED
));
3830 tw32_f(MAC_TX_AUTO_NEG
, 0);
3832 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3833 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3834 tw32_f(MAC_MODE
, tp
->mac_mode
);
3837 if (tp
->phy_id
== PHY_ID_BCM8002
)
3838 tg3_init_bcm8002(tp
);
3840 /* Enable link change event even when serdes polling. */
3841 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3844 current_link_up
= 0;
3845 mac_status
= tr32(MAC_STATUS
);
3847 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3848 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3850 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3852 tp
->hw_status
->status
=
3853 (SD_STATUS_UPDATED
|
3854 (tp
->hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3856 for (i
= 0; i
< 100; i
++) {
3857 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3858 MAC_STATUS_CFG_CHANGED
));
3860 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3861 MAC_STATUS_CFG_CHANGED
|
3862 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3866 mac_status
= tr32(MAC_STATUS
);
3867 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3868 current_link_up
= 0;
3869 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3870 tp
->serdes_counter
== 0) {
3871 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3872 MAC_MODE_SEND_CONFIGS
));
3874 tw32_f(MAC_MODE
, tp
->mac_mode
);
3878 if (current_link_up
== 1) {
3879 tp
->link_config
.active_speed
= SPEED_1000
;
3880 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3881 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3882 LED_CTRL_LNKLED_OVERRIDE
|
3883 LED_CTRL_1000MBPS_ON
));
3885 tp
->link_config
.active_speed
= SPEED_INVALID
;
3886 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3887 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3888 LED_CTRL_LNKLED_OVERRIDE
|
3889 LED_CTRL_TRAFFIC_OVERRIDE
));
3892 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3893 if (current_link_up
)
3894 netif_carrier_on(tp
->dev
);
3896 netif_carrier_off(tp
->dev
);
3897 tg3_link_report(tp
);
3899 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
3900 if (orig_pause_cfg
!= now_pause_cfg
||
3901 orig_active_speed
!= tp
->link_config
.active_speed
||
3902 orig_active_duplex
!= tp
->link_config
.active_duplex
)
3903 tg3_link_report(tp
);
3909 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
3911 int current_link_up
, err
= 0;
3915 u32 local_adv
, remote_adv
;
3917 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3918 tw32_f(MAC_MODE
, tp
->mac_mode
);
3924 (MAC_STATUS_SYNC_CHANGED
|
3925 MAC_STATUS_CFG_CHANGED
|
3926 MAC_STATUS_MI_COMPLETION
|
3927 MAC_STATUS_LNKSTATE_CHANGED
));
3933 current_link_up
= 0;
3934 current_speed
= SPEED_INVALID
;
3935 current_duplex
= DUPLEX_INVALID
;
3937 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3938 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3939 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
3940 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
3941 bmsr
|= BMSR_LSTATUS
;
3943 bmsr
&= ~BMSR_LSTATUS
;
3946 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3948 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
3949 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
3950 /* do nothing, just check for link up at the end */
3951 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3954 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
3955 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
3956 ADVERTISE_1000XPAUSE
|
3957 ADVERTISE_1000XPSE_ASYM
|
3960 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3962 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
3963 new_adv
|= ADVERTISE_1000XHALF
;
3964 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
3965 new_adv
|= ADVERTISE_1000XFULL
;
3967 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
3968 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
3969 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
3970 tg3_writephy(tp
, MII_BMCR
, bmcr
);
3972 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3973 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
3974 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3981 bmcr
&= ~BMCR_SPEED1000
;
3982 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
3984 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
3985 new_bmcr
|= BMCR_FULLDPLX
;
3987 if (new_bmcr
!= bmcr
) {
3988 /* BMCR_SPEED1000 is a reserved bit that needs
3989 * to be set on write.
3991 new_bmcr
|= BMCR_SPEED1000
;
3993 /* Force a linkdown */
3994 if (netif_carrier_ok(tp
->dev
)) {
3997 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
3998 adv
&= ~(ADVERTISE_1000XFULL
|
3999 ADVERTISE_1000XHALF
|
4001 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4002 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4006 netif_carrier_off(tp
->dev
);
4008 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4010 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4011 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4012 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4014 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4015 bmsr
|= BMSR_LSTATUS
;
4017 bmsr
&= ~BMSR_LSTATUS
;
4019 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4023 if (bmsr
& BMSR_LSTATUS
) {
4024 current_speed
= SPEED_1000
;
4025 current_link_up
= 1;
4026 if (bmcr
& BMCR_FULLDPLX
)
4027 current_duplex
= DUPLEX_FULL
;
4029 current_duplex
= DUPLEX_HALF
;
4034 if (bmcr
& BMCR_ANENABLE
) {
4037 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4038 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4039 common
= local_adv
& remote_adv
;
4040 if (common
& (ADVERTISE_1000XHALF
|
4041 ADVERTISE_1000XFULL
)) {
4042 if (common
& ADVERTISE_1000XFULL
)
4043 current_duplex
= DUPLEX_FULL
;
4045 current_duplex
= DUPLEX_HALF
;
4048 current_link_up
= 0;
4052 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4053 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4055 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4056 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4057 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4059 tw32_f(MAC_MODE
, tp
->mac_mode
);
4062 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4064 tp
->link_config
.active_speed
= current_speed
;
4065 tp
->link_config
.active_duplex
= current_duplex
;
4067 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4068 if (current_link_up
)
4069 netif_carrier_on(tp
->dev
);
4071 netif_carrier_off(tp
->dev
);
4072 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4074 tg3_link_report(tp
);
4079 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4081 if (tp
->serdes_counter
) {
4082 /* Give autoneg time to complete. */
4083 tp
->serdes_counter
--;
4086 if (!netif_carrier_ok(tp
->dev
) &&
4087 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4090 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4091 if (bmcr
& BMCR_ANENABLE
) {
4094 /* Select shadow register 0x1f */
4095 tg3_writephy(tp
, 0x1c, 0x7c00);
4096 tg3_readphy(tp
, 0x1c, &phy1
);
4098 /* Select expansion interrupt status register */
4099 tg3_writephy(tp
, 0x17, 0x0f01);
4100 tg3_readphy(tp
, 0x15, &phy2
);
4101 tg3_readphy(tp
, 0x15, &phy2
);
4103 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4104 /* We have signal detect and not receiving
4105 * config code words, link is up by parallel
4109 bmcr
&= ~BMCR_ANENABLE
;
4110 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4111 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4112 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4116 else if (netif_carrier_ok(tp
->dev
) &&
4117 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4118 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4121 /* Select expansion interrupt status register */
4122 tg3_writephy(tp
, 0x17, 0x0f01);
4123 tg3_readphy(tp
, 0x15, &phy2
);
4127 /* Config code words received, turn on autoneg. */
4128 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4129 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4131 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4137 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4141 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4142 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4143 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
4144 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4146 err
= tg3_setup_copper_phy(tp
, force_reset
);
4149 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4152 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4153 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4155 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4160 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4161 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4162 tw32(GRC_MISC_CFG
, val
);
4165 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4166 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4167 tw32(MAC_TX_LENGTHS
,
4168 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4169 (6 << TX_LENGTHS_IPG_SHIFT
) |
4170 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4172 tw32(MAC_TX_LENGTHS
,
4173 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4174 (6 << TX_LENGTHS_IPG_SHIFT
) |
4175 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4177 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4178 if (netif_carrier_ok(tp
->dev
)) {
4179 tw32(HOSTCC_STAT_COAL_TICKS
,
4180 tp
->coal
.stats_block_coalesce_usecs
);
4182 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4186 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4187 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4188 if (!netif_carrier_ok(tp
->dev
))
4189 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4192 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4193 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4199 /* This is called whenever we suspect that the system chipset is re-
4200 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4201 * is bogus tx completions. We try to recover by setting the
4202 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4205 static void tg3_tx_recover(struct tg3
*tp
)
4207 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4208 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4210 printk(KERN_WARNING PFX
"%s: The system may be re-ordering memory-"
4211 "mapped I/O cycles to the network device, attempting to "
4212 "recover. Please report the problem to the driver maintainer "
4213 "and include system chipset information.\n", tp
->dev
->name
);
4215 spin_lock(&tp
->lock
);
4216 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4217 spin_unlock(&tp
->lock
);
4220 static inline u32
tg3_tx_avail(struct tg3
*tp
)
4223 return (tp
->tx_pending
-
4224 ((tp
->tx_prod
- tp
->tx_cons
) & (TG3_TX_RING_SIZE
- 1)));
4227 /* Tigon3 never reports partial packet sends. So we do not
4228 * need special logic to handle SKBs that have not had all
4229 * of their frags sent yet, like SunGEM does.
4231 static void tg3_tx(struct tg3
*tp
)
4233 u32 hw_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
4234 u32 sw_idx
= tp
->tx_cons
;
4236 while (sw_idx
!= hw_idx
) {
4237 struct tx_ring_info
*ri
= &tp
->tx_buffers
[sw_idx
];
4238 struct sk_buff
*skb
= ri
->skb
;
4241 if (unlikely(skb
== NULL
)) {
4246 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4250 sw_idx
= NEXT_TX(sw_idx
);
4252 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4253 ri
= &tp
->tx_buffers
[sw_idx
];
4254 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4256 sw_idx
= NEXT_TX(sw_idx
);
4261 if (unlikely(tx_bug
)) {
4267 tp
->tx_cons
= sw_idx
;
4269 /* Need to make the tx_cons update visible to tg3_start_xmit()
4270 * before checking for netif_queue_stopped(). Without the
4271 * memory barrier, there is a small possibility that tg3_start_xmit()
4272 * will miss it and cause the queue to be stopped forever.
4276 if (unlikely(netif_queue_stopped(tp
->dev
) &&
4277 (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
)))) {
4278 netif_tx_lock(tp
->dev
);
4279 if (netif_queue_stopped(tp
->dev
) &&
4280 (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
)))
4281 netif_wake_queue(tp
->dev
);
4282 netif_tx_unlock(tp
->dev
);
4286 /* Returns size of skb allocated or < 0 on error.
4288 * We only need to fill in the address because the other members
4289 * of the RX descriptor are invariant, see tg3_init_rings.
4291 * Note the purposeful assymetry of cpu vs. chip accesses. For
4292 * posting buffers we only dirty the first cache line of the RX
4293 * descriptor (containing the address). Whereas for the RX status
4294 * buffers the cpu only reads the last cacheline of the RX descriptor
4295 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4297 static int tg3_alloc_rx_skb(struct tg3
*tp
, u32 opaque_key
,
4298 int src_idx
, u32 dest_idx_unmasked
)
4300 struct tg3_rx_buffer_desc
*desc
;
4301 struct ring_info
*map
, *src_map
;
4302 struct sk_buff
*skb
;
4304 int skb_size
, dest_idx
;
4307 switch (opaque_key
) {
4308 case RXD_OPAQUE_RING_STD
:
4309 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4310 desc
= &tp
->rx_std
[dest_idx
];
4311 map
= &tp
->rx_std_buffers
[dest_idx
];
4313 src_map
= &tp
->rx_std_buffers
[src_idx
];
4314 skb_size
= tp
->rx_pkt_buf_sz
;
4317 case RXD_OPAQUE_RING_JUMBO
:
4318 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4319 desc
= &tp
->rx_jumbo
[dest_idx
];
4320 map
= &tp
->rx_jumbo_buffers
[dest_idx
];
4322 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
4323 skb_size
= RX_JUMBO_PKT_BUF_SZ
;
4330 /* Do not overwrite any of the map or rp information
4331 * until we are sure we can commit to a new buffer.
4333 * Callers depend upon this behavior and assume that
4334 * we leave everything unchanged if we fail.
4336 skb
= netdev_alloc_skb(tp
->dev
, skb_size
);
4340 skb_reserve(skb
, tp
->rx_offset
);
4342 mapping
= pci_map_single(tp
->pdev
, skb
->data
,
4343 skb_size
- tp
->rx_offset
,
4344 PCI_DMA_FROMDEVICE
);
4347 pci_unmap_addr_set(map
, mapping
, mapping
);
4349 if (src_map
!= NULL
)
4350 src_map
->skb
= NULL
;
4352 desc
->addr_hi
= ((u64
)mapping
>> 32);
4353 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4358 /* We only need to move over in the address because the other
4359 * members of the RX descriptor are invariant. See notes above
4360 * tg3_alloc_rx_skb for full details.
4362 static void tg3_recycle_rx(struct tg3
*tp
, u32 opaque_key
,
4363 int src_idx
, u32 dest_idx_unmasked
)
4365 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4366 struct ring_info
*src_map
, *dest_map
;
4369 switch (opaque_key
) {
4370 case RXD_OPAQUE_RING_STD
:
4371 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4372 dest_desc
= &tp
->rx_std
[dest_idx
];
4373 dest_map
= &tp
->rx_std_buffers
[dest_idx
];
4374 src_desc
= &tp
->rx_std
[src_idx
];
4375 src_map
= &tp
->rx_std_buffers
[src_idx
];
4378 case RXD_OPAQUE_RING_JUMBO
:
4379 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4380 dest_desc
= &tp
->rx_jumbo
[dest_idx
];
4381 dest_map
= &tp
->rx_jumbo_buffers
[dest_idx
];
4382 src_desc
= &tp
->rx_jumbo
[src_idx
];
4383 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
4390 dest_map
->skb
= src_map
->skb
;
4391 pci_unmap_addr_set(dest_map
, mapping
,
4392 pci_unmap_addr(src_map
, mapping
));
4393 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4394 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4396 src_map
->skb
= NULL
;
4399 #if TG3_VLAN_TAG_USED
4400 static int tg3_vlan_rx(struct tg3
*tp
, struct sk_buff
*skb
, u16 vlan_tag
)
4402 return vlan_gro_receive(&tp
->napi
, tp
->vlgrp
, vlan_tag
, skb
);
4406 /* The RX ring scheme is composed of multiple rings which post fresh
4407 * buffers to the chip, and one special ring the chip uses to report
4408 * status back to the host.
4410 * The special ring reports the status of received packets to the
4411 * host. The chip does not write into the original descriptor the
4412 * RX buffer was obtained from. The chip simply takes the original
4413 * descriptor as provided by the host, updates the status and length
4414 * field, then writes this into the next status ring entry.
4416 * Each ring the host uses to post buffers to the chip is described
4417 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4418 * it is first placed into the on-chip ram. When the packet's length
4419 * is known, it walks down the TG3_BDINFO entries to select the ring.
4420 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4421 * which is within the range of the new packet's length is chosen.
4423 * The "separate ring for rx status" scheme may sound queer, but it makes
4424 * sense from a cache coherency perspective. If only the host writes
4425 * to the buffer post rings, and only the chip writes to the rx status
4426 * rings, then cache lines never move beyond shared-modified state.
4427 * If both the host and chip were to write into the same ring, cache line
4428 * eviction could occur since both entities want it in an exclusive state.
4430 static int tg3_rx(struct tg3
*tp
, int budget
)
4432 u32 work_mask
, rx_std_posted
= 0;
4433 u32 sw_idx
= tp
->rx_rcb_ptr
;
4437 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
4439 * We need to order the read of hw_idx and the read of
4440 * the opaque cookie.
4445 while (sw_idx
!= hw_idx
&& budget
> 0) {
4446 struct tg3_rx_buffer_desc
*desc
= &tp
->rx_rcb
[sw_idx
];
4448 struct sk_buff
*skb
;
4449 dma_addr_t dma_addr
;
4450 u32 opaque_key
, desc_idx
, *post_ptr
;
4452 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4453 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4454 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4455 dma_addr
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
],
4457 skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
4458 post_ptr
= &tp
->rx_std_ptr
;
4460 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4461 dma_addr
= pci_unmap_addr(&tp
->rx_jumbo_buffers
[desc_idx
],
4463 skb
= tp
->rx_jumbo_buffers
[desc_idx
].skb
;
4464 post_ptr
= &tp
->rx_jumbo_ptr
;
4467 goto next_pkt_nopost
;
4470 work_mask
|= opaque_key
;
4472 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4473 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4475 tg3_recycle_rx(tp
, opaque_key
,
4476 desc_idx
, *post_ptr
);
4478 /* Other statistics kept track of by card. */
4479 tp
->net_stats
.rx_dropped
++;
4483 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4486 if (len
> RX_COPY_THRESHOLD
4487 && tp
->rx_offset
== NET_IP_ALIGN
4488 /* rx_offset will likely not equal NET_IP_ALIGN
4489 * if this is a 5701 card running in PCI-X mode
4490 * [see tg3_get_invariants()]
4495 skb_size
= tg3_alloc_rx_skb(tp
, opaque_key
,
4496 desc_idx
, *post_ptr
);
4500 pci_unmap_single(tp
->pdev
, dma_addr
,
4501 skb_size
- tp
->rx_offset
,
4502 PCI_DMA_FROMDEVICE
);
4506 struct sk_buff
*copy_skb
;
4508 tg3_recycle_rx(tp
, opaque_key
,
4509 desc_idx
, *post_ptr
);
4511 copy_skb
= netdev_alloc_skb(tp
->dev
,
4512 len
+ TG3_RAW_IP_ALIGN
);
4513 if (copy_skb
== NULL
)
4514 goto drop_it_no_recycle
;
4516 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4517 skb_put(copy_skb
, len
);
4518 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4519 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4520 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4522 /* We'll reuse the original ring buffer. */
4526 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4527 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4528 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4529 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4530 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4532 skb
->ip_summed
= CHECKSUM_NONE
;
4534 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4536 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4537 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4542 #if TG3_VLAN_TAG_USED
4543 if (tp
->vlgrp
!= NULL
&&
4544 desc
->type_flags
& RXD_FLAG_VLAN
) {
4545 tg3_vlan_rx(tp
, skb
,
4546 desc
->err_vlan
& RXD_VLAN_MASK
);
4549 napi_gro_receive(&tp
->napi
, skb
);
4557 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4558 u32 idx
= *post_ptr
% TG3_RX_RING_SIZE
;
4560 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+
4561 TG3_64BIT_REG_LOW
, idx
);
4562 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4567 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4569 /* Refresh hw_idx to see if there is new work */
4570 if (sw_idx
== hw_idx
) {
4571 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
4576 /* ACK the status ring. */
4577 tp
->rx_rcb_ptr
= sw_idx
;
4578 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, sw_idx
);
4580 /* Refill RX ring(s). */
4581 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4582 sw_idx
= tp
->rx_std_ptr
% TG3_RX_RING_SIZE
;
4583 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4586 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4587 sw_idx
= tp
->rx_jumbo_ptr
% TG3_RX_JUMBO_RING_SIZE
;
4588 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4596 static int tg3_poll_work(struct tg3
*tp
, int work_done
, int budget
)
4598 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4600 /* handle link change and other phy events */
4601 if (!(tp
->tg3_flags
&
4602 (TG3_FLAG_USE_LINKCHG_REG
|
4603 TG3_FLAG_POLL_SERDES
))) {
4604 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4605 sblk
->status
= SD_STATUS_UPDATED
|
4606 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4607 spin_lock(&tp
->lock
);
4608 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4610 (MAC_STATUS_SYNC_CHANGED
|
4611 MAC_STATUS_CFG_CHANGED
|
4612 MAC_STATUS_MI_COMPLETION
|
4613 MAC_STATUS_LNKSTATE_CHANGED
));
4616 tg3_setup_phy(tp
, 0);
4617 spin_unlock(&tp
->lock
);
4621 /* run TX completion thread */
4622 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
) {
4624 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4628 /* run RX thread, within the bounds set by NAPI.
4629 * All RX "locking" is done by ensuring outside
4630 * code synchronizes with tg3->napi.poll()
4632 if (sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
4633 work_done
+= tg3_rx(tp
, budget
- work_done
);
4638 static int tg3_poll(struct napi_struct
*napi
, int budget
)
4640 struct tg3
*tp
= container_of(napi
, struct tg3
, napi
);
4642 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4645 work_done
= tg3_poll_work(tp
, work_done
, budget
);
4647 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4650 if (unlikely(work_done
>= budget
))
4653 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
4654 /* tp->last_tag is used in tg3_restart_ints() below
4655 * to tell the hw how much work has been processed,
4656 * so we must read it before checking for more work.
4658 tp
->last_tag
= sblk
->status_tag
;
4659 tp
->last_irq_tag
= tp
->last_tag
;
4662 sblk
->status
&= ~SD_STATUS_UPDATED
;
4664 if (likely(!tg3_has_work(tp
))) {
4665 napi_complete(napi
);
4666 tg3_restart_ints(tp
);
4674 /* work_done is guaranteed to be less than budget. */
4675 napi_complete(napi
);
4676 schedule_work(&tp
->reset_task
);
4680 static void tg3_irq_quiesce(struct tg3
*tp
)
4682 BUG_ON(tp
->irq_sync
);
4687 synchronize_irq(tp
->pdev
->irq
);
4690 static inline int tg3_irq_sync(struct tg3
*tp
)
4692 return tp
->irq_sync
;
4695 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4696 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4697 * with as well. Most of the time, this is not necessary except when
4698 * shutting down the device.
4700 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
4702 spin_lock_bh(&tp
->lock
);
4704 tg3_irq_quiesce(tp
);
4707 static inline void tg3_full_unlock(struct tg3
*tp
)
4709 spin_unlock_bh(&tp
->lock
);
4712 /* One-shot MSI handler - Chip automatically disables interrupt
4713 * after sending MSI so driver doesn't have to do it.
4715 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
4717 struct net_device
*dev
= dev_id
;
4718 struct tg3
*tp
= netdev_priv(dev
);
4720 prefetch(tp
->hw_status
);
4721 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4723 if (likely(!tg3_irq_sync(tp
)))
4724 napi_schedule(&tp
->napi
);
4729 /* MSI ISR - No need to check for interrupt sharing and no need to
4730 * flush status block and interrupt mailbox. PCI ordering rules
4731 * guarantee that MSI will arrive after the status block.
4733 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
4735 struct net_device
*dev
= dev_id
;
4736 struct tg3
*tp
= netdev_priv(dev
);
4738 prefetch(tp
->hw_status
);
4739 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4741 * Writing any value to intr-mbox-0 clears PCI INTA# and
4742 * chip-internal interrupt pending events.
4743 * Writing non-zero to intr-mbox-0 additional tells the
4744 * NIC to stop sending us irqs, engaging "in-intr-handler"
4747 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4748 if (likely(!tg3_irq_sync(tp
)))
4749 napi_schedule(&tp
->napi
);
4751 return IRQ_RETVAL(1);
4754 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
4756 struct net_device
*dev
= dev_id
;
4757 struct tg3
*tp
= netdev_priv(dev
);
4758 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4759 unsigned int handled
= 1;
4761 /* In INTx mode, it is possible for the interrupt to arrive at
4762 * the CPU before the status block posted prior to the interrupt.
4763 * Reading the PCI State register will confirm whether the
4764 * interrupt is ours and will flush the status block.
4766 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
4767 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4768 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4775 * Writing any value to intr-mbox-0 clears PCI INTA# and
4776 * chip-internal interrupt pending events.
4777 * Writing non-zero to intr-mbox-0 additional tells the
4778 * NIC to stop sending us irqs, engaging "in-intr-handler"
4781 * Flush the mailbox to de-assert the IRQ immediately to prevent
4782 * spurious interrupts. The flush impacts performance but
4783 * excessive spurious interrupts can be worse in some cases.
4785 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4786 if (tg3_irq_sync(tp
))
4788 sblk
->status
&= ~SD_STATUS_UPDATED
;
4789 if (likely(tg3_has_work(tp
))) {
4790 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4791 napi_schedule(&tp
->napi
);
4793 /* No work, shared interrupt perhaps? re-enable
4794 * interrupts, and flush that PCI write
4796 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
4800 return IRQ_RETVAL(handled
);
4803 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
4805 struct net_device
*dev
= dev_id
;
4806 struct tg3
*tp
= netdev_priv(dev
);
4807 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4808 unsigned int handled
= 1;
4810 /* In INTx mode, it is possible for the interrupt to arrive at
4811 * the CPU before the status block posted prior to the interrupt.
4812 * Reading the PCI State register will confirm whether the
4813 * interrupt is ours and will flush the status block.
4815 if (unlikely(sblk
->status_tag
== tp
->last_irq_tag
)) {
4816 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4817 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4824 * writing any value to intr-mbox-0 clears PCI INTA# and
4825 * chip-internal interrupt pending events.
4826 * writing non-zero to intr-mbox-0 additional tells the
4827 * NIC to stop sending us irqs, engaging "in-intr-handler"
4830 * Flush the mailbox to de-assert the IRQ immediately to prevent
4831 * spurious interrupts. The flush impacts performance but
4832 * excessive spurious interrupts can be worse in some cases.
4834 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4837 * In a shared interrupt configuration, sometimes other devices'
4838 * interrupts will scream. We record the current status tag here
4839 * so that the above check can report that the screaming interrupts
4840 * are unhandled. Eventually they will be silenced.
4842 tp
->last_irq_tag
= sblk
->status_tag
;
4844 if (tg3_irq_sync(tp
))
4847 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4849 napi_schedule(&tp
->napi
);
4852 return IRQ_RETVAL(handled
);
4855 /* ISR for interrupt test */
4856 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
4858 struct net_device
*dev
= dev_id
;
4859 struct tg3
*tp
= netdev_priv(dev
);
4860 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4862 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
4863 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4864 tg3_disable_ints(tp
);
4865 return IRQ_RETVAL(1);
4867 return IRQ_RETVAL(0);
4870 static int tg3_init_hw(struct tg3
*, int);
4871 static int tg3_halt(struct tg3
*, int, int);
4873 /* Restart hardware after configuration changes, self-test, etc.
4874 * Invoked with tp->lock held.
4876 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
4877 __releases(tp
->lock
)
4878 __acquires(tp
->lock
)
4882 err
= tg3_init_hw(tp
, reset_phy
);
4884 printk(KERN_ERR PFX
"%s: Failed to re-initialize device, "
4885 "aborting.\n", tp
->dev
->name
);
4886 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
4887 tg3_full_unlock(tp
);
4888 del_timer_sync(&tp
->timer
);
4890 napi_enable(&tp
->napi
);
4892 tg3_full_lock(tp
, 0);
4897 #ifdef CONFIG_NET_POLL_CONTROLLER
4898 static void tg3_poll_controller(struct net_device
*dev
)
4900 struct tg3
*tp
= netdev_priv(dev
);
4902 tg3_interrupt(tp
->pdev
->irq
, dev
);
4906 static void tg3_reset_task(struct work_struct
*work
)
4908 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
4910 unsigned int restart_timer
;
4912 tg3_full_lock(tp
, 0);
4914 if (!netif_running(tp
->dev
)) {
4915 tg3_full_unlock(tp
);
4919 tg3_full_unlock(tp
);
4925 tg3_full_lock(tp
, 1);
4927 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
4928 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
4930 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
4931 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
4932 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
4933 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
4934 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
4937 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
4938 err
= tg3_init_hw(tp
, 1);
4942 tg3_netif_start(tp
);
4945 mod_timer(&tp
->timer
, jiffies
+ 1);
4948 tg3_full_unlock(tp
);
4954 static void tg3_dump_short_state(struct tg3
*tp
)
4956 printk(KERN_ERR PFX
"DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4957 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
4958 printk(KERN_ERR PFX
"DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4959 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
4962 static void tg3_tx_timeout(struct net_device
*dev
)
4964 struct tg3
*tp
= netdev_priv(dev
);
4966 if (netif_msg_tx_err(tp
)) {
4967 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
4969 tg3_dump_short_state(tp
);
4972 schedule_work(&tp
->reset_task
);
4975 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4976 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
4978 u32 base
= (u32
) mapping
& 0xffffffff;
4980 return ((base
> 0xffffdcc0) &&
4981 (base
+ len
+ 8 < base
));
4984 /* Test for DMA addresses > 40-bit */
4985 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
4988 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4989 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
4990 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
4997 static void tg3_set_txd(struct tg3
*, int, dma_addr_t
, int, u32
, u32
);
4999 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5000 static int tigon3_dma_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
5001 u32 last_plus_one
, u32
*start
,
5002 u32 base_flags
, u32 mss
)
5004 struct sk_buff
*new_skb
;
5005 dma_addr_t new_addr
= 0;
5009 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5010 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5012 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5014 new_skb
= skb_copy_expand(skb
,
5015 skb_headroom(skb
) + more_headroom
,
5016 skb_tailroom(skb
), GFP_ATOMIC
);
5022 /* New SKB is guaranteed to be linear. */
5024 ret
= skb_dma_map(&tp
->pdev
->dev
, new_skb
, DMA_TO_DEVICE
);
5025 new_addr
= skb_shinfo(new_skb
)->dma_maps
[0];
5027 /* Make sure new skb does not cross any 4G boundaries.
5028 * Drop the packet if it does.
5030 if (ret
|| tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5032 skb_dma_unmap(&tp
->pdev
->dev
, new_skb
,
5035 dev_kfree_skb(new_skb
);
5038 tg3_set_txd(tp
, entry
, new_addr
, new_skb
->len
,
5039 base_flags
, 1 | (mss
<< 1));
5040 *start
= NEXT_TX(entry
);
5044 /* Now clean up the sw ring entries. */
5046 while (entry
!= last_plus_one
) {
5048 tp
->tx_buffers
[entry
].skb
= new_skb
;
5050 tp
->tx_buffers
[entry
].skb
= NULL
;
5052 entry
= NEXT_TX(entry
);
5056 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5062 static void tg3_set_txd(struct tg3
*tp
, int entry
,
5063 dma_addr_t mapping
, int len
, u32 flags
,
5066 struct tg3_tx_buffer_desc
*txd
= &tp
->tx_ring
[entry
];
5067 int is_end
= (mss_and_is_end
& 0x1);
5068 u32 mss
= (mss_and_is_end
>> 1);
5072 flags
|= TXD_FLAG_END
;
5073 if (flags
& TXD_FLAG_VLAN
) {
5074 vlan_tag
= flags
>> 16;
5077 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5079 txd
->addr_hi
= ((u64
) mapping
>> 32);
5080 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5081 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5082 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5085 /* hard_start_xmit for devices that don't have any bugs and
5086 * support TG3_FLG2_HW_TSO_2 only.
5088 static int tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
5090 struct tg3
*tp
= netdev_priv(dev
);
5091 u32 len
, entry
, base_flags
, mss
;
5092 struct skb_shared_info
*sp
;
5095 len
= skb_headlen(skb
);
5097 /* We are running in BH disabled context with netif_tx_lock
5098 * and TX reclaim runs via tp->napi.poll inside of a software
5099 * interrupt. Furthermore, IRQ processing runs lockless so we have
5100 * no IRQ context deadlocks to worry about either. Rejoice!
5102 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5103 if (!netif_queue_stopped(dev
)) {
5104 netif_stop_queue(dev
);
5106 /* This is a hard error, log it. */
5107 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5108 "queue awake!\n", dev
->name
);
5110 return NETDEV_TX_BUSY
;
5113 entry
= tp
->tx_prod
;
5116 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5117 int tcp_opt_len
, ip_tcp_len
;
5119 if (skb_header_cloned(skb
) &&
5120 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5125 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5126 mss
|= (skb_headlen(skb
) - ETH_HLEN
) << 9;
5128 struct iphdr
*iph
= ip_hdr(skb
);
5130 tcp_opt_len
= tcp_optlen(skb
);
5131 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5134 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5135 mss
|= (ip_tcp_len
+ tcp_opt_len
) << 9;
5138 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5139 TXD_FLAG_CPU_POST_DMA
);
5141 tcp_hdr(skb
)->check
= 0;
5144 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5145 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5146 #if TG3_VLAN_TAG_USED
5147 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5148 base_flags
|= (TXD_FLAG_VLAN
|
5149 (vlan_tx_tag_get(skb
) << 16));
5152 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5157 sp
= skb_shinfo(skb
);
5159 mapping
= sp
->dma_maps
[0];
5161 tp
->tx_buffers
[entry
].skb
= skb
;
5163 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
5164 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5166 entry
= NEXT_TX(entry
);
5168 /* Now loop through additional data fragments, and queue them. */
5169 if (skb_shinfo(skb
)->nr_frags
> 0) {
5170 unsigned int i
, last
;
5172 last
= skb_shinfo(skb
)->nr_frags
- 1;
5173 for (i
= 0; i
<= last
; i
++) {
5174 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5177 mapping
= sp
->dma_maps
[i
+ 1];
5178 tp
->tx_buffers
[entry
].skb
= NULL
;
5180 tg3_set_txd(tp
, entry
, mapping
, len
,
5181 base_flags
, (i
== last
) | (mss
<< 1));
5183 entry
= NEXT_TX(entry
);
5187 /* Packets are ready, update Tx producer idx local and on card. */
5188 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
5190 tp
->tx_prod
= entry
;
5191 if (unlikely(tg3_tx_avail(tp
) <= (MAX_SKB_FRAGS
+ 1))) {
5192 netif_stop_queue(dev
);
5193 if (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
))
5194 netif_wake_queue(tp
->dev
);
5200 dev
->trans_start
= jiffies
;
5202 return NETDEV_TX_OK
;
5205 static int tg3_start_xmit_dma_bug(struct sk_buff
*, struct net_device
*);
5207 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5208 * TSO header is greater than 80 bytes.
5210 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5212 struct sk_buff
*segs
, *nskb
;
5214 /* Estimate the number of fragments in the worst case */
5215 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->gso_segs
* 3))) {
5216 netif_stop_queue(tp
->dev
);
5217 if (tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->gso_segs
* 3))
5218 return NETDEV_TX_BUSY
;
5220 netif_wake_queue(tp
->dev
);
5223 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5225 goto tg3_tso_bug_end
;
5231 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5237 return NETDEV_TX_OK
;
5240 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5241 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5243 static int tg3_start_xmit_dma_bug(struct sk_buff
*skb
, struct net_device
*dev
)
5245 struct tg3
*tp
= netdev_priv(dev
);
5246 u32 len
, entry
, base_flags
, mss
;
5247 struct skb_shared_info
*sp
;
5248 int would_hit_hwbug
;
5251 len
= skb_headlen(skb
);
5253 /* We are running in BH disabled context with netif_tx_lock
5254 * and TX reclaim runs via tp->napi.poll inside of a software
5255 * interrupt. Furthermore, IRQ processing runs lockless so we have
5256 * no IRQ context deadlocks to worry about either. Rejoice!
5258 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5259 if (!netif_queue_stopped(dev
)) {
5260 netif_stop_queue(dev
);
5262 /* This is a hard error, log it. */
5263 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5264 "queue awake!\n", dev
->name
);
5266 return NETDEV_TX_BUSY
;
5269 entry
= tp
->tx_prod
;
5271 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5272 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5274 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5276 int tcp_opt_len
, ip_tcp_len
, hdr_len
;
5278 if (skb_header_cloned(skb
) &&
5279 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5284 tcp_opt_len
= tcp_optlen(skb
);
5285 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5287 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5288 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5289 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5290 return (tg3_tso_bug(tp
, skb
));
5292 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5293 TXD_FLAG_CPU_POST_DMA
);
5297 iph
->tot_len
= htons(mss
+ hdr_len
);
5298 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5299 tcp_hdr(skb
)->check
= 0;
5300 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5302 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5307 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
5308 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
5309 if (tcp_opt_len
|| iph
->ihl
> 5) {
5312 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5313 mss
|= (tsflags
<< 11);
5316 if (tcp_opt_len
|| iph
->ihl
> 5) {
5319 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5320 base_flags
|= tsflags
<< 12;
5324 #if TG3_VLAN_TAG_USED
5325 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5326 base_flags
|= (TXD_FLAG_VLAN
|
5327 (vlan_tx_tag_get(skb
) << 16));
5330 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5335 sp
= skb_shinfo(skb
);
5337 mapping
= sp
->dma_maps
[0];
5339 tp
->tx_buffers
[entry
].skb
= skb
;
5341 would_hit_hwbug
= 0;
5343 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5344 would_hit_hwbug
= 1;
5345 else if (tg3_4g_overflow_test(mapping
, len
))
5346 would_hit_hwbug
= 1;
5348 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
5349 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5351 entry
= NEXT_TX(entry
);
5353 /* Now loop through additional data fragments, and queue them. */
5354 if (skb_shinfo(skb
)->nr_frags
> 0) {
5355 unsigned int i
, last
;
5357 last
= skb_shinfo(skb
)->nr_frags
- 1;
5358 for (i
= 0; i
<= last
; i
++) {
5359 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5362 mapping
= sp
->dma_maps
[i
+ 1];
5364 tp
->tx_buffers
[entry
].skb
= NULL
;
5366 if (tg3_4g_overflow_test(mapping
, len
))
5367 would_hit_hwbug
= 1;
5369 if (tg3_40bit_overflow_test(tp
, mapping
, len
))
5370 would_hit_hwbug
= 1;
5372 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5373 tg3_set_txd(tp
, entry
, mapping
, len
,
5374 base_flags
, (i
== last
)|(mss
<< 1));
5376 tg3_set_txd(tp
, entry
, mapping
, len
,
5377 base_flags
, (i
== last
));
5379 entry
= NEXT_TX(entry
);
5383 if (would_hit_hwbug
) {
5384 u32 last_plus_one
= entry
;
5387 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5388 start
&= (TG3_TX_RING_SIZE
- 1);
5390 /* If the workaround fails due to memory/mapping
5391 * failure, silently drop this packet.
5393 if (tigon3_dma_hwbug_workaround(tp
, skb
, last_plus_one
,
5394 &start
, base_flags
, mss
))
5400 /* Packets are ready, update Tx producer idx local and on card. */
5401 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
5403 tp
->tx_prod
= entry
;
5404 if (unlikely(tg3_tx_avail(tp
) <= (MAX_SKB_FRAGS
+ 1))) {
5405 netif_stop_queue(dev
);
5406 if (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
))
5407 netif_wake_queue(tp
->dev
);
5413 dev
->trans_start
= jiffies
;
5415 return NETDEV_TX_OK
;
5418 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5423 if (new_mtu
> ETH_DATA_LEN
) {
5424 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5425 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5426 ethtool_op_set_tso(dev
, 0);
5429 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5431 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5432 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5433 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5437 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5439 struct tg3
*tp
= netdev_priv(dev
);
5442 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5445 if (!netif_running(dev
)) {
5446 /* We'll just catch it later when the
5449 tg3_set_mtu(dev
, tp
, new_mtu
);
5457 tg3_full_lock(tp
, 1);
5459 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5461 tg3_set_mtu(dev
, tp
, new_mtu
);
5463 err
= tg3_restart_hw(tp
, 0);
5466 tg3_netif_start(tp
);
5468 tg3_full_unlock(tp
);
5476 /* Free up pending packets in all rx/tx rings.
5478 * The chip has been shut down and the driver detached from
5479 * the networking, so no interrupts or new tx packets will
5480 * end up in the driver. tp->{tx,}lock is not held and we are not
5481 * in an interrupt context and thus may sleep.
5483 static void tg3_free_rings(struct tg3
*tp
)
5485 struct ring_info
*rxp
;
5488 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5489 rxp
= &tp
->rx_std_buffers
[i
];
5491 if (rxp
->skb
== NULL
)
5493 pci_unmap_single(tp
->pdev
,
5494 pci_unmap_addr(rxp
, mapping
),
5495 tp
->rx_pkt_buf_sz
- tp
->rx_offset
,
5496 PCI_DMA_FROMDEVICE
);
5497 dev_kfree_skb_any(rxp
->skb
);
5501 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5502 rxp
= &tp
->rx_jumbo_buffers
[i
];
5504 if (rxp
->skb
== NULL
)
5506 pci_unmap_single(tp
->pdev
,
5507 pci_unmap_addr(rxp
, mapping
),
5508 RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
,
5509 PCI_DMA_FROMDEVICE
);
5510 dev_kfree_skb_any(rxp
->skb
);
5514 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
5515 struct tx_ring_info
*txp
;
5516 struct sk_buff
*skb
;
5518 txp
= &tp
->tx_buffers
[i
];
5526 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5530 i
+= skb_shinfo(skb
)->nr_frags
+ 1;
5532 dev_kfree_skb_any(skb
);
5536 /* Initialize tx/rx rings for packet processing.
5538 * The chip has been shut down and the driver detached from
5539 * the networking, so no interrupts or new tx packets will
5540 * end up in the driver. tp->{tx,}lock are held and thus
5543 static int tg3_init_rings(struct tg3
*tp
)
5547 /* Free up all the SKBs. */
5550 /* Zero out all descriptors. */
5551 memset(tp
->rx_std
, 0, TG3_RX_RING_BYTES
);
5552 memset(tp
->rx_jumbo
, 0, TG3_RX_JUMBO_RING_BYTES
);
5553 memset(tp
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5554 memset(tp
->tx_ring
, 0, TG3_TX_RING_BYTES
);
5556 tp
->rx_pkt_buf_sz
= RX_PKT_BUF_SZ
;
5557 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
5558 (tp
->dev
->mtu
> ETH_DATA_LEN
))
5559 tp
->rx_pkt_buf_sz
= RX_JUMBO_PKT_BUF_SZ
;
5561 /* Initialize invariants of the rings, we only set this
5562 * stuff once. This works because the card does not
5563 * write into the rx buffer posting rings.
5565 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5566 struct tg3_rx_buffer_desc
*rxd
;
5568 rxd
= &tp
->rx_std
[i
];
5569 rxd
->idx_len
= (tp
->rx_pkt_buf_sz
- tp
->rx_offset
- 64)
5571 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
5572 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
5573 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5576 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5577 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5578 struct tg3_rx_buffer_desc
*rxd
;
5580 rxd
= &tp
->rx_jumbo
[i
];
5581 rxd
->idx_len
= (RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
- 64)
5583 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
5585 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
5586 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5590 /* Now allocate fresh SKBs for each rx ring. */
5591 for (i
= 0; i
< tp
->rx_pending
; i
++) {
5592 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_STD
, -1, i
) < 0) {
5593 printk(KERN_WARNING PFX
5594 "%s: Using a smaller RX standard ring, "
5595 "only %d out of %d buffers were allocated "
5597 tp
->dev
->name
, i
, tp
->rx_pending
);
5605 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5606 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
5607 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_JUMBO
,
5609 printk(KERN_WARNING PFX
5610 "%s: Using a smaller RX jumbo ring, "
5611 "only %d out of %d buffers were "
5612 "allocated successfully.\n",
5613 tp
->dev
->name
, i
, tp
->rx_jumbo_pending
);
5618 tp
->rx_jumbo_pending
= i
;
5627 * Must not be invoked with interrupt sources disabled and
5628 * the hardware shutdown down.
5630 static void tg3_free_consistent(struct tg3
*tp
)
5632 kfree(tp
->rx_std_buffers
);
5633 tp
->rx_std_buffers
= NULL
;
5635 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5636 tp
->rx_std
, tp
->rx_std_mapping
);
5640 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5641 tp
->rx_jumbo
, tp
->rx_jumbo_mapping
);
5642 tp
->rx_jumbo
= NULL
;
5645 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5646 tp
->rx_rcb
, tp
->rx_rcb_mapping
);
5650 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5651 tp
->tx_ring
, tp
->tx_desc_mapping
);
5654 if (tp
->hw_status
) {
5655 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
5656 tp
->hw_status
, tp
->status_mapping
);
5657 tp
->hw_status
= NULL
;
5660 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
5661 tp
->hw_stats
, tp
->stats_mapping
);
5662 tp
->hw_stats
= NULL
;
5667 * Must not be invoked with interrupt sources disabled and
5668 * the hardware shutdown down. Can sleep.
5670 static int tg3_alloc_consistent(struct tg3
*tp
)
5672 tp
->rx_std_buffers
= kzalloc((sizeof(struct ring_info
) *
5674 TG3_RX_JUMBO_RING_SIZE
)) +
5675 (sizeof(struct tx_ring_info
) *
5678 if (!tp
->rx_std_buffers
)
5681 tp
->rx_jumbo_buffers
= &tp
->rx_std_buffers
[TG3_RX_RING_SIZE
];
5682 tp
->tx_buffers
= (struct tx_ring_info
*)
5683 &tp
->rx_jumbo_buffers
[TG3_RX_JUMBO_RING_SIZE
];
5685 tp
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5686 &tp
->rx_std_mapping
);
5690 tp
->rx_jumbo
= pci_alloc_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5691 &tp
->rx_jumbo_mapping
);
5696 tp
->rx_rcb
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5697 &tp
->rx_rcb_mapping
);
5701 tp
->tx_ring
= pci_alloc_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5702 &tp
->tx_desc_mapping
);
5706 tp
->hw_status
= pci_alloc_consistent(tp
->pdev
,
5708 &tp
->status_mapping
);
5712 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
5713 sizeof(struct tg3_hw_stats
),
5714 &tp
->stats_mapping
);
5718 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5719 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5724 tg3_free_consistent(tp
);
5728 #define MAX_WAIT_CNT 1000
5730 /* To stop a block, clear the enable bit and poll till it
5731 * clears. tp->lock is held.
5733 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
5738 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5745 /* We can't enable/disable these bits of the
5746 * 5705/5750, just say success.
5759 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5762 if ((val
& enable_bit
) == 0)
5766 if (i
== MAX_WAIT_CNT
&& !silent
) {
5767 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
5768 "ofs=%lx enable_bit=%x\n",
5776 /* tp->lock is held. */
5777 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
5781 tg3_disable_ints(tp
);
5783 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
5784 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5787 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
5788 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
5789 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
5790 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
5791 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
5792 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
5794 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
5795 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
5796 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
5797 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
5798 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
5799 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
5800 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
5802 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
5803 tw32_f(MAC_MODE
, tp
->mac_mode
);
5806 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
5807 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5809 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5811 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
5814 if (i
>= MAX_WAIT_CNT
) {
5815 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
5816 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5817 tp
->dev
->name
, tr32(MAC_TX_MODE
));
5821 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
5822 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
5823 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
5825 tw32(FTQ_RESET
, 0xffffffff);
5826 tw32(FTQ_RESET
, 0x00000000);
5828 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
5829 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
5832 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5834 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5839 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
5844 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
5845 if (apedata
!= APE_SEG_SIG_MAGIC
)
5848 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
5849 if (!(apedata
& APE_FW_STATUS_READY
))
5852 /* Wait for up to 1 millisecond for APE to service previous event. */
5853 for (i
= 0; i
< 10; i
++) {
5854 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
5857 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
5859 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5860 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
5861 event
| APE_EVENT_STATUS_EVENT_PENDING
);
5863 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
5865 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5871 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5872 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
5875 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
5880 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
5884 case RESET_KIND_INIT
:
5885 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
5886 APE_HOST_SEG_SIG_MAGIC
);
5887 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
5888 APE_HOST_SEG_LEN_MAGIC
);
5889 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
5890 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
5891 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
5892 APE_HOST_DRIVER_ID_MAGIC
);
5893 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
5894 APE_HOST_BEHAV_NO_PHYLOCK
);
5896 event
= APE_EVENT_STATUS_STATE_START
;
5898 case RESET_KIND_SHUTDOWN
:
5899 /* With the interface we are currently using,
5900 * APE does not track driver state. Wiping
5901 * out the HOST SEGMENT SIGNATURE forces
5902 * the APE to assume OS absent status.
5904 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
5906 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
5908 case RESET_KIND_SUSPEND
:
5909 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
5915 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
5917 tg3_ape_send_event(tp
, event
);
5920 /* tp->lock is held. */
5921 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
5923 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
5924 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
5926 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
5928 case RESET_KIND_INIT
:
5929 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5933 case RESET_KIND_SHUTDOWN
:
5934 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5938 case RESET_KIND_SUSPEND
:
5939 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5948 if (kind
== RESET_KIND_INIT
||
5949 kind
== RESET_KIND_SUSPEND
)
5950 tg3_ape_driver_state_change(tp
, kind
);
5953 /* tp->lock is held. */
5954 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
5956 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
5958 case RESET_KIND_INIT
:
5959 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5960 DRV_STATE_START_DONE
);
5963 case RESET_KIND_SHUTDOWN
:
5964 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5965 DRV_STATE_UNLOAD_DONE
);
5973 if (kind
== RESET_KIND_SHUTDOWN
)
5974 tg3_ape_driver_state_change(tp
, kind
);
5977 /* tp->lock is held. */
5978 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
5980 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
5982 case RESET_KIND_INIT
:
5983 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5987 case RESET_KIND_SHUTDOWN
:
5988 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5992 case RESET_KIND_SUSPEND
:
5993 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6003 static int tg3_poll_fw(struct tg3
*tp
)
6008 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6009 /* Wait up to 20ms for init done. */
6010 for (i
= 0; i
< 200; i
++) {
6011 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6018 /* Wait for firmware initialization to complete. */
6019 for (i
= 0; i
< 100000; i
++) {
6020 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6021 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6026 /* Chip might not be fitted with firmware. Some Sun onboard
6027 * parts are configured like that. So don't signal the timeout
6028 * of the above loop as an error, but do report the lack of
6029 * running firmware once.
6032 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6033 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6035 printk(KERN_INFO PFX
"%s: No firmware running.\n",
6042 /* Save PCI command register before chip reset */
6043 static void tg3_save_pci_state(struct tg3
*tp
)
6045 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6048 /* Restore PCI state after chip reset */
6049 static void tg3_restore_pci_state(struct tg3
*tp
)
6053 /* Re-enable indirect register accesses. */
6054 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6055 tp
->misc_host_ctrl
);
6057 /* Set MAX PCI retry to zero. */
6058 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6059 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6060 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6061 val
|= PCISTATE_RETRY_SAME_DMA
;
6062 /* Allow reads and writes to the APE register and memory space. */
6063 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6064 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6065 PCISTATE_ALLOW_APE_SHMEM_WR
;
6066 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6068 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6070 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6071 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6072 pcie_set_readrq(tp
->pdev
, 4096);
6074 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6075 tp
->pci_cacheline_sz
);
6076 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6081 /* Make sure PCI-X relaxed ordering bit is clear. */
6082 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6085 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6087 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6088 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6092 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6094 /* Chip reset on 5780 will reset MSI enable bit,
6095 * so need to restore it.
6097 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6100 pci_read_config_word(tp
->pdev
,
6101 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6103 pci_write_config_word(tp
->pdev
,
6104 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6105 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6106 val
= tr32(MSGINT_MODE
);
6107 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6112 static void tg3_stop_fw(struct tg3
*);
6114 /* tp->lock is held. */
6115 static int tg3_chip_reset(struct tg3
*tp
)
6118 void (*write_op
)(struct tg3
*, u32
, u32
);
6125 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6127 /* No matching tg3_nvram_unlock() after this because
6128 * chip reset below will undo the nvram lock.
6130 tp
->nvram_lock_cnt
= 0;
6132 /* GRC_MISC_CFG core clock reset will clear the memory
6133 * enable bit in PCI register 4 and the MSI enable bit
6134 * on some chips, so we save relevant registers here.
6136 tg3_save_pci_state(tp
);
6138 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6139 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6140 tw32(GRC_FASTBOOT_PC
, 0);
6143 * We must avoid the readl() that normally takes place.
6144 * It locks machines, causes machine checks, and other
6145 * fun things. So, temporarily disable the 5701
6146 * hardware workaround, while we do the reset.
6148 write_op
= tp
->write32
;
6149 if (write_op
== tg3_write_flush_reg32
)
6150 tp
->write32
= tg3_write32
;
6152 /* Prevent the irq handler from reading or writing PCI registers
6153 * during chip reset when the memory enable bit in the PCI command
6154 * register may be cleared. The chip does not generate interrupt
6155 * at this time, but the irq handler may still be called due to irq
6156 * sharing or irqpoll.
6158 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6159 if (tp
->hw_status
) {
6160 tp
->hw_status
->status
= 0;
6161 tp
->hw_status
->status_tag
= 0;
6164 tp
->last_irq_tag
= 0;
6166 synchronize_irq(tp
->pdev
->irq
);
6169 val
= GRC_MISC_CFG_CORECLK_RESET
;
6171 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6172 if (tr32(0x7e2c) == 0x60) {
6175 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6176 tw32(GRC_MISC_CFG
, (1 << 29));
6181 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6182 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6183 tw32(GRC_VCPU_EXT_CTRL
,
6184 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6187 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6188 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6189 tw32(GRC_MISC_CFG
, val
);
6191 /* restore 5701 hardware bug workaround write method */
6192 tp
->write32
= write_op
;
6194 /* Unfortunately, we have to delay before the PCI read back.
6195 * Some 575X chips even will not respond to a PCI cfg access
6196 * when the reset command is given to the chip.
6198 * How do these hardware designers expect things to work
6199 * properly if the PCI write is posted for a long period
6200 * of time? It is always necessary to have some method by
6201 * which a register read back can occur to push the write
6202 * out which does the reset.
6204 * For most tg3 variants the trick below was working.
6209 /* Flush PCI posted writes. The normal MMIO registers
6210 * are inaccessible at this time so this is the only
6211 * way to make this reliably (actually, this is no longer
6212 * the case, see above). I tried to use indirect
6213 * register read/write but this upset some 5701 variants.
6215 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6219 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6220 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6224 /* Wait for link training to complete. */
6225 for (i
= 0; i
< 5000; i
++)
6228 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6229 pci_write_config_dword(tp
->pdev
, 0xc4,
6230 cfg_val
| (1 << 15));
6233 /* Set PCIE max payload size to 128 bytes and
6234 * clear the "no snoop" and "relaxed ordering" bits.
6236 pci_write_config_word(tp
->pdev
,
6237 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6240 pcie_set_readrq(tp
->pdev
, 4096);
6242 /* Clear error status */
6243 pci_write_config_word(tp
->pdev
,
6244 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6245 PCI_EXP_DEVSTA_CED
|
6246 PCI_EXP_DEVSTA_NFED
|
6247 PCI_EXP_DEVSTA_FED
|
6248 PCI_EXP_DEVSTA_URD
);
6251 tg3_restore_pci_state(tp
);
6253 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6256 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6257 val
= tr32(MEMARB_MODE
);
6258 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
6260 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
6262 tw32(0x5000, 0x400);
6265 tw32(GRC_MODE
, tp
->grc_mode
);
6267 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
6270 tw32(0xc4, val
| (1 << 15));
6273 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
6274 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6275 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
6276 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
6277 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
6278 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6281 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6282 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
6283 tw32_f(MAC_MODE
, tp
->mac_mode
);
6284 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6285 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
6286 tw32_f(MAC_MODE
, tp
->mac_mode
);
6287 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6288 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
6289 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
6290 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
6291 tw32_f(MAC_MODE
, tp
->mac_mode
);
6293 tw32_f(MAC_MODE
, 0);
6298 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
6300 err
= tg3_poll_fw(tp
);
6304 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
6305 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6308 tw32(0x7c00, val
| (1 << 25));
6311 /* Reprobe ASF enable state. */
6312 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
6313 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
6314 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
6315 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
6318 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
6319 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
6320 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
6321 tp
->last_event_jiffies
= jiffies
;
6322 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
6323 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
6330 /* tp->lock is held. */
6331 static void tg3_stop_fw(struct tg3
*tp
)
6333 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
6334 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
6335 /* Wait for RX cpu to ACK the previous event. */
6336 tg3_wait_for_event_ack(tp
);
6338 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
6340 tg3_generate_fw_event(tp
);
6342 /* Wait for RX cpu to ACK this event. */
6343 tg3_wait_for_event_ack(tp
);
6347 /* tp->lock is held. */
6348 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
6354 tg3_write_sig_pre_reset(tp
, kind
);
6356 tg3_abort_hw(tp
, silent
);
6357 err
= tg3_chip_reset(tp
);
6359 tg3_write_sig_legacy(tp
, kind
);
6360 tg3_write_sig_post_reset(tp
, kind
);
6368 #define RX_CPU_SCRATCH_BASE 0x30000
6369 #define RX_CPU_SCRATCH_SIZE 0x04000
6370 #define TX_CPU_SCRATCH_BASE 0x34000
6371 #define TX_CPU_SCRATCH_SIZE 0x04000
6373 /* tp->lock is held. */
6374 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
6378 BUG_ON(offset
== TX_CPU_BASE
&&
6379 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
6381 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6382 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
6384 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
6387 if (offset
== RX_CPU_BASE
) {
6388 for (i
= 0; i
< 10000; i
++) {
6389 tw32(offset
+ CPU_STATE
, 0xffffffff);
6390 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6391 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6395 tw32(offset
+ CPU_STATE
, 0xffffffff);
6396 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6399 for (i
= 0; i
< 10000; i
++) {
6400 tw32(offset
+ CPU_STATE
, 0xffffffff);
6401 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6402 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6408 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
6411 (offset
== RX_CPU_BASE
? "RX" : "TX"));
6415 /* Clear firmware's nvram arbitration. */
6416 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6417 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
6422 unsigned int fw_base
;
6423 unsigned int fw_len
;
6424 const __be32
*fw_data
;
6427 /* tp->lock is held. */
6428 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
6429 int cpu_scratch_size
, struct fw_info
*info
)
6431 int err
, lock_err
, i
;
6432 void (*write_op
)(struct tg3
*, u32
, u32
);
6434 if (cpu_base
== TX_CPU_BASE
&&
6435 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6436 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
6437 "TX cpu firmware on %s which is 5705.\n",
6442 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6443 write_op
= tg3_write_mem
;
6445 write_op
= tg3_write_indirect_reg32
;
6447 /* It is possible that bootcode is still loading at this point.
6448 * Get the nvram lock first before halting the cpu.
6450 lock_err
= tg3_nvram_lock(tp
);
6451 err
= tg3_halt_cpu(tp
, cpu_base
);
6453 tg3_nvram_unlock(tp
);
6457 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
6458 write_op(tp
, cpu_scratch_base
+ i
, 0);
6459 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6460 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
6461 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
6462 write_op(tp
, (cpu_scratch_base
+
6463 (info
->fw_base
& 0xffff) +
6465 be32_to_cpu(info
->fw_data
[i
]));
6473 /* tp->lock is held. */
6474 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
6476 struct fw_info info
;
6477 const __be32
*fw_data
;
6480 fw_data
= (void *)tp
->fw
->data
;
6482 /* Firmware blob starts with version numbers, followed by
6483 start address and length. We are setting complete length.
6484 length = end_address_of_bss - start_address_of_text.
6485 Remainder is the blob to be loaded contiguously
6486 from start address. */
6488 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6489 info
.fw_len
= tp
->fw
->size
- 12;
6490 info
.fw_data
= &fw_data
[3];
6492 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
6493 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
6498 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
6499 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
6504 /* Now startup only the RX cpu. */
6505 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6506 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6508 for (i
= 0; i
< 5; i
++) {
6509 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
6511 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6512 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
6513 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6517 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
6518 "to set RX CPU PC, is %08x should be %08x\n",
6519 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
6523 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6524 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
6529 /* 5705 needs a special version of the TSO firmware. */
6531 /* tp->lock is held. */
6532 static int tg3_load_tso_firmware(struct tg3
*tp
)
6534 struct fw_info info
;
6535 const __be32
*fw_data
;
6536 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
6539 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6542 fw_data
= (void *)tp
->fw
->data
;
6544 /* Firmware blob starts with version numbers, followed by
6545 start address and length. We are setting complete length.
6546 length = end_address_of_bss - start_address_of_text.
6547 Remainder is the blob to be loaded contiguously
6548 from start address. */
6550 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6551 cpu_scratch_size
= tp
->fw_len
;
6552 info
.fw_len
= tp
->fw
->size
- 12;
6553 info
.fw_data
= &fw_data
[3];
6555 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6556 cpu_base
= RX_CPU_BASE
;
6557 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
6559 cpu_base
= TX_CPU_BASE
;
6560 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
6561 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
6564 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
6565 cpu_scratch_base
, cpu_scratch_size
,
6570 /* Now startup the cpu. */
6571 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6572 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6574 for (i
= 0; i
< 5; i
++) {
6575 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
6577 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6578 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
6579 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6583 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
6584 "to set CPU PC, is %08x should be %08x\n",
6585 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
6589 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6590 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
6595 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
6597 struct tg3
*tp
= netdev_priv(dev
);
6598 struct sockaddr
*addr
= p
;
6599 int err
= 0, skip_mac_1
= 0;
6601 if (!is_valid_ether_addr(addr
->sa_data
))
6604 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6606 if (!netif_running(dev
))
6609 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6610 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
6612 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
6613 addr0_low
= tr32(MAC_ADDR_0_LOW
);
6614 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
6615 addr1_low
= tr32(MAC_ADDR_1_LOW
);
6617 /* Skip MAC addr 1 if ASF is using it. */
6618 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
6619 !(addr1_high
== 0 && addr1_low
== 0))
6622 spin_lock_bh(&tp
->lock
);
6623 __tg3_set_mac_addr(tp
, skip_mac_1
);
6624 spin_unlock_bh(&tp
->lock
);
6629 /* tp->lock is held. */
6630 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
6631 dma_addr_t mapping
, u32 maxlen_flags
,
6635 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6636 ((u64
) mapping
>> 32));
6638 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
6639 ((u64
) mapping
& 0xffffffff));
6641 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
6644 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6646 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
6650 static void __tg3_set_rx_mode(struct net_device
*);
6651 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
6653 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
6654 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
6655 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
6656 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
6657 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6658 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
6659 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
6661 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
6662 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
6663 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6664 u32 val
= ec
->stats_block_coalesce_usecs
;
6666 if (!netif_carrier_ok(tp
->dev
))
6669 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
6673 /* tp->lock is held. */
6674 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
6676 u32 val
, rdmac_mode
;
6679 tg3_disable_ints(tp
);
6683 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
6685 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
6686 tg3_abort_hw(tp
, 1);
6690 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
))
6693 err
= tg3_chip_reset(tp
);
6697 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
6699 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
6700 val
= tr32(TG3_CPMU_CTRL
);
6701 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
6702 tw32(TG3_CPMU_CTRL
, val
);
6704 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
6705 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
6706 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
6707 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
6709 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
6710 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
6711 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
6712 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
6714 val
= tr32(TG3_CPMU_HST_ACC
);
6715 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
6716 val
|= CPMU_HST_ACC_MACCLK_6_25
;
6717 tw32(TG3_CPMU_HST_ACC
, val
);
6720 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6721 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
6722 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
6723 PCIE_PWR_MGMT_L1_THRESH_4MS
;
6724 tw32(PCIE_PWR_MGMT_THRESH
, val
);
6727 /* This works around an issue with Athlon chipsets on
6728 * B3 tigon3 silicon. This bit has no effect on any
6729 * other revision. But do not set this on PCI Express
6730 * chips and don't even touch the clocks if the CPMU is present.
6732 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
6733 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
6734 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
6735 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6738 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6739 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
6740 val
= tr32(TG3PCI_PCISTATE
);
6741 val
|= PCISTATE_RETRY_SAME_DMA
;
6742 tw32(TG3PCI_PCISTATE
, val
);
6745 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6746 /* Allow reads and writes to the
6747 * APE register and memory space.
6749 val
= tr32(TG3PCI_PCISTATE
);
6750 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6751 PCISTATE_ALLOW_APE_SHMEM_WR
;
6752 tw32(TG3PCI_PCISTATE
, val
);
6755 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
6756 /* Enable some hw fixes. */
6757 val
= tr32(TG3PCI_MSI_DATA
);
6758 val
|= (1 << 26) | (1 << 28) | (1 << 29);
6759 tw32(TG3PCI_MSI_DATA
, val
);
6762 /* Descriptor ring init may make accesses to the
6763 * NIC SRAM area to setup the TX descriptors, so we
6764 * can only do this after the hardware has been
6765 * successfully reset.
6767 err
= tg3_init_rings(tp
);
6771 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
6772 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
6773 /* This value is determined during the probe time DMA
6774 * engine test, tg3_test_dma.
6776 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
6779 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
6780 GRC_MODE_4X_NIC_SEND_RINGS
|
6781 GRC_MODE_NO_TX_PHDR_CSUM
|
6782 GRC_MODE_NO_RX_PHDR_CSUM
);
6783 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
6785 /* Pseudo-header checksum is done by hardware logic and not
6786 * the offload processers, so make the chip do the pseudo-
6787 * header checksums on receive. For transmit it is more
6788 * convenient to do the pseudo-header checksum in software
6789 * as Linux does that on transmit for us in all cases.
6791 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
6795 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
6797 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6798 val
= tr32(GRC_MISC_CFG
);
6800 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
6801 tw32(GRC_MISC_CFG
, val
);
6803 /* Initialize MBUF/DESC pool. */
6804 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
6806 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
6807 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
6808 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
6809 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
6811 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
6812 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
6813 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
6815 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
6818 fw_len
= tp
->fw_len
;
6819 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
6820 tw32(BUFMGR_MB_POOL_ADDR
,
6821 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
6822 tw32(BUFMGR_MB_POOL_SIZE
,
6823 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
6826 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
6827 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
6828 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
6829 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
6830 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
6831 tw32(BUFMGR_MB_HIGH_WATER
,
6832 tp
->bufmgr_config
.mbuf_high_water
);
6834 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
6835 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
6836 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
6837 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
6838 tw32(BUFMGR_MB_HIGH_WATER
,
6839 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
6841 tw32(BUFMGR_DMA_LOW_WATER
,
6842 tp
->bufmgr_config
.dma_low_water
);
6843 tw32(BUFMGR_DMA_HIGH_WATER
,
6844 tp
->bufmgr_config
.dma_high_water
);
6846 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
6847 for (i
= 0; i
< 2000; i
++) {
6848 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
6853 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
6858 /* Setup replenish threshold. */
6859 val
= tp
->rx_pending
/ 8;
6862 else if (val
> tp
->rx_std_max_post
)
6863 val
= tp
->rx_std_max_post
;
6864 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6865 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
6866 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
6868 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
6869 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
6872 tw32(RCVBDI_STD_THRESH
, val
);
6874 /* Initialize TG3_BDINFO's at:
6875 * RCVDBDI_STD_BD: standard eth size rx ring
6876 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6877 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6880 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6881 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6882 * ring attribute flags
6883 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6885 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6886 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6888 * The size of each ring is fixed in the firmware, but the location is
6891 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6892 ((u64
) tp
->rx_std_mapping
>> 32));
6893 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6894 ((u64
) tp
->rx_std_mapping
& 0xffffffff));
6895 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
6896 NIC_SRAM_RX_BUFFER_DESC
);
6898 /* Don't even try to program the JUMBO/MINI buffer descriptor
6901 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6902 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6903 RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6905 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6906 RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6908 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6909 BDINFO_FLAGS_DISABLED
);
6911 /* Setup replenish threshold. */
6912 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
6914 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
6915 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6916 ((u64
) tp
->rx_jumbo_mapping
>> 32));
6917 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6918 ((u64
) tp
->rx_jumbo_mapping
& 0xffffffff));
6919 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6920 RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6921 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
6922 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
6924 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6925 BDINFO_FLAGS_DISABLED
);
6930 /* There is only one send ring on 5705/5750, no need to explicitly
6931 * disable the others.
6933 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6934 /* Clear out send RCB ring in SRAM. */
6935 for (i
= NIC_SRAM_SEND_RCB
; i
< NIC_SRAM_RCV_RET_RCB
; i
+= TG3_BDINFO_SIZE
)
6936 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
6937 BDINFO_FLAGS_DISABLED
);
6942 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6943 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6945 tg3_set_bdinfo(tp
, NIC_SRAM_SEND_RCB
,
6946 tp
->tx_desc_mapping
,
6947 (TG3_TX_RING_SIZE
<<
6948 BDINFO_FLAGS_MAXLEN_SHIFT
),
6949 NIC_SRAM_TX_BUFFER_DESC
);
6951 /* There is only one receive return ring on 5705/5750, no need
6952 * to explicitly disable the others.
6954 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6955 for (i
= NIC_SRAM_RCV_RET_RCB
; i
< NIC_SRAM_STATS_BLK
;
6956 i
+= TG3_BDINFO_SIZE
) {
6957 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
6958 BDINFO_FLAGS_DISABLED
);
6963 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6965 tg3_set_bdinfo(tp
, NIC_SRAM_RCV_RET_RCB
,
6967 (TG3_RX_RCB_RING_SIZE(tp
) <<
6968 BDINFO_FLAGS_MAXLEN_SHIFT
),
6971 tp
->rx_std_ptr
= tp
->rx_pending
;
6972 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
6975 tp
->rx_jumbo_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
6976 tp
->rx_jumbo_pending
: 0;
6977 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
6980 /* Initialize MAC address and backoff seed. */
6981 __tg3_set_mac_addr(tp
, 0);
6983 /* MTU + ethernet header + FCS + optional VLAN tag */
6984 tw32(MAC_RX_MTU_SIZE
,
6985 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
6987 /* The slot time is changed by tg3_setup_phy if we
6988 * run at gigabit with half duplex.
6990 tw32(MAC_TX_LENGTHS
,
6991 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
6992 (6 << TX_LENGTHS_IPG_SHIFT
) |
6993 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
6995 /* Receive rules. */
6996 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
6997 tw32(RCVLPC_CONFIG
, 0x0181);
6999 /* Calculate RDMAC_MODE setting early, we need it to determine
7000 * the RCVLPC_STATE_ENABLE mask.
7002 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7003 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7004 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7005 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7006 RDMAC_MODE_LNGREAD_ENAB
);
7008 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7009 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7010 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7011 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7012 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7013 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7015 /* If statement applies to 5705 and 5750 PCI devices only */
7016 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7017 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7018 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7019 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7020 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7021 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7022 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7023 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7024 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7028 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7029 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7031 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7032 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
7034 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7035 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7036 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
7038 /* Receive/send statistics. */
7039 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7040 val
= tr32(RCVLPC_STATS_ENABLE
);
7041 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
7042 tw32(RCVLPC_STATS_ENABLE
, val
);
7043 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
7044 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7045 val
= tr32(RCVLPC_STATS_ENABLE
);
7046 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
7047 tw32(RCVLPC_STATS_ENABLE
, val
);
7049 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
7051 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
7052 tw32(SNDDATAI_STATSENAB
, 0xffffff);
7053 tw32(SNDDATAI_STATSCTRL
,
7054 (SNDDATAI_SCTRL_ENABLE
|
7055 SNDDATAI_SCTRL_FASTUPD
));
7057 /* Setup host coalescing engine. */
7058 tw32(HOSTCC_MODE
, 0);
7059 for (i
= 0; i
< 2000; i
++) {
7060 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
7065 __tg3_set_coalesce(tp
, &tp
->coal
);
7067 /* set status block DMA address */
7068 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7069 ((u64
) tp
->status_mapping
>> 32));
7070 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7071 ((u64
) tp
->status_mapping
& 0xffffffff));
7073 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7074 /* Status/statistics block address. See tg3_timer,
7075 * the tg3_periodic_fetch_stats call there, and
7076 * tg3_get_stats to see how this works for 5705/5750 chips.
7078 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7079 ((u64
) tp
->stats_mapping
>> 32));
7080 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7081 ((u64
) tp
->stats_mapping
& 0xffffffff));
7082 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
7083 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
7086 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
7088 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
7089 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
7090 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7091 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
7093 /* Clear statistics/status block in chip, and status block in ram. */
7094 for (i
= NIC_SRAM_STATS_BLK
;
7095 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
7097 tg3_write_mem(tp
, i
, 0);
7100 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7102 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7103 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
7104 /* reset to prevent losing 1st rx packet intermittently */
7105 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7109 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7110 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
7113 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
7114 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
7115 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7116 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7117 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
7118 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
7119 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
7122 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7123 * If TG3_FLG2_IS_NIC is zero, we should read the
7124 * register to preserve the GPIO settings for LOMs. The GPIOs,
7125 * whether used as inputs or outputs, are set by boot code after
7128 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
7131 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
7132 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
7133 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
7135 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7136 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
7137 GRC_LCLCTRL_GPIO_OUTPUT3
;
7139 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
7140 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
7142 tp
->grc_local_ctrl
&= ~gpio_mask
;
7143 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
7145 /* GPIO1 must be driven high for eeprom write protect */
7146 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
7147 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
7148 GRC_LCLCTRL_GPIO_OUTPUT1
);
7150 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7153 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0);
7155 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7156 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
7160 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
7161 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
7162 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
7163 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
7164 WDMAC_MODE_LNGREAD_ENAB
);
7166 /* If statement applies to 5705 and 5750 PCI devices only */
7167 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7168 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7169 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7170 if ((tp
->tg3_flags
& TG3_FLG2_TSO_CAPABLE
) &&
7171 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
7172 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
7174 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7175 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7176 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
7177 val
|= WDMAC_MODE_RX_ACCEL
;
7181 /* Enable host coalescing bug fix */
7182 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7183 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
7185 tw32_f(WDMAC_MODE
, val
);
7188 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7191 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7193 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
7194 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
7195 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7196 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
7197 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
7198 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7200 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7204 tw32_f(RDMAC_MODE
, rdmac_mode
);
7207 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
7208 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7209 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
7211 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
7213 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
7215 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
7217 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
7218 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
7219 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
7220 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
7221 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7222 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
7223 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
7224 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
7226 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7227 err
= tg3_load_5701_a0_firmware_fix(tp
);
7232 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7233 err
= tg3_load_tso_firmware(tp
);
7238 tp
->tx_mode
= TX_MODE_ENABLE
;
7239 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
7242 tp
->rx_mode
= RX_MODE_ENABLE
;
7243 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7244 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
7246 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7249 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
7251 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
7252 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7253 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7256 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7259 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7260 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
7261 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
7262 /* Set drive transmission level to 1.2V */
7263 /* only if the signal pre-emphasis bit is not set */
7264 val
= tr32(MAC_SERDES_CFG
);
7267 tw32(MAC_SERDES_CFG
, val
);
7269 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
7270 tw32(MAC_SERDES_CFG
, 0x616000);
7273 /* Prevent chip from dropping frames when flow control
7276 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
7278 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
7279 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
7280 /* Use hardware link auto-negotiation */
7281 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
7284 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
7285 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
7288 tmp
= tr32(SERDES_RX_CTRL
);
7289 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
7290 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
7291 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
7292 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7295 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
7296 if (tp
->link_config
.phy_is_low_power
) {
7297 tp
->link_config
.phy_is_low_power
= 0;
7298 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
7299 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
7300 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
7303 err
= tg3_setup_phy(tp
, 0);
7307 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7308 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
) {
7311 /* Clear CRC stats. */
7312 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
7313 tg3_writephy(tp
, MII_TG3_TEST1
,
7314 tmp
| MII_TG3_TEST1_CRC_EN
);
7315 tg3_readphy(tp
, 0x14, &tmp
);
7320 __tg3_set_rx_mode(tp
->dev
);
7322 /* Initialize receive rules. */
7323 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
7324 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7325 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
7326 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7328 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7329 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
7333 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
7337 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
7339 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
7341 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
7343 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
7345 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
7347 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
7349 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
7351 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
7353 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
7355 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
7357 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
7359 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
7361 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7363 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7371 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7372 /* Write our heartbeat update interval to APE. */
7373 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
7374 APE_HOST_HEARTBEAT_INT_DISABLE
);
7376 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
7381 /* Called at device open time to get the chip ready for
7382 * packet processing. Invoked with tp->lock held.
7384 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
7386 tg3_switch_clocks(tp
);
7388 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
7390 return tg3_reset_hw(tp
, reset_phy
);
7393 #define TG3_STAT_ADD32(PSTAT, REG) \
7394 do { u32 __val = tr32(REG); \
7395 (PSTAT)->low += __val; \
7396 if ((PSTAT)->low < __val) \
7397 (PSTAT)->high += 1; \
7400 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
7402 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
7404 if (!netif_carrier_ok(tp
->dev
))
7407 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
7408 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
7409 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
7410 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
7411 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
7412 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
7413 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
7414 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
7415 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
7416 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
7417 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
7418 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
7419 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
7421 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
7422 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
7423 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
7424 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
7425 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
7426 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
7427 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
7428 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
7429 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
7430 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
7431 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
7432 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
7433 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
7434 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
7436 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
7437 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
7438 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
7441 static void tg3_timer(unsigned long __opaque
)
7443 struct tg3
*tp
= (struct tg3
*) __opaque
;
7448 spin_lock(&tp
->lock
);
7450 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7451 /* All of this garbage is because when using non-tagged
7452 * IRQ status the mailbox/status_block protocol the chip
7453 * uses with the cpu is race prone.
7455 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
) {
7456 tw32(GRC_LOCAL_CTRL
,
7457 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
7459 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7460 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
7463 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
7464 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
7465 spin_unlock(&tp
->lock
);
7466 schedule_work(&tp
->reset_task
);
7471 /* This part only runs once per second. */
7472 if (!--tp
->timer_counter
) {
7473 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7474 tg3_periodic_fetch_stats(tp
);
7476 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
7480 mac_stat
= tr32(MAC_STATUS
);
7483 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
7484 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
7486 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
7490 tg3_setup_phy(tp
, 0);
7491 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
7492 u32 mac_stat
= tr32(MAC_STATUS
);
7495 if (netif_carrier_ok(tp
->dev
) &&
7496 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
7499 if (! netif_carrier_ok(tp
->dev
) &&
7500 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
7501 MAC_STATUS_SIGNAL_DET
))) {
7505 if (!tp
->serdes_counter
) {
7508 ~MAC_MODE_PORT_MODE_MASK
));
7510 tw32_f(MAC_MODE
, tp
->mac_mode
);
7513 tg3_setup_phy(tp
, 0);
7515 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
7516 tg3_serdes_parallel_detect(tp
);
7518 tp
->timer_counter
= tp
->timer_multiplier
;
7521 /* Heartbeat is only sent once every 2 seconds.
7523 * The heartbeat is to tell the ASF firmware that the host
7524 * driver is still alive. In the event that the OS crashes,
7525 * ASF needs to reset the hardware to free up the FIFO space
7526 * that may be filled with rx packets destined for the host.
7527 * If the FIFO is full, ASF will no longer function properly.
7529 * Unintended resets have been reported on real time kernels
7530 * where the timer doesn't run on time. Netpoll will also have
7533 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7534 * to check the ring condition when the heartbeat is expiring
7535 * before doing the reset. This will prevent most unintended
7538 if (!--tp
->asf_counter
) {
7539 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7540 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7541 tg3_wait_for_event_ack(tp
);
7543 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
7544 FWCMD_NICDRV_ALIVE3
);
7545 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
7546 /* 5 seconds timeout */
7547 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 5);
7549 tg3_generate_fw_event(tp
);
7551 tp
->asf_counter
= tp
->asf_multiplier
;
7554 spin_unlock(&tp
->lock
);
7557 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7558 add_timer(&tp
->timer
);
7561 static int tg3_request_irq(struct tg3
*tp
)
7564 unsigned long flags
;
7565 struct net_device
*dev
= tp
->dev
;
7567 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7569 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
7571 flags
= IRQF_SAMPLE_RANDOM
;
7574 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7575 fn
= tg3_interrupt_tagged
;
7576 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
7578 return (request_irq(tp
->pdev
->irq
, fn
, flags
, dev
->name
, dev
));
7581 static int tg3_test_interrupt(struct tg3
*tp
)
7583 struct net_device
*dev
= tp
->dev
;
7584 int err
, i
, intr_ok
= 0;
7586 if (!netif_running(dev
))
7589 tg3_disable_ints(tp
);
7591 free_irq(tp
->pdev
->irq
, dev
);
7593 err
= request_irq(tp
->pdev
->irq
, tg3_test_isr
,
7594 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, dev
);
7598 tp
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
7599 tg3_enable_ints(tp
);
7601 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7604 for (i
= 0; i
< 5; i
++) {
7605 u32 int_mbox
, misc_host_ctrl
;
7607 int_mbox
= tr32_mailbox(MAILBOX_INTERRUPT_0
+
7609 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
7611 if ((int_mbox
!= 0) ||
7612 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
7620 tg3_disable_ints(tp
);
7622 free_irq(tp
->pdev
->irq
, dev
);
7624 err
= tg3_request_irq(tp
);
7635 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7636 * successfully restored
7638 static int tg3_test_msi(struct tg3
*tp
)
7640 struct net_device
*dev
= tp
->dev
;
7644 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
7647 /* Turn off SERR reporting in case MSI terminates with Master
7650 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7651 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
7652 pci_cmd
& ~PCI_COMMAND_SERR
);
7654 err
= tg3_test_interrupt(tp
);
7656 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
7661 /* other failures */
7665 /* MSI test failed, go back to INTx mode */
7666 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
7667 "switching to INTx mode. Please report this failure to "
7668 "the PCI maintainer and include system chipset information.\n",
7671 free_irq(tp
->pdev
->irq
, dev
);
7672 pci_disable_msi(tp
->pdev
);
7674 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7676 err
= tg3_request_irq(tp
);
7680 /* Need to reset the chip because the MSI cycle may have terminated
7681 * with Master Abort.
7683 tg3_full_lock(tp
, 1);
7685 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7686 err
= tg3_init_hw(tp
, 1);
7688 tg3_full_unlock(tp
);
7691 free_irq(tp
->pdev
->irq
, dev
);
7696 static int tg3_request_firmware(struct tg3
*tp
)
7698 const __be32
*fw_data
;
7700 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
7701 printk(KERN_ERR
"%s: Failed to load firmware \"%s\"\n",
7702 tp
->dev
->name
, tp
->fw_needed
);
7706 fw_data
= (void *)tp
->fw
->data
;
7708 /* Firmware blob starts with version numbers, followed by
7709 * start address and _full_ length including BSS sections
7710 * (which must be longer than the actual data, of course
7713 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
7714 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
7715 printk(KERN_ERR
"%s: bogus length %d in \"%s\"\n",
7716 tp
->dev
->name
, tp
->fw_len
, tp
->fw_needed
);
7717 release_firmware(tp
->fw
);
7722 /* We no longer need firmware; we have it. */
7723 tp
->fw_needed
= NULL
;
7727 static int tg3_open(struct net_device
*dev
)
7729 struct tg3
*tp
= netdev_priv(dev
);
7732 if (tp
->fw_needed
) {
7733 err
= tg3_request_firmware(tp
);
7734 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7738 printk(KERN_WARNING
"%s: TSO capability disabled.\n",
7740 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
7741 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7742 printk(KERN_NOTICE
"%s: TSO capability restored.\n",
7744 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
7748 netif_carrier_off(tp
->dev
);
7750 err
= tg3_set_power_state(tp
, PCI_D0
);
7754 tg3_full_lock(tp
, 0);
7756 tg3_disable_ints(tp
);
7757 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
7759 tg3_full_unlock(tp
);
7761 /* The placement of this call is tied
7762 * to the setup and use of Host TX descriptors.
7764 err
= tg3_alloc_consistent(tp
);
7768 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) {
7769 /* All MSI supporting chips should support tagged
7770 * status. Assert that this is the case.
7772 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7773 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
7774 "Not using MSI.\n", tp
->dev
->name
);
7775 } else if (pci_enable_msi(tp
->pdev
) == 0) {
7778 msi_mode
= tr32(MSGINT_MODE
);
7779 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
7780 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
7783 err
= tg3_request_irq(tp
);
7786 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7787 pci_disable_msi(tp
->pdev
);
7788 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7790 tg3_free_consistent(tp
);
7794 napi_enable(&tp
->napi
);
7796 tg3_full_lock(tp
, 0);
7798 err
= tg3_init_hw(tp
, 1);
7800 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7803 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7804 tp
->timer_offset
= HZ
;
7806 tp
->timer_offset
= HZ
/ 10;
7808 BUG_ON(tp
->timer_offset
> HZ
);
7809 tp
->timer_counter
= tp
->timer_multiplier
=
7810 (HZ
/ tp
->timer_offset
);
7811 tp
->asf_counter
= tp
->asf_multiplier
=
7812 ((HZ
/ tp
->timer_offset
) * 2);
7814 init_timer(&tp
->timer
);
7815 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7816 tp
->timer
.data
= (unsigned long) tp
;
7817 tp
->timer
.function
= tg3_timer
;
7820 tg3_full_unlock(tp
);
7823 napi_disable(&tp
->napi
);
7824 free_irq(tp
->pdev
->irq
, dev
);
7825 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7826 pci_disable_msi(tp
->pdev
);
7827 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7829 tg3_free_consistent(tp
);
7833 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7834 err
= tg3_test_msi(tp
);
7837 tg3_full_lock(tp
, 0);
7839 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7840 pci_disable_msi(tp
->pdev
);
7841 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7843 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7845 tg3_free_consistent(tp
);
7847 tg3_full_unlock(tp
);
7849 napi_disable(&tp
->napi
);
7854 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7855 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
) {
7856 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
7858 tw32(PCIE_TRANSACTION_CFG
,
7859 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
7866 tg3_full_lock(tp
, 0);
7868 add_timer(&tp
->timer
);
7869 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
7870 tg3_enable_ints(tp
);
7872 tg3_full_unlock(tp
);
7874 netif_start_queue(dev
);
7880 /*static*/ void tg3_dump_state(struct tg3
*tp
)
7882 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
7886 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
7887 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
7888 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7892 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7893 tr32(MAC_MODE
), tr32(MAC_STATUS
));
7894 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7895 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
7896 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7897 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
7898 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7899 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
7901 /* Send data initiator control block */
7902 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7903 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
7904 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7905 tr32(SNDDATAI_STATSCTRL
));
7907 /* Send data completion control block */
7908 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
7910 /* Send BD ring selector block */
7911 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7912 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
7914 /* Send BD initiator control block */
7915 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7916 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
7918 /* Send BD completion control block */
7919 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
7921 /* Receive list placement control block */
7922 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7923 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
7924 printk(" RCVLPC_STATSCTRL[%08x]\n",
7925 tr32(RCVLPC_STATSCTRL
));
7927 /* Receive data and receive BD initiator control block */
7928 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7929 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
7931 /* Receive data completion control block */
7932 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7935 /* Receive BD initiator control block */
7936 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7937 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
7939 /* Receive BD completion control block */
7940 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7941 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
7943 /* Receive list selector control block */
7944 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7945 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
7947 /* Mbuf cluster free block */
7948 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7949 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
7951 /* Host coalescing control block */
7952 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7953 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
7954 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7955 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7956 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
7957 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7958 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7959 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
7960 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7961 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
7962 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7963 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
7965 /* Memory arbiter control block */
7966 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7967 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
7969 /* Buffer manager control block */
7970 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7971 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
7972 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7973 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
7974 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7975 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7976 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
7977 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
7979 /* Read DMA control block */
7980 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7981 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
7983 /* Write DMA control block */
7984 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7985 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
7987 /* DMA completion block */
7988 printk("DEBUG: DMAC_MODE[%08x]\n",
7992 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7993 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
7994 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7995 tr32(GRC_LOCAL_CTRL
));
7998 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7999 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
8000 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
8001 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
8002 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
8003 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8004 tr32(RCVDBDI_STD_BD
+ 0x0),
8005 tr32(RCVDBDI_STD_BD
+ 0x4),
8006 tr32(RCVDBDI_STD_BD
+ 0x8),
8007 tr32(RCVDBDI_STD_BD
+ 0xc));
8008 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8009 tr32(RCVDBDI_MINI_BD
+ 0x0),
8010 tr32(RCVDBDI_MINI_BD
+ 0x4),
8011 tr32(RCVDBDI_MINI_BD
+ 0x8),
8012 tr32(RCVDBDI_MINI_BD
+ 0xc));
8014 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
8015 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
8016 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
8017 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
8018 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8019 val32
, val32_2
, val32_3
, val32_4
);
8021 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
8022 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
8023 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
8024 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
8025 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8026 val32
, val32_2
, val32_3
, val32_4
);
8028 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
8029 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
8030 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
8031 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
8032 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
8033 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8034 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
8036 /* SW status block */
8037 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8038 tp
->hw_status
->status
,
8039 tp
->hw_status
->status_tag
,
8040 tp
->hw_status
->rx_jumbo_consumer
,
8041 tp
->hw_status
->rx_consumer
,
8042 tp
->hw_status
->rx_mini_consumer
,
8043 tp
->hw_status
->idx
[0].rx_producer
,
8044 tp
->hw_status
->idx
[0].tx_consumer
);
8046 /* SW statistics block */
8047 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8048 ((u32
*)tp
->hw_stats
)[0],
8049 ((u32
*)tp
->hw_stats
)[1],
8050 ((u32
*)tp
->hw_stats
)[2],
8051 ((u32
*)tp
->hw_stats
)[3]);
8054 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8055 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
8056 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
8057 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
8058 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
8060 /* NIC side send descriptors. */
8061 for (i
= 0; i
< 6; i
++) {
8064 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
8065 + (i
* sizeof(struct tg3_tx_buffer_desc
));
8066 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8068 readl(txd
+ 0x0), readl(txd
+ 0x4),
8069 readl(txd
+ 0x8), readl(txd
+ 0xc));
8072 /* NIC side RX descriptors. */
8073 for (i
= 0; i
< 6; i
++) {
8076 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
8077 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8078 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8080 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8081 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8082 rxd
+= (4 * sizeof(u32
));
8083 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8085 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8086 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8089 for (i
= 0; i
< 6; i
++) {
8092 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
8093 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8094 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8096 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8097 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8098 rxd
+= (4 * sizeof(u32
));
8099 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8101 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8102 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8107 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
8108 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
8110 static int tg3_close(struct net_device
*dev
)
8112 struct tg3
*tp
= netdev_priv(dev
);
8114 napi_disable(&tp
->napi
);
8115 cancel_work_sync(&tp
->reset_task
);
8117 netif_stop_queue(dev
);
8119 del_timer_sync(&tp
->timer
);
8121 tg3_full_lock(tp
, 1);
8126 tg3_disable_ints(tp
);
8128 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8130 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8132 tg3_full_unlock(tp
);
8134 free_irq(tp
->pdev
->irq
, dev
);
8135 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8136 pci_disable_msi(tp
->pdev
);
8137 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8140 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
8141 sizeof(tp
->net_stats_prev
));
8142 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
8143 sizeof(tp
->estats_prev
));
8145 tg3_free_consistent(tp
);
8147 tg3_set_power_state(tp
, PCI_D3hot
);
8149 netif_carrier_off(tp
->dev
);
8154 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
8158 #if (BITS_PER_LONG == 32)
8161 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8166 static inline u64
get_estat64(tg3_stat64_t
*val
)
8168 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8171 static unsigned long calc_crc_errors(struct tg3
*tp
)
8173 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8175 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8176 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8177 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
8180 spin_lock_bh(&tp
->lock
);
8181 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
8182 tg3_writephy(tp
, MII_TG3_TEST1
,
8183 val
| MII_TG3_TEST1_CRC_EN
);
8184 tg3_readphy(tp
, 0x14, &val
);
8187 spin_unlock_bh(&tp
->lock
);
8189 tp
->phy_crc_errors
+= val
;
8191 return tp
->phy_crc_errors
;
8194 return get_stat64(&hw_stats
->rx_fcs_errors
);
8197 #define ESTAT_ADD(member) \
8198 estats->member = old_estats->member + \
8199 get_estat64(&hw_stats->member)
8201 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
8203 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
8204 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
8205 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8210 ESTAT_ADD(rx_octets
);
8211 ESTAT_ADD(rx_fragments
);
8212 ESTAT_ADD(rx_ucast_packets
);
8213 ESTAT_ADD(rx_mcast_packets
);
8214 ESTAT_ADD(rx_bcast_packets
);
8215 ESTAT_ADD(rx_fcs_errors
);
8216 ESTAT_ADD(rx_align_errors
);
8217 ESTAT_ADD(rx_xon_pause_rcvd
);
8218 ESTAT_ADD(rx_xoff_pause_rcvd
);
8219 ESTAT_ADD(rx_mac_ctrl_rcvd
);
8220 ESTAT_ADD(rx_xoff_entered
);
8221 ESTAT_ADD(rx_frame_too_long_errors
);
8222 ESTAT_ADD(rx_jabbers
);
8223 ESTAT_ADD(rx_undersize_packets
);
8224 ESTAT_ADD(rx_in_length_errors
);
8225 ESTAT_ADD(rx_out_length_errors
);
8226 ESTAT_ADD(rx_64_or_less_octet_packets
);
8227 ESTAT_ADD(rx_65_to_127_octet_packets
);
8228 ESTAT_ADD(rx_128_to_255_octet_packets
);
8229 ESTAT_ADD(rx_256_to_511_octet_packets
);
8230 ESTAT_ADD(rx_512_to_1023_octet_packets
);
8231 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
8232 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
8233 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
8234 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
8235 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
8237 ESTAT_ADD(tx_octets
);
8238 ESTAT_ADD(tx_collisions
);
8239 ESTAT_ADD(tx_xon_sent
);
8240 ESTAT_ADD(tx_xoff_sent
);
8241 ESTAT_ADD(tx_flow_control
);
8242 ESTAT_ADD(tx_mac_errors
);
8243 ESTAT_ADD(tx_single_collisions
);
8244 ESTAT_ADD(tx_mult_collisions
);
8245 ESTAT_ADD(tx_deferred
);
8246 ESTAT_ADD(tx_excessive_collisions
);
8247 ESTAT_ADD(tx_late_collisions
);
8248 ESTAT_ADD(tx_collide_2times
);
8249 ESTAT_ADD(tx_collide_3times
);
8250 ESTAT_ADD(tx_collide_4times
);
8251 ESTAT_ADD(tx_collide_5times
);
8252 ESTAT_ADD(tx_collide_6times
);
8253 ESTAT_ADD(tx_collide_7times
);
8254 ESTAT_ADD(tx_collide_8times
);
8255 ESTAT_ADD(tx_collide_9times
);
8256 ESTAT_ADD(tx_collide_10times
);
8257 ESTAT_ADD(tx_collide_11times
);
8258 ESTAT_ADD(tx_collide_12times
);
8259 ESTAT_ADD(tx_collide_13times
);
8260 ESTAT_ADD(tx_collide_14times
);
8261 ESTAT_ADD(tx_collide_15times
);
8262 ESTAT_ADD(tx_ucast_packets
);
8263 ESTAT_ADD(tx_mcast_packets
);
8264 ESTAT_ADD(tx_bcast_packets
);
8265 ESTAT_ADD(tx_carrier_sense_errors
);
8266 ESTAT_ADD(tx_discards
);
8267 ESTAT_ADD(tx_errors
);
8269 ESTAT_ADD(dma_writeq_full
);
8270 ESTAT_ADD(dma_write_prioq_full
);
8271 ESTAT_ADD(rxbds_empty
);
8272 ESTAT_ADD(rx_discards
);
8273 ESTAT_ADD(rx_errors
);
8274 ESTAT_ADD(rx_threshold_hit
);
8276 ESTAT_ADD(dma_readq_full
);
8277 ESTAT_ADD(dma_read_prioq_full
);
8278 ESTAT_ADD(tx_comp_queue_full
);
8280 ESTAT_ADD(ring_set_send_prod_index
);
8281 ESTAT_ADD(ring_status_update
);
8282 ESTAT_ADD(nic_irqs
);
8283 ESTAT_ADD(nic_avoided_irqs
);
8284 ESTAT_ADD(nic_tx_threshold_hit
);
8289 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
8291 struct tg3
*tp
= netdev_priv(dev
);
8292 struct net_device_stats
*stats
= &tp
->net_stats
;
8293 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
8294 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8299 stats
->rx_packets
= old_stats
->rx_packets
+
8300 get_stat64(&hw_stats
->rx_ucast_packets
) +
8301 get_stat64(&hw_stats
->rx_mcast_packets
) +
8302 get_stat64(&hw_stats
->rx_bcast_packets
);
8304 stats
->tx_packets
= old_stats
->tx_packets
+
8305 get_stat64(&hw_stats
->tx_ucast_packets
) +
8306 get_stat64(&hw_stats
->tx_mcast_packets
) +
8307 get_stat64(&hw_stats
->tx_bcast_packets
);
8309 stats
->rx_bytes
= old_stats
->rx_bytes
+
8310 get_stat64(&hw_stats
->rx_octets
);
8311 stats
->tx_bytes
= old_stats
->tx_bytes
+
8312 get_stat64(&hw_stats
->tx_octets
);
8314 stats
->rx_errors
= old_stats
->rx_errors
+
8315 get_stat64(&hw_stats
->rx_errors
);
8316 stats
->tx_errors
= old_stats
->tx_errors
+
8317 get_stat64(&hw_stats
->tx_errors
) +
8318 get_stat64(&hw_stats
->tx_mac_errors
) +
8319 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
8320 get_stat64(&hw_stats
->tx_discards
);
8322 stats
->multicast
= old_stats
->multicast
+
8323 get_stat64(&hw_stats
->rx_mcast_packets
);
8324 stats
->collisions
= old_stats
->collisions
+
8325 get_stat64(&hw_stats
->tx_collisions
);
8327 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
8328 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
8329 get_stat64(&hw_stats
->rx_undersize_packets
);
8331 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
8332 get_stat64(&hw_stats
->rxbds_empty
);
8333 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
8334 get_stat64(&hw_stats
->rx_align_errors
);
8335 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
8336 get_stat64(&hw_stats
->tx_discards
);
8337 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
8338 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
8340 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
8341 calc_crc_errors(tp
);
8343 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
8344 get_stat64(&hw_stats
->rx_discards
);
8349 static inline u32
calc_crc(unsigned char *buf
, int len
)
8357 for (j
= 0; j
< len
; j
++) {
8360 for (k
= 0; k
< 8; k
++) {
8374 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
8376 /* accept or reject all multicast frames */
8377 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
8378 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
8379 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
8380 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
8383 static void __tg3_set_rx_mode(struct net_device
*dev
)
8385 struct tg3
*tp
= netdev_priv(dev
);
8388 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
8389 RX_MODE_KEEP_VLAN_TAG
);
8391 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8394 #if TG3_VLAN_TAG_USED
8396 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8397 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8399 /* By definition, VLAN is disabled always in this
8402 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8403 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8406 if (dev
->flags
& IFF_PROMISC
) {
8407 /* Promiscuous mode. */
8408 rx_mode
|= RX_MODE_PROMISC
;
8409 } else if (dev
->flags
& IFF_ALLMULTI
) {
8410 /* Accept all multicast. */
8411 tg3_set_multi (tp
, 1);
8412 } else if (dev
->mc_count
< 1) {
8413 /* Reject all multicast. */
8414 tg3_set_multi (tp
, 0);
8416 /* Accept one or more multicast(s). */
8417 struct dev_mc_list
*mclist
;
8419 u32 mc_filter
[4] = { 0, };
8424 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
8425 i
++, mclist
= mclist
->next
) {
8427 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
8429 regidx
= (bit
& 0x60) >> 5;
8431 mc_filter
[regidx
] |= (1 << bit
);
8434 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
8435 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
8436 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
8437 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
8440 if (rx_mode
!= tp
->rx_mode
) {
8441 tp
->rx_mode
= rx_mode
;
8442 tw32_f(MAC_RX_MODE
, rx_mode
);
8447 static void tg3_set_rx_mode(struct net_device
*dev
)
8449 struct tg3
*tp
= netdev_priv(dev
);
8451 if (!netif_running(dev
))
8454 tg3_full_lock(tp
, 0);
8455 __tg3_set_rx_mode(dev
);
8456 tg3_full_unlock(tp
);
8459 #define TG3_REGDUMP_LEN (32 * 1024)
8461 static int tg3_get_regs_len(struct net_device
*dev
)
8463 return TG3_REGDUMP_LEN
;
8466 static void tg3_get_regs(struct net_device
*dev
,
8467 struct ethtool_regs
*regs
, void *_p
)
8470 struct tg3
*tp
= netdev_priv(dev
);
8476 memset(p
, 0, TG3_REGDUMP_LEN
);
8478 if (tp
->link_config
.phy_is_low_power
)
8481 tg3_full_lock(tp
, 0);
8483 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8484 #define GET_REG32_LOOP(base,len) \
8485 do { p = (u32 *)(orig_p + (base)); \
8486 for (i = 0; i < len; i += 4) \
8487 __GET_REG32((base) + i); \
8489 #define GET_REG32_1(reg) \
8490 do { p = (u32 *)(orig_p + (reg)); \
8491 __GET_REG32((reg)); \
8494 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
8495 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
8496 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
8497 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
8498 GET_REG32_1(SNDDATAC_MODE
);
8499 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
8500 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
8501 GET_REG32_1(SNDBDC_MODE
);
8502 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
8503 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
8504 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
8505 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
8506 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
8507 GET_REG32_1(RCVDCC_MODE
);
8508 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
8509 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
8510 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
8511 GET_REG32_1(MBFREE_MODE
);
8512 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
8513 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
8514 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
8515 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
8516 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
8517 GET_REG32_1(RX_CPU_MODE
);
8518 GET_REG32_1(RX_CPU_STATE
);
8519 GET_REG32_1(RX_CPU_PGMCTR
);
8520 GET_REG32_1(RX_CPU_HWBKPT
);
8521 GET_REG32_1(TX_CPU_MODE
);
8522 GET_REG32_1(TX_CPU_STATE
);
8523 GET_REG32_1(TX_CPU_PGMCTR
);
8524 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
8525 GET_REG32_LOOP(FTQ_RESET
, 0x120);
8526 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
8527 GET_REG32_1(DMAC_MODE
);
8528 GET_REG32_LOOP(GRC_MODE
, 0x4c);
8529 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
8530 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
8533 #undef GET_REG32_LOOP
8536 tg3_full_unlock(tp
);
8539 static int tg3_get_eeprom_len(struct net_device
*dev
)
8541 struct tg3
*tp
= netdev_priv(dev
);
8543 return tp
->nvram_size
;
8546 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8548 struct tg3
*tp
= netdev_priv(dev
);
8551 u32 i
, offset
, len
, b_offset
, b_count
;
8554 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
8557 if (tp
->link_config
.phy_is_low_power
)
8560 offset
= eeprom
->offset
;
8564 eeprom
->magic
= TG3_EEPROM_MAGIC
;
8567 /* adjustments to start on required 4 byte boundary */
8568 b_offset
= offset
& 3;
8569 b_count
= 4 - b_offset
;
8570 if (b_count
> len
) {
8571 /* i.e. offset=1 len=2 */
8574 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
8577 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
8580 eeprom
->len
+= b_count
;
8583 /* read bytes upto the last 4 byte boundary */
8584 pd
= &data
[eeprom
->len
];
8585 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
8586 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
8591 memcpy(pd
+ i
, &val
, 4);
8596 /* read last bytes not ending on 4 byte boundary */
8597 pd
= &data
[eeprom
->len
];
8599 b_offset
= offset
+ len
- b_count
;
8600 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
8603 memcpy(pd
, &val
, b_count
);
8604 eeprom
->len
+= b_count
;
8609 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
8611 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8613 struct tg3
*tp
= netdev_priv(dev
);
8615 u32 offset
, len
, b_offset
, odd_len
;
8619 if (tp
->link_config
.phy_is_low_power
)
8622 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
8623 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
8626 offset
= eeprom
->offset
;
8629 if ((b_offset
= (offset
& 3))) {
8630 /* adjustments to start on required 4 byte boundary */
8631 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
8642 /* adjustments to end on required 4 byte boundary */
8644 len
= (len
+ 3) & ~3;
8645 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
8651 if (b_offset
|| odd_len
) {
8652 buf
= kmalloc(len
, GFP_KERNEL
);
8656 memcpy(buf
, &start
, 4);
8658 memcpy(buf
+len
-4, &end
, 4);
8659 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
8662 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
8670 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8672 struct tg3
*tp
= netdev_priv(dev
);
8674 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8675 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8677 return phy_ethtool_gset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8680 cmd
->supported
= (SUPPORTED_Autoneg
);
8682 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8683 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
8684 SUPPORTED_1000baseT_Full
);
8686 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
8687 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
8688 SUPPORTED_100baseT_Full
|
8689 SUPPORTED_10baseT_Half
|
8690 SUPPORTED_10baseT_Full
|
8692 cmd
->port
= PORT_TP
;
8694 cmd
->supported
|= SUPPORTED_FIBRE
;
8695 cmd
->port
= PORT_FIBRE
;
8698 cmd
->advertising
= tp
->link_config
.advertising
;
8699 if (netif_running(dev
)) {
8700 cmd
->speed
= tp
->link_config
.active_speed
;
8701 cmd
->duplex
= tp
->link_config
.active_duplex
;
8703 cmd
->phy_address
= PHY_ADDR
;
8704 cmd
->transceiver
= XCVR_INTERNAL
;
8705 cmd
->autoneg
= tp
->link_config
.autoneg
;
8711 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8713 struct tg3
*tp
= netdev_priv(dev
);
8715 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8716 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8718 return phy_ethtool_sset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8721 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
8722 cmd
->autoneg
!= AUTONEG_DISABLE
)
8725 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
8726 cmd
->duplex
!= DUPLEX_FULL
&&
8727 cmd
->duplex
!= DUPLEX_HALF
)
8730 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8731 u32 mask
= ADVERTISED_Autoneg
|
8733 ADVERTISED_Asym_Pause
;
8735 if (!(tp
->tg3_flags2
& TG3_FLAG_10_100_ONLY
))
8736 mask
|= ADVERTISED_1000baseT_Half
|
8737 ADVERTISED_1000baseT_Full
;
8739 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
8740 mask
|= ADVERTISED_100baseT_Half
|
8741 ADVERTISED_100baseT_Full
|
8742 ADVERTISED_10baseT_Half
|
8743 ADVERTISED_10baseT_Full
|
8746 mask
|= ADVERTISED_FIBRE
;
8748 if (cmd
->advertising
& ~mask
)
8751 mask
&= (ADVERTISED_1000baseT_Half
|
8752 ADVERTISED_1000baseT_Full
|
8753 ADVERTISED_100baseT_Half
|
8754 ADVERTISED_100baseT_Full
|
8755 ADVERTISED_10baseT_Half
|
8756 ADVERTISED_10baseT_Full
);
8758 cmd
->advertising
&= mask
;
8760 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
8761 if (cmd
->speed
!= SPEED_1000
)
8764 if (cmd
->duplex
!= DUPLEX_FULL
)
8767 if (cmd
->speed
!= SPEED_100
&&
8768 cmd
->speed
!= SPEED_10
)
8773 tg3_full_lock(tp
, 0);
8775 tp
->link_config
.autoneg
= cmd
->autoneg
;
8776 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8777 tp
->link_config
.advertising
= (cmd
->advertising
|
8778 ADVERTISED_Autoneg
);
8779 tp
->link_config
.speed
= SPEED_INVALID
;
8780 tp
->link_config
.duplex
= DUPLEX_INVALID
;
8782 tp
->link_config
.advertising
= 0;
8783 tp
->link_config
.speed
= cmd
->speed
;
8784 tp
->link_config
.duplex
= cmd
->duplex
;
8787 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
8788 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
8789 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
8791 if (netif_running(dev
))
8792 tg3_setup_phy(tp
, 1);
8794 tg3_full_unlock(tp
);
8799 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
8801 struct tg3
*tp
= netdev_priv(dev
);
8803 strcpy(info
->driver
, DRV_MODULE_NAME
);
8804 strcpy(info
->version
, DRV_MODULE_VERSION
);
8805 strcpy(info
->fw_version
, tp
->fw_ver
);
8806 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
8809 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8811 struct tg3
*tp
= netdev_priv(dev
);
8813 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
8814 device_can_wakeup(&tp
->pdev
->dev
))
8815 wol
->supported
= WAKE_MAGIC
;
8819 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
8820 device_can_wakeup(&tp
->pdev
->dev
))
8821 wol
->wolopts
= WAKE_MAGIC
;
8822 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
8825 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8827 struct tg3
*tp
= netdev_priv(dev
);
8828 struct device
*dp
= &tp
->pdev
->dev
;
8830 if (wol
->wolopts
& ~WAKE_MAGIC
)
8832 if ((wol
->wolopts
& WAKE_MAGIC
) &&
8833 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
8836 spin_lock_bh(&tp
->lock
);
8837 if (wol
->wolopts
& WAKE_MAGIC
) {
8838 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
8839 device_set_wakeup_enable(dp
, true);
8841 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
8842 device_set_wakeup_enable(dp
, false);
8844 spin_unlock_bh(&tp
->lock
);
8849 static u32
tg3_get_msglevel(struct net_device
*dev
)
8851 struct tg3
*tp
= netdev_priv(dev
);
8852 return tp
->msg_enable
;
8855 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
8857 struct tg3
*tp
= netdev_priv(dev
);
8858 tp
->msg_enable
= value
;
8861 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
8863 struct tg3
*tp
= netdev_priv(dev
);
8865 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8870 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
8871 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)) {
8873 dev
->features
|= NETIF_F_TSO6
;
8874 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8875 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
8876 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
8877 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8878 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8879 dev
->features
|= NETIF_F_TSO_ECN
;
8881 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
8883 return ethtool_op_set_tso(dev
, value
);
8886 static int tg3_nway_reset(struct net_device
*dev
)
8888 struct tg3
*tp
= netdev_priv(dev
);
8891 if (!netif_running(dev
))
8894 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
8897 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8898 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8900 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
8904 spin_lock_bh(&tp
->lock
);
8906 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
8907 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
8908 ((bmcr
& BMCR_ANENABLE
) ||
8909 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
8910 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
8914 spin_unlock_bh(&tp
->lock
);
8920 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
8922 struct tg3
*tp
= netdev_priv(dev
);
8924 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
8925 ering
->rx_mini_max_pending
= 0;
8926 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
8927 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
8929 ering
->rx_jumbo_max_pending
= 0;
8931 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
8933 ering
->rx_pending
= tp
->rx_pending
;
8934 ering
->rx_mini_pending
= 0;
8935 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
8936 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
8938 ering
->rx_jumbo_pending
= 0;
8940 ering
->tx_pending
= tp
->tx_pending
;
8943 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
8945 struct tg3
*tp
= netdev_priv(dev
);
8946 int irq_sync
= 0, err
= 0;
8948 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
8949 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
8950 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
8951 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
8952 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
8953 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
8956 if (netif_running(dev
)) {
8962 tg3_full_lock(tp
, irq_sync
);
8964 tp
->rx_pending
= ering
->rx_pending
;
8966 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
8967 tp
->rx_pending
> 63)
8968 tp
->rx_pending
= 63;
8969 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
8970 tp
->tx_pending
= ering
->tx_pending
;
8972 if (netif_running(dev
)) {
8973 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8974 err
= tg3_restart_hw(tp
, 1);
8976 tg3_netif_start(tp
);
8979 tg3_full_unlock(tp
);
8981 if (irq_sync
&& !err
)
8987 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
8989 struct tg3
*tp
= netdev_priv(dev
);
8991 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
8993 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
8994 epause
->rx_pause
= 1;
8996 epause
->rx_pause
= 0;
8998 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
8999 epause
->tx_pause
= 1;
9001 epause
->tx_pause
= 0;
9004 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9006 struct tg3
*tp
= netdev_priv(dev
);
9009 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9010 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9013 if (epause
->autoneg
) {
9015 struct phy_device
*phydev
;
9017 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
9019 if (epause
->rx_pause
) {
9020 if (epause
->tx_pause
)
9021 newadv
= ADVERTISED_Pause
;
9023 newadv
= ADVERTISED_Pause
|
9024 ADVERTISED_Asym_Pause
;
9025 } else if (epause
->tx_pause
) {
9026 newadv
= ADVERTISED_Asym_Pause
;
9030 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9031 u32 oldadv
= phydev
->advertising
&
9033 ADVERTISED_Asym_Pause
);
9034 if (oldadv
!= newadv
) {
9035 phydev
->advertising
&=
9036 ~(ADVERTISED_Pause
|
9037 ADVERTISED_Asym_Pause
);
9038 phydev
->advertising
|= newadv
;
9039 err
= phy_start_aneg(phydev
);
9042 tp
->link_config
.advertising
&=
9043 ~(ADVERTISED_Pause
|
9044 ADVERTISED_Asym_Pause
);
9045 tp
->link_config
.advertising
|= newadv
;
9048 if (epause
->rx_pause
)
9049 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9051 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9053 if (epause
->tx_pause
)
9054 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9056 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9058 if (netif_running(dev
))
9059 tg3_setup_flow_control(tp
, 0, 0);
9064 if (netif_running(dev
)) {
9069 tg3_full_lock(tp
, irq_sync
);
9071 if (epause
->autoneg
)
9072 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9074 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9075 if (epause
->rx_pause
)
9076 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9078 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9079 if (epause
->tx_pause
)
9080 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9082 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9084 if (netif_running(dev
)) {
9085 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9086 err
= tg3_restart_hw(tp
, 1);
9088 tg3_netif_start(tp
);
9091 tg3_full_unlock(tp
);
9097 static u32
tg3_get_rx_csum(struct net_device
*dev
)
9099 struct tg3
*tp
= netdev_priv(dev
);
9100 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
9103 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
9105 struct tg3
*tp
= netdev_priv(dev
);
9107 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9113 spin_lock_bh(&tp
->lock
);
9115 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
9117 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
9118 spin_unlock_bh(&tp
->lock
);
9123 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
9125 struct tg3
*tp
= netdev_priv(dev
);
9127 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9133 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9134 ethtool_op_set_tx_ipv6_csum(dev
, data
);
9136 ethtool_op_set_tx_csum(dev
, data
);
9141 static int tg3_get_sset_count (struct net_device
*dev
, int sset
)
9145 return TG3_NUM_TEST
;
9147 return TG3_NUM_STATS
;
9153 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
9155 switch (stringset
) {
9157 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
9160 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
9163 WARN_ON(1); /* we need a WARN() */
9168 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
9170 struct tg3
*tp
= netdev_priv(dev
);
9173 if (!netif_running(tp
->dev
))
9177 data
= UINT_MAX
/ 2;
9179 for (i
= 0; i
< (data
* 2); i
++) {
9181 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9182 LED_CTRL_1000MBPS_ON
|
9183 LED_CTRL_100MBPS_ON
|
9184 LED_CTRL_10MBPS_ON
|
9185 LED_CTRL_TRAFFIC_OVERRIDE
|
9186 LED_CTRL_TRAFFIC_BLINK
|
9187 LED_CTRL_TRAFFIC_LED
);
9190 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9191 LED_CTRL_TRAFFIC_OVERRIDE
);
9193 if (msleep_interruptible(500))
9196 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
9200 static void tg3_get_ethtool_stats (struct net_device
*dev
,
9201 struct ethtool_stats
*estats
, u64
*tmp_stats
)
9203 struct tg3
*tp
= netdev_priv(dev
);
9204 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
9207 #define NVRAM_TEST_SIZE 0x100
9208 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9209 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9210 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9211 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9212 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9214 static int tg3_test_nvram(struct tg3
*tp
)
9218 int i
, j
, k
, err
= 0, size
;
9220 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9223 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
9226 if (magic
== TG3_EEPROM_MAGIC
)
9227 size
= NVRAM_TEST_SIZE
;
9228 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
9229 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
9230 TG3_EEPROM_SB_FORMAT_1
) {
9231 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
9232 case TG3_EEPROM_SB_REVISION_0
:
9233 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
9235 case TG3_EEPROM_SB_REVISION_2
:
9236 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
9238 case TG3_EEPROM_SB_REVISION_3
:
9239 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
9246 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
9247 size
= NVRAM_SELFBOOT_HW_SIZE
;
9251 buf
= kmalloc(size
, GFP_KERNEL
);
9256 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
9257 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
9264 /* Selfboot format */
9265 magic
= be32_to_cpu(buf
[0]);
9266 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
9267 TG3_EEPROM_MAGIC_FW
) {
9268 u8
*buf8
= (u8
*) buf
, csum8
= 0;
9270 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
9271 TG3_EEPROM_SB_REVISION_2
) {
9272 /* For rev 2, the csum doesn't include the MBA. */
9273 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
9275 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
9278 for (i
= 0; i
< size
; i
++)
9291 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
9292 TG3_EEPROM_MAGIC_HW
) {
9293 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
9294 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
9295 u8
*buf8
= (u8
*) buf
;
9297 /* Separate the parity bits and the data bytes. */
9298 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
9299 if ((i
== 0) || (i
== 8)) {
9303 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
9304 parity
[k
++] = buf8
[i
] & msk
;
9311 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
9312 parity
[k
++] = buf8
[i
] & msk
;
9315 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
9316 parity
[k
++] = buf8
[i
] & msk
;
9319 data
[j
++] = buf8
[i
];
9323 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
9324 u8 hw8
= hweight8(data
[i
]);
9326 if ((hw8
& 0x1) && parity
[i
])
9328 else if (!(hw8
& 0x1) && !parity
[i
])
9335 /* Bootstrap checksum at offset 0x10 */
9336 csum
= calc_crc((unsigned char *) buf
, 0x10);
9337 if (csum
!= be32_to_cpu(buf
[0x10/4]))
9340 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9341 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
9342 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
9352 #define TG3_SERDES_TIMEOUT_SEC 2
9353 #define TG3_COPPER_TIMEOUT_SEC 6
9355 static int tg3_test_link(struct tg3
*tp
)
9359 if (!netif_running(tp
->dev
))
9362 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
9363 max
= TG3_SERDES_TIMEOUT_SEC
;
9365 max
= TG3_COPPER_TIMEOUT_SEC
;
9367 for (i
= 0; i
< max
; i
++) {
9368 if (netif_carrier_ok(tp
->dev
))
9371 if (msleep_interruptible(1000))
9378 /* Only test the commonly used registers */
9379 static int tg3_test_registers(struct tg3
*tp
)
9381 int i
, is_5705
, is_5750
;
9382 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
9386 #define TG3_FL_5705 0x1
9387 #define TG3_FL_NOT_5705 0x2
9388 #define TG3_FL_NOT_5788 0x4
9389 #define TG3_FL_NOT_5750 0x8
9393 /* MAC Control Registers */
9394 { MAC_MODE
, TG3_FL_NOT_5705
,
9395 0x00000000, 0x00ef6f8c },
9396 { MAC_MODE
, TG3_FL_5705
,
9397 0x00000000, 0x01ef6b8c },
9398 { MAC_STATUS
, TG3_FL_NOT_5705
,
9399 0x03800107, 0x00000000 },
9400 { MAC_STATUS
, TG3_FL_5705
,
9401 0x03800100, 0x00000000 },
9402 { MAC_ADDR_0_HIGH
, 0x0000,
9403 0x00000000, 0x0000ffff },
9404 { MAC_ADDR_0_LOW
, 0x0000,
9405 0x00000000, 0xffffffff },
9406 { MAC_RX_MTU_SIZE
, 0x0000,
9407 0x00000000, 0x0000ffff },
9408 { MAC_TX_MODE
, 0x0000,
9409 0x00000000, 0x00000070 },
9410 { MAC_TX_LENGTHS
, 0x0000,
9411 0x00000000, 0x00003fff },
9412 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
9413 0x00000000, 0x000007fc },
9414 { MAC_RX_MODE
, TG3_FL_5705
,
9415 0x00000000, 0x000007dc },
9416 { MAC_HASH_REG_0
, 0x0000,
9417 0x00000000, 0xffffffff },
9418 { MAC_HASH_REG_1
, 0x0000,
9419 0x00000000, 0xffffffff },
9420 { MAC_HASH_REG_2
, 0x0000,
9421 0x00000000, 0xffffffff },
9422 { MAC_HASH_REG_3
, 0x0000,
9423 0x00000000, 0xffffffff },
9425 /* Receive Data and Receive BD Initiator Control Registers. */
9426 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
9427 0x00000000, 0xffffffff },
9428 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
9429 0x00000000, 0xffffffff },
9430 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
9431 0x00000000, 0x00000003 },
9432 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
9433 0x00000000, 0xffffffff },
9434 { RCVDBDI_STD_BD
+0, 0x0000,
9435 0x00000000, 0xffffffff },
9436 { RCVDBDI_STD_BD
+4, 0x0000,
9437 0x00000000, 0xffffffff },
9438 { RCVDBDI_STD_BD
+8, 0x0000,
9439 0x00000000, 0xffff0002 },
9440 { RCVDBDI_STD_BD
+0xc, 0x0000,
9441 0x00000000, 0xffffffff },
9443 /* Receive BD Initiator Control Registers. */
9444 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
9445 0x00000000, 0xffffffff },
9446 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
9447 0x00000000, 0x000003ff },
9448 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
9449 0x00000000, 0xffffffff },
9451 /* Host Coalescing Control Registers. */
9452 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
9453 0x00000000, 0x00000004 },
9454 { HOSTCC_MODE
, TG3_FL_5705
,
9455 0x00000000, 0x000000f6 },
9456 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
9457 0x00000000, 0xffffffff },
9458 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
9459 0x00000000, 0x000003ff },
9460 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
9461 0x00000000, 0xffffffff },
9462 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
9463 0x00000000, 0x000003ff },
9464 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
9465 0x00000000, 0xffffffff },
9466 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9467 0x00000000, 0x000000ff },
9468 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
9469 0x00000000, 0xffffffff },
9470 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9471 0x00000000, 0x000000ff },
9472 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9473 0x00000000, 0xffffffff },
9474 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9475 0x00000000, 0xffffffff },
9476 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9477 0x00000000, 0xffffffff },
9478 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9479 0x00000000, 0x000000ff },
9480 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9481 0x00000000, 0xffffffff },
9482 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9483 0x00000000, 0x000000ff },
9484 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
9485 0x00000000, 0xffffffff },
9486 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
9487 0x00000000, 0xffffffff },
9488 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
9489 0x00000000, 0xffffffff },
9490 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
9491 0x00000000, 0xffffffff },
9492 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
9493 0x00000000, 0xffffffff },
9494 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
9495 0xffffffff, 0x00000000 },
9496 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
9497 0xffffffff, 0x00000000 },
9499 /* Buffer Manager Control Registers. */
9500 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
9501 0x00000000, 0x007fff80 },
9502 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
9503 0x00000000, 0x007fffff },
9504 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
9505 0x00000000, 0x0000003f },
9506 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
9507 0x00000000, 0x000001ff },
9508 { BUFMGR_MB_HIGH_WATER
, 0x0000,
9509 0x00000000, 0x000001ff },
9510 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
9511 0xffffffff, 0x00000000 },
9512 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
9513 0xffffffff, 0x00000000 },
9515 /* Mailbox Registers */
9516 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
9517 0x00000000, 0x000001ff },
9518 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
9519 0x00000000, 0x000001ff },
9520 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
9521 0x00000000, 0x000007ff },
9522 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
9523 0x00000000, 0x000001ff },
9525 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9528 is_5705
= is_5750
= 0;
9529 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9531 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
9535 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
9536 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
9539 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
9542 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
9543 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
9546 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
9549 offset
= (u32
) reg_tbl
[i
].offset
;
9550 read_mask
= reg_tbl
[i
].read_mask
;
9551 write_mask
= reg_tbl
[i
].write_mask
;
9553 /* Save the original register content */
9554 save_val
= tr32(offset
);
9556 /* Determine the read-only value. */
9557 read_val
= save_val
& read_mask
;
9559 /* Write zero to the register, then make sure the read-only bits
9560 * are not changed and the read/write bits are all zeros.
9566 /* Test the read-only and read/write bits. */
9567 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
9570 /* Write ones to all the bits defined by RdMask and WrMask, then
9571 * make sure the read-only bits are not changed and the
9572 * read/write bits are all ones.
9574 tw32(offset
, read_mask
| write_mask
);
9578 /* Test the read-only bits. */
9579 if ((val
& read_mask
) != read_val
)
9582 /* Test the read/write bits. */
9583 if ((val
& write_mask
) != write_mask
)
9586 tw32(offset
, save_val
);
9592 if (netif_msg_hw(tp
))
9593 printk(KERN_ERR PFX
"Register test failed at offset %x\n",
9595 tw32(offset
, save_val
);
9599 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
9601 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9605 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
9606 for (j
= 0; j
< len
; j
+= 4) {
9609 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
9610 tg3_read_mem(tp
, offset
+ j
, &val
);
9611 if (val
!= test_pattern
[i
])
9618 static int tg3_test_memory(struct tg3
*tp
)
9620 static struct mem_entry
{
9623 } mem_tbl_570x
[] = {
9624 { 0x00000000, 0x00b50},
9625 { 0x00002000, 0x1c000},
9626 { 0xffffffff, 0x00000}
9627 }, mem_tbl_5705
[] = {
9628 { 0x00000100, 0x0000c},
9629 { 0x00000200, 0x00008},
9630 { 0x00004000, 0x00800},
9631 { 0x00006000, 0x01000},
9632 { 0x00008000, 0x02000},
9633 { 0x00010000, 0x0e000},
9634 { 0xffffffff, 0x00000}
9635 }, mem_tbl_5755
[] = {
9636 { 0x00000200, 0x00008},
9637 { 0x00004000, 0x00800},
9638 { 0x00006000, 0x00800},
9639 { 0x00008000, 0x02000},
9640 { 0x00010000, 0x0c000},
9641 { 0xffffffff, 0x00000}
9642 }, mem_tbl_5906
[] = {
9643 { 0x00000200, 0x00008},
9644 { 0x00004000, 0x00400},
9645 { 0x00006000, 0x00400},
9646 { 0x00008000, 0x01000},
9647 { 0x00010000, 0x01000},
9648 { 0xffffffff, 0x00000}
9650 struct mem_entry
*mem_tbl
;
9654 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9655 mem_tbl
= mem_tbl_5755
;
9656 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
9657 mem_tbl
= mem_tbl_5906
;
9658 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
9659 mem_tbl
= mem_tbl_5705
;
9661 mem_tbl
= mem_tbl_570x
;
9663 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
9664 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
9665 mem_tbl
[i
].len
)) != 0)
9672 #define TG3_MAC_LOOPBACK 0
9673 #define TG3_PHY_LOOPBACK 1
9675 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
9677 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
9679 struct sk_buff
*skb
, *rx_skb
;
9682 int num_pkts
, tx_len
, rx_len
, i
, err
;
9683 struct tg3_rx_buffer_desc
*desc
;
9685 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
9686 /* HW errata - mac loopback fails in some cases on 5780.
9687 * Normal traffic and PHY loopback are not affected by
9690 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
9693 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
9694 MAC_MODE_PORT_INT_LPBACK
;
9695 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9696 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9697 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
9698 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9700 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9701 tw32(MAC_MODE
, mac_mode
);
9702 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
9705 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
9708 if (!tg3_readphy(tp
, MII_TG3_EPHY_TEST
, &phytest
)) {
9711 tg3_writephy(tp
, MII_TG3_EPHY_TEST
,
9712 phytest
| MII_TG3_EPHY_SHADOW_EN
);
9713 if (!tg3_readphy(tp
, 0x1b, &phy
))
9714 tg3_writephy(tp
, 0x1b, phy
& ~0x20);
9715 tg3_writephy(tp
, MII_TG3_EPHY_TEST
, phytest
);
9717 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
9719 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
9721 tg3_phy_toggle_automdix(tp
, 0);
9723 tg3_writephy(tp
, MII_BMCR
, val
);
9726 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
9727 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
9728 tg3_writephy(tp
, MII_TG3_EPHY_PTEST
, 0x1800);
9729 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9731 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9733 /* reset to prevent losing 1st rx packet intermittently */
9734 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
9735 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
9737 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
9739 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
9740 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)
9741 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
9742 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
)
9743 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9744 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
9745 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
9747 tw32(MAC_MODE
, mac_mode
);
9755 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
9759 tx_data
= skb_put(skb
, tx_len
);
9760 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
9761 memset(tx_data
+ 6, 0x0, 8);
9763 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
9765 for (i
= 14; i
< tx_len
; i
++)
9766 tx_data
[i
] = (u8
) (i
& 0xff);
9768 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
9770 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9775 rx_start_idx
= tp
->hw_status
->idx
[0].rx_producer
;
9779 tg3_set_txd(tp
, tp
->tx_prod
, map
, tx_len
, 0, 1);
9784 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
,
9786 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
);
9790 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9791 for (i
= 0; i
< 25; i
++) {
9792 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9797 tx_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
9798 rx_idx
= tp
->hw_status
->idx
[0].rx_producer
;
9799 if ((tx_idx
== tp
->tx_prod
) &&
9800 (rx_idx
== (rx_start_idx
+ num_pkts
)))
9804 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
9807 if (tx_idx
!= tp
->tx_prod
)
9810 if (rx_idx
!= rx_start_idx
+ num_pkts
)
9813 desc
= &tp
->rx_rcb
[rx_start_idx
];
9814 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
9815 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
9816 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
9819 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
9820 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
9823 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
9824 if (rx_len
!= tx_len
)
9827 rx_skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
9829 map
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
], mapping
);
9830 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
9832 for (i
= 14; i
< tx_len
; i
++) {
9833 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
9838 /* tg3_free_rings will unmap and free the rx_skb */
9843 #define TG3_MAC_LOOPBACK_FAILED 1
9844 #define TG3_PHY_LOOPBACK_FAILED 2
9845 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9846 TG3_PHY_LOOPBACK_FAILED)
9848 static int tg3_test_loopback(struct tg3
*tp
)
9853 if (!netif_running(tp
->dev
))
9854 return TG3_LOOPBACK_FAILED
;
9856 err
= tg3_reset_hw(tp
, 1);
9858 return TG3_LOOPBACK_FAILED
;
9860 /* Turn off gphy autopowerdown. */
9861 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
9862 tg3_phy_toggle_apd(tp
, false);
9864 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
9868 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
9870 /* Wait for up to 40 microseconds to acquire lock. */
9871 for (i
= 0; i
< 4; i
++) {
9872 status
= tr32(TG3_CPMU_MUTEX_GNT
);
9873 if (status
== CPMU_MUTEX_GNT_DRIVER
)
9878 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
9879 return TG3_LOOPBACK_FAILED
;
9881 /* Turn off link-based power management. */
9882 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
9884 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
9885 CPMU_CTRL_LINK_AWARE_MODE
));
9888 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
9889 err
|= TG3_MAC_LOOPBACK_FAILED
;
9891 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
9892 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
9894 /* Release the mutex */
9895 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
9898 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
9899 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
9900 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
9901 err
|= TG3_PHY_LOOPBACK_FAILED
;
9904 /* Re-enable gphy autopowerdown. */
9905 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
9906 tg3_phy_toggle_apd(tp
, true);
9911 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
9914 struct tg3
*tp
= netdev_priv(dev
);
9916 if (tp
->link_config
.phy_is_low_power
)
9917 tg3_set_power_state(tp
, PCI_D0
);
9919 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
9921 if (tg3_test_nvram(tp
) != 0) {
9922 etest
->flags
|= ETH_TEST_FL_FAILED
;
9925 if (tg3_test_link(tp
) != 0) {
9926 etest
->flags
|= ETH_TEST_FL_FAILED
;
9929 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
9930 int err
, err2
= 0, irq_sync
= 0;
9932 if (netif_running(dev
)) {
9938 tg3_full_lock(tp
, irq_sync
);
9940 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
9941 err
= tg3_nvram_lock(tp
);
9942 tg3_halt_cpu(tp
, RX_CPU_BASE
);
9943 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9944 tg3_halt_cpu(tp
, TX_CPU_BASE
);
9946 tg3_nvram_unlock(tp
);
9948 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
9951 if (tg3_test_registers(tp
) != 0) {
9952 etest
->flags
|= ETH_TEST_FL_FAILED
;
9955 if (tg3_test_memory(tp
) != 0) {
9956 etest
->flags
|= ETH_TEST_FL_FAILED
;
9959 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
9960 etest
->flags
|= ETH_TEST_FL_FAILED
;
9962 tg3_full_unlock(tp
);
9964 if (tg3_test_interrupt(tp
) != 0) {
9965 etest
->flags
|= ETH_TEST_FL_FAILED
;
9969 tg3_full_lock(tp
, 0);
9971 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9972 if (netif_running(dev
)) {
9973 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9974 err2
= tg3_restart_hw(tp
, 1);
9976 tg3_netif_start(tp
);
9979 tg3_full_unlock(tp
);
9981 if (irq_sync
&& !err2
)
9984 if (tp
->link_config
.phy_is_low_power
)
9985 tg3_set_power_state(tp
, PCI_D3hot
);
9989 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
9991 struct mii_ioctl_data
*data
= if_mii(ifr
);
9992 struct tg3
*tp
= netdev_priv(dev
);
9995 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9996 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9998 return phy_mii_ioctl(tp
->mdio_bus
->phy_map
[PHY_ADDR
], data
, cmd
);
10003 data
->phy_id
= PHY_ADDR
;
10006 case SIOCGMIIREG
: {
10009 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10010 break; /* We have no PHY */
10012 if (tp
->link_config
.phy_is_low_power
)
10015 spin_lock_bh(&tp
->lock
);
10016 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10017 spin_unlock_bh(&tp
->lock
);
10019 data
->val_out
= mii_regval
;
10025 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10026 break; /* We have no PHY */
10028 if (!capable(CAP_NET_ADMIN
))
10031 if (tp
->link_config
.phy_is_low_power
)
10034 spin_lock_bh(&tp
->lock
);
10035 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10036 spin_unlock_bh(&tp
->lock
);
10044 return -EOPNOTSUPP
;
10047 #if TG3_VLAN_TAG_USED
10048 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10050 struct tg3
*tp
= netdev_priv(dev
);
10052 if (!netif_running(dev
)) {
10057 tg3_netif_stop(tp
);
10059 tg3_full_lock(tp
, 0);
10063 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10064 __tg3_set_rx_mode(dev
);
10066 tg3_netif_start(tp
);
10068 tg3_full_unlock(tp
);
10072 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10074 struct tg3
*tp
= netdev_priv(dev
);
10076 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
10080 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10082 struct tg3
*tp
= netdev_priv(dev
);
10083 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
10084 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
10086 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
10087 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
10088 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
10089 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
10090 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
10093 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
10094 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
10095 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
10096 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
10097 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
10098 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
10099 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
10100 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
10101 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
10102 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
10105 /* No rx interrupts will be generated if both are zero */
10106 if ((ec
->rx_coalesce_usecs
== 0) &&
10107 (ec
->rx_max_coalesced_frames
== 0))
10110 /* No tx interrupts will be generated if both are zero */
10111 if ((ec
->tx_coalesce_usecs
== 0) &&
10112 (ec
->tx_max_coalesced_frames
== 0))
10115 /* Only copy relevant parameters, ignore all others. */
10116 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
10117 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
10118 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
10119 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
10120 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
10121 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
10122 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
10123 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
10124 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
10126 if (netif_running(dev
)) {
10127 tg3_full_lock(tp
, 0);
10128 __tg3_set_coalesce(tp
, &tp
->coal
);
10129 tg3_full_unlock(tp
);
10134 static const struct ethtool_ops tg3_ethtool_ops
= {
10135 .get_settings
= tg3_get_settings
,
10136 .set_settings
= tg3_set_settings
,
10137 .get_drvinfo
= tg3_get_drvinfo
,
10138 .get_regs_len
= tg3_get_regs_len
,
10139 .get_regs
= tg3_get_regs
,
10140 .get_wol
= tg3_get_wol
,
10141 .set_wol
= tg3_set_wol
,
10142 .get_msglevel
= tg3_get_msglevel
,
10143 .set_msglevel
= tg3_set_msglevel
,
10144 .nway_reset
= tg3_nway_reset
,
10145 .get_link
= ethtool_op_get_link
,
10146 .get_eeprom_len
= tg3_get_eeprom_len
,
10147 .get_eeprom
= tg3_get_eeprom
,
10148 .set_eeprom
= tg3_set_eeprom
,
10149 .get_ringparam
= tg3_get_ringparam
,
10150 .set_ringparam
= tg3_set_ringparam
,
10151 .get_pauseparam
= tg3_get_pauseparam
,
10152 .set_pauseparam
= tg3_set_pauseparam
,
10153 .get_rx_csum
= tg3_get_rx_csum
,
10154 .set_rx_csum
= tg3_set_rx_csum
,
10155 .set_tx_csum
= tg3_set_tx_csum
,
10156 .set_sg
= ethtool_op_set_sg
,
10157 .set_tso
= tg3_set_tso
,
10158 .self_test
= tg3_self_test
,
10159 .get_strings
= tg3_get_strings
,
10160 .phys_id
= tg3_phys_id
,
10161 .get_ethtool_stats
= tg3_get_ethtool_stats
,
10162 .get_coalesce
= tg3_get_coalesce
,
10163 .set_coalesce
= tg3_set_coalesce
,
10164 .get_sset_count
= tg3_get_sset_count
,
10167 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
10169 u32 cursize
, val
, magic
;
10171 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
10173 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10176 if ((magic
!= TG3_EEPROM_MAGIC
) &&
10177 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
10178 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
10182 * Size the chip by reading offsets at increasing powers of two.
10183 * When we encounter our validation signature, we know the addressing
10184 * has wrapped around, and thus have our chip size.
10188 while (cursize
< tp
->nvram_size
) {
10189 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
10198 tp
->nvram_size
= cursize
;
10201 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
10205 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
10206 tg3_nvram_read(tp
, 0, &val
) != 0)
10209 /* Selfboot format */
10210 if (val
!= TG3_EEPROM_MAGIC
) {
10211 tg3_get_eeprom_size(tp
);
10215 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
10217 /* This is confusing. We want to operate on the
10218 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10219 * call will read from NVRAM and byteswap the data
10220 * according to the byteswapping settings for all
10221 * other register accesses. This ensures the data we
10222 * want will always reside in the lower 16-bits.
10223 * However, the data in NVRAM is in LE format, which
10224 * means the data from the NVRAM read will always be
10225 * opposite the endianness of the CPU. The 16-bit
10226 * byteswap then brings the data to CPU endianness.
10228 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
10232 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10235 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
10239 nvcfg1
= tr32(NVRAM_CFG1
);
10240 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
10241 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10244 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10245 tw32(NVRAM_CFG1
, nvcfg1
);
10248 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
10249 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
10250 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
10251 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
10252 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10253 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10254 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10256 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
10257 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10258 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
10260 case FLASH_VENDOR_ATMEL_EEPROM
:
10261 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10262 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10263 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10265 case FLASH_VENDOR_ST
:
10266 tp
->nvram_jedecnum
= JEDEC_ST
;
10267 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
10268 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10270 case FLASH_VENDOR_SAIFUN
:
10271 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
10272 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
10274 case FLASH_VENDOR_SST_SMALL
:
10275 case FLASH_VENDOR_SST_LARGE
:
10276 tp
->nvram_jedecnum
= JEDEC_SST
;
10277 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
10282 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10283 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10284 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10288 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
10292 nvcfg1
= tr32(NVRAM_CFG1
);
10294 /* NVRAM protection for TPM */
10295 if (nvcfg1
& (1 << 27))
10296 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10298 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10299 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
10300 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
10301 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10302 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10304 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10305 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10306 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10307 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10309 case FLASH_5752VENDOR_ST_M45PE10
:
10310 case FLASH_5752VENDOR_ST_M45PE20
:
10311 case FLASH_5752VENDOR_ST_M45PE40
:
10312 tp
->nvram_jedecnum
= JEDEC_ST
;
10313 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10314 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10318 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
10319 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10320 case FLASH_5752PAGE_SIZE_256
:
10321 tp
->nvram_pagesize
= 256;
10323 case FLASH_5752PAGE_SIZE_512
:
10324 tp
->nvram_pagesize
= 512;
10326 case FLASH_5752PAGE_SIZE_1K
:
10327 tp
->nvram_pagesize
= 1024;
10329 case FLASH_5752PAGE_SIZE_2K
:
10330 tp
->nvram_pagesize
= 2048;
10332 case FLASH_5752PAGE_SIZE_4K
:
10333 tp
->nvram_pagesize
= 4096;
10335 case FLASH_5752PAGE_SIZE_264
:
10336 tp
->nvram_pagesize
= 264;
10341 /* For eeprom, set pagesize to maximum eeprom size */
10342 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10344 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10345 tw32(NVRAM_CFG1
, nvcfg1
);
10349 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
10351 u32 nvcfg1
, protect
= 0;
10353 nvcfg1
= tr32(NVRAM_CFG1
);
10355 /* NVRAM protection for TPM */
10356 if (nvcfg1
& (1 << 27)) {
10357 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10361 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10363 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10364 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10365 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10366 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
10367 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10368 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10369 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10370 tp
->nvram_pagesize
= 264;
10371 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
10372 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
10373 tp
->nvram_size
= (protect
? 0x3e200 :
10374 TG3_NVRAM_SIZE_512KB
);
10375 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
10376 tp
->nvram_size
= (protect
? 0x1f200 :
10377 TG3_NVRAM_SIZE_256KB
);
10379 tp
->nvram_size
= (protect
? 0x1f200 :
10380 TG3_NVRAM_SIZE_128KB
);
10382 case FLASH_5752VENDOR_ST_M45PE10
:
10383 case FLASH_5752VENDOR_ST_M45PE20
:
10384 case FLASH_5752VENDOR_ST_M45PE40
:
10385 tp
->nvram_jedecnum
= JEDEC_ST
;
10386 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10387 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10388 tp
->nvram_pagesize
= 256;
10389 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
10390 tp
->nvram_size
= (protect
?
10391 TG3_NVRAM_SIZE_64KB
:
10392 TG3_NVRAM_SIZE_128KB
);
10393 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
10394 tp
->nvram_size
= (protect
?
10395 TG3_NVRAM_SIZE_64KB
:
10396 TG3_NVRAM_SIZE_256KB
);
10398 tp
->nvram_size
= (protect
?
10399 TG3_NVRAM_SIZE_128KB
:
10400 TG3_NVRAM_SIZE_512KB
);
10405 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
10409 nvcfg1
= tr32(NVRAM_CFG1
);
10411 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10412 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
10413 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10414 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
10415 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10416 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10417 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10418 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10420 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10421 tw32(NVRAM_CFG1
, nvcfg1
);
10423 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10424 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10425 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10426 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10427 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10428 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10429 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10430 tp
->nvram_pagesize
= 264;
10432 case FLASH_5752VENDOR_ST_M45PE10
:
10433 case FLASH_5752VENDOR_ST_M45PE20
:
10434 case FLASH_5752VENDOR_ST_M45PE40
:
10435 tp
->nvram_jedecnum
= JEDEC_ST
;
10436 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10437 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10438 tp
->nvram_pagesize
= 256;
10443 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
10445 u32 nvcfg1
, protect
= 0;
10447 nvcfg1
= tr32(NVRAM_CFG1
);
10449 /* NVRAM protection for TPM */
10450 if (nvcfg1
& (1 << 27)) {
10451 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10455 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10457 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10458 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10459 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10460 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10461 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10462 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10463 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10464 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10465 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10466 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10467 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10468 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10469 tp
->nvram_pagesize
= 256;
10471 case FLASH_5761VENDOR_ST_A_M45PE20
:
10472 case FLASH_5761VENDOR_ST_A_M45PE40
:
10473 case FLASH_5761VENDOR_ST_A_M45PE80
:
10474 case FLASH_5761VENDOR_ST_A_M45PE16
:
10475 case FLASH_5761VENDOR_ST_M_M45PE20
:
10476 case FLASH_5761VENDOR_ST_M_M45PE40
:
10477 case FLASH_5761VENDOR_ST_M_M45PE80
:
10478 case FLASH_5761VENDOR_ST_M_M45PE16
:
10479 tp
->nvram_jedecnum
= JEDEC_ST
;
10480 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10481 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10482 tp
->nvram_pagesize
= 256;
10487 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
10490 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10491 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10492 case FLASH_5761VENDOR_ST_A_M45PE16
:
10493 case FLASH_5761VENDOR_ST_M_M45PE16
:
10494 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
10496 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10497 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10498 case FLASH_5761VENDOR_ST_A_M45PE80
:
10499 case FLASH_5761VENDOR_ST_M_M45PE80
:
10500 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
10502 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10503 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10504 case FLASH_5761VENDOR_ST_A_M45PE40
:
10505 case FLASH_5761VENDOR_ST_M_M45PE40
:
10506 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10508 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10509 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10510 case FLASH_5761VENDOR_ST_A_M45PE20
:
10511 case FLASH_5761VENDOR_ST_M_M45PE20
:
10512 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10518 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
10520 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10521 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10522 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10525 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
10529 nvcfg1
= tr32(NVRAM_CFG1
);
10531 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10532 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10533 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10534 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10535 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10536 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10538 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10539 tw32(NVRAM_CFG1
, nvcfg1
);
10541 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10542 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10543 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10544 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10545 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10546 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10547 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10548 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10549 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10550 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10552 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10553 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10554 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10555 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10556 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10558 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10559 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10560 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10562 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10563 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10564 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10568 case FLASH_5752VENDOR_ST_M45PE10
:
10569 case FLASH_5752VENDOR_ST_M45PE20
:
10570 case FLASH_5752VENDOR_ST_M45PE40
:
10571 tp
->nvram_jedecnum
= JEDEC_ST
;
10572 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10573 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10575 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10576 case FLASH_5752VENDOR_ST_M45PE10
:
10577 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10579 case FLASH_5752VENDOR_ST_M45PE20
:
10580 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10582 case FLASH_5752VENDOR_ST_M45PE40
:
10583 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10588 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
10592 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10593 case FLASH_5752PAGE_SIZE_256
:
10594 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10595 tp
->nvram_pagesize
= 256;
10597 case FLASH_5752PAGE_SIZE_512
:
10598 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10599 tp
->nvram_pagesize
= 512;
10601 case FLASH_5752PAGE_SIZE_1K
:
10602 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10603 tp
->nvram_pagesize
= 1024;
10605 case FLASH_5752PAGE_SIZE_2K
:
10606 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10607 tp
->nvram_pagesize
= 2048;
10609 case FLASH_5752PAGE_SIZE_4K
:
10610 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10611 tp
->nvram_pagesize
= 4096;
10613 case FLASH_5752PAGE_SIZE_264
:
10614 tp
->nvram_pagesize
= 264;
10616 case FLASH_5752PAGE_SIZE_528
:
10617 tp
->nvram_pagesize
= 528;
10622 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10623 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
10625 tw32_f(GRC_EEPROM_ADDR
,
10626 (EEPROM_ADDR_FSM_RESET
|
10627 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
10628 EEPROM_ADDR_CLKPERD_SHIFT
)));
10632 /* Enable seeprom accesses. */
10633 tw32_f(GRC_LOCAL_CTRL
,
10634 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
10637 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
10638 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
10639 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
10641 if (tg3_nvram_lock(tp
)) {
10642 printk(KERN_WARNING PFX
"%s: Cannot get nvarm lock, "
10643 "tg3_nvram_init failed.\n", tp
->dev
->name
);
10646 tg3_enable_nvram_access(tp
);
10648 tp
->nvram_size
= 0;
10650 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
10651 tg3_get_5752_nvram_info(tp
);
10652 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
10653 tg3_get_5755_nvram_info(tp
);
10654 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
10655 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
10656 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10657 tg3_get_5787_nvram_info(tp
);
10658 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
10659 tg3_get_5761_nvram_info(tp
);
10660 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10661 tg3_get_5906_nvram_info(tp
);
10662 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
10663 tg3_get_57780_nvram_info(tp
);
10665 tg3_get_nvram_info(tp
);
10667 if (tp
->nvram_size
== 0)
10668 tg3_get_nvram_size(tp
);
10670 tg3_disable_nvram_access(tp
);
10671 tg3_nvram_unlock(tp
);
10674 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
10676 tg3_get_eeprom_size(tp
);
10680 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
10681 u32 offset
, u32 len
, u8
*buf
)
10686 for (i
= 0; i
< len
; i
+= 4) {
10692 memcpy(&data
, buf
+ i
, 4);
10695 * The SEEPROM interface expects the data to always be opposite
10696 * the native endian format. We accomplish this by reversing
10697 * all the operations that would have been performed on the
10698 * data from a call to tg3_nvram_read_be32().
10700 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
10702 val
= tr32(GRC_EEPROM_ADDR
);
10703 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
10705 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
10707 tw32(GRC_EEPROM_ADDR
, val
|
10708 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
10709 (addr
& EEPROM_ADDR_ADDR_MASK
) |
10710 EEPROM_ADDR_START
|
10711 EEPROM_ADDR_WRITE
);
10713 for (j
= 0; j
< 1000; j
++) {
10714 val
= tr32(GRC_EEPROM_ADDR
);
10716 if (val
& EEPROM_ADDR_COMPLETE
)
10720 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
10729 /* offset and length are dword aligned */
10730 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
10734 u32 pagesize
= tp
->nvram_pagesize
;
10735 u32 pagemask
= pagesize
- 1;
10739 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
10745 u32 phy_addr
, page_off
, size
;
10747 phy_addr
= offset
& ~pagemask
;
10749 for (j
= 0; j
< pagesize
; j
+= 4) {
10750 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
10751 (__be32
*) (tmp
+ j
));
10758 page_off
= offset
& pagemask
;
10765 memcpy(tmp
+ page_off
, buf
, size
);
10767 offset
= offset
+ (pagesize
- page_off
);
10769 tg3_enable_nvram_access(tp
);
10772 * Before we can erase the flash page, we need
10773 * to issue a special "write enable" command.
10775 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10777 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10780 /* Erase the target page */
10781 tw32(NVRAM_ADDR
, phy_addr
);
10783 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
10784 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
10786 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10789 /* Issue another write enable to start the write. */
10790 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10792 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10795 for (j
= 0; j
< pagesize
; j
+= 4) {
10798 data
= *((__be32
*) (tmp
+ j
));
10800 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
10802 tw32(NVRAM_ADDR
, phy_addr
+ j
);
10804 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
10808 nvram_cmd
|= NVRAM_CMD_FIRST
;
10809 else if (j
== (pagesize
- 4))
10810 nvram_cmd
|= NVRAM_CMD_LAST
;
10812 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
10819 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10820 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
10827 /* offset and length are dword aligned */
10828 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
10833 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
10834 u32 page_off
, phy_addr
, nvram_cmd
;
10837 memcpy(&data
, buf
+ i
, 4);
10838 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
10840 page_off
= offset
% tp
->nvram_pagesize
;
10842 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
10844 tw32(NVRAM_ADDR
, phy_addr
);
10846 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
10848 if ((page_off
== 0) || (i
== 0))
10849 nvram_cmd
|= NVRAM_CMD_FIRST
;
10850 if (page_off
== (tp
->nvram_pagesize
- 4))
10851 nvram_cmd
|= NVRAM_CMD_LAST
;
10853 if (i
== (len
- 4))
10854 nvram_cmd
|= NVRAM_CMD_LAST
;
10856 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
10857 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
10858 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
10859 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
10861 if ((ret
= tg3_nvram_exec_cmd(tp
,
10862 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
10867 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
10868 /* We always do complete word writes to eeprom. */
10869 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
10872 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
10878 /* offset and length are dword aligned */
10879 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
10883 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
10884 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
10885 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
10889 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
10890 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
10895 ret
= tg3_nvram_lock(tp
);
10899 tg3_enable_nvram_access(tp
);
10900 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
10901 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
10902 tw32(NVRAM_WRITE1
, 0x406);
10904 grc_mode
= tr32(GRC_MODE
);
10905 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
10907 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
10908 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
10910 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
10914 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
10918 grc_mode
= tr32(GRC_MODE
);
10919 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
10921 tg3_disable_nvram_access(tp
);
10922 tg3_nvram_unlock(tp
);
10925 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
10926 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10933 struct subsys_tbl_ent
{
10934 u16 subsys_vendor
, subsys_devid
;
10938 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
10939 /* Broadcom boards. */
10940 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
10941 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
10942 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
10943 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
10944 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
10945 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
10946 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
10947 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
10948 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
10949 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
10950 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
10953 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
10954 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
10955 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
10956 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
10957 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
10960 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
10961 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
10962 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
10963 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
10965 /* Compaq boards. */
10966 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
10967 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
10968 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
10969 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
10970 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
10973 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
10976 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
10980 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
10981 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
10982 tp
->pdev
->subsystem_vendor
) &&
10983 (subsys_id_to_phy_id
[i
].subsys_devid
==
10984 tp
->pdev
->subsystem_device
))
10985 return &subsys_id_to_phy_id
[i
];
10990 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
10995 /* On some early chips the SRAM cannot be accessed in D3hot state,
10996 * so need make sure we're in D0.
10998 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
10999 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
11000 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
11003 /* Make sure register accesses (indirect or otherwise)
11004 * will function correctly.
11006 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11007 tp
->misc_host_ctrl
);
11009 /* The memory arbiter has to be enabled in order for SRAM accesses
11010 * to succeed. Normally on powerup the tg3 chip firmware will make
11011 * sure it is enabled, but other entities such as system netboot
11012 * code might disable it.
11014 val
= tr32(MEMARB_MODE
);
11015 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
11017 tp
->phy_id
= PHY_ID_INVALID
;
11018 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11020 /* Assume an onboard device and WOL capable by default. */
11021 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
11023 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11024 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
11025 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11026 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11028 val
= tr32(VCPU_CFGSHDW
);
11029 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
11030 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11031 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
11032 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
11033 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11037 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
11038 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
11039 u32 nic_cfg
, led_cfg
;
11040 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
11041 int eeprom_phy_serdes
= 0;
11043 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
11044 tp
->nic_sram_data_cfg
= nic_cfg
;
11046 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
11047 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
11048 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
11049 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
11050 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
11051 (ver
> 0) && (ver
< 0x100))
11052 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
11054 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11055 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
11057 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
11058 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
11059 eeprom_phy_serdes
= 1;
11061 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
11062 if (nic_phy_id
!= 0) {
11063 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
11064 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
11066 eeprom_phy_id
= (id1
>> 16) << 10;
11067 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
11068 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
11072 tp
->phy_id
= eeprom_phy_id
;
11073 if (eeprom_phy_serdes
) {
11074 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
11075 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
11077 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11080 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11081 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
11082 SHASTA_EXT_LED_MODE_MASK
);
11084 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
11088 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
11089 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11092 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
11093 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11096 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
11097 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
11099 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11100 * read on some older 5700/5701 bootcode.
11102 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11104 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11106 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11110 case SHASTA_EXT_LED_SHARED
:
11111 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
11112 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
11113 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
11114 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11115 LED_CTRL_MODE_PHY_2
);
11118 case SHASTA_EXT_LED_MAC
:
11119 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
11122 case SHASTA_EXT_LED_COMBO
:
11123 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
11124 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
11125 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11126 LED_CTRL_MODE_PHY_2
);
11131 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11132 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
11133 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
11134 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11136 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
11137 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11139 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
11140 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
11141 if ((tp
->pdev
->subsystem_vendor
==
11142 PCI_VENDOR_ID_ARIMA
) &&
11143 (tp
->pdev
->subsystem_device
== 0x205a ||
11144 tp
->pdev
->subsystem_device
== 0x2063))
11145 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11147 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11148 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11151 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
11152 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
11153 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11154 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
11157 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
11158 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11159 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
11161 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
11162 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
11163 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
11165 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
11166 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
11167 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11169 if (cfg2
& (1 << 17))
11170 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
11172 /* serdes signal pre-emphasis in register 0x590 set by */
11173 /* bootcode if bit 18 is set */
11174 if (cfg2
& (1 << 18))
11175 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
11177 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
11178 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
11179 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
11180 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
11182 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
11185 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
11186 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
11187 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11190 if (cfg4
& NIC_SRAM_RGMII_STD_IBND_DISABLE
)
11191 tp
->tg3_flags3
|= TG3_FLG3_RGMII_STD_IBND_DISABLE
;
11192 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
11193 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
11194 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
11195 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
11198 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
11199 device_set_wakeup_enable(&tp
->pdev
->dev
,
11200 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
11203 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
11208 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
11209 tw32(OTP_CTRL
, cmd
);
11211 /* Wait for up to 1 ms for command to execute. */
11212 for (i
= 0; i
< 100; i
++) {
11213 val
= tr32(OTP_STATUS
);
11214 if (val
& OTP_STATUS_CMD_DONE
)
11219 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
11222 /* Read the gphy configuration from the OTP region of the chip. The gphy
11223 * configuration is a 32-bit value that straddles the alignment boundary.
11224 * We do two 32-bit reads and then shift and merge the results.
11226 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
11228 u32 bhalf_otp
, thalf_otp
;
11230 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
11232 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
11235 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
11237 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11240 thalf_otp
= tr32(OTP_READ_DATA
);
11242 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
11244 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11247 bhalf_otp
= tr32(OTP_READ_DATA
);
11249 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
11252 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
11254 u32 hw_phy_id_1
, hw_phy_id_2
;
11255 u32 hw_phy_id
, hw_phy_id_masked
;
11258 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
11259 return tg3_phy_init(tp
);
11261 /* Reading the PHY ID register can conflict with ASF
11262 * firmware access to the PHY hardware.
11265 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11266 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
11267 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
11269 /* Now read the physical PHY_ID from the chip and verify
11270 * that it is sane. If it doesn't look good, we fall back
11271 * to either the hard-coded table based PHY_ID and failing
11272 * that the value found in the eeprom area.
11274 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
11275 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
11277 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
11278 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
11279 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
11281 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
11284 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
11285 tp
->phy_id
= hw_phy_id
;
11286 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
11287 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11289 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
11291 if (tp
->phy_id
!= PHY_ID_INVALID
) {
11292 /* Do nothing, phy ID already set up in
11293 * tg3_get_eeprom_hw_cfg().
11296 struct subsys_tbl_ent
*p
;
11298 /* No eeprom signature? Try the hardcoded
11299 * subsys device table.
11301 p
= lookup_by_subsys(tp
);
11305 tp
->phy_id
= p
->phy_id
;
11307 tp
->phy_id
== PHY_ID_BCM8002
)
11308 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11312 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
11313 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
11314 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
11315 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
11317 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
11318 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
11319 (bmsr
& BMSR_LSTATUS
))
11320 goto skip_phy_reset
;
11322 err
= tg3_phy_reset(tp
);
11326 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
11327 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
11328 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
11330 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
11331 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
11332 MII_TG3_CTRL_ADV_1000_FULL
);
11333 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
11334 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
11335 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
11336 MII_TG3_CTRL_ENABLE_AS_MASTER
);
11339 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
11340 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
11341 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
11342 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
11343 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11345 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11346 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11348 tg3_writephy(tp
, MII_BMCR
,
11349 BMCR_ANENABLE
| BMCR_ANRESTART
);
11351 tg3_phy_set_wirespeed(tp
);
11353 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11354 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11355 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11359 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
11360 err
= tg3_init_5401phy_dsp(tp
);
11365 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
11366 err
= tg3_init_5401phy_dsp(tp
);
11369 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
11370 tp
->link_config
.advertising
=
11371 (ADVERTISED_1000baseT_Half
|
11372 ADVERTISED_1000baseT_Full
|
11373 ADVERTISED_Autoneg
|
11375 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
11376 tp
->link_config
.advertising
&=
11377 ~(ADVERTISED_1000baseT_Half
|
11378 ADVERTISED_1000baseT_Full
);
11383 static void __devinit
tg3_read_partno(struct tg3
*tp
)
11385 unsigned char vpd_data
[256]; /* in little-endian format */
11389 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11390 tg3_nvram_read(tp
, 0x0, &magic
))
11391 goto out_not_found
;
11393 if (magic
== TG3_EEPROM_MAGIC
) {
11394 for (i
= 0; i
< 256; i
+= 4) {
11397 /* The data is in little-endian format in NVRAM.
11398 * Use the big-endian read routines to preserve
11399 * the byte order as it exists in NVRAM.
11401 if (tg3_nvram_read_be32(tp
, 0x100 + i
, &tmp
))
11402 goto out_not_found
;
11404 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
11409 vpd_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_VPD
);
11410 for (i
= 0; i
< 256; i
+= 4) {
11415 pci_write_config_word(tp
->pdev
, vpd_cap
+ PCI_VPD_ADDR
,
11417 while (j
++ < 100) {
11418 pci_read_config_word(tp
->pdev
, vpd_cap
+
11419 PCI_VPD_ADDR
, &tmp16
);
11420 if (tmp16
& 0x8000)
11424 if (!(tmp16
& 0x8000))
11425 goto out_not_found
;
11427 pci_read_config_dword(tp
->pdev
, vpd_cap
+ PCI_VPD_DATA
,
11429 v
= cpu_to_le32(tmp
);
11430 memcpy(&vpd_data
[i
], &v
, sizeof(v
));
11434 /* Now parse and find the part number. */
11435 for (i
= 0; i
< 254; ) {
11436 unsigned char val
= vpd_data
[i
];
11437 unsigned int block_end
;
11439 if (val
== 0x82 || val
== 0x91) {
11442 (vpd_data
[i
+ 2] << 8)));
11447 goto out_not_found
;
11449 block_end
= (i
+ 3 +
11451 (vpd_data
[i
+ 2] << 8)));
11454 if (block_end
> 256)
11455 goto out_not_found
;
11457 while (i
< (block_end
- 2)) {
11458 if (vpd_data
[i
+ 0] == 'P' &&
11459 vpd_data
[i
+ 1] == 'N') {
11460 int partno_len
= vpd_data
[i
+ 2];
11463 if (partno_len
> 24 || (partno_len
+ i
) > 256)
11464 goto out_not_found
;
11466 memcpy(tp
->board_part_number
,
11467 &vpd_data
[i
], partno_len
);
11472 i
+= 3 + vpd_data
[i
+ 2];
11475 /* Part number not found. */
11476 goto out_not_found
;
11480 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11481 strcpy(tp
->board_part_number
, "BCM95906");
11482 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11483 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
11484 strcpy(tp
->board_part_number
, "BCM57780");
11485 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11486 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
11487 strcpy(tp
->board_part_number
, "BCM57760");
11488 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11489 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
11490 strcpy(tp
->board_part_number
, "BCM57790");
11492 strcpy(tp
->board_part_number
, "none");
11495 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
11499 if (tg3_nvram_read(tp
, offset
, &val
) ||
11500 (val
& 0xfc000000) != 0x0c000000 ||
11501 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
11508 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
11510 u32 val
, offset
, start
, ver_offset
;
11512 bool newver
= false;
11514 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
11515 tg3_nvram_read(tp
, 0x4, &start
))
11518 offset
= tg3_nvram_logical_addr(tp
, offset
);
11520 if (tg3_nvram_read(tp
, offset
, &val
))
11523 if ((val
& 0xfc000000) == 0x0c000000) {
11524 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
11532 if (tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
11535 offset
= offset
+ ver_offset
- start
;
11536 for (i
= 0; i
< 16; i
+= 4) {
11538 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
11541 memcpy(tp
->fw_ver
+ i
, &v
, sizeof(v
));
11546 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
11549 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
11550 TG3_NVM_BCVER_MAJSFT
;
11551 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
11552 snprintf(&tp
->fw_ver
[0], 32, "v%d.%02d", major
, minor
);
11556 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
11558 u32 val
, major
, minor
;
11560 /* Use native endian representation */
11561 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
11564 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
11565 TG3_NVM_HWSB_CFG1_MAJSFT
;
11566 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
11567 TG3_NVM_HWSB_CFG1_MINSFT
;
11569 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
11572 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
11574 u32 offset
, major
, minor
, build
;
11576 tp
->fw_ver
[0] = 's';
11577 tp
->fw_ver
[1] = 'b';
11578 tp
->fw_ver
[2] = '\0';
11580 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
11583 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
11584 case TG3_EEPROM_SB_REVISION_0
:
11585 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
11587 case TG3_EEPROM_SB_REVISION_2
:
11588 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
11590 case TG3_EEPROM_SB_REVISION_3
:
11591 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
11597 if (tg3_nvram_read(tp
, offset
, &val
))
11600 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
11601 TG3_EEPROM_SB_EDH_BLD_SHFT
;
11602 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
11603 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
11604 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
11606 if (minor
> 99 || build
> 26)
11609 snprintf(&tp
->fw_ver
[2], 30, " v%d.%02d", major
, minor
);
11612 tp
->fw_ver
[8] = 'a' + build
- 1;
11613 tp
->fw_ver
[9] = '\0';
11617 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
11619 u32 val
, offset
, start
;
11622 for (offset
= TG3_NVM_DIR_START
;
11623 offset
< TG3_NVM_DIR_END
;
11624 offset
+= TG3_NVM_DIRENT_SIZE
) {
11625 if (tg3_nvram_read(tp
, offset
, &val
))
11628 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
11632 if (offset
== TG3_NVM_DIR_END
)
11635 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11636 start
= 0x08000000;
11637 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
11640 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
11641 !tg3_fw_img_is_valid(tp
, offset
) ||
11642 tg3_nvram_read(tp
, offset
+ 8, &val
))
11645 offset
+= val
- start
;
11647 vlen
= strlen(tp
->fw_ver
);
11649 tp
->fw_ver
[vlen
++] = ',';
11650 tp
->fw_ver
[vlen
++] = ' ';
11652 for (i
= 0; i
< 4; i
++) {
11654 if (tg3_nvram_read_be32(tp
, offset
, &v
))
11657 offset
+= sizeof(v
);
11659 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
11660 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
11664 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
11669 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
11674 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
11675 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
11678 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
11679 if (apedata
!= APE_SEG_SIG_MAGIC
)
11682 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
11683 if (!(apedata
& APE_FW_STATUS_READY
))
11686 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
11688 vlen
= strlen(tp
->fw_ver
);
11690 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
11691 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
11692 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
11693 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
11694 (apedata
& APE_FW_VERSION_BLDMSK
));
11697 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
11701 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
11702 tp
->fw_ver
[0] = 's';
11703 tp
->fw_ver
[1] = 'b';
11704 tp
->fw_ver
[2] = '\0';
11709 if (tg3_nvram_read(tp
, 0, &val
))
11712 if (val
== TG3_EEPROM_MAGIC
)
11713 tg3_read_bc_ver(tp
);
11714 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
11715 tg3_read_sb_ver(tp
, val
);
11716 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
11717 tg3_read_hwsb_ver(tp
);
11721 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11722 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
11725 tg3_read_mgmtfw_ver(tp
);
11727 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
11730 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
11732 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
11734 static struct pci_device_id write_reorder_chipsets
[] = {
11735 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11736 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
11737 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11738 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
11739 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
11740 PCI_DEVICE_ID_VIA_8385_0
) },
11744 u32 pci_state_reg
, grc_misc_cfg
;
11749 /* Force memory write invalidate off. If we leave it on,
11750 * then on 5700_BX chips we have to enable a workaround.
11751 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11752 * to match the cacheline size. The Broadcom driver have this
11753 * workaround but turns MWI off all the times so never uses
11754 * it. This seems to suggest that the workaround is insufficient.
11756 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11757 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
11758 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11760 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11761 * has the register indirect write enable bit set before
11762 * we try to access any of the MMIO registers. It is also
11763 * critical that the PCI-X hw workaround situation is decided
11764 * before that as well.
11766 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11769 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
11770 MISC_HOST_CTRL_CHIPREV_SHIFT
);
11771 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
11772 u32 prod_id_asic_rev
;
11774 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
11775 &prod_id_asic_rev
);
11776 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
11779 /* Wrong chip ID in 5752 A0. This code can be removed later
11780 * as A0 is not in production.
11782 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
11783 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
11785 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11786 * we need to disable memory and use config. cycles
11787 * only to access all registers. The 5702/03 chips
11788 * can mistakenly decode the special cycles from the
11789 * ICH chipsets as memory write cycles, causing corruption
11790 * of register and memory space. Only certain ICH bridges
11791 * will drive special cycles with non-zero data during the
11792 * address phase which can fall within the 5703's address
11793 * range. This is not an ICH bug as the PCI spec allows
11794 * non-zero address during special cycles. However, only
11795 * these ICH bridges are known to drive non-zero addresses
11796 * during special cycles.
11798 * Since special cycles do not cross PCI bridges, we only
11799 * enable this workaround if the 5703 is on the secondary
11800 * bus of these ICH bridges.
11802 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
11803 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
11804 static struct tg3_dev_id
{
11808 } ich_chipsets
[] = {
11809 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
11811 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
11813 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
11815 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
11819 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
11820 struct pci_dev
*bridge
= NULL
;
11822 while (pci_id
->vendor
!= 0) {
11823 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
11829 if (pci_id
->rev
!= PCI_ANY_ID
) {
11830 if (bridge
->revision
> pci_id
->rev
)
11833 if (bridge
->subordinate
&&
11834 (bridge
->subordinate
->number
==
11835 tp
->pdev
->bus
->number
)) {
11837 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
11838 pci_dev_put(bridge
);
11844 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
11845 static struct tg3_dev_id
{
11848 } bridge_chipsets
[] = {
11849 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
11850 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
11853 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
11854 struct pci_dev
*bridge
= NULL
;
11856 while (pci_id
->vendor
!= 0) {
11857 bridge
= pci_get_device(pci_id
->vendor
,
11864 if (bridge
->subordinate
&&
11865 (bridge
->subordinate
->number
<=
11866 tp
->pdev
->bus
->number
) &&
11867 (bridge
->subordinate
->subordinate
>=
11868 tp
->pdev
->bus
->number
)) {
11869 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
11870 pci_dev_put(bridge
);
11876 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11877 * DMA addresses > 40-bit. This bridge may have other additional
11878 * 57xx devices behind it in some 4-port NIC designs for example.
11879 * Any tg3 device found behind the bridge will also need the 40-bit
11882 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
11883 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
11884 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
11885 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
11886 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
11889 struct pci_dev
*bridge
= NULL
;
11892 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
11893 PCI_DEVICE_ID_SERVERWORKS_EPB
,
11895 if (bridge
&& bridge
->subordinate
&&
11896 (bridge
->subordinate
->number
<=
11897 tp
->pdev
->bus
->number
) &&
11898 (bridge
->subordinate
->subordinate
>=
11899 tp
->pdev
->bus
->number
)) {
11900 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
11901 pci_dev_put(bridge
);
11907 /* Initialize misc host control in PCI block. */
11908 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
11909 MISC_HOST_CTRL_CHIPREV
);
11910 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11911 tp
->misc_host_ctrl
);
11913 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
11914 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
))
11915 tp
->pdev_peer
= tg3_find_peer(tp
);
11917 /* Intentionally exclude ASIC_REV_5906 */
11918 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
11919 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11920 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11921 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11922 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
11923 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11924 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
11926 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
11927 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
11928 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
11929 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
11930 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
11931 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
11933 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
11934 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11935 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
11937 /* 5700 B0 chips do not support checksumming correctly due
11938 * to hardware bugs.
11940 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
11941 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
11943 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
11944 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
11945 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
11946 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
11949 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
11950 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
11951 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
11952 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
11953 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
11954 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
11955 tp
->pdev_peer
== tp
->pdev
))
11956 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
11958 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
11959 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11960 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
11961 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
11963 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
11964 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11966 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
11967 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
11971 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
11972 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
11973 tp
->tg3_flags2
|= TG3_FLG2_JUMBO_CAPABLE
;
11975 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
11978 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
11979 if (tp
->pcie_cap
!= 0) {
11982 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
11984 pcie_set_readrq(tp
->pdev
, 4096);
11986 pci_read_config_word(tp
->pdev
,
11987 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
11989 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
11990 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11991 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
11992 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11993 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11994 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11995 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
11997 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
11998 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
11999 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12000 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12001 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
12002 if (!tp
->pcix_cap
) {
12003 printk(KERN_ERR PFX
"Cannot find PCI-X "
12004 "capability, aborting.\n");
12008 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
12009 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
12012 /* If we have an AMD 762 or VIA K8T800 chipset, write
12013 * reordering to the mailbox registers done by the host
12014 * controller can cause major troubles. We read back from
12015 * every mailbox register write to force the writes to be
12016 * posted to the chip in order.
12018 if (pci_dev_present(write_reorder_chipsets
) &&
12019 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12020 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
12022 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
12023 &tp
->pci_cacheline_sz
);
12024 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12025 &tp
->pci_lat_timer
);
12026 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12027 tp
->pci_lat_timer
< 64) {
12028 tp
->pci_lat_timer
= 64;
12029 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12030 tp
->pci_lat_timer
);
12033 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
12034 /* 5700 BX chips need to have their TX producer index
12035 * mailboxes written twice to workaround a bug.
12037 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
12039 /* If we are in PCI-X mode, enable register write workaround.
12041 * The workaround is to use indirect register accesses
12042 * for all chip writes not to mailbox registers.
12044 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
12047 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12049 /* The chip can have it's power management PCI config
12050 * space registers clobbered due to this bug.
12051 * So explicitly force the chip into D0 here.
12053 pci_read_config_dword(tp
->pdev
,
12054 tp
->pm_cap
+ PCI_PM_CTRL
,
12056 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
12057 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
12058 pci_write_config_dword(tp
->pdev
,
12059 tp
->pm_cap
+ PCI_PM_CTRL
,
12062 /* Also, force SERR#/PERR# in PCI command. */
12063 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12064 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
12065 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12069 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
12070 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
12071 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
12072 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
12074 /* Chip-specific fixup from Broadcom driver */
12075 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
12076 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
12077 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
12078 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
12081 /* Default fast path register access methods */
12082 tp
->read32
= tg3_read32
;
12083 tp
->write32
= tg3_write32
;
12084 tp
->read32_mbox
= tg3_read32
;
12085 tp
->write32_mbox
= tg3_write32
;
12086 tp
->write32_tx_mbox
= tg3_write32
;
12087 tp
->write32_rx_mbox
= tg3_write32
;
12089 /* Various workaround register access methods */
12090 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
12091 tp
->write32
= tg3_write_indirect_reg32
;
12092 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
12093 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12094 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
12096 * Back to back register writes can cause problems on these
12097 * chips, the workaround is to read back all reg writes
12098 * except those to mailbox regs.
12100 * See tg3_write_indirect_reg32().
12102 tp
->write32
= tg3_write_flush_reg32
;
12106 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
12107 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
12108 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
12109 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
12110 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
12113 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
12114 tp
->read32
= tg3_read_indirect_reg32
;
12115 tp
->write32
= tg3_write_indirect_reg32
;
12116 tp
->read32_mbox
= tg3_read_indirect_mbox
;
12117 tp
->write32_mbox
= tg3_write_indirect_mbox
;
12118 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
12119 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
12124 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12125 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
12126 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12128 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12129 tp
->read32_mbox
= tg3_read32_mbox_5906
;
12130 tp
->write32_mbox
= tg3_write32_mbox_5906
;
12131 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
12132 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
12135 if (tp
->write32
== tg3_write_indirect_reg32
||
12136 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12137 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12138 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
12139 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
12141 /* Get eeprom hw config before calling tg3_set_power_state().
12142 * In particular, the TG3_FLG2_IS_NIC flag must be
12143 * determined before calling tg3_set_power_state() so that
12144 * we know whether or not to switch out of Vaux power.
12145 * When the flag is set, it means that GPIO1 is used for eeprom
12146 * write protect and also implies that it is a LOM where GPIOs
12147 * are not used to switch power.
12149 tg3_get_eeprom_hw_cfg(tp
);
12151 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
12152 /* Allow reads and writes to the
12153 * APE register and memory space.
12155 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
12156 PCISTATE_ALLOW_APE_SHMEM_WR
;
12157 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12161 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12162 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12163 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12164 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12165 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
12167 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12168 * GPIO1 driven high will bring 5700's external PHY out of reset.
12169 * It is also used as eeprom write protect on LOMs.
12171 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
12172 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12173 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
12174 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
12175 GRC_LCLCTRL_GPIO_OUTPUT1
);
12176 /* Unused GPIO3 must be driven as output on 5752 because there
12177 * are no pull-up resistors on unused GPIO pins.
12179 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12180 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
12182 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12183 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12184 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12186 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
) {
12187 /* Turn off the debug UART. */
12188 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12189 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
12190 /* Keep VMain power. */
12191 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
12192 GRC_LCLCTRL_GPIO_OUTPUT0
;
12195 /* Force the chip into D0. */
12196 err
= tg3_set_power_state(tp
, PCI_D0
);
12198 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
12199 pci_name(tp
->pdev
));
12203 /* Derive initial jumbo mode from MTU assigned in
12204 * ether_setup() via the alloc_etherdev() call
12206 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
12207 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12208 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
12210 /* Determine WakeOnLan speed to use. */
12211 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12212 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12213 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
12214 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
12215 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
12217 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
12220 /* A few boards don't want Ethernet@WireSpeed phy feature */
12221 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12222 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
12223 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
12224 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
12225 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) ||
12226 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
12227 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
12229 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
12230 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
12231 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
12232 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
12233 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
12235 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
12236 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
&&
12237 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12238 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
) {
12239 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12240 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12241 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12242 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
12243 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
12244 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
12245 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
12246 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
12247 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
12249 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
12252 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12253 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
12254 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
12255 if (tp
->phy_otp
== 0)
12256 tp
->phy_otp
= TG3_OTP_DEFAULT
;
12259 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
12260 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
12262 tp
->mi_mode
= MAC_MI_MODE_BASE
;
12264 tp
->coalesce_mode
= 0;
12265 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
12266 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
12267 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
12269 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12270 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12271 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
12273 err
= tg3_mdio_init(tp
);
12277 /* Initialize data/descriptor byte/word swapping. */
12278 val
= tr32(GRC_MODE
);
12279 val
&= GRC_MODE_HOST_STACKUP
;
12280 tw32(GRC_MODE
, val
| tp
->grc_mode
);
12282 tg3_switch_clocks(tp
);
12284 /* Clear this out for sanity. */
12285 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12287 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12289 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
12290 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
12291 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
12293 if (chiprevid
== CHIPREV_ID_5701_A0
||
12294 chiprevid
== CHIPREV_ID_5701_B0
||
12295 chiprevid
== CHIPREV_ID_5701_B2
||
12296 chiprevid
== CHIPREV_ID_5701_B5
) {
12297 void __iomem
*sram_base
;
12299 /* Write some dummy words into the SRAM status block
12300 * area, see if it reads back correctly. If the return
12301 * value is bad, force enable the PCIX workaround.
12303 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
12305 writel(0x00000000, sram_base
);
12306 writel(0x00000000, sram_base
+ 4);
12307 writel(0xffffffff, sram_base
+ 4);
12308 if (readl(sram_base
) != 0x00000000)
12309 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12314 tg3_nvram_init(tp
);
12316 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
12317 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
12319 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12320 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
12321 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
12322 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
12324 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
12325 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
12326 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
12327 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
12328 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
12329 HOSTCC_MODE_CLRTICK_TXBD
);
12331 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
12332 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12333 tp
->misc_host_ctrl
);
12336 /* Preserve the APE MAC_MODE bits */
12337 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
12338 tp
->mac_mode
= tr32(MAC_MODE
) |
12339 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
12341 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
12343 /* these are limited to 10/100 only */
12344 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12345 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
12346 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12347 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12348 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
12349 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
12350 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
12351 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12352 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
12353 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
12354 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
12355 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
12356 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12357 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
12359 err
= tg3_phy_probe(tp
);
12361 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
12362 pci_name(tp
->pdev
), err
);
12363 /* ... but do not return immediately ... */
12367 tg3_read_partno(tp
);
12368 tg3_read_fw_ver(tp
);
12370 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
12371 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12373 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12374 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
12376 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12379 /* 5700 {AX,BX} chips have a broken status block link
12380 * change bit implementation, so we must use the
12381 * status register in those cases.
12383 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12384 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
12386 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
12388 /* The led_ctrl is set during tg3_phy_probe, here we might
12389 * have to force the link status polling mechanism based
12390 * upon subsystem IDs.
12392 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
12393 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12394 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
12395 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
12396 TG3_FLAG_USE_LINKCHG_REG
);
12399 /* For all SERDES we poll the MAC status register. */
12400 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
12401 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
12403 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
12405 tp
->rx_offset
= NET_IP_ALIGN
;
12406 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12407 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
12410 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
12412 /* Increment the rx prod index on the rx std ring by at most
12413 * 8 for these chips to workaround hw errata.
12415 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12416 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12417 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12418 tp
->rx_std_max_post
= 8;
12420 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
12421 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
12422 PCIE_PWR_MGMT_L1_THRESH_MSK
;
12427 #ifdef CONFIG_SPARC
12428 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
12430 struct net_device
*dev
= tp
->dev
;
12431 struct pci_dev
*pdev
= tp
->pdev
;
12432 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
12433 const unsigned char *addr
;
12436 addr
= of_get_property(dp
, "local-mac-address", &len
);
12437 if (addr
&& len
== 6) {
12438 memcpy(dev
->dev_addr
, addr
, 6);
12439 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
12445 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
12447 struct net_device
*dev
= tp
->dev
;
12449 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
12450 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
12455 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
12457 struct net_device
*dev
= tp
->dev
;
12458 u32 hi
, lo
, mac_offset
;
12461 #ifdef CONFIG_SPARC
12462 if (!tg3_get_macaddr_sparc(tp
))
12467 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12468 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12469 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
12471 if (tg3_nvram_lock(tp
))
12472 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
12474 tg3_nvram_unlock(tp
);
12476 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12479 /* First try to get it from MAC address mailbox. */
12480 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
12481 if ((hi
>> 16) == 0x484b) {
12482 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12483 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
12485 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
12486 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12487 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12488 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12489 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
12491 /* Some old bootcode may report a 0 MAC address in SRAM */
12492 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
12495 /* Next, try NVRAM. */
12496 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
12497 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
12498 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
12499 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
12500 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
12502 /* Finally just fetch it out of the MAC control regs. */
12504 hi
= tr32(MAC_ADDR_0_HIGH
);
12505 lo
= tr32(MAC_ADDR_0_LOW
);
12507 dev
->dev_addr
[5] = lo
& 0xff;
12508 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12509 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12510 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12511 dev
->dev_addr
[1] = hi
& 0xff;
12512 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12516 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
12517 #ifdef CONFIG_SPARC
12518 if (!tg3_get_default_macaddr_sparc(tp
))
12523 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
12527 #define BOUNDARY_SINGLE_CACHELINE 1
12528 #define BOUNDARY_MULTI_CACHELINE 2
12530 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
12532 int cacheline_size
;
12536 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
12538 cacheline_size
= 1024;
12540 cacheline_size
= (int) byte
* 4;
12542 /* On 5703 and later chips, the boundary bits have no
12545 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12546 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
12547 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12550 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12551 goal
= BOUNDARY_MULTI_CACHELINE
;
12553 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12554 goal
= BOUNDARY_SINGLE_CACHELINE
;
12563 /* PCI controllers on most RISC systems tend to disconnect
12564 * when a device tries to burst across a cache-line boundary.
12565 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12567 * Unfortunately, for PCI-E there are only limited
12568 * write-side controls for this, and thus for reads
12569 * we will still get the disconnects. We'll also waste
12570 * these PCI cycles for both read and write for chips
12571 * other than 5700 and 5701 which do not implement the
12574 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12575 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
12576 switch (cacheline_size
) {
12581 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12582 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
12583 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
12585 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12586 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12591 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
12592 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
12596 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12597 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12600 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12601 switch (cacheline_size
) {
12605 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12606 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12607 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
12613 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12614 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
12618 switch (cacheline_size
) {
12620 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12621 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
12622 DMA_RWCTRL_WRITE_BNDRY_16
);
12627 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12628 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
12629 DMA_RWCTRL_WRITE_BNDRY_32
);
12634 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12635 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
12636 DMA_RWCTRL_WRITE_BNDRY_64
);
12641 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12642 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
12643 DMA_RWCTRL_WRITE_BNDRY_128
);
12648 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
12649 DMA_RWCTRL_WRITE_BNDRY_256
);
12652 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
12653 DMA_RWCTRL_WRITE_BNDRY_512
);
12657 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
12658 DMA_RWCTRL_WRITE_BNDRY_1024
);
12667 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
12669 struct tg3_internal_buffer_desc test_desc
;
12670 u32 sram_dma_descs
;
12673 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
12675 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
12676 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
12677 tw32(RDMAC_STATUS
, 0);
12678 tw32(WDMAC_STATUS
, 0);
12680 tw32(BUFMGR_MODE
, 0);
12681 tw32(FTQ_RESET
, 0);
12683 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
12684 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
12685 test_desc
.nic_mbuf
= 0x00002100;
12686 test_desc
.len
= size
;
12689 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12690 * the *second* time the tg3 driver was getting loaded after an
12693 * Broadcom tells me:
12694 * ...the DMA engine is connected to the GRC block and a DMA
12695 * reset may affect the GRC block in some unpredictable way...
12696 * The behavior of resets to individual blocks has not been tested.
12698 * Broadcom noted the GRC reset will also reset all sub-components.
12701 test_desc
.cqid_sqid
= (13 << 8) | 2;
12703 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
12706 test_desc
.cqid_sqid
= (16 << 8) | 7;
12708 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
12711 test_desc
.flags
= 0x00000005;
12713 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
12716 val
= *(((u32
*)&test_desc
) + i
);
12717 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
12718 sram_dma_descs
+ (i
* sizeof(u32
)));
12719 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
12721 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12724 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
12726 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
12730 for (i
= 0; i
< 40; i
++) {
12734 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
12736 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
12737 if ((val
& 0xffff) == sram_dma_descs
) {
12748 #define TEST_BUFFER_SIZE 0x2000
12750 static int __devinit
tg3_test_dma(struct tg3
*tp
)
12752 dma_addr_t buf_dma
;
12753 u32
*buf
, saved_dma_rwctrl
;
12756 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
12762 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
12763 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
12765 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
12767 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12768 /* DMA read watermark not used on PCIE */
12769 tp
->dma_rwctrl
|= 0x00180000;
12770 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
12771 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
12772 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
12773 tp
->dma_rwctrl
|= 0x003f0000;
12775 tp
->dma_rwctrl
|= 0x003f000f;
12777 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
12778 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
12779 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
12780 u32 read_water
= 0x7;
12782 /* If the 5704 is behind the EPB bridge, we can
12783 * do the less restrictive ONE_DMA workaround for
12784 * better performance.
12786 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
12787 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
12788 tp
->dma_rwctrl
|= 0x8000;
12789 else if (ccval
== 0x6 || ccval
== 0x7)
12790 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
12792 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
12794 /* Set bit 23 to enable PCIX hw bug fix */
12796 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
12797 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
12799 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
12800 /* 5780 always in PCIX mode */
12801 tp
->dma_rwctrl
|= 0x00144000;
12802 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12803 /* 5714 always in PCIX mode */
12804 tp
->dma_rwctrl
|= 0x00148000;
12806 tp
->dma_rwctrl
|= 0x001b000f;
12810 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
12811 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
12812 tp
->dma_rwctrl
&= 0xfffffff0;
12814 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12815 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
12816 /* Remove this if it causes problems for some boards. */
12817 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
12819 /* On 5700/5701 chips, we need to set this bit.
12820 * Otherwise the chip will issue cacheline transactions
12821 * to streamable DMA memory with not all the byte
12822 * enables turned on. This is an error on several
12823 * RISC PCI controllers, in particular sparc64.
12825 * On 5703/5704 chips, this bit has been reassigned
12826 * a different meaning. In particular, it is used
12827 * on those chips to enable a PCI-X workaround.
12829 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
12832 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12835 /* Unneeded, already done by tg3_get_invariants. */
12836 tg3_switch_clocks(tp
);
12840 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12841 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
12844 /* It is best to perform DMA test with maximum write burst size
12845 * to expose the 5700/5701 write DMA bug.
12847 saved_dma_rwctrl
= tp
->dma_rwctrl
;
12848 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12849 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12854 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
12857 /* Send the buffer to the chip. */
12858 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
12860 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
12865 /* validate data reached card RAM correctly. */
12866 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
12868 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
12869 if (le32_to_cpu(val
) != p
[i
]) {
12870 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
12871 /* ret = -ENODEV here? */
12876 /* Now read it back. */
12877 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
12879 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
12885 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
12889 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
12890 DMA_RWCTRL_WRITE_BNDRY_16
) {
12891 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12892 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
12893 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12896 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
12902 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
12908 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
12909 DMA_RWCTRL_WRITE_BNDRY_16
) {
12910 static struct pci_device_id dma_wait_state_chipsets
[] = {
12911 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
12912 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
12916 /* DMA test passed without adjusting DMA boundary,
12917 * now look for chipsets that are known to expose the
12918 * DMA bug without failing the test.
12920 if (pci_dev_present(dma_wait_state_chipsets
)) {
12921 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12922 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
12925 /* Safe to use the calculated DMA boundary. */
12926 tp
->dma_rwctrl
= saved_dma_rwctrl
;
12928 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12932 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
12937 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
12939 tp
->link_config
.advertising
=
12940 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12941 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12942 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
12943 ADVERTISED_Autoneg
| ADVERTISED_MII
);
12944 tp
->link_config
.speed
= SPEED_INVALID
;
12945 tp
->link_config
.duplex
= DUPLEX_INVALID
;
12946 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
12947 tp
->link_config
.active_speed
= SPEED_INVALID
;
12948 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
12949 tp
->link_config
.phy_is_low_power
= 0;
12950 tp
->link_config
.orig_speed
= SPEED_INVALID
;
12951 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
12952 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
12955 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
12957 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
12958 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
12959 DEFAULT_MB_RDMA_LOW_WATER_5705
;
12960 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12961 DEFAULT_MB_MACRX_LOW_WATER_5705
;
12962 tp
->bufmgr_config
.mbuf_high_water
=
12963 DEFAULT_MB_HIGH_WATER_5705
;
12964 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12965 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12966 DEFAULT_MB_MACRX_LOW_WATER_5906
;
12967 tp
->bufmgr_config
.mbuf_high_water
=
12968 DEFAULT_MB_HIGH_WATER_5906
;
12971 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
12972 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
12973 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
12974 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
12975 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
12976 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
12978 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
12979 DEFAULT_MB_RDMA_LOW_WATER
;
12980 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12981 DEFAULT_MB_MACRX_LOW_WATER
;
12982 tp
->bufmgr_config
.mbuf_high_water
=
12983 DEFAULT_MB_HIGH_WATER
;
12985 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
12986 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
12987 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
12988 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
12989 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
12990 DEFAULT_MB_HIGH_WATER_JUMBO
;
12993 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
12994 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
12997 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
12999 switch (tp
->phy_id
& PHY_ID_MASK
) {
13000 case PHY_ID_BCM5400
: return "5400";
13001 case PHY_ID_BCM5401
: return "5401";
13002 case PHY_ID_BCM5411
: return "5411";
13003 case PHY_ID_BCM5701
: return "5701";
13004 case PHY_ID_BCM5703
: return "5703";
13005 case PHY_ID_BCM5704
: return "5704";
13006 case PHY_ID_BCM5705
: return "5705";
13007 case PHY_ID_BCM5750
: return "5750";
13008 case PHY_ID_BCM5752
: return "5752";
13009 case PHY_ID_BCM5714
: return "5714";
13010 case PHY_ID_BCM5780
: return "5780";
13011 case PHY_ID_BCM5755
: return "5755";
13012 case PHY_ID_BCM5787
: return "5787";
13013 case PHY_ID_BCM5784
: return "5784";
13014 case PHY_ID_BCM5756
: return "5722/5756";
13015 case PHY_ID_BCM5906
: return "5906";
13016 case PHY_ID_BCM5761
: return "5761";
13017 case PHY_ID_BCM8002
: return "8002/serdes";
13018 case 0: return "serdes";
13019 default: return "unknown";
13023 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
13025 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13026 strcpy(str
, "PCI Express");
13028 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13029 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
13031 strcpy(str
, "PCIX:");
13033 if ((clock_ctrl
== 7) ||
13034 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
13035 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
13036 strcat(str
, "133MHz");
13037 else if (clock_ctrl
== 0)
13038 strcat(str
, "33MHz");
13039 else if (clock_ctrl
== 2)
13040 strcat(str
, "50MHz");
13041 else if (clock_ctrl
== 4)
13042 strcat(str
, "66MHz");
13043 else if (clock_ctrl
== 6)
13044 strcat(str
, "100MHz");
13046 strcpy(str
, "PCI:");
13047 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
13048 strcat(str
, "66MHz");
13050 strcat(str
, "33MHz");
13052 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
13053 strcat(str
, ":32-bit");
13055 strcat(str
, ":64-bit");
13059 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
13061 struct pci_dev
*peer
;
13062 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
13064 for (func
= 0; func
< 8; func
++) {
13065 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
13066 if (peer
&& peer
!= tp
->pdev
)
13070 /* 5704 can be configured in single-port mode, set peer to
13071 * tp->pdev in that case.
13079 * We don't need to keep the refcount elevated; there's no way
13080 * to remove one half of this device without removing the other
13087 static void __devinit
tg3_init_coal(struct tg3
*tp
)
13089 struct ethtool_coalesce
*ec
= &tp
->coal
;
13091 memset(ec
, 0, sizeof(*ec
));
13092 ec
->cmd
= ETHTOOL_GCOALESCE
;
13093 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
13094 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
13095 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
13096 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
13097 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
13098 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
13099 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
13100 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
13101 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
13103 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
13104 HOSTCC_MODE_CLRTICK_TXBD
)) {
13105 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
13106 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
13107 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
13108 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
13111 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13112 ec
->rx_coalesce_usecs_irq
= 0;
13113 ec
->tx_coalesce_usecs_irq
= 0;
13114 ec
->stats_block_coalesce_usecs
= 0;
13118 static const struct net_device_ops tg3_netdev_ops
= {
13119 .ndo_open
= tg3_open
,
13120 .ndo_stop
= tg3_close
,
13121 .ndo_start_xmit
= tg3_start_xmit
,
13122 .ndo_get_stats
= tg3_get_stats
,
13123 .ndo_validate_addr
= eth_validate_addr
,
13124 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13125 .ndo_set_mac_address
= tg3_set_mac_addr
,
13126 .ndo_do_ioctl
= tg3_ioctl
,
13127 .ndo_tx_timeout
= tg3_tx_timeout
,
13128 .ndo_change_mtu
= tg3_change_mtu
,
13129 #if TG3_VLAN_TAG_USED
13130 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13132 #ifdef CONFIG_NET_POLL_CONTROLLER
13133 .ndo_poll_controller
= tg3_poll_controller
,
13137 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
13138 .ndo_open
= tg3_open
,
13139 .ndo_stop
= tg3_close
,
13140 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
13141 .ndo_get_stats
= tg3_get_stats
,
13142 .ndo_validate_addr
= eth_validate_addr
,
13143 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13144 .ndo_set_mac_address
= tg3_set_mac_addr
,
13145 .ndo_do_ioctl
= tg3_ioctl
,
13146 .ndo_tx_timeout
= tg3_tx_timeout
,
13147 .ndo_change_mtu
= tg3_change_mtu
,
13148 #if TG3_VLAN_TAG_USED
13149 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13151 #ifdef CONFIG_NET_POLL_CONTROLLER
13152 .ndo_poll_controller
= tg3_poll_controller
,
13156 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
13157 const struct pci_device_id
*ent
)
13159 static int tg3_version_printed
= 0;
13160 struct net_device
*dev
;
13164 u64 dma_mask
, persist_dma_mask
;
13166 if (tg3_version_printed
++ == 0)
13167 printk(KERN_INFO
"%s", version
);
13169 err
= pci_enable_device(pdev
);
13171 printk(KERN_ERR PFX
"Cannot enable PCI device, "
13176 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13178 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
13180 goto err_out_disable_pdev
;
13183 pci_set_master(pdev
);
13185 /* Find power-management capability. */
13186 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
13188 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
13191 goto err_out_free_res
;
13194 dev
= alloc_etherdev(sizeof(*tp
));
13196 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
13198 goto err_out_free_res
;
13201 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13203 #if TG3_VLAN_TAG_USED
13204 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
13207 tp
= netdev_priv(dev
);
13210 tp
->pm_cap
= pm_cap
;
13211 tp
->rx_mode
= TG3_DEF_RX_MODE
;
13212 tp
->tx_mode
= TG3_DEF_TX_MODE
;
13215 tp
->msg_enable
= tg3_debug
;
13217 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
13219 /* The word/byte swap controls here control register access byte
13220 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13223 tp
->misc_host_ctrl
=
13224 MISC_HOST_CTRL_MASK_PCI_INT
|
13225 MISC_HOST_CTRL_WORD_SWAP
|
13226 MISC_HOST_CTRL_INDIR_ACCESS
|
13227 MISC_HOST_CTRL_PCISTATE_RW
;
13229 /* The NONFRM (non-frame) byte/word swap controls take effect
13230 * on descriptor entries, anything which isn't packet data.
13232 * The StrongARM chips on the board (one for tx, one for rx)
13233 * are running in big-endian mode.
13235 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
13236 GRC_MODE_WSWAP_NONFRM_DATA
);
13237 #ifdef __BIG_ENDIAN
13238 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
13240 spin_lock_init(&tp
->lock
);
13241 spin_lock_init(&tp
->indirect_lock
);
13242 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
13244 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
13246 printk(KERN_ERR PFX
"Cannot map device registers, "
13249 goto err_out_free_dev
;
13252 tg3_init_link_config(tp
);
13254 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
13255 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
13256 tp
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
13258 netif_napi_add(dev
, &tp
->napi
, tg3_poll
, 64);
13259 dev
->ethtool_ops
= &tg3_ethtool_ops
;
13260 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
13261 dev
->irq
= pdev
->irq
;
13263 err
= tg3_get_invariants(tp
);
13265 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
13267 goto err_out_iounmap
;
13270 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13271 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13272 dev
->netdev_ops
= &tg3_netdev_ops
;
13274 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
13277 /* The EPB bridge inside 5714, 5715, and 5780 and any
13278 * device behind the EPB cannot support DMA addresses > 40-bit.
13279 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13280 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13281 * do DMA address check in tg3_start_xmit().
13283 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
13284 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
13285 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
13286 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
13287 #ifdef CONFIG_HIGHMEM
13288 dma_mask
= DMA_BIT_MASK(64);
13291 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
13293 /* Configure DMA attributes. */
13294 if (dma_mask
> DMA_BIT_MASK(32)) {
13295 err
= pci_set_dma_mask(pdev
, dma_mask
);
13297 dev
->features
|= NETIF_F_HIGHDMA
;
13298 err
= pci_set_consistent_dma_mask(pdev
,
13301 printk(KERN_ERR PFX
"Unable to obtain 64 bit "
13302 "DMA for consistent allocations\n");
13303 goto err_out_iounmap
;
13307 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
13308 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
13310 printk(KERN_ERR PFX
"No usable DMA configuration, "
13312 goto err_out_iounmap
;
13316 tg3_init_bufmgr_config(tp
);
13318 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
13319 tp
->fw_needed
= FIRMWARE_TG3
;
13321 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13322 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
13324 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13325 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13326 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
13327 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13328 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
13329 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
13331 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
;
13332 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13333 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13335 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13338 /* TSO is on by default on chips that support hardware TSO.
13339 * Firmware TSO on older chips gives lower performance, so it
13340 * is off by default, but can be enabled using ethtool.
13342 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13343 if (dev
->features
& NETIF_F_IP_CSUM
)
13344 dev
->features
|= NETIF_F_TSO
;
13345 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
13346 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
))
13347 dev
->features
|= NETIF_F_TSO6
;
13348 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13349 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13350 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
13351 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13352 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13353 dev
->features
|= NETIF_F_TSO_ECN
;
13357 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
13358 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
13359 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
13360 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
13361 tp
->rx_pending
= 63;
13364 err
= tg3_get_device_address(tp
);
13366 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
13371 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13372 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
13373 if (!tp
->aperegs
) {
13374 printk(KERN_ERR PFX
"Cannot map APE registers, "
13380 tg3_ape_lock_init(tp
);
13382 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
13383 tg3_read_dash_ver(tp
);
13387 * Reset chip in case UNDI or EFI driver did not shutdown
13388 * DMA self test will enable WDMAC and we'll see (spurious)
13389 * pending DMA on the PCI bus at that point.
13391 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
13392 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
13393 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
13394 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13397 err
= tg3_test_dma(tp
);
13399 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
13400 goto err_out_apeunmap
;
13403 /* flow control autonegotiation is default behavior */
13404 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
13405 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
13409 pci_set_drvdata(pdev
, dev
);
13411 err
= register_netdev(dev
);
13413 printk(KERN_ERR PFX
"Cannot register net device, "
13415 goto err_out_apeunmap
;
13418 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13420 tp
->board_part_number
,
13421 tp
->pci_chip_rev_id
,
13422 tg3_bus_string(tp
, str
),
13425 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
13427 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13429 tp
->mdio_bus
->phy_map
[PHY_ADDR
]->drv
->name
,
13430 dev_name(&tp
->mdio_bus
->phy_map
[PHY_ADDR
]->dev
));
13433 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13434 tp
->dev
->name
, tg3_phy_string(tp
),
13435 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
13436 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
13437 "10/100/1000Base-T")),
13438 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
13440 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13442 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
13443 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
13444 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
13445 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
13446 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
13447 printk(KERN_INFO
"%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13448 dev
->name
, tp
->dma_rwctrl
,
13449 (pdev
->dma_mask
== DMA_BIT_MASK(32)) ? 32 :
13450 (((u64
) pdev
->dma_mask
== DMA_BIT_MASK(40)) ? 40 : 64));
13456 iounmap(tp
->aperegs
);
13457 tp
->aperegs
= NULL
;
13462 release_firmware(tp
->fw
);
13474 pci_release_regions(pdev
);
13476 err_out_disable_pdev
:
13477 pci_disable_device(pdev
);
13478 pci_set_drvdata(pdev
, NULL
);
13482 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
13484 struct net_device
*dev
= pci_get_drvdata(pdev
);
13487 struct tg3
*tp
= netdev_priv(dev
);
13490 release_firmware(tp
->fw
);
13492 flush_scheduled_work();
13494 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
13499 unregister_netdev(dev
);
13501 iounmap(tp
->aperegs
);
13502 tp
->aperegs
= NULL
;
13509 pci_release_regions(pdev
);
13510 pci_disable_device(pdev
);
13511 pci_set_drvdata(pdev
, NULL
);
13515 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
13517 struct net_device
*dev
= pci_get_drvdata(pdev
);
13518 struct tg3
*tp
= netdev_priv(dev
);
13519 pci_power_t target_state
;
13522 /* PCI register 4 needs to be saved whether netif_running() or not.
13523 * MSI address and data need to be saved if using MSI and
13526 pci_save_state(pdev
);
13528 if (!netif_running(dev
))
13531 flush_scheduled_work();
13533 tg3_netif_stop(tp
);
13535 del_timer_sync(&tp
->timer
);
13537 tg3_full_lock(tp
, 1);
13538 tg3_disable_ints(tp
);
13539 tg3_full_unlock(tp
);
13541 netif_device_detach(dev
);
13543 tg3_full_lock(tp
, 0);
13544 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13545 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
13546 tg3_full_unlock(tp
);
13548 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
13550 err
= tg3_set_power_state(tp
, target_state
);
13554 tg3_full_lock(tp
, 0);
13556 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13557 err2
= tg3_restart_hw(tp
, 1);
13561 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13562 add_timer(&tp
->timer
);
13564 netif_device_attach(dev
);
13565 tg3_netif_start(tp
);
13568 tg3_full_unlock(tp
);
13577 static int tg3_resume(struct pci_dev
*pdev
)
13579 struct net_device
*dev
= pci_get_drvdata(pdev
);
13580 struct tg3
*tp
= netdev_priv(dev
);
13583 pci_restore_state(tp
->pdev
);
13585 if (!netif_running(dev
))
13588 err
= tg3_set_power_state(tp
, PCI_D0
);
13592 netif_device_attach(dev
);
13594 tg3_full_lock(tp
, 0);
13596 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13597 err
= tg3_restart_hw(tp
, 1);
13601 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13602 add_timer(&tp
->timer
);
13604 tg3_netif_start(tp
);
13607 tg3_full_unlock(tp
);
13615 static struct pci_driver tg3_driver
= {
13616 .name
= DRV_MODULE_NAME
,
13617 .id_table
= tg3_pci_tbl
,
13618 .probe
= tg3_init_one
,
13619 .remove
= __devexit_p(tg3_remove_one
),
13620 .suspend
= tg3_suspend
,
13621 .resume
= tg3_resume
13624 static int __init
tg3_init(void)
13626 return pci_register_driver(&tg3_driver
);
13629 static void __exit
tg3_cleanup(void)
13631 pci_unregister_driver(&tg3_driver
);
13634 module_init(tg3_init
);
13635 module_exit(tg3_cleanup
);