1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
15 #ifdef CONFIG_X86_LOCAL_APIC
16 #include <asm/mpspec.h>
18 #include <mach_apic.h>
23 DEFINE_PER_CPU(struct Xgt_desc_struct
, cpu_gdt_descr
);
24 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr
);
26 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack
[CPU_16BIT_STACK_SIZE
]);
27 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack
);
29 static int cachesize_override __cpuinitdata
= -1;
30 static int disable_x86_fxsr __cpuinitdata
;
31 static int disable_x86_serial_nr __cpuinitdata
= 1;
32 static int disable_x86_sep __cpuinitdata
;
34 struct cpu_dev
* cpu_devs
[X86_VENDOR_NUM
] = {};
36 extern int disable_pse
;
38 static void default_init(struct cpuinfo_x86
* c
)
40 /* Not much we can do here... */
41 /* Check if at least it has cpuid */
42 if (c
->cpuid_level
== -1) {
43 /* No cpuid. It must be an ancient CPU */
45 strcpy(c
->x86_model_id
, "486");
47 strcpy(c
->x86_model_id
, "386");
51 static struct cpu_dev default_cpu
= {
52 .c_init
= default_init
,
53 .c_vendor
= "Unknown",
55 static struct cpu_dev
* this_cpu
= &default_cpu
;
57 static int __init
cachesize_setup(char *str
)
59 get_option (&str
, &cachesize_override
);
62 __setup("cachesize=", cachesize_setup
);
64 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
69 if (cpuid_eax(0x80000000) < 0x80000004)
72 v
= (unsigned int *) c
->x86_model_id
;
73 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
74 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
75 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
76 c
->x86_model_id
[48] = 0;
78 /* Intel chips right-justify this string for some dumb reason;
79 undo that brain damage */
80 p
= q
= &c
->x86_model_id
[0];
86 while ( q
<= &c
->x86_model_id
[48] )
87 *q
++ = '\0'; /* Zero-pad the rest */
94 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
96 unsigned int n
, dummy
, ecx
, edx
, l2size
;
98 n
= cpuid_eax(0x80000000);
100 if (n
>= 0x80000005) {
101 cpuid(0x80000005, &dummy
, &dummy
, &ecx
, &edx
);
102 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
103 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
104 c
->x86_cache_size
=(ecx
>>24)+(edx
>>24);
107 if (n
< 0x80000006) /* Some chips just has a large L1. */
110 ecx
= cpuid_ecx(0x80000006);
113 /* do processor-specific cache resizing */
114 if (this_cpu
->c_size_cache
)
115 l2size
= this_cpu
->c_size_cache(c
,l2size
);
117 /* Allow user to override all this if necessary. */
118 if (cachesize_override
!= -1)
119 l2size
= cachesize_override
;
122 return; /* Again, no L2 cache is possible */
124 c
->x86_cache_size
= l2size
;
126 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
130 /* Naming convention should be: <Name> [(<Codename>)] */
131 /* This table only is used unless init_<vendor>() below doesn't set it; */
132 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
134 /* Look up CPU names by table lookup. */
135 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
137 struct cpu_model_info
*info
;
139 if ( c
->x86_model
>= 16 )
140 return NULL
; /* Range check */
145 info
= this_cpu
->c_models
;
147 while (info
&& info
->family
) {
148 if (info
->family
== c
->x86
)
149 return info
->model_names
[c
->x86_model
];
152 return NULL
; /* Not found */
156 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
, int early
)
158 char *v
= c
->x86_vendor_id
;
162 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
164 if (!strcmp(v
,cpu_devs
[i
]->c_ident
[0]) ||
165 (cpu_devs
[i
]->c_ident
[1] &&
166 !strcmp(v
,cpu_devs
[i
]->c_ident
[1]))) {
169 this_cpu
= cpu_devs
[i
];
176 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
177 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
179 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
180 this_cpu
= &default_cpu
;
184 static int __init
x86_fxsr_setup(char * s
)
186 disable_x86_fxsr
= 1;
189 __setup("nofxsr", x86_fxsr_setup
);
192 static int __init
x86_sep_setup(char * s
)
197 __setup("nosep", x86_sep_setup
);
200 /* Standard macro to see if a specific flag is changeable */
201 static inline int flag_is_changeable_p(u32 flag
)
215 : "=&r" (f1
), "=&r" (f2
)
218 return ((f1
^f2
) & flag
) != 0;
222 /* Probe for the CPUID instruction */
223 static int __cpuinit
have_cpuid_p(void)
225 return flag_is_changeable_p(X86_EFLAGS_ID
);
228 /* Do minimum CPU detection early.
229 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
230 The others are not touched to avoid unwanted side effects.
232 WARNING: this function is only called on the BP. Don't add code here
233 that is supposed to run on all CPUs. */
234 static void __init
early_cpu_detect(void)
236 struct cpuinfo_x86
*c
= &boot_cpu_data
;
238 c
->x86_cache_alignment
= 32;
243 /* Get vendor name */
244 cpuid(0x00000000, &c
->cpuid_level
,
245 (int *)&c
->x86_vendor_id
[0],
246 (int *)&c
->x86_vendor_id
[8],
247 (int *)&c
->x86_vendor_id
[4]);
249 get_cpu_vendor(c
, 1);
252 if (c
->cpuid_level
>= 0x00000001) {
253 u32 junk
, tfms
, cap0
, misc
;
254 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
255 c
->x86
= (tfms
>> 8) & 15;
256 c
->x86_model
= (tfms
>> 4) & 15;
258 c
->x86
+= (tfms
>> 20) & 0xff;
260 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
261 c
->x86_mask
= tfms
& 15;
263 c
->x86_cache_alignment
= ((misc
>> 8) & 0xff) * 8;
267 void __cpuinit
generic_identify(struct cpuinfo_x86
* c
)
272 if (have_cpuid_p()) {
273 /* Get vendor name */
274 cpuid(0x00000000, &c
->cpuid_level
,
275 (int *)&c
->x86_vendor_id
[0],
276 (int *)&c
->x86_vendor_id
[8],
277 (int *)&c
->x86_vendor_id
[4]);
279 get_cpu_vendor(c
, 0);
280 /* Initialize the standard set of capabilities */
281 /* Note that the vendor-specific code below might override */
283 /* Intel-defined flags: level 0x00000001 */
284 if ( c
->cpuid_level
>= 0x00000001 ) {
285 u32 capability
, excap
;
286 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
287 c
->x86_capability
[0] = capability
;
288 c
->x86_capability
[4] = excap
;
289 c
->x86
= (tfms
>> 8) & 15;
290 c
->x86_model
= (tfms
>> 4) & 15;
292 c
->x86
+= (tfms
>> 20) & 0xff;
294 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
295 c
->x86_mask
= tfms
& 15;
297 c
->apicid
= phys_pkg_id((ebx
>> 24) & 0xFF, 0);
299 c
->apicid
= (ebx
>> 24) & 0xFF;
302 /* Have CPUID level 0 only - unheard of */
306 /* AMD-defined flags: level 0x80000001 */
307 xlvl
= cpuid_eax(0x80000000);
308 if ( (xlvl
& 0xffff0000) == 0x80000000 ) {
309 if ( xlvl
>= 0x80000001 ) {
310 c
->x86_capability
[1] = cpuid_edx(0x80000001);
311 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
313 if ( xlvl
>= 0x80000004 )
314 get_model_name(c
); /* Default name */
318 early_intel_workaround(c
);
321 phys_proc_id
[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
325 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
327 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
328 /* Disable processor serial number */
330 rdmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
332 wrmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
333 printk(KERN_NOTICE
"CPU serial number disabled.\n");
334 clear_bit(X86_FEATURE_PN
, c
->x86_capability
);
336 /* Disabling the serial number may affect the cpuid level */
337 c
->cpuid_level
= cpuid_eax(0);
341 static int __init
x86_serial_nr_setup(char *s
)
343 disable_x86_serial_nr
= 0;
346 __setup("serialnumber", x86_serial_nr_setup
);
351 * This does the hard work of actually picking apart the CPU stuff...
353 void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
357 c
->loops_per_jiffy
= loops_per_jiffy
;
358 c
->x86_cache_size
= -1;
359 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
360 c
->cpuid_level
= -1; /* CPUID not detected */
361 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
362 c
->x86_vendor_id
[0] = '\0'; /* Unset */
363 c
->x86_model_id
[0] = '\0'; /* Unset */
364 c
->x86_max_cores
= 1;
365 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
367 if (!have_cpuid_p()) {
368 /* First of all, decide if this is a 486 or higher */
369 /* It's a 486 if we can modify the AC flag */
370 if ( flag_is_changeable_p(X86_EFLAGS_AC
) )
378 printk(KERN_DEBUG
"CPU: After generic identify, caps:");
379 for (i
= 0; i
< NCAPINTS
; i
++)
380 printk(" %08lx", c
->x86_capability
[i
]);
383 if (this_cpu
->c_identify
) {
384 this_cpu
->c_identify(c
);
386 printk(KERN_DEBUG
"CPU: After vendor identify, caps:");
387 for (i
= 0; i
< NCAPINTS
; i
++)
388 printk(" %08lx", c
->x86_capability
[i
]);
393 * Vendor-specific initialization. In this section we
394 * canonicalize the feature flags, meaning if there are
395 * features a certain CPU supports which CPUID doesn't
396 * tell us, CPUID claiming incorrect flags, or other bugs,
397 * we handle them here.
399 * At the end of this section, c->x86_capability better
400 * indicate the features this CPU genuinely supports!
402 if (this_cpu
->c_init
)
405 /* Disable the PN if appropriate */
406 squash_the_stupid_serial_number(c
);
409 * The vendor-specific functions might have changed features. Now
410 * we do "generic changes."
415 clear_bit(X86_FEATURE_TSC
, c
->x86_capability
);
418 if (disable_x86_fxsr
) {
419 clear_bit(X86_FEATURE_FXSR
, c
->x86_capability
);
420 clear_bit(X86_FEATURE_XMM
, c
->x86_capability
);
425 clear_bit(X86_FEATURE_SEP
, c
->x86_capability
);
428 clear_bit(X86_FEATURE_PSE
, c
->x86_capability
);
430 /* If the model name is still unset, do table lookup. */
431 if ( !c
->x86_model_id
[0] ) {
433 p
= table_lookup_model(c
);
435 strcpy(c
->x86_model_id
, p
);
438 sprintf(c
->x86_model_id
, "%02x/%02x",
439 c
->x86
, c
->x86_model
);
442 /* Now the feature flags better reflect actual CPU features! */
444 printk(KERN_DEBUG
"CPU: After all inits, caps:");
445 for (i
= 0; i
< NCAPINTS
; i
++)
446 printk(" %08lx", c
->x86_capability
[i
]);
450 * On SMP, boot_cpu_data holds the common feature set between
451 * all CPUs; so make sure that we indicate which features are
452 * common between the CPUs. The first time this routine gets
453 * executed, c == &boot_cpu_data.
455 if ( c
!= &boot_cpu_data
) {
456 /* AND the already accumulated flags with these */
457 for ( i
= 0 ; i
< NCAPINTS
; i
++ )
458 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
461 /* Init Machine Check Exception if available. */
464 if (c
== &boot_cpu_data
)
468 if (c
== &boot_cpu_data
)
475 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
477 u32 eax
, ebx
, ecx
, edx
;
478 int index_msb
, core_bits
;
479 int cpu
= smp_processor_id();
481 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
484 if (!cpu_has(c
, X86_FEATURE_HT
) || cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
487 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
489 if (smp_num_siblings
== 1) {
490 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
491 } else if (smp_num_siblings
> 1 ) {
493 if (smp_num_siblings
> NR_CPUS
) {
494 printk(KERN_WARNING
"CPU: Unsupported number of the siblings %d", smp_num_siblings
);
495 smp_num_siblings
= 1;
499 index_msb
= get_count_order(smp_num_siblings
);
500 phys_proc_id
[cpu
] = phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
);
502 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
505 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
507 index_msb
= get_count_order(smp_num_siblings
) ;
509 core_bits
= get_count_order(c
->x86_max_cores
);
511 cpu_core_id
[cpu
] = phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
) &
512 ((1 << core_bits
) - 1);
514 if (c
->x86_max_cores
> 1)
515 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
521 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
525 if (c
->x86_vendor
< X86_VENDOR_NUM
)
526 vendor
= this_cpu
->c_vendor
;
527 else if (c
->cpuid_level
>= 0)
528 vendor
= c
->x86_vendor_id
;
530 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
531 printk("%s ", vendor
);
533 if (!c
->x86_model_id
[0])
534 printk("%d86", c
->x86
);
536 printk("%s", c
->x86_model_id
);
538 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
539 printk(" stepping %02x\n", c
->x86_mask
);
544 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
547 * We're emulating future behavior.
548 * In the future, the cpu-specific init functions will be called implicitly
549 * via the magic of initcalls.
550 * They will insert themselves into the cpu_devs structure.
551 * Then, when cpu_init() is called, we can just iterate over that array.
554 extern int intel_cpu_init(void);
555 extern int cyrix_init_cpu(void);
556 extern int nsc_init_cpu(void);
557 extern int amd_init_cpu(void);
558 extern int centaur_init_cpu(void);
559 extern int transmeta_init_cpu(void);
560 extern int rise_init_cpu(void);
561 extern int nexgen_init_cpu(void);
562 extern int umc_init_cpu(void);
564 void __init
early_cpu_init(void)
571 transmeta_init_cpu();
577 #ifdef CONFIG_DEBUG_PAGEALLOC
578 /* pse is not compatible with on-the-fly unmapping,
579 * disable it even if the cpus claim to support it.
581 clear_bit(X86_FEATURE_PSE
, boot_cpu_data
.x86_capability
);
586 * cpu_init() initializes state that is per-CPU. Some data is already
587 * initialized (naturally) in the bootstrap process, such as the GDT
588 * and IDT. We reload them nevertheless, this function acts as a
589 * 'CPU state barrier', nothing should get across.
591 void __cpuinit
cpu_init(void)
593 int cpu
= smp_processor_id();
594 struct tss_struct
* t
= &per_cpu(init_tss
, cpu
);
595 struct thread_struct
*thread
= ¤t
->thread
;
596 struct desc_struct
*gdt
;
597 __u32 stk16_off
= (__u32
)&per_cpu(cpu_16bit_stack
, cpu
);
598 struct Xgt_desc_struct
*cpu_gdt_descr
= &per_cpu(cpu_gdt_descr
, cpu
);
600 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
601 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
602 for (;;) local_irq_enable();
604 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
606 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
607 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
608 if (tsc_disable
&& cpu_has_tsc
) {
609 printk(KERN_NOTICE
"Disabling TSC...\n");
610 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
611 clear_bit(X86_FEATURE_TSC
, boot_cpu_data
.x86_capability
);
612 set_in_cr4(X86_CR4_TSD
);
616 * This is a horrible hack to allocate the GDT. The problem
617 * is that cpu_init() is called really early for the boot CPU
618 * (and hence needs bootmem) but much later for the secondary
619 * CPUs, when bootmem will have gone away
621 if (NODE_DATA(0)->bdata
->node_bootmem_map
) {
622 gdt
= (struct desc_struct
*)alloc_bootmem_pages(PAGE_SIZE
);
623 /* alloc_bootmem_pages panics on failure, so no check */
624 memset(gdt
, 0, PAGE_SIZE
);
626 gdt
= (struct desc_struct
*)get_zeroed_page(GFP_KERNEL
);
627 if (unlikely(!gdt
)) {
628 printk(KERN_CRIT
"CPU%d failed to allocate GDT\n", cpu
);
635 * Initialize the per-CPU GDT with the boot GDT,
636 * and set up the GDT descriptor:
638 memcpy(gdt
, cpu_gdt_table
, GDT_SIZE
);
640 /* Set up GDT entry for 16bit stack */
641 *(__u64
*)(&gdt
[GDT_ENTRY_ESPFIX_SS
]) |=
642 ((((__u64
)stk16_off
) << 16) & 0x000000ffffff0000ULL
) |
643 ((((__u64
)stk16_off
) << 32) & 0xff00000000000000ULL
) |
644 (CPU_16BIT_STACK_SIZE
- 1);
646 cpu_gdt_descr
->size
= GDT_SIZE
- 1;
647 cpu_gdt_descr
->address
= (unsigned long)gdt
;
649 load_gdt(cpu_gdt_descr
);
650 load_idt(&idt_descr
);
653 * Set up and load the per-CPU TSS and LDT
655 atomic_inc(&init_mm
.mm_count
);
656 current
->active_mm
= &init_mm
;
659 enter_lazy_tlb(&init_mm
, current
);
661 load_esp0(t
, thread
);
664 load_LDT(&init_mm
.context
);
666 #ifdef CONFIG_DOUBLEFAULT
667 /* Set up doublefault TSS pointer in the GDT */
668 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
671 /* Clear %fs and %gs. */
672 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
674 /* Clear all 6 debug registers: */
683 * Force FPU initialization:
685 current_thread_info()->status
= 0;
687 mxcsr_feature_mask_init();
690 #ifdef CONFIG_HOTPLUG_CPU
691 void __cpuinit
cpu_uninit(void)
693 int cpu
= raw_smp_processor_id();
694 cpu_clear(cpu
, cpu_initialized
);
697 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
698 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;