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libata: update libata LLDs to use devres
[linux-2.6/cjktty.git] / drivers / ata / sata_sil24.c
blobc7a3c0275bee3f02324a054dad8e2038cfe3f56a
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "0.3"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 /*
64 * Global controller registers (128 bytes @ BAR0)
65 */
66 /* 32 bit regs */
67 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
68 HOST_CTRL = 0x40,
69 HOST_IRQ_STAT = 0x44,
70 HOST_PHY_CFG = 0x48,
71 HOST_BIST_CTRL = 0x50,
72 HOST_BIST_PTRN = 0x54,
73 HOST_BIST_STAT = 0x58,
74 HOST_MEM_BIST_STAT = 0x5c,
75 HOST_FLASH_CMD = 0x70,
76 /* 8 bit regs */
77 HOST_FLASH_DATA = 0x74,
78 HOST_TRANSITION_DETECT = 0x75,
79 HOST_GPIO_CTRL = 0x76,
80 HOST_I2C_ADDR = 0x78, /* 32 bit */
81 HOST_I2C_DATA = 0x7c,
82 HOST_I2C_XFER_CNT = 0x7e,
83 HOST_I2C_CTRL = 0x7f,
84
85 /* HOST_SLOT_STAT bits */
86 HOST_SSTAT_ATTN = (1 << 31),
87
88 /* HOST_CTRL bits */
89 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
90 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
91 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
92 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
93 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
94 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
95
96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
101
102 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
103 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
104
105 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
106 PORT_PMP_STATUS = 0x0000, /* port device status offset */
107 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
108 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
109
110 /* 32 bit regs */
111 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
112 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
113 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
114 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
115 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
116 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
117 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
118 PORT_CMD_ERR = 0x1024, /* command error number */
119 PORT_FIS_CFG = 0x1028,
120 PORT_FIFO_THRES = 0x102c,
121 /* 16 bit regs */
122 PORT_DECODE_ERR_CNT = 0x1040,
123 PORT_DECODE_ERR_THRESH = 0x1042,
124 PORT_CRC_ERR_CNT = 0x1044,
125 PORT_CRC_ERR_THRESH = 0x1046,
126 PORT_HSHK_ERR_CNT = 0x1048,
127 PORT_HSHK_ERR_THRESH = 0x104a,
128 /* 32 bit regs */
129 PORT_PHY_CFG = 0x1050,
130 PORT_SLOT_STAT = 0x1800,
131 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
132 PORT_CONTEXT = 0x1e04,
133 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
134 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
135 PORT_SCONTROL = 0x1f00,
136 PORT_SSTATUS = 0x1f04,
137 PORT_SERROR = 0x1f08,
138 PORT_SACTIVE = 0x1f0c,
139
140 /* PORT_CTRL_STAT bits */
141 PORT_CS_PORT_RST = (1 << 0), /* port reset */
142 PORT_CS_DEV_RST = (1 << 1), /* device reset */
143 PORT_CS_INIT = (1 << 2), /* port initialize */
144 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
145 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
146 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
147 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
148 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
149 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
150
151 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
152 /* bits[11:0] are masked */
153 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
154 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
155 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
156 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
157 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
158 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
159 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
160 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
161 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
162 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
163 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
164 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
165
166 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
167 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
168 PORT_IRQ_UNK_FIS,
169
170 /* bits[27:16] are unmasked (raw) */
171 PORT_IRQ_RAW_SHIFT = 16,
172 PORT_IRQ_MASKED_MASK = 0x7ff,
173 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
174
175 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
176 PORT_IRQ_STEER_SHIFT = 30,
177 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
178
179 /* PORT_CMD_ERR constants */
180 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
181 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
182 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
183 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
184 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
185 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
186 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
187 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
188 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
189 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
190 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
191 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
192 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
193 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
194 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
195 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
196 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
197 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
198 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
199 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
200 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
201 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
202
203 /* bits of PRB control field */
204 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
205 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
206 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
207 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
208 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
209
210 /* PRB protocol field */
211 PRB_PROT_PACKET = (1 << 0),
212 PRB_PROT_TCQ = (1 << 1),
213 PRB_PROT_NCQ = (1 << 2),
214 PRB_PROT_READ = (1 << 3),
215 PRB_PROT_WRITE = (1 << 4),
216 PRB_PROT_TRANSPARENT = (1 << 5),
217
218 /*
219 * Other constants
220 */
221 SGE_TRM = (1 << 31), /* Last SGE in chain */
222 SGE_LNK = (1 << 30), /* linked list
223 Points to SGT, not SGE */
224 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
225 data address ignored */
226
227 SIL24_MAX_CMDS = 31,
228
229 /* board id */
230 BID_SIL3124 = 0,
231 BID_SIL3132 = 1,
232 BID_SIL3131 = 2,
233
234 /* host flags */
235 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
236 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
237 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
238 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
239
240 IRQ_STAT_4PORTS = 0xf,
241 };
242
243 struct sil24_ata_block {
244 struct sil24_prb prb;
245 struct sil24_sge sge[LIBATA_MAX_PRD];
246 };
247
248 struct sil24_atapi_block {
249 struct sil24_prb prb;
250 u8 cdb[16];
251 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
252 };
253
254 union sil24_cmd_block {
255 struct sil24_ata_block ata;
256 struct sil24_atapi_block atapi;
257 };
258
259 static struct sil24_cerr_info {
260 unsigned int err_mask, action;
261 const char *desc;
262 } sil24_cerr_db[] = {
263 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
264 "device error" },
265 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
266 "device error via D2H FIS" },
267 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
268 "device error via SDB FIS" },
269 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
270 "error in data FIS" },
271 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
272 "failed to transmit command FIS" },
273 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
274 "protocol mismatch" },
275 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
276 "data directon mismatch" },
277 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
278 "ran out of SGEs while writing" },
279 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
280 "ran out of SGEs while reading" },
281 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
282 "invalid data directon for ATAPI CDB" },
283 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
284 "SGT no on qword boundary" },
285 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
286 "PCI target abort while fetching SGT" },
287 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
288 "PCI master abort while fetching SGT" },
289 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI parity error while fetching SGT" },
291 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
292 "PRB not on qword boundary" },
293 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "PCI target abort while fetching PRB" },
295 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
296 "PCI master abort while fetching PRB" },
297 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI parity error while fetching PRB" },
299 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "undefined error while transferring data" },
301 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
302 "PCI target abort while transferring data" },
303 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
304 "PCI master abort while transferring data" },
305 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
306 "PCI parity error while transferring data" },
307 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
308 "FIS received while sending service FIS" },
309 };
310
311 /*
312 * ap->private_data
313 *
314 * The preview driver always returned 0 for status. We emulate it
315 * here from the previous interrupt.
316 */
317 struct sil24_port_priv {
318 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
319 dma_addr_t cmd_block_dma; /* DMA base addr for them */
320 struct ata_taskfile tf; /* Cached taskfile registers */
321 };
322
323 /* ap->host->private_data */
324 struct sil24_host_priv {
325 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
326 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
327 };
328
329 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
330 static u8 sil24_check_status(struct ata_port *ap);
331 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
332 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
333 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
334 static void sil24_qc_prep(struct ata_queued_cmd *qc);
335 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
336 static void sil24_irq_clear(struct ata_port *ap);
337 static irqreturn_t sil24_interrupt(int irq, void *dev_instance);
338 static void sil24_freeze(struct ata_port *ap);
339 static void sil24_thaw(struct ata_port *ap);
340 static void sil24_error_handler(struct ata_port *ap);
341 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
342 static int sil24_port_start(struct ata_port *ap);
343 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
344 #ifdef CONFIG_PM
345 static int sil24_pci_device_resume(struct pci_dev *pdev);
346 #endif
347
348 static const struct pci_device_id sil24_pci_tbl[] = {
349 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
350 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
351 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
352 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
353 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
354
355 { } /* terminate list */
356 };
357
358 static struct pci_driver sil24_pci_driver = {
359 .name = DRV_NAME,
360 .id_table = sil24_pci_tbl,
361 .probe = sil24_init_one,
362 .remove = ata_pci_remove_one,
363 #ifdef CONFIG_PM
364 .suspend = ata_pci_device_suspend,
365 .resume = sil24_pci_device_resume,
366 #endif
367 };
368
369 static struct scsi_host_template sil24_sht = {
370 .module = THIS_MODULE,
371 .name = DRV_NAME,
372 .ioctl = ata_scsi_ioctl,
373 .queuecommand = ata_scsi_queuecmd,
374 .change_queue_depth = ata_scsi_change_queue_depth,
375 .can_queue = SIL24_MAX_CMDS,
376 .this_id = ATA_SHT_THIS_ID,
377 .sg_tablesize = LIBATA_MAX_PRD,
378 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
379 .emulated = ATA_SHT_EMULATED,
380 .use_clustering = ATA_SHT_USE_CLUSTERING,
381 .proc_name = DRV_NAME,
382 .dma_boundary = ATA_DMA_BOUNDARY,
383 .slave_configure = ata_scsi_slave_config,
384 .slave_destroy = ata_scsi_slave_destroy,
385 .bios_param = ata_std_bios_param,
386 .suspend = ata_scsi_device_suspend,
387 .resume = ata_scsi_device_resume,
388 };
389
390 static const struct ata_port_operations sil24_ops = {
391 .port_disable = ata_port_disable,
392
393 .dev_config = sil24_dev_config,
394
395 .check_status = sil24_check_status,
396 .check_altstatus = sil24_check_status,
397 .dev_select = ata_noop_dev_select,
398
399 .tf_read = sil24_tf_read,
400
401 .qc_prep = sil24_qc_prep,
402 .qc_issue = sil24_qc_issue,
403
404 .irq_handler = sil24_interrupt,
405 .irq_clear = sil24_irq_clear,
406
407 .scr_read = sil24_scr_read,
408 .scr_write = sil24_scr_write,
409
410 .freeze = sil24_freeze,
411 .thaw = sil24_thaw,
412 .error_handler = sil24_error_handler,
413 .post_internal_cmd = sil24_post_internal_cmd,
414
415 .port_start = sil24_port_start,
416 };
417
418 /*
419 * Use bits 30-31 of port_flags to encode available port numbers.
420 * Current maxium is 4.
421 */
422 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
423 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
424
425 static struct ata_port_info sil24_port_info[] = {
426 /* sil_3124 */
427 {
428 .sht = &sil24_sht,
429 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
430 SIL24_FLAG_PCIX_IRQ_WOC,
431 .pio_mask = 0x1f, /* pio0-4 */
432 .mwdma_mask = 0x07, /* mwdma0-2 */
433 .udma_mask = 0x3f, /* udma0-5 */
434 .port_ops = &sil24_ops,
435 },
436 /* sil_3132 */
437 {
438 .sht = &sil24_sht,
439 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
440 .pio_mask = 0x1f, /* pio0-4 */
441 .mwdma_mask = 0x07, /* mwdma0-2 */
442 .udma_mask = 0x3f, /* udma0-5 */
443 .port_ops = &sil24_ops,
444 },
445 /* sil_3131/sil_3531 */
446 {
447 .sht = &sil24_sht,
448 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
449 .pio_mask = 0x1f, /* pio0-4 */
450 .mwdma_mask = 0x07, /* mwdma0-2 */
451 .udma_mask = 0x3f, /* udma0-5 */
452 .port_ops = &sil24_ops,
453 },
454 };
455
456 static int sil24_tag(int tag)
457 {
458 if (unlikely(ata_tag_internal(tag)))
459 return 0;
460 return tag;
461 }
462
463 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
464 {
465 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
466
467 if (dev->cdb_len == 16)
468 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
469 else
470 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
471 }
472
473 static inline void sil24_update_tf(struct ata_port *ap)
474 {
475 struct sil24_port_priv *pp = ap->private_data;
476 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
477 struct sil24_prb __iomem *prb = port;
478 u8 fis[6 * 4];
479
480 memcpy_fromio(fis, prb->fis, 6 * 4);
481 ata_tf_from_fis(fis, &pp->tf);
482 }
483
484 static u8 sil24_check_status(struct ata_port *ap)
485 {
486 struct sil24_port_priv *pp = ap->private_data;
487 return pp->tf.command;
488 }
489
490 static int sil24_scr_map[] = {
491 [SCR_CONTROL] = 0,
492 [SCR_STATUS] = 1,
493 [SCR_ERROR] = 2,
494 [SCR_ACTIVE] = 3,
495 };
496
497 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
498 {
499 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
500 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
501 void __iomem *addr;
502 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
503 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
504 }
505 return 0xffffffffU;
506 }
507
508 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
509 {
510 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
511 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
512 void __iomem *addr;
513 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
514 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
515 }
516 }
517
518 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
519 {
520 struct sil24_port_priv *pp = ap->private_data;
521 *tf = pp->tf;
522 }
523
524 static int sil24_init_port(struct ata_port *ap)
525 {
526 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
527 u32 tmp;
528
529 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
530 ata_wait_register(port + PORT_CTRL_STAT,
531 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
532 tmp = ata_wait_register(port + PORT_CTRL_STAT,
533 PORT_CS_RDY, 0, 10, 100);
534
535 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
536 return -EIO;
537 return 0;
538 }
539
540 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
541 {
542 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
543 struct sil24_port_priv *pp = ap->private_data;
544 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
545 dma_addr_t paddr = pp->cmd_block_dma;
546 u32 mask, irq_stat;
547 const char *reason;
548
549 DPRINTK("ENTER\n");
550
551 if (ata_port_offline(ap)) {
552 DPRINTK("PHY reports no device\n");
553 *class = ATA_DEV_NONE;
554 goto out;
555 }
556
557 /* put the port into known state */
558 if (sil24_init_port(ap)) {
559 reason ="port not ready";
560 goto err;
561 }
562
563 /* do SRST */
564 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
565 prb->fis[1] = 0; /* no PMP yet */
566
567 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
568 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
569
570 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
571 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
572 100, ATA_TMOUT_BOOT / HZ * 1000);
573
574 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
575 irq_stat >>= PORT_IRQ_RAW_SHIFT;
576
577 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
578 if (irq_stat & PORT_IRQ_ERROR)
579 reason = "SRST command error";
580 else
581 reason = "timeout";
582 goto err;
583 }
584
585 sil24_update_tf(ap);
586 *class = ata_dev_classify(&pp->tf);
587
588 if (*class == ATA_DEV_UNKNOWN)
589 *class = ATA_DEV_NONE;
590
591 out:
592 DPRINTK("EXIT, class=%u\n", *class);
593 return 0;
594
595 err:
596 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
597 return -EIO;
598 }
599
600 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
601 {
602 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
603 const char *reason;
604 int tout_msec, rc;
605 u32 tmp;
606
607 /* sil24 does the right thing(tm) without any protection */
608 sata_set_spd(ap);
609
610 tout_msec = 100;
611 if (ata_port_online(ap))
612 tout_msec = 5000;
613
614 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
615 tmp = ata_wait_register(port + PORT_CTRL_STAT,
616 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
617
618 /* SStatus oscillates between zero and valid status after
619 * DEV_RST, debounce it.
620 */
621 rc = sata_phy_debounce(ap, sata_deb_timing_long);
622 if (rc) {
623 reason = "PHY debouncing failed";
624 goto err;
625 }
626
627 if (tmp & PORT_CS_DEV_RST) {
628 if (ata_port_offline(ap))
629 return 0;
630 reason = "link not ready";
631 goto err;
632 }
633
634 /* Sil24 doesn't store signature FIS after hardreset, so we
635 * can't wait for BSY to clear. Some devices take a long time
636 * to get ready and those devices will choke if we don't wait
637 * for BSY clearance here. Tell libata to perform follow-up
638 * softreset.
639 */
640 return -EAGAIN;
641
642 err:
643 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
644 return -EIO;
645 }
646
647 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
648 struct sil24_sge *sge)
649 {
650 struct scatterlist *sg;
651 unsigned int idx = 0;
652
653 ata_for_each_sg(sg, qc) {
654 sge->addr = cpu_to_le64(sg_dma_address(sg));
655 sge->cnt = cpu_to_le32(sg_dma_len(sg));
656 if (ata_sg_is_last(sg, qc))
657 sge->flags = cpu_to_le32(SGE_TRM);
658 else
659 sge->flags = 0;
660
661 sge++;
662 idx++;
663 }
664 }
665
666 static void sil24_qc_prep(struct ata_queued_cmd *qc)
667 {
668 struct ata_port *ap = qc->ap;
669 struct sil24_port_priv *pp = ap->private_data;
670 union sil24_cmd_block *cb;
671 struct sil24_prb *prb;
672 struct sil24_sge *sge;
673 u16 ctrl = 0;
674
675 cb = &pp->cmd_block[sil24_tag(qc->tag)];
676
677 switch (qc->tf.protocol) {
678 case ATA_PROT_PIO:
679 case ATA_PROT_DMA:
680 case ATA_PROT_NCQ:
681 case ATA_PROT_NODATA:
682 prb = &cb->ata.prb;
683 sge = cb->ata.sge;
684 break;
685
686 case ATA_PROT_ATAPI:
687 case ATA_PROT_ATAPI_DMA:
688 case ATA_PROT_ATAPI_NODATA:
689 prb = &cb->atapi.prb;
690 sge = cb->atapi.sge;
691 memset(cb->atapi.cdb, 0, 32);
692 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
693
694 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
695 if (qc->tf.flags & ATA_TFLAG_WRITE)
696 ctrl = PRB_CTRL_PACKET_WRITE;
697 else
698 ctrl = PRB_CTRL_PACKET_READ;
699 }
700 break;
701
702 default:
703 prb = NULL; /* shut up, gcc */
704 sge = NULL;
705 BUG();
706 }
707
708 prb->ctrl = cpu_to_le16(ctrl);
709 ata_tf_to_fis(&qc->tf, prb->fis, 0);
710
711 if (qc->flags & ATA_QCFLAG_DMAMAP)
712 sil24_fill_sg(qc, sge);
713 }
714
715 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
716 {
717 struct ata_port *ap = qc->ap;
718 struct sil24_port_priv *pp = ap->private_data;
719 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
720 unsigned int tag = sil24_tag(qc->tag);
721 dma_addr_t paddr;
722 void __iomem *activate;
723
724 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
725 activate = port + PORT_CMD_ACTIVATE + tag * 8;
726
727 writel((u32)paddr, activate);
728 writel((u64)paddr >> 32, activate + 4);
729
730 return 0;
731 }
732
733 static void sil24_irq_clear(struct ata_port *ap)
734 {
735 /* unused */
736 }
737
738 static void sil24_freeze(struct ata_port *ap)
739 {
740 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
741
742 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
743 * PORT_IRQ_ENABLE instead.
744 */
745 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
746 }
747
748 static void sil24_thaw(struct ata_port *ap)
749 {
750 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
751 u32 tmp;
752
753 /* clear IRQ */
754 tmp = readl(port + PORT_IRQ_STAT);
755 writel(tmp, port + PORT_IRQ_STAT);
756
757 /* turn IRQ back on */
758 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
759 }
760
761 static void sil24_error_intr(struct ata_port *ap)
762 {
763 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
764 struct ata_eh_info *ehi = &ap->eh_info;
765 int freeze = 0;
766 u32 irq_stat;
767
768 /* on error, we need to clear IRQ explicitly */
769 irq_stat = readl(port + PORT_IRQ_STAT);
770 writel(irq_stat, port + PORT_IRQ_STAT);
771
772 /* first, analyze and record host port events */
773 ata_ehi_clear_desc(ehi);
774
775 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
776
777 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
778 ata_ehi_hotplugged(ehi);
779 ata_ehi_push_desc(ehi, ", %s",
780 irq_stat & PORT_IRQ_PHYRDY_CHG ?
781 "PHY RDY changed" : "device exchanged");
782 freeze = 1;
783 }
784
785 if (irq_stat & PORT_IRQ_UNK_FIS) {
786 ehi->err_mask |= AC_ERR_HSM;
787 ehi->action |= ATA_EH_SOFTRESET;
788 ata_ehi_push_desc(ehi , ", unknown FIS");
789 freeze = 1;
790 }
791
792 /* deal with command error */
793 if (irq_stat & PORT_IRQ_ERROR) {
794 struct sil24_cerr_info *ci = NULL;
795 unsigned int err_mask = 0, action = 0;
796 struct ata_queued_cmd *qc;
797 u32 cerr;
798
799 /* analyze CMD_ERR */
800 cerr = readl(port + PORT_CMD_ERR);
801 if (cerr < ARRAY_SIZE(sil24_cerr_db))
802 ci = &sil24_cerr_db[cerr];
803
804 if (ci && ci->desc) {
805 err_mask |= ci->err_mask;
806 action |= ci->action;
807 ata_ehi_push_desc(ehi, ", %s", ci->desc);
808 } else {
809 err_mask |= AC_ERR_OTHER;
810 action |= ATA_EH_SOFTRESET;
811 ata_ehi_push_desc(ehi, ", unknown command error %d",
812 cerr);
813 }
814
815 /* record error info */
816 qc = ata_qc_from_tag(ap, ap->active_tag);
817 if (qc) {
818 sil24_update_tf(ap);
819 qc->err_mask |= err_mask;
820 } else
821 ehi->err_mask |= err_mask;
822
823 ehi->action |= action;
824 }
825
826 /* freeze or abort */
827 if (freeze)
828 ata_port_freeze(ap);
829 else
830 ata_port_abort(ap);
831 }
832
833 static void sil24_finish_qc(struct ata_queued_cmd *qc)
834 {
835 if (qc->flags & ATA_QCFLAG_RESULT_TF)
836 sil24_update_tf(qc->ap);
837 }
838
839 static inline void sil24_host_intr(struct ata_port *ap)
840 {
841 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
842 u32 slot_stat, qc_active;
843 int rc;
844
845 slot_stat = readl(port + PORT_SLOT_STAT);
846
847 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
848 sil24_error_intr(ap);
849 return;
850 }
851
852 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
853 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
854
855 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
856 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
857 if (rc > 0)
858 return;
859 if (rc < 0) {
860 struct ata_eh_info *ehi = &ap->eh_info;
861 ehi->err_mask |= AC_ERR_HSM;
862 ehi->action |= ATA_EH_SOFTRESET;
863 ata_port_freeze(ap);
864 return;
865 }
866
867 if (ata_ratelimit())
868 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
869 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
870 slot_stat, ap->active_tag, ap->sactive);
871 }
872
873 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
874 {
875 struct ata_host *host = dev_instance;
876 struct sil24_host_priv *hpriv = host->private_data;
877 unsigned handled = 0;
878 u32 status;
879 int i;
880
881 status = readl(hpriv->host_base + HOST_IRQ_STAT);
882
883 if (status == 0xffffffff) {
884 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
885 "PCI fault or device removal?\n");
886 goto out;
887 }
888
889 if (!(status & IRQ_STAT_4PORTS))
890 goto out;
891
892 spin_lock(&host->lock);
893
894 for (i = 0; i < host->n_ports; i++)
895 if (status & (1 << i)) {
896 struct ata_port *ap = host->ports[i];
897 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
898 sil24_host_intr(host->ports[i]);
899 handled++;
900 } else
901 printk(KERN_ERR DRV_NAME
902 ": interrupt from disabled port %d\n", i);
903 }
904
905 spin_unlock(&host->lock);
906 out:
907 return IRQ_RETVAL(handled);
908 }
909
910 static void sil24_error_handler(struct ata_port *ap)
911 {
912 struct ata_eh_context *ehc = &ap->eh_context;
913
914 if (sil24_init_port(ap)) {
915 ata_eh_freeze_port(ap);
916 ehc->i.action |= ATA_EH_HARDRESET;
917 }
918
919 /* perform recovery */
920 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
921 ata_std_postreset);
922 }
923
924 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
925 {
926 struct ata_port *ap = qc->ap;
927
928 if (qc->flags & ATA_QCFLAG_FAILED)
929 qc->err_mask |= AC_ERR_OTHER;
930
931 /* make DMA engine forget about the failed command */
932 if (qc->err_mask)
933 sil24_init_port(ap);
934 }
935
936 static int sil24_port_start(struct ata_port *ap)
937 {
938 struct device *dev = ap->host->dev;
939 struct sil24_port_priv *pp;
940 union sil24_cmd_block *cb;
941 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
942 dma_addr_t cb_dma;
943 int rc;
944
945 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
946 if (!pp)
947 return -ENOMEM;
948
949 pp->tf.command = ATA_DRDY;
950
951 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
952 if (!cb)
953 return -ENOMEM;
954 memset(cb, 0, cb_size);
955
956 rc = ata_pad_alloc(ap, dev);
957 if (rc)
958 return rc;
959
960 pp->cmd_block = cb;
961 pp->cmd_block_dma = cb_dma;
962
963 ap->private_data = pp;
964
965 return 0;
966 }
967
968 static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
969 unsigned long port_flags,
970 void __iomem *host_base,
971 void __iomem *port_base)
972 {
973 u32 tmp;
974 int i;
975
976 /* GPIO off */
977 writel(0, host_base + HOST_FLASH_CMD);
978
979 /* clear global reset & mask interrupts during initialization */
980 writel(0, host_base + HOST_CTRL);
981
982 /* init ports */
983 for (i = 0; i < n_ports; i++) {
984 void __iomem *port = port_base + i * PORT_REGS_SIZE;
985
986 /* Initial PHY setting */
987 writel(0x20c, port + PORT_PHY_CFG);
988
989 /* Clear port RST */
990 tmp = readl(port + PORT_CTRL_STAT);
991 if (tmp & PORT_CS_PORT_RST) {
992 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
993 tmp = ata_wait_register(port + PORT_CTRL_STAT,
994 PORT_CS_PORT_RST,
995 PORT_CS_PORT_RST, 10, 100);
996 if (tmp & PORT_CS_PORT_RST)
997 dev_printk(KERN_ERR, &pdev->dev,
998 "failed to clear port RST\n");
999 }
1000
1001 /* Configure IRQ WoC */
1002 if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1003 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1004 else
1005 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1006
1007 /* Zero error counters. */
1008 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1009 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1010 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1011 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1012 writel(0x0000, port + PORT_CRC_ERR_CNT);
1013 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1014
1015 /* Always use 64bit activation */
1016 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1017
1018 /* Clear port multiplier enable and resume bits */
1019 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1020 port + PORT_CTRL_CLR);
1021 }
1022
1023 /* Turn on interrupts */
1024 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1025 }
1026
1027 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1028 {
1029 static int printed_version = 0;
1030 struct device *dev = &pdev->dev;
1031 unsigned int board_id = (unsigned int)ent->driver_data;
1032 struct ata_port_info *pinfo = &sil24_port_info[board_id];
1033 struct ata_probe_ent *probe_ent;
1034 struct sil24_host_priv *hpriv;
1035 void __iomem *host_base;
1036 void __iomem *port_base;
1037 int i, rc;
1038 u32 tmp;
1039
1040 if (!printed_version++)
1041 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1042
1043 rc = pcim_enable_device(pdev);
1044 if (rc)
1045 return rc;
1046
1047 rc = pci_request_regions(pdev, DRV_NAME);
1048 if (rc)
1049 return rc;
1050
1051 /* map mmio registers */
1052 host_base = pcim_iomap(pdev, 0, 0);
1053 port_base = pcim_iomap(pdev, 2, 0);
1054 if (!host_base || !port_base)
1055 return -ENOMEM;
1056
1057 /* allocate & init probe_ent and hpriv */
1058 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1059 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1060 if (!probe_ent || !hpriv)
1061 return -ENOMEM;
1062
1063 probe_ent->dev = pci_dev_to_dev(pdev);
1064 INIT_LIST_HEAD(&probe_ent->node);
1065
1066 probe_ent->sht = pinfo->sht;
1067 probe_ent->port_flags = pinfo->flags;
1068 probe_ent->pio_mask = pinfo->pio_mask;
1069 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1070 probe_ent->udma_mask = pinfo->udma_mask;
1071 probe_ent->port_ops = pinfo->port_ops;
1072 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags);
1073
1074 probe_ent->irq = pdev->irq;
1075 probe_ent->irq_flags = IRQF_SHARED;
1076 probe_ent->private_data = hpriv;
1077
1078 hpriv->host_base = host_base;
1079 hpriv->port_base = port_base;
1080
1081 /*
1082 * Configure the device
1083 */
1084 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1085 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1086 if (rc) {
1087 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1088 if (rc) {
1089 dev_printk(KERN_ERR, &pdev->dev,
1090 "64-bit DMA enable failed\n");
1091 return rc;
1092 }
1093 }
1094 } else {
1095 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1096 if (rc) {
1097 dev_printk(KERN_ERR, &pdev->dev,
1098 "32-bit DMA enable failed\n");
1099 return rc;
1100 }
1101 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1102 if (rc) {
1103 dev_printk(KERN_ERR, &pdev->dev,
1104 "32-bit consistent DMA enable failed\n");
1105 return rc;
1106 }
1107 }
1108
1109 /* Apply workaround for completion IRQ loss on PCI-X errata */
1110 if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1111 tmp = readl(host_base + HOST_CTRL);
1112 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1113 dev_printk(KERN_INFO, &pdev->dev,
1114 "Applying completion IRQ loss on PCI-X "
1115 "errata fix\n");
1116 else
1117 probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1118 }
1119
1120 for (i = 0; i < probe_ent->n_ports; i++) {
1121 unsigned long portu =
1122 (unsigned long)port_base + i * PORT_REGS_SIZE;
1123
1124 probe_ent->port[i].cmd_addr = portu;
1125 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1126
1127 ata_std_ports(&probe_ent->port[i]);
1128 }
1129
1130 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
1131 host_base, port_base);
1132
1133 pci_set_master(pdev);
1134
1135 if (!ata_device_add(probe_ent))
1136 return -ENODEV;
1137
1138 devm_kfree(dev, probe_ent);
1139 return 0;
1140 }
1141
1142 #ifdef CONFIG_PM
1143 static int sil24_pci_device_resume(struct pci_dev *pdev)
1144 {
1145 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1146 struct sil24_host_priv *hpriv = host->private_data;
1147 int rc;
1148
1149 rc = ata_pci_device_do_resume(pdev);
1150 if (rc)
1151 return rc;
1152
1153 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1154 writel(HOST_CTRL_GLOBAL_RST, hpriv->host_base + HOST_CTRL);
1155
1156 sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags,
1157 hpriv->host_base, hpriv->port_base);
1158
1159 ata_host_resume(host);
1160
1161 return 0;
1162 }
1163 #endif
1164
1165 static int __init sil24_init(void)
1166 {
1167 return pci_register_driver(&sil24_pci_driver);
1168 }
1169
1170 static void __exit sil24_exit(void)
1171 {
1172 pci_unregister_driver(&sil24_pci_driver);
1173 }
1174
1175 MODULE_AUTHOR("Tejun Heo");
1176 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1177 MODULE_LICENSE("GPL");
1178 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1179
1180 module_init(sil24_init);
1181 module_exit(sil24_exit);
CJK support for tty framebuffer vt