2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
15 #include <linux/errno.h>
16 #include <linux/tty.h>
17 #include <linux/serial.h>
18 #include <linux/serialP.h>
19 #include <linux/circ_buf.h>
20 #include <linux/serial_reg.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/ioc4.h>
24 #include <linux/serial_core.h>
27 * interesting things about the ioc4
30 #define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
31 #define IOC4_NUM_CARDS 8 /* max cards per partition */
33 #define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
34 (_n == 1) ? (IOC4_SIO_IR_S1) : \
35 (_n == 2) ? (IOC4_SIO_IR_S2) : \
38 #define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
39 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
40 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
41 (IOC4_OTHER_IR_S3_MEMERR)
45 * All IOC4 registers are 32 bits wide.
49 * PCI Memory Space Map
51 #define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
52 #define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
53 #define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
54 #define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
55 #define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
56 #define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
57 #define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
60 #define IOC4_SIO_INTR_TYPE 0
61 #define IOC4_OTHER_INTR_TYPE 1
62 #define IOC4_NUM_INTR_TYPES 2
64 /* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
65 #define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
66 #define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
67 #define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
68 #define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
69 #define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
70 #define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
71 #define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
72 #define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
73 #define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
74 #define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
75 #define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
76 #define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
77 #define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
78 #define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
79 #define IOC4_SIO_IR_S1_INT 0x00004000 /* */
80 #define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
81 #define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
82 #define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
83 #define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
84 #define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
85 #define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
86 #define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
87 #define IOC4_SIO_IR_S2_INT 0x00400000 /* */
88 #define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
89 #define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
90 #define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
91 #define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
92 #define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
93 #define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
94 #define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
95 #define IOC4_SIO_IR_S3_INT 0x40000000 /* */
96 #define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
98 /* Per device interrupt masks */
99 #define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
100 IOC4_SIO_IR_S0_RX_FULL | \
101 IOC4_SIO_IR_S0_RX_HIGH | \
102 IOC4_SIO_IR_S0_RX_TIMER | \
103 IOC4_SIO_IR_S0_DELTA_DCD | \
104 IOC4_SIO_IR_S0_DELTA_CTS | \
105 IOC4_SIO_IR_S0_INT | \
106 IOC4_SIO_IR_S0_TX_EXPLICIT)
107 #define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
108 IOC4_SIO_IR_S1_RX_FULL | \
109 IOC4_SIO_IR_S1_RX_HIGH | \
110 IOC4_SIO_IR_S1_RX_TIMER | \
111 IOC4_SIO_IR_S1_DELTA_DCD | \
112 IOC4_SIO_IR_S1_DELTA_CTS | \
113 IOC4_SIO_IR_S1_INT | \
114 IOC4_SIO_IR_S1_TX_EXPLICIT)
115 #define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
116 IOC4_SIO_IR_S2_RX_FULL | \
117 IOC4_SIO_IR_S2_RX_HIGH | \
118 IOC4_SIO_IR_S2_RX_TIMER | \
119 IOC4_SIO_IR_S2_DELTA_DCD | \
120 IOC4_SIO_IR_S2_DELTA_CTS | \
121 IOC4_SIO_IR_S2_INT | \
122 IOC4_SIO_IR_S2_TX_EXPLICIT)
123 #define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
124 IOC4_SIO_IR_S3_RX_FULL | \
125 IOC4_SIO_IR_S3_RX_HIGH | \
126 IOC4_SIO_IR_S3_RX_TIMER | \
127 IOC4_SIO_IR_S3_DELTA_DCD | \
128 IOC4_SIO_IR_S3_DELTA_CTS | \
129 IOC4_SIO_IR_S3_INT | \
130 IOC4_SIO_IR_S3_TX_EXPLICIT)
132 /* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
133 #define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
134 #define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
135 #define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
136 #define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
137 #define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
138 #define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
139 #define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
140 #define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
141 #define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
142 #define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
144 #define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
145 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
147 /* Bitmasks for IOC4_SIO_CR */
148 #define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
149 #define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
150 #define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
151 #define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
152 #define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
153 #define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
154 #define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
155 #define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
156 #define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
157 #define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
159 /* Defs for some of the generic I/O pins */
160 #define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
162 #define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
164 #define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
166 #define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
169 #define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
170 uart 0 mode select */
171 #define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
172 uart 1 mode select */
173 #define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
174 uart 2 mode select */
175 #define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
176 uart 3 mode select */
178 /* Bitmasks for serial RX status byte */
179 #define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
180 #define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
181 #define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
182 #define IOC4_RXSB_BREAK 0x08 /* Break character */
183 #define IOC4_RXSB_CTS 0x10 /* State of CTS */
184 #define IOC4_RXSB_DCD 0x20 /* State of DCD */
185 #define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
186 #define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
189 /* Bitmasks for serial TX control byte */
190 #define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
191 #define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
192 #define IOC4_TXCB_VALID 0x40 /* Byte is valid */
193 #define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
194 #define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
196 /* Bitmasks for IOC4_SBBR_L */
197 #define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
199 /* Bitmasks for IOC4_SSCR_<3:0> */
200 #define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
201 #define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
202 #define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
203 #define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
204 #define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
205 #define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
206 #define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
207 #define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
208 #define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
209 #define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
210 #define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
212 /* All producer/comsumer pointers are the same bitfield */
213 #define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
214 #define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
215 #define IOC4_PROD_CONS_PTR_OFF 3
217 /* Bitmasks for IOC4_SRCIR_<3:0> */
218 #define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
220 /* Bitmasks for IOC4_SHADOW_<3:0> */
221 #define IOC4_SHADOW_DR 0x00000001 /* Data ready */
222 #define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
223 #define IOC4_SHADOW_PE 0x00000004 /* Parity error */
224 #define IOC4_SHADOW_FE 0x00000008 /* Framing error */
225 #define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
226 #define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
227 #define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
228 #define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
229 #define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
230 #define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
231 #define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
232 #define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
233 #define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
234 #define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
235 #define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
236 #define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
237 #define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
239 /* Bitmasks for IOC4_SRTR_<3:0> */
240 #define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
241 #define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
242 #define IOC4_SRTR_CNT_VAL_SHIFT 16
243 #define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
245 /* Serial port register map used for DMA and PIO serial I/O */
246 struct ioc4_serialregs
{
256 /* IOC4 UART register map */
257 struct ioc4_uartregs
{
260 char iir
; /* read only */
261 char fcr
; /* write only */
264 char ier
; /* DLAB == 0 */
265 char dlm
; /* DLAB == 1 */
268 char rbr
; /* read only, DLAB == 0 */
269 char thr
; /* write only, DLAB == 0 */
270 char dll
; /* DLAB == 1 */
279 #define i4u_dll u1.dll
280 #define i4u_ier u2.ier
281 #define i4u_dlm u2.dlm
282 #define i4u_fcr u3.fcr
284 /* Serial port registers used for DMA serial I/O */
291 struct ioc4_serialregs port_0
;
292 struct ioc4_serialregs port_1
;
293 struct ioc4_serialregs port_2
;
294 struct ioc4_serialregs port_3
;
295 struct ioc4_uartregs uart_0
;
296 struct ioc4_uartregs uart_1
;
297 struct ioc4_uartregs uart_2
;
298 struct ioc4_uartregs uart_3
;
301 /* UART clock speed */
302 #define IOC4_SER_XIN_CLK IOC4_SER_XIN_CLK_66
303 #define IOC4_SER_XIN_CLK_66 66666667
304 #define IOC4_SER_XIN_CLK_33 33333333
309 typedef void ioc4_intr_func_f(void *, uint32_t);
310 typedef ioc4_intr_func_f
*ioc4_intr_func_t
;
312 /* defining this will get you LOTS of great debug info */
313 //#define DEBUG_INTERRUPTS
314 #define DPRINT_CONFIG(_x...) ;
315 //#define DPRINT_CONFIG(_x...) printk _x
317 /* number of characters left in xmit buffer before we ask for more */
318 #define WAKEUP_CHARS 256
320 /* number of characters we want to transmit to the lower level at a time */
321 #define IOC4_MAX_CHARS 128
323 /* Device name we're using */
324 #define DEVICE_NAME "ttyIOC"
325 #define DEVICE_MAJOR 204
326 #define DEVICE_MINOR 50
328 /* register offsets */
329 #define IOC4_SERIAL_OFFSET 0x300
331 /* flags for next_char_state */
332 #define NCS_BREAK 0x1
333 #define NCS_PARITY 0x2
334 #define NCS_FRAMING 0x4
335 #define NCS_OVERRUN 0x8
337 /* cause we need SOME parameters ... */
338 #define MIN_BAUD_SUPPORTED 1200
339 #define MAX_BAUD_SUPPORTED 115200
341 /* protocol types supported */
347 /* Notification types */
348 #define N_DATA_READY 0x01
349 #define N_OUTPUT_LOWAT 0x02
351 #define N_PARITY_ERROR 0x08
352 #define N_FRAMING_ERROR 0x10
353 #define N_OVERRUN_ERROR 0x20
357 #define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
358 N_PARITY_ERROR | N_FRAMING_ERROR | \
359 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
361 #define N_ALL_OUTPUT N_OUTPUT_LOWAT
363 #define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
365 #define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
366 N_PARITY_ERROR | N_FRAMING_ERROR | \
367 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
369 #define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
370 #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
373 #define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
374 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
375 #define LCR_MASK_STOP_BITS (UART_LCR_STOP)
377 #define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
378 #define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
380 /* Default to 4k buffers */
381 #ifdef IOC4_1K_BUFFERS
382 #define RING_BUF_SIZE 1024
383 #define IOC4_BUF_SIZE_BIT 0
384 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
386 #define RING_BUF_SIZE 4096
387 #define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
388 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
391 #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
394 * This is the entry saved by the driver - one per card
396 struct ioc4_control
{
399 /* uart ports are allocated here */
400 struct uart_port icp_uart_port
;
401 /* Handy reference material */
402 struct ioc4_port
*icp_port
;
403 } ic_port
[IOC4_NUM_SERIAL_PORTS
];
404 struct ioc4_soft
*ic_soft
;
408 * per-IOC4 data structure
410 #define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
412 struct ioc4_misc_regs __iomem
*is_ioc4_misc_addr
;
413 struct ioc4_serial __iomem
*is_ioc4_serial_addr
;
415 /* Each interrupt type has an entry in the array */
416 struct ioc4_intr_type
{
419 * Each in-use entry in this array contains at least
420 * one nonzero bit in sd_bits; no two entries in this
421 * array have overlapping sd_bits values.
423 struct ioc4_intr_info
{
425 ioc4_intr_func_f
*sd_intr
;
427 } is_intr_info
[MAX_IOC4_INTR_ENTS
];
429 /* Number of entries active in the above array */
430 atomic_t is_num_intrs
;
431 } is_intr_type
[IOC4_NUM_INTR_TYPES
];
433 /* is_ir_lock must be held while
434 * modifying sio_ie values, so
435 * we can be sure that sio_ie is
436 * not changing when we read it
439 spinlock_t is_ir_lock
; /* SIO_IE[SC] mod lock */
442 /* Local port info for each IOC4 serial ports */
444 struct uart_port
*ip_port
;
445 /* Back ptrs for this port */
446 struct ioc4_control
*ip_control
;
447 struct pci_dev
*ip_pdev
;
448 struct ioc4_soft
*ip_ioc4_soft
;
450 /* pci mem addresses */
451 struct ioc4_misc_regs __iomem
*ip_mem
;
452 struct ioc4_serial __iomem
*ip_serial
;
453 struct ioc4_serialregs __iomem
*ip_serial_regs
;
454 struct ioc4_uartregs __iomem
*ip_uart_regs
;
456 /* Ring buffer page for this port */
457 dma_addr_t ip_dma_ringbuf
;
458 /* vaddr of ring buffer */
459 struct ring_buffer
*ip_cpu_ringbuf
;
461 /* Rings for this port */
462 struct ring
*ip_inring
;
463 struct ring
*ip_outring
;
465 /* Hook to port specific values */
466 struct hooks
*ip_hooks
;
470 /* Various rx/tx parameters */
475 /* Copy of notification bits */
478 /* Shadow copies of various registers so we don't need to PIO
479 * read them constantly
481 uint32_t ip_ienb
; /* Enabled interrupts */
485 int ip_pci_bus_speed
;
486 unsigned char ip_flags
;
489 /* tx low water mark. We need to notify the driver whenever tx is getting
490 * close to empty so it can refill the tx buffer and keep things going.
491 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
492 * have no trouble getting in more chars in time (I certainly hope so).
494 #define TX_LOWAT_LATENCY 1000
495 #define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
496 #define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
499 #define INPUT_HIGH 0x01
501 #define LOWAT_WRITTEN 0x04
502 #define READ_ABORTED 0x08
504 /* Since each port has different register offsets and bitmasks
505 * for everything, we'll store those that we need in tables so we
506 * don't have to be constantly checking the port we are dealing with.
509 uint32_t intr_delta_dcd
;
510 uint32_t intr_delta_cts
;
512 uint32_t intr_rx_timer
;
513 uint32_t intr_rx_high
;
514 uint32_t intr_tx_explicit
;
515 uint32_t intr_dma_error
;
518 int rs422_select_pin
;
521 static struct hooks hooks_array
[IOC4_NUM_SERIAL_PORTS
] = {
522 /* Values for port 0 */
524 IOC4_SIO_IR_S0_DELTA_DCD
, IOC4_SIO_IR_S0_DELTA_CTS
,
525 IOC4_SIO_IR_S0_TX_MT
, IOC4_SIO_IR_S0_RX_TIMER
,
526 IOC4_SIO_IR_S0_RX_HIGH
, IOC4_SIO_IR_S0_TX_EXPLICIT
,
527 IOC4_OTHER_IR_S0_MEMERR
,
528 (IOC4_SIO_IR_S0_TX_MT
| IOC4_SIO_IR_S0_RX_FULL
|
529 IOC4_SIO_IR_S0_RX_HIGH
| IOC4_SIO_IR_S0_RX_TIMER
|
530 IOC4_SIO_IR_S0_DELTA_DCD
| IOC4_SIO_IR_S0_DELTA_CTS
|
531 IOC4_SIO_IR_S0_INT
| IOC4_SIO_IR_S0_TX_EXPLICIT
),
532 IOC4_SIO_IR_S0
, IOC4_GPPR_UART0_MODESEL_PIN
,
535 /* Values for port 1 */
537 IOC4_SIO_IR_S1_DELTA_DCD
, IOC4_SIO_IR_S1_DELTA_CTS
,
538 IOC4_SIO_IR_S1_TX_MT
, IOC4_SIO_IR_S1_RX_TIMER
,
539 IOC4_SIO_IR_S1_RX_HIGH
, IOC4_SIO_IR_S1_TX_EXPLICIT
,
540 IOC4_OTHER_IR_S1_MEMERR
,
541 (IOC4_SIO_IR_S1_TX_MT
| IOC4_SIO_IR_S1_RX_FULL
|
542 IOC4_SIO_IR_S1_RX_HIGH
| IOC4_SIO_IR_S1_RX_TIMER
|
543 IOC4_SIO_IR_S1_DELTA_DCD
| IOC4_SIO_IR_S1_DELTA_CTS
|
544 IOC4_SIO_IR_S1_INT
| IOC4_SIO_IR_S1_TX_EXPLICIT
),
545 IOC4_SIO_IR_S1
, IOC4_GPPR_UART1_MODESEL_PIN
,
548 /* Values for port 2 */
550 IOC4_SIO_IR_S2_DELTA_DCD
, IOC4_SIO_IR_S2_DELTA_CTS
,
551 IOC4_SIO_IR_S2_TX_MT
, IOC4_SIO_IR_S2_RX_TIMER
,
552 IOC4_SIO_IR_S2_RX_HIGH
, IOC4_SIO_IR_S2_TX_EXPLICIT
,
553 IOC4_OTHER_IR_S2_MEMERR
,
554 (IOC4_SIO_IR_S2_TX_MT
| IOC4_SIO_IR_S2_RX_FULL
|
555 IOC4_SIO_IR_S2_RX_HIGH
| IOC4_SIO_IR_S2_RX_TIMER
|
556 IOC4_SIO_IR_S2_DELTA_DCD
| IOC4_SIO_IR_S2_DELTA_CTS
|
557 IOC4_SIO_IR_S2_INT
| IOC4_SIO_IR_S2_TX_EXPLICIT
),
558 IOC4_SIO_IR_S2
, IOC4_GPPR_UART2_MODESEL_PIN
,
561 /* Values for port 3 */
563 IOC4_SIO_IR_S3_DELTA_DCD
, IOC4_SIO_IR_S3_DELTA_CTS
,
564 IOC4_SIO_IR_S3_TX_MT
, IOC4_SIO_IR_S3_RX_TIMER
,
565 IOC4_SIO_IR_S3_RX_HIGH
, IOC4_SIO_IR_S3_TX_EXPLICIT
,
566 IOC4_OTHER_IR_S3_MEMERR
,
567 (IOC4_SIO_IR_S3_TX_MT
| IOC4_SIO_IR_S3_RX_FULL
|
568 IOC4_SIO_IR_S3_RX_HIGH
| IOC4_SIO_IR_S3_RX_TIMER
|
569 IOC4_SIO_IR_S3_DELTA_DCD
| IOC4_SIO_IR_S3_DELTA_CTS
|
570 IOC4_SIO_IR_S3_INT
| IOC4_SIO_IR_S3_TX_EXPLICIT
),
571 IOC4_SIO_IR_S3
, IOC4_GPPR_UART3_MODESEL_PIN
,
575 /* A ring buffer entry */
583 char data
[4]; /* data bytes */
584 char sc
[4]; /* status/control */
589 /* Test the valid bits in any of the 4 sc chars using "allsc" member */
590 #define RING_ANY_VALID \
591 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
593 #define ring_sc u.s.sc
594 #define ring_data u.s.data
595 #define ring_allsc u.all.allsc
597 /* Number of entries per ring buffer. */
598 #define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
600 /* An individual ring */
602 struct ring_entry entries
[ENTRIES_PER_RING
];
605 /* The whole enchilada */
607 struct ring TX_0_OR_2
;
608 struct ring RX_0_OR_2
;
609 struct ring TX_1_OR_3
;
610 struct ring RX_1_OR_3
;
613 /* Get a ring from a port struct */
614 #define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
616 /* Infinite loop detection.
618 #define MAXITER 10000000
621 static void receive_chars(struct uart_port
*);
622 static void handle_intr(void *arg
, uint32_t sio_ir
);
625 * write_ireg - write the interrupt regs
626 * @ioc4_soft: ptr to soft struct for this port
627 * @val: value to write
628 * @which: which register
629 * @type: which ireg set
632 write_ireg(struct ioc4_soft
*ioc4_soft
, uint32_t val
, int which
, int type
)
634 struct ioc4_misc_regs __iomem
*mem
= ioc4_soft
->is_ioc4_misc_addr
;
637 spin_lock_irqsave(&ioc4_soft
->is_ir_lock
, flags
);
640 case IOC4_SIO_INTR_TYPE
:
643 writel(val
, &mem
->sio_ies
.raw
);
647 writel(val
, &mem
->sio_iec
.raw
);
652 case IOC4_OTHER_INTR_TYPE
:
655 writel(val
, &mem
->other_ies
.raw
);
659 writel(val
, &mem
->other_iec
.raw
);
667 spin_unlock_irqrestore(&ioc4_soft
->is_ir_lock
, flags
);
671 * set_baud - Baud rate setting code
673 * @baud: baud rate to use
675 static int set_baud(struct ioc4_port
*port
, int baud
)
680 unsigned short divisor
;
681 struct ioc4_uartregs __iomem
*uart
;
683 divisor
= SER_DIVISOR(baud
, port
->ip_pci_bus_speed
);
686 actual_baud
= DIVISOR_TO_BAUD(divisor
, port
->ip_pci_bus_speed
);
688 diff
= actual_baud
- baud
;
692 /* If we're within 1%, we've found a match */
693 if (diff
* 100 > actual_baud
)
696 uart
= port
->ip_uart_regs
;
697 lcr
= readb(&uart
->i4u_lcr
);
698 writeb(lcr
| UART_LCR_DLAB
, &uart
->i4u_lcr
);
699 writeb((unsigned char)divisor
, &uart
->i4u_dll
);
700 writeb((unsigned char)(divisor
>> 8), &uart
->i4u_dlm
);
701 writeb(lcr
, &uart
->i4u_lcr
);
707 * get_ioc4_port - given a uart port, return the control structure
710 static struct ioc4_port
*get_ioc4_port(struct uart_port
*the_port
)
712 struct ioc4_driver_data
*idd
= dev_get_drvdata(the_port
->dev
);
713 struct ioc4_control
*control
= idd
->idd_serial_data
;
717 for ( ii
= 0; ii
< IOC4_NUM_SERIAL_PORTS
; ii
++ ) {
718 if (!control
->ic_port
[ii
].icp_port
)
720 if (the_port
== control
->ic_port
[ii
].icp_port
->ip_port
)
721 return control
->ic_port
[ii
].icp_port
;
727 /* The IOC4 hardware provides no atomic way to determine if interrupts
728 * are pending since two reads are required to do so. The handler must
729 * read the SIO_IR and the SIO_IES, and take the logical and of the
730 * two. When this value is zero, all interrupts have been serviced and
731 * the handler may return.
733 * This has the unfortunate "hole" that, if some other CPU or
734 * some other thread or some higher level interrupt manages to
735 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
736 * think we have observed SIO_IR&SIO_IE==0 when in fact this
737 * condition never really occurred.
739 * To solve this, we use a simple spinlock that must be held
740 * whenever modifying SIO_IE; holding this lock while observing
741 * both SIO_IR and SIO_IE guarantees that we do not falsely
742 * conclude that no enabled interrupts are pending.
745 static inline uint32_t
746 pending_intrs(struct ioc4_soft
*soft
, int type
)
748 struct ioc4_misc_regs __iomem
*mem
= soft
->is_ioc4_misc_addr
;
752 BUG_ON(!((type
== IOC4_SIO_INTR_TYPE
)
753 || (type
== IOC4_OTHER_INTR_TYPE
)));
755 spin_lock_irqsave(&soft
->is_ir_lock
, flag
);
758 case IOC4_SIO_INTR_TYPE
:
759 intrs
= readl(&mem
->sio_ir
.raw
) & readl(&mem
->sio_ies
.raw
);
762 case IOC4_OTHER_INTR_TYPE
:
763 intrs
= readl(&mem
->other_ir
.raw
) & readl(&mem
->other_ies
.raw
);
765 /* Don't process any ATA interrupte */
766 intrs
&= ~(IOC4_OTHER_IR_ATA_INT
| IOC4_OTHER_IR_ATA_MEMERR
);
772 spin_unlock_irqrestore(&soft
->is_ir_lock
, flag
);
777 * port_init - Initialize the sio and ioc4 hardware for a given port
778 * called per port from attach...
779 * @port: port to initialize
781 static int inline port_init(struct ioc4_port
*port
)
784 struct hooks
*hooks
= port
->ip_hooks
;
785 struct ioc4_uartregs __iomem
*uart
;
787 /* Idle the IOC4 serial interface */
788 writel(IOC4_SSCR_RESET
, &port
->ip_serial_regs
->sscr
);
790 /* Wait until any pending bus activity for this port has ceased */
792 sio_cr
= readl(&port
->ip_mem
->sio_cr
.raw
);
793 while (!(sio_cr
& IOC4_SIO_CR_SIO_DIAG_IDLE
));
795 /* Finish reset sequence */
796 writel(0, &port
->ip_serial_regs
->sscr
);
798 /* Once RESET is done, reload cached tx_prod and rx_cons values
799 * and set rings to empty by making prod == cons
801 port
->ip_tx_prod
= readl(&port
->ip_serial_regs
->stcir
) & PROD_CONS_MASK
;
802 writel(port
->ip_tx_prod
, &port
->ip_serial_regs
->stpir
);
803 port
->ip_rx_cons
= readl(&port
->ip_serial_regs
->srpir
) & PROD_CONS_MASK
;
804 writel(port
->ip_rx_cons
| IOC4_SRCIR_ARM
, &port
->ip_serial_regs
->srcir
);
806 /* Disable interrupts for this 16550 */
807 uart
= port
->ip_uart_regs
;
808 writeb(0, &uart
->i4u_lcr
);
809 writeb(0, &uart
->i4u_ier
);
811 /* Set the default baud */
812 set_baud(port
, port
->ip_baud
);
814 /* Set line control to 8 bits no parity */
815 writeb(UART_LCR_WLEN8
| 0, &uart
->i4u_lcr
);
816 /* UART_LCR_STOP == 1 stop */
818 /* Enable the FIFOs */
819 writeb(UART_FCR_ENABLE_FIFO
, &uart
->i4u_fcr
);
820 /* then reset 16550 FIFOs */
821 writeb(UART_FCR_ENABLE_FIFO
| UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
,
824 /* Clear modem control register */
825 writeb(0, &uart
->i4u_mcr
);
827 /* Clear deltas in modem status register */
828 readb(&uart
->i4u_msr
);
830 /* Only do this once per port pair */
831 if (port
->ip_hooks
== &hooks_array
[0]
832 || port
->ip_hooks
== &hooks_array
[2]) {
833 unsigned long ring_pci_addr
;
834 uint32_t __iomem
*sbbr_l
;
835 uint32_t __iomem
*sbbr_h
;
837 if (port
->ip_hooks
== &hooks_array
[0]) {
838 sbbr_l
= &port
->ip_serial
->sbbr01_l
;
839 sbbr_h
= &port
->ip_serial
->sbbr01_h
;
841 sbbr_l
= &port
->ip_serial
->sbbr23_l
;
842 sbbr_h
= &port
->ip_serial
->sbbr23_h
;
845 ring_pci_addr
= (unsigned long __iomem
)port
->ip_dma_ringbuf
;
846 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
847 __FUNCTION__
, ring_pci_addr
));
849 writel((unsigned int)((uint64_t)ring_pci_addr
>> 32), sbbr_h
);
850 writel((unsigned int)ring_pci_addr
| IOC4_BUF_SIZE_BIT
, sbbr_l
);
853 /* Set the receive timeout value to 10 msec */
854 writel(IOC4_SRTR_HZ
/ 100, &port
->ip_serial_regs
->srtr
);
856 /* Set rx threshold, enable DMA */
857 /* Set high water mark at 3/4 of full ring */
858 port
->ip_sscr
= (ENTRIES_PER_RING
* 3 / 4);
859 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
861 /* Disable and clear all serial related interrupt bits */
862 write_ireg(port
->ip_ioc4_soft
, hooks
->intr_clear
,
863 IOC4_W_IEC
, IOC4_SIO_INTR_TYPE
);
864 port
->ip_ienb
&= ~hooks
->intr_clear
;
865 writel(hooks
->intr_clear
, &port
->ip_mem
->sio_ir
.raw
);
870 * handle_dma_error_intr - service any pending DMA error interrupts for the
871 * given port - 2nd level called via sd_intr
873 * @other_ir: ioc4regs
875 static void handle_dma_error_intr(void *arg
, uint32_t other_ir
)
877 struct ioc4_port
*port
= (struct ioc4_port
*)arg
;
878 struct hooks
*hooks
= port
->ip_hooks
;
881 spin_lock_irqsave(&port
->ip_lock
, flags
);
883 /* ACK the interrupt */
884 writel(hooks
->intr_dma_error
, &port
->ip_mem
->other_ir
.raw
);
886 if (readl(&port
->ip_mem
->pci_err_addr_l
.raw
) & IOC4_PCI_ERR_ADDR_VLD
) {
888 "PCI error address is 0x%lx, "
889 "master is serial port %c %s\n",
890 (((uint64_t)readl(&port
->ip_mem
->pci_err_addr_h
)
892 | readl(&port
->ip_mem
->pci_err_addr_l
.raw
))
893 & IOC4_PCI_ERR_ADDR_ADDR_MSK
, '1' +
894 ((char)(readl(&port
->ip_mem
->pci_err_addr_l
.raw
) &
895 IOC4_PCI_ERR_ADDR_MST_NUM_MSK
) >> 1),
896 (readl(&port
->ip_mem
->pci_err_addr_l
.raw
)
897 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK
)
900 if (readl(&port
->ip_mem
->pci_err_addr_l
.raw
)
901 & IOC4_PCI_ERR_ADDR_MUL_ERR
) {
903 "Multiple errors occurred\n");
906 spin_unlock_irqrestore(&port
->ip_lock
, flags
);
908 /* Re-enable DMA error interrupts */
909 write_ireg(port
->ip_ioc4_soft
, hooks
->intr_dma_error
, IOC4_W_IES
,
910 IOC4_OTHER_INTR_TYPE
);
914 * intr_connect - interrupt connect function
915 * @soft: soft struct for this card
916 * @type: interrupt type
917 * @intrbits: bit pattern to set
918 * @intr: handler function
922 intr_connect(struct ioc4_soft
*soft
, int type
,
923 uint32_t intrbits
, ioc4_intr_func_f
* intr
, void *info
)
926 struct ioc4_intr_info
*intr_ptr
;
928 BUG_ON(!((type
== IOC4_SIO_INTR_TYPE
)
929 || (type
== IOC4_OTHER_INTR_TYPE
)));
931 i
= atomic_inc(&soft
-> is_intr_type
[type
].is_num_intrs
) - 1;
932 BUG_ON(!(i
< MAX_IOC4_INTR_ENTS
|| (printk("i %d\n", i
), 0)));
934 /* Save off the lower level interrupt handler */
935 intr_ptr
= &soft
->is_intr_type
[type
].is_intr_info
[i
];
936 intr_ptr
->sd_bits
= intrbits
;
937 intr_ptr
->sd_intr
= intr
;
938 intr_ptr
->sd_info
= info
;
942 * ioc4_intr - Top level IOC4 interrupt handler.
947 static irqreturn_t
ioc4_intr(int irq
, void *arg
, struct pt_regs
*regs
)
949 struct ioc4_soft
*soft
;
950 uint32_t this_ir
, this_mir
;
951 int xx
, num_intrs
= 0;
954 struct ioc4_intr_info
*ii
;
957 for (intr_type
= 0; intr_type
< IOC4_NUM_INTR_TYPES
; intr_type
++) {
958 num_intrs
= (int)atomic_read(
959 &soft
->is_intr_type
[intr_type
].is_num_intrs
);
961 this_mir
= this_ir
= pending_intrs(soft
, intr_type
);
963 /* Farm out the interrupt to the various drivers depending on
964 * which interrupt bits are set.
966 for (xx
= 0; xx
< num_intrs
; xx
++) {
967 ii
= &soft
->is_intr_type
[intr_type
].is_intr_info
[xx
];
968 if ((this_mir
= this_ir
& ii
->sd_bits
)) {
969 /* Disable owned interrupts, call handler */
971 write_ireg(soft
, ii
->sd_bits
, IOC4_W_IEC
,
973 ii
->sd_intr(ii
->sd_info
, this_mir
);
974 this_ir
&= ~this_mir
;
979 "unknown IOC4 %s interrupt 0x%x, sio_ir = 0x%x,"
980 " sio_ies = 0x%x, other_ir = 0x%x :"
981 "other_ies = 0x%x\n",
982 (intr_type
== IOC4_SIO_INTR_TYPE
) ? "sio" :
984 readl(&soft
->is_ioc4_misc_addr
->sio_ir
.raw
),
985 readl(&soft
->is_ioc4_misc_addr
->sio_ies
.raw
),
986 readl(&soft
->is_ioc4_misc_addr
->other_ir
.raw
),
987 readl(&soft
->is_ioc4_misc_addr
->other_ies
.raw
));
990 #ifdef DEBUG_INTERRUPTS
992 struct ioc4_misc_regs __iomem
*mem
= soft
->is_ioc4_misc_addr
;
993 spinlock_t
*lp
= &soft
->is_ir_lock
;
996 spin_lock_irqsave(&soft
->is_ir_lock
, flag
);
997 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
998 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
999 __FUNCTION__
, __LINE__
,
1000 (void *)mem
, readl(&mem
->sio_ir
.raw
),
1001 readl(&mem
->sio_ies
.raw
),
1002 readl(&mem
->other_ir
.raw
),
1003 readl(&mem
->other_ies
.raw
),
1004 IOC4_OTHER_IR_ATA_INT
| IOC4_OTHER_IR_ATA_MEMERR
);
1005 spin_unlock_irqrestore(&soft
->is_ir_lock
, flag
);
1008 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1012 * ioc4_attach_local - Device initialization.
1013 * Called at *_attach() time for each
1014 * IOC4 with serial ports in the system.
1015 * @control: ioc4_control ptr
1016 * @pdev: PCI handle for this device
1017 * @soft: soft struct for this device
1018 * @ioc4: ioc4 mem space
1020 static int inline ioc4_attach_local(struct pci_dev
*pdev
,
1021 struct ioc4_control
*control
,
1022 struct ioc4_soft
*soft
, void __iomem
*ioc4_misc
,
1023 void __iomem
*ioc4_serial
)
1025 struct ioc4_port
*port
;
1026 struct ioc4_port
*ports
[IOC4_NUM_SERIAL_PORTS
];
1028 uint16_t ioc4_revid_min
= 62;
1029 uint16_t ioc4_revid
;
1031 /* IOC4 firmware must be at least rev 62 */
1032 pci_read_config_word(pdev
, PCI_COMMAND_SPECIAL
, &ioc4_revid
);
1034 printk(KERN_INFO
"IOC4 firmware revision %d\n", ioc4_revid
);
1035 if (ioc4_revid
< ioc4_revid_min
) {
1037 "IOC4 serial not supported on firmware rev %d, "
1038 "please upgrade to rev %d or higher\n",
1039 ioc4_revid
, ioc4_revid_min
);
1042 BUG_ON(ioc4_misc
== NULL
);
1043 BUG_ON(ioc4_serial
== NULL
);
1045 /* Create port structures for each port */
1046 for (port_number
= 0; port_number
< IOC4_NUM_SERIAL_PORTS
;
1048 port
= kmalloc(sizeof(struct ioc4_port
), GFP_KERNEL
);
1051 "IOC4 serial memory not available for port\n");
1054 memset(port
, 0, sizeof(struct ioc4_port
));
1056 /* we need to remember the previous ones, to point back to
1057 * them farther down - setting up the ring buffers.
1059 ports
[port_number
] = port
;
1061 /* Allocate buffers and jumpstart the hardware. */
1062 control
->ic_port
[port_number
].icp_port
= port
;
1063 port
->ip_ioc4_soft
= soft
;
1064 port
->ip_pdev
= pdev
;
1066 port
->ip_pci_bus_speed
= IOC4_SER_XIN_CLK
;
1067 port
->ip_baud
= 9600;
1068 port
->ip_control
= control
;
1069 port
->ip_mem
= ioc4_misc
;
1070 port
->ip_serial
= ioc4_serial
;
1072 /* point to the right hook */
1073 port
->ip_hooks
= &hooks_array
[port_number
];
1075 /* Get direct hooks to the serial regs and uart regs
1078 switch (port_number
) {
1080 port
->ip_serial_regs
= &(port
->ip_serial
->port_0
);
1081 port
->ip_uart_regs
= &(port
->ip_serial
->uart_0
);
1084 port
->ip_serial_regs
= &(port
->ip_serial
->port_1
);
1085 port
->ip_uart_regs
= &(port
->ip_serial
->uart_1
);
1088 port
->ip_serial_regs
= &(port
->ip_serial
->port_2
);
1089 port
->ip_uart_regs
= &(port
->ip_serial
->uart_2
);
1093 port
->ip_serial_regs
= &(port
->ip_serial
->port_3
);
1094 port
->ip_uart_regs
= &(port
->ip_serial
->uart_3
);
1098 /* ring buffers are 1 to a pair of ports */
1099 if (port_number
&& (port_number
& 1)) {
1100 /* odd use the evens buffer */
1101 port
->ip_dma_ringbuf
=
1102 ports
[port_number
- 1]->ip_dma_ringbuf
;
1103 port
->ip_cpu_ringbuf
=
1104 ports
[port_number
- 1]->ip_cpu_ringbuf
;
1105 port
->ip_inring
= RING(port
, RX_1_OR_3
);
1106 port
->ip_outring
= RING(port
, TX_1_OR_3
);
1109 if (port
->ip_dma_ringbuf
== 0) {
1110 port
->ip_cpu_ringbuf
= pci_alloc_consistent
1111 (pdev
, TOTAL_RING_BUF_SIZE
,
1112 &port
->ip_dma_ringbuf
);
1115 BUG_ON(!((((int64_t)port
->ip_dma_ringbuf
) &
1116 (TOTAL_RING_BUF_SIZE
- 1)) == 0));
1117 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1118 "ip_dma_ringbuf 0x%p\n",
1120 (void *)port
->ip_cpu_ringbuf
,
1121 (void *)port
->ip_dma_ringbuf
));
1122 port
->ip_inring
= RING(port
, RX_0_OR_2
);
1123 port
->ip_outring
= RING(port
, TX_0_OR_2
);
1125 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1127 port_number
, (void *)port
, (void *)control
));
1128 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1129 (void *)port
->ip_serial_regs
,
1130 (void *)port
->ip_uart_regs
));
1132 /* Initialize the hardware for IOC4 */
1135 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1138 port_number
, (void *)port
,
1139 (void *)port
->ip_inring
,
1140 (void *)port
->ip_outring
));
1142 /* Attach interrupt handlers */
1143 intr_connect(soft
, IOC4_SIO_INTR_TYPE
,
1144 GET_SIO_IR(port_number
),
1147 intr_connect(soft
, IOC4_OTHER_INTR_TYPE
,
1148 GET_OTHER_IR(port_number
),
1149 handle_dma_error_intr
, port
);
1155 * enable_intrs - enable interrupts
1156 * @port: port to enable
1157 * @mask: mask to use
1159 static void enable_intrs(struct ioc4_port
*port
, uint32_t mask
)
1161 struct hooks
*hooks
= port
->ip_hooks
;
1163 if ((port
->ip_ienb
& mask
) != mask
) {
1164 write_ireg(port
->ip_ioc4_soft
, mask
, IOC4_W_IES
,
1165 IOC4_SIO_INTR_TYPE
);
1166 port
->ip_ienb
|= mask
;
1170 write_ireg(port
->ip_ioc4_soft
, hooks
->intr_dma_error
,
1171 IOC4_W_IES
, IOC4_OTHER_INTR_TYPE
);
1175 * local_open - local open a port
1176 * @port: port to open
1178 static inline int local_open(struct ioc4_port
*port
)
1184 /* Pause the DMA interface if necessary */
1185 if (port
->ip_sscr
& IOC4_SSCR_DMA_EN
) {
1186 writel(port
->ip_sscr
| IOC4_SSCR_DMA_PAUSE
,
1187 &port
->ip_serial_regs
->sscr
);
1188 while((readl(&port
->ip_serial_regs
-> sscr
)
1189 & IOC4_SSCR_PAUSE_STATE
) == 0) {
1191 if (spiniter
> MAXITER
) {
1197 /* Reset the input fifo. If the uart received chars while the port
1198 * was closed and DMA is not enabled, the uart may have a bunch of
1199 * chars hanging around in its rx fifo which will not be discarded
1200 * by rclr in the upper layer. We must get rid of them here.
1202 writeb(UART_FCR_ENABLE_FIFO
| UART_FCR_CLEAR_RCVR
,
1203 &port
->ip_uart_regs
->i4u_fcr
);
1205 writeb(UART_LCR_WLEN8
, &port
->ip_uart_regs
->i4u_lcr
);
1206 /* UART_LCR_STOP == 1 stop */
1208 /* Re-enable DMA, set default threshold to intr whenever there is
1211 port
->ip_sscr
&= ~IOC4_SSCR_RX_THRESHOLD
;
1212 port
->ip_sscr
|= 1; /* default threshold */
1214 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1215 * flag if it was set above
1217 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1218 port
->ip_tx_lowat
= 1;
1223 * set_rx_timeout - Set rx timeout and threshold values.
1224 * @port: port to use
1225 * @timeout: timeout value in ticks
1227 static inline int set_rx_timeout(struct ioc4_port
*port
, int timeout
)
1231 port
->ip_rx_timeout
= timeout
;
1233 /* Timeout is in ticks. Let's figure out how many chars we
1234 * can receive at the current baud rate in that interval
1235 * and set the rx threshold to that amount. There are 4 chars
1236 * per ring entry, so we'll divide the number of chars that will
1237 * arrive in timeout by 4.
1238 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1240 threshold
= timeout
* port
->ip_baud
/ 4000;
1242 threshold
= 1; /* otherwise we'll intr all the time! */
1244 if ((unsigned)threshold
> (unsigned)IOC4_SSCR_RX_THRESHOLD
)
1247 port
->ip_sscr
&= ~IOC4_SSCR_RX_THRESHOLD
;
1248 port
->ip_sscr
|= threshold
;
1250 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1252 /* Now set the rx timeout to the given value
1253 * again timeout * IOC4_SRTR_HZ / HZ
1255 timeout
= timeout
* IOC4_SRTR_HZ
/ 100;
1256 if (timeout
> IOC4_SRTR_CNT
)
1257 timeout
= IOC4_SRTR_CNT
;
1259 writel(timeout
, &port
->ip_serial_regs
->srtr
);
1264 * config_port - config the hardware
1265 * @port: port to config
1266 * @baud: baud rate for the port
1267 * @byte_size: data size
1268 * @stop_bits: number of stop bits
1269 * @parenb: parity enable ?
1270 * @parodd: odd parity ?
1273 config_port(struct ioc4_port
*port
,
1274 int baud
, int byte_size
, int stop_bits
, int parenb
, int parodd
)
1279 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1280 __FUNCTION__
, baud
, byte_size
, stop_bits
, parenb
, parodd
));
1282 if (set_baud(port
, baud
))
1285 switch (byte_size
) {
1287 sizebits
= UART_LCR_WLEN5
;
1290 sizebits
= UART_LCR_WLEN6
;
1293 sizebits
= UART_LCR_WLEN7
;
1296 sizebits
= UART_LCR_WLEN8
;
1302 /* Pause the DMA interface if necessary */
1303 if (port
->ip_sscr
& IOC4_SSCR_DMA_EN
) {
1304 writel(port
->ip_sscr
| IOC4_SSCR_DMA_PAUSE
,
1305 &port
->ip_serial_regs
->sscr
);
1306 while((readl(&port
->ip_serial_regs
->sscr
)
1307 & IOC4_SSCR_PAUSE_STATE
) == 0) {
1309 if (spiniter
> MAXITER
)
1314 /* Clear relevant fields in lcr */
1315 lcr
= readb(&port
->ip_uart_regs
->i4u_lcr
);
1316 lcr
&= ~(LCR_MASK_BITS_CHAR
| UART_LCR_EPAR
|
1317 UART_LCR_PARITY
| LCR_MASK_STOP_BITS
);
1319 /* Set byte size in lcr */
1324 lcr
|= UART_LCR_PARITY
;
1326 lcr
|= UART_LCR_EPAR
;
1331 lcr
|= UART_LCR_STOP
/* 2 stop bits */ ;
1333 writeb(lcr
, &port
->ip_uart_regs
->i4u_lcr
);
1335 /* Re-enable the DMA interface if necessary */
1336 if (port
->ip_sscr
& IOC4_SSCR_DMA_EN
) {
1337 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1339 port
->ip_baud
= baud
;
1341 /* When we get within this number of ring entries of filling the
1342 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1343 * notification when output has drained.
1345 port
->ip_tx_lowat
= (TX_LOWAT_CHARS(baud
) + 3) / 4;
1346 if (port
->ip_tx_lowat
== 0)
1347 port
->ip_tx_lowat
= 1;
1349 set_rx_timeout(port
, 2);
1355 * do_write - Write bytes to the port. Returns the number of bytes
1356 * actually written. Called from transmit_chars
1357 * @port: port to use
1358 * @buf: the stuff to write
1359 * @len: how many bytes in 'buf'
1361 static inline int do_write(struct ioc4_port
*port
, char *buf
, int len
)
1363 int prod_ptr
, cons_ptr
, total
= 0;
1364 struct ring
*outring
;
1365 struct ring_entry
*entry
;
1366 struct hooks
*hooks
= port
->ip_hooks
;
1368 BUG_ON(!(len
>= 0));
1370 prod_ptr
= port
->ip_tx_prod
;
1371 cons_ptr
= readl(&port
->ip_serial_regs
->stcir
) & PROD_CONS_MASK
;
1372 outring
= port
->ip_outring
;
1374 /* Maintain a 1-entry red-zone. The ring buffer is full when
1375 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1376 * in the body of the loop, I'll do it now.
1378 cons_ptr
= (cons_ptr
- (int)sizeof(struct ring_entry
)) & PROD_CONS_MASK
;
1380 /* Stuff the bytes into the output */
1381 while ((prod_ptr
!= cons_ptr
) && (len
> 0)) {
1384 /* Get 4 bytes (one ring entry) at a time */
1385 entry
= (struct ring_entry
*)((caddr_t
) outring
+ prod_ptr
);
1387 /* Invalidate all entries */
1388 entry
->ring_allsc
= 0;
1390 /* Copy in some bytes */
1391 for (xx
= 0; (xx
< 4) && (len
> 0); xx
++) {
1392 entry
->ring_data
[xx
] = *buf
++;
1393 entry
->ring_sc
[xx
] = IOC4_TXCB_VALID
;
1398 /* If we are within some small threshold of filling up the
1399 * entire ring buffer, we must place an EXPLICIT intr here
1400 * to generate a lowat interrupt in case we subsequently
1401 * really do fill up the ring and the caller goes to sleep.
1402 * No need to place more than one though.
1404 if (!(port
->ip_flags
& LOWAT_WRITTEN
) &&
1405 ((cons_ptr
- prod_ptr
) & PROD_CONS_MASK
)
1406 <= port
->ip_tx_lowat
1407 * (int)sizeof(struct ring_entry
)) {
1408 port
->ip_flags
|= LOWAT_WRITTEN
;
1409 entry
->ring_sc
[0] |= IOC4_TXCB_INT_WHEN_DONE
;
1412 /* Go on to next entry */
1413 prod_ptr
+= sizeof(struct ring_entry
);
1414 prod_ptr
&= PROD_CONS_MASK
;
1417 /* If we sent something, start DMA if necessary */
1418 if (total
> 0 && !(port
->ip_sscr
& IOC4_SSCR_DMA_EN
)) {
1419 port
->ip_sscr
|= IOC4_SSCR_DMA_EN
;
1420 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1423 /* Store the new producer pointer. If tx is disabled, we stuff the
1424 * data into the ring buffer, but we don't actually start tx.
1426 if (!uart_tx_stopped(port
->ip_port
)) {
1427 writel(prod_ptr
, &port
->ip_serial_regs
->stpir
);
1429 /* If we are now transmitting, enable tx_mt interrupt so we
1430 * can disable DMA if necessary when the tx finishes.
1433 enable_intrs(port
, hooks
->intr_tx_mt
);
1435 port
->ip_tx_prod
= prod_ptr
;
1440 * disable_intrs - disable interrupts
1441 * @port: port to enable
1442 * @mask: mask to use
1444 static void disable_intrs(struct ioc4_port
*port
, uint32_t mask
)
1446 struct hooks
*hooks
= port
->ip_hooks
;
1448 if (port
->ip_ienb
& mask
) {
1449 write_ireg(port
->ip_ioc4_soft
, mask
, IOC4_W_IEC
,
1450 IOC4_SIO_INTR_TYPE
);
1451 port
->ip_ienb
&= ~mask
;
1455 write_ireg(port
->ip_ioc4_soft
, hooks
->intr_dma_error
,
1456 IOC4_W_IEC
, IOC4_OTHER_INTR_TYPE
);
1460 * set_notification - Modify event notification
1461 * @port: port to use
1462 * @mask: events mask
1465 static int set_notification(struct ioc4_port
*port
, int mask
, int set_on
)
1467 struct hooks
*hooks
= port
->ip_hooks
;
1468 uint32_t intrbits
, sscrbits
;
1472 intrbits
= sscrbits
= 0;
1474 if (mask
& N_DATA_READY
)
1475 intrbits
|= (hooks
->intr_rx_timer
| hooks
->intr_rx_high
);
1476 if (mask
& N_OUTPUT_LOWAT
)
1477 intrbits
|= hooks
->intr_tx_explicit
;
1478 if (mask
& N_DDCD
) {
1479 intrbits
|= hooks
->intr_delta_dcd
;
1480 sscrbits
|= IOC4_SSCR_RX_RING_DCD
;
1483 intrbits
|= hooks
->intr_delta_cts
;
1486 enable_intrs(port
, intrbits
);
1487 port
->ip_notify
|= mask
;
1488 port
->ip_sscr
|= sscrbits
;
1490 disable_intrs(port
, intrbits
);
1491 port
->ip_notify
&= ~mask
;
1492 port
->ip_sscr
&= ~sscrbits
;
1495 /* We require DMA if either DATA_READY or DDCD notification is
1496 * currently requested. If neither of these is requested and
1497 * there is currently no tx in progress, DMA may be disabled.
1499 if (port
->ip_notify
& (N_DATA_READY
| N_DDCD
))
1500 port
->ip_sscr
|= IOC4_SSCR_DMA_EN
;
1501 else if (!(port
->ip_ienb
& hooks
->intr_tx_mt
))
1502 port
->ip_sscr
&= ~IOC4_SSCR_DMA_EN
;
1504 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1509 * set_mcr - set the master control reg
1510 * @the_port: port to use
1513 * @mask2: shadow mask
1515 static inline int set_mcr(struct uart_port
*the_port
, int set
,
1516 int mask1
, int mask2
)
1518 struct ioc4_port
*port
= get_ioc4_port(the_port
);
1526 /* Pause the DMA interface if necessary */
1527 if (port
->ip_sscr
& IOC4_SSCR_DMA_EN
) {
1528 writel(port
->ip_sscr
| IOC4_SSCR_DMA_PAUSE
,
1529 &port
->ip_serial_regs
->sscr
);
1530 while ((readl(&port
->ip_serial_regs
->sscr
)
1531 & IOC4_SSCR_PAUSE_STATE
) == 0) {
1533 if (spiniter
> MAXITER
)
1537 shadow
= readl(&port
->ip_serial_regs
->shadow
);
1538 mcr
= (shadow
& 0xff000000) >> 24;
1548 writeb(mcr
, &port
->ip_uart_regs
->i4u_mcr
);
1549 writel(shadow
, &port
->ip_serial_regs
->shadow
);
1551 /* Re-enable the DMA interface if necessary */
1552 if (port
->ip_sscr
& IOC4_SSCR_DMA_EN
) {
1553 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1559 * ioc4_set_proto - set the protocol for the port
1560 * @port: port to use
1561 * @proto: protocol to use
1563 static int ioc4_set_proto(struct ioc4_port
*port
, enum sio_proto proto
)
1565 struct hooks
*hooks
= port
->ip_hooks
;
1569 /* Clear the appropriate GIO pin */
1570 writel(0, (&port
->ip_mem
->gppr
[hooks
->rs422_select_pin
].raw
));
1574 /* Set the appropriate GIO pin */
1575 writel(1, (&port
->ip_mem
->gppr
[hooks
->rs422_select_pin
].raw
));
1585 * transmit_chars - upper level write, called with ip_lock
1586 * @the_port: port to write
1588 static void transmit_chars(struct uart_port
*the_port
)
1590 int xmit_count
, tail
, head
;
1593 struct tty_struct
*tty
;
1594 struct ioc4_port
*port
= get_ioc4_port(the_port
);
1595 struct uart_info
*info
;
1602 info
= the_port
->info
;
1605 if (uart_circ_empty(&info
->xmit
) || uart_tx_stopped(the_port
)) {
1606 /* Nothing to do or hw stopped */
1607 set_notification(port
, N_ALL_OUTPUT
, 0);
1611 head
= info
->xmit
.head
;
1612 tail
= info
->xmit
.tail
;
1613 start
= (char *)&info
->xmit
.buf
[tail
];
1615 /* write out all the data or until the end of the buffer */
1616 xmit_count
= (head
< tail
) ? (UART_XMIT_SIZE
- tail
) : (head
- tail
);
1617 if (xmit_count
> 0) {
1618 result
= do_write(port
, start
, xmit_count
);
1621 xmit_count
-= result
;
1622 the_port
->icount
.tx
+= result
;
1623 /* advance the pointers */
1625 tail
&= UART_XMIT_SIZE
- 1;
1626 info
->xmit
.tail
= tail
;
1627 start
= (char *)&info
->xmit
.buf
[tail
];
1630 if (uart_circ_chars_pending(&info
->xmit
) < WAKEUP_CHARS
)
1631 uart_write_wakeup(the_port
);
1633 if (uart_circ_empty(&info
->xmit
)) {
1634 set_notification(port
, N_OUTPUT_LOWAT
, 0);
1636 set_notification(port
, N_OUTPUT_LOWAT
, 1);
1641 * ioc4_change_speed - change the speed of the port
1642 * @the_port: port to change
1643 * @new_termios: new termios settings
1644 * @old_termios: old termios settings
1647 ioc4_change_speed(struct uart_port
*the_port
,
1648 struct termios
*new_termios
, struct termios
*old_termios
)
1650 struct ioc4_port
*port
= get_ioc4_port(the_port
);
1653 int new_parity
= 0, new_parity_enable
= 0, new_stop
= 0, new_data
= 8;
1654 struct uart_info
*info
= the_port
->info
;
1656 cflag
= new_termios
->c_cflag
;
1658 switch (cflag
& CSIZE
) {
1676 /* cuz we always need a default ... */
1681 if (cflag
& CSTOPB
) {
1685 if (cflag
& PARENB
) {
1687 new_parity_enable
= 1;
1691 baud
= uart_get_baud_rate(the_port
, new_termios
, old_termios
,
1692 MIN_BAUD_SUPPORTED
, MAX_BAUD_SUPPORTED
);
1693 DPRINT_CONFIG(("%s: returned baud %d\n", __FUNCTION__
, baud
));
1695 /* default is 9600 */
1699 if (!the_port
->fifosize
)
1700 the_port
->fifosize
= IOC4_MAX_CHARS
;
1701 the_port
->timeout
= ((the_port
->fifosize
* HZ
* bits
) / (baud
/ 10));
1702 the_port
->timeout
+= HZ
/ 50; /* Add .02 seconds of slop */
1704 the_port
->ignore_status_mask
= N_ALL_INPUT
;
1706 if (I_IGNPAR(info
->tty
))
1707 the_port
->ignore_status_mask
&= ~(N_PARITY_ERROR
1709 if (I_IGNBRK(info
->tty
)) {
1710 the_port
->ignore_status_mask
&= ~N_BREAK
;
1711 if (I_IGNPAR(info
->tty
))
1712 the_port
->ignore_status_mask
&= ~N_OVERRUN_ERROR
;
1714 if (!(cflag
& CREAD
)) {
1715 /* ignore everything */
1716 the_port
->ignore_status_mask
&= ~N_DATA_READY
;
1719 if (cflag
& CRTSCTS
) {
1720 info
->flags
|= ASYNC_CTS_FLOW
;
1721 port
->ip_sscr
|= IOC4_SSCR_HFC_EN
;
1724 info
->flags
&= ~ASYNC_CTS_FLOW
;
1725 port
->ip_sscr
&= ~IOC4_SSCR_HFC_EN
;
1727 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
1729 /* Set the configuration and proper notification call */
1730 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1731 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1732 " notification 0x%x\n",
1733 __FUNCTION__
, (void *)port
, cflag
, baud
, new_data
, new_stop
,
1734 new_parity_enable
, new_parity
, the_port
->ignore_status_mask
));
1736 if ((config_port(port
, baud
, /* baud */
1737 new_data
, /* byte size */
1738 new_stop
, /* stop bits */
1739 new_parity_enable
, /* set parity */
1740 new_parity
)) >= 0) { /* parity 1==odd */
1741 set_notification(port
, the_port
->ignore_status_mask
, 1);
1746 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1747 * @the_port: Port to operate on
1749 static inline int ic4_startup_local(struct uart_port
*the_port
)
1752 struct ioc4_port
*port
;
1753 struct uart_info
*info
;
1758 port
= get_ioc4_port(the_port
);
1762 info
= the_port
->info
;
1763 if (info
->flags
& UIF_INITIALIZED
) {
1768 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1769 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1770 if ((info
->flags
& ASYNC_SPD_MASK
) == ASYNC_SPD_HI
)
1771 info
->tty
->alt_speed
= 57600;
1772 if ((info
->flags
& ASYNC_SPD_MASK
) == ASYNC_SPD_VHI
)
1773 info
->tty
->alt_speed
= 115200;
1774 if ((info
->flags
& ASYNC_SPD_MASK
) == ASYNC_SPD_SHI
)
1775 info
->tty
->alt_speed
= 230400;
1776 if ((info
->flags
& ASYNC_SPD_MASK
) == ASYNC_SPD_WARP
)
1777 info
->tty
->alt_speed
= 460800;
1781 /* set the speed of the serial port */
1782 ioc4_change_speed(the_port
, info
->tty
->termios
, (struct termios
*)0);
1784 info
->flags
|= UIF_INITIALIZED
;
1789 * ioc4_cb_output_lowat - called when the output low water mark is hit
1790 * @port: port to output
1792 static void ioc4_cb_output_lowat(struct ioc4_port
*port
)
1794 /* ip_lock is set on the call here */
1795 if (port
->ip_port
) {
1796 transmit_chars(port
->ip_port
);
1801 * handle_intr - service any interrupts for the given port - 2nd level
1802 * called via sd_intr
1806 static void handle_intr(void *arg
, uint32_t sio_ir
)
1808 struct ioc4_port
*port
= (struct ioc4_port
*)arg
;
1809 struct hooks
*hooks
= port
->ip_hooks
;
1810 unsigned int rx_high_rd_aborted
= 0;
1812 struct uart_port
*the_port
;
1815 /* Possible race condition here: The tx_mt interrupt bit may be
1816 * cleared without the intervention of the interrupt handler,
1817 * e.g. by a write. If the top level interrupt handler reads a
1818 * tx_mt, then some other processor does a write, starting up
1819 * output, then we come in here, see the tx_mt and stop DMA, the
1820 * output started by the other processor will hang. Thus we can
1821 * only rely on tx_mt being legitimate if it is read while the
1822 * port lock is held. Therefore this bit must be ignored in the
1823 * passed in interrupt mask which was read by the top level
1824 * interrupt handler since the port lock was not held at the time
1825 * it was read. We can only rely on this bit being accurate if it
1826 * is read while the port lock is held. So we'll clear it for now,
1827 * and reload it later once we have the port lock.
1829 sio_ir
&= ~(hooks
->intr_tx_mt
);
1831 spin_lock_irqsave(&port
->ip_lock
, flags
);
1833 loop_counter
= MAXITER
; /* to avoid hangs */
1838 if ( loop_counter
-- <= 0 ) {
1839 printk(KERN_WARNING
"IOC4 serial: "
1840 "possible hang condition/"
1841 "port stuck on interrupt.\n");
1845 /* Handle a DCD change */
1846 if (sio_ir
& hooks
->intr_delta_dcd
) {
1847 /* ACK the interrupt */
1848 writel(hooks
->intr_delta_dcd
,
1849 &port
->ip_mem
->sio_ir
.raw
);
1851 shadow
= readl(&port
->ip_serial_regs
->shadow
);
1853 if ((port
->ip_notify
& N_DDCD
)
1854 && (shadow
& IOC4_SHADOW_DCD
)
1855 && (port
->ip_port
)) {
1856 the_port
= port
->ip_port
;
1857 the_port
->icount
.dcd
= 1;
1858 wake_up_interruptible
1859 (&the_port
-> info
->delta_msr_wait
);
1860 } else if ((port
->ip_notify
& N_DDCD
)
1861 && !(shadow
& IOC4_SHADOW_DCD
)) {
1862 /* Flag delta DCD/no DCD */
1863 port
->ip_flags
|= DCD_ON
;
1867 /* Handle a CTS change */
1868 if (sio_ir
& hooks
->intr_delta_cts
) {
1869 /* ACK the interrupt */
1870 writel(hooks
->intr_delta_cts
,
1871 &port
->ip_mem
->sio_ir
.raw
);
1873 shadow
= readl(&port
->ip_serial_regs
->shadow
);
1875 if ((port
->ip_notify
& N_DCTS
)
1876 && (port
->ip_port
)) {
1877 the_port
= port
->ip_port
;
1878 the_port
->icount
.cts
=
1879 (shadow
& IOC4_SHADOW_CTS
) ? 1 : 0;
1880 wake_up_interruptible
1881 (&the_port
->info
->delta_msr_wait
);
1885 /* rx timeout interrupt. Must be some data available. Put this
1886 * before the check for rx_high since servicing this condition
1887 * may cause that condition to clear.
1889 if (sio_ir
& hooks
->intr_rx_timer
) {
1890 /* ACK the interrupt */
1891 writel(hooks
->intr_rx_timer
,
1892 &port
->ip_mem
->sio_ir
.raw
);
1894 if ((port
->ip_notify
& N_DATA_READY
)
1895 && (port
->ip_port
)) {
1896 /* ip_lock is set on call here */
1897 receive_chars(port
->ip_port
);
1901 /* rx high interrupt. Must be after rx_timer. */
1902 else if (sio_ir
& hooks
->intr_rx_high
) {
1903 /* Data available, notify upper layer */
1904 if ((port
->ip_notify
& N_DATA_READY
)
1906 /* ip_lock is set on call here */
1907 receive_chars(port
->ip_port
);
1910 /* We can't ACK this interrupt. If receive_chars didn't
1911 * cause the condition to clear, we'll have to disable
1912 * the interrupt until the data is drained.
1913 * If the read was aborted, don't disable the interrupt
1914 * as this may cause us to hang indefinitely. An
1915 * aborted read generally means that this interrupt
1916 * hasn't been delivered to the cpu yet anyway, even
1917 * though we see it as asserted when we read the sio_ir.
1919 if ((sio_ir
= PENDING(port
)) & hooks
->intr_rx_high
) {
1920 if ((port
->ip_flags
& READ_ABORTED
) == 0) {
1921 port
->ip_ienb
&= ~hooks
->intr_rx_high
;
1922 port
->ip_flags
|= INPUT_HIGH
;
1924 rx_high_rd_aborted
++;
1929 /* We got a low water interrupt: notify upper layer to
1930 * send more data. Must come before tx_mt since servicing
1931 * this condition may cause that condition to clear.
1933 if (sio_ir
& hooks
->intr_tx_explicit
) {
1934 port
->ip_flags
&= ~LOWAT_WRITTEN
;
1936 /* ACK the interrupt */
1937 writel(hooks
->intr_tx_explicit
,
1938 &port
->ip_mem
->sio_ir
.raw
);
1940 if (port
->ip_notify
& N_OUTPUT_LOWAT
)
1941 ioc4_cb_output_lowat(port
);
1944 /* Handle tx_mt. Must come after tx_explicit. */
1945 else if (sio_ir
& hooks
->intr_tx_mt
) {
1946 /* If we are expecting a lowat notification
1947 * and we get to this point it probably means that for
1948 * some reason the tx_explicit didn't work as expected
1949 * (that can legitimately happen if the output buffer is
1950 * filled up in just the right way).
1951 * So send the notification now.
1953 if (port
->ip_notify
& N_OUTPUT_LOWAT
) {
1954 ioc4_cb_output_lowat(port
);
1956 /* We need to reload the sio_ir since the lowat
1957 * call may have caused another write to occur,
1958 * clearing the tx_mt condition.
1960 sio_ir
= PENDING(port
);
1963 /* If the tx_mt condition still persists even after the
1964 * lowat call, we've got some work to do.
1966 if (sio_ir
& hooks
->intr_tx_mt
) {
1968 /* If we are not currently expecting DMA input,
1969 * and the transmitter has just gone idle,
1970 * there is no longer any reason for DMA, so
1973 if (!(port
->ip_notify
1974 & (N_DATA_READY
| N_DDCD
))) {
1975 BUG_ON(!(port
->ip_sscr
1976 & IOC4_SSCR_DMA_EN
));
1977 port
->ip_sscr
&= ~IOC4_SSCR_DMA_EN
;
1978 writel(port
->ip_sscr
,
1979 &port
->ip_serial_regs
->sscr
);
1982 /* Prevent infinite tx_mt interrupt */
1983 port
->ip_ienb
&= ~hooks
->intr_tx_mt
;
1986 sio_ir
= PENDING(port
);
1988 /* if the read was aborted and only hooks->intr_rx_high,
1989 * clear hooks->intr_rx_high, so we do not loop forever.
1992 if (rx_high_rd_aborted
&& (sio_ir
== hooks
->intr_rx_high
)) {
1993 sio_ir
&= ~hooks
->intr_rx_high
;
1995 } while (sio_ir
& hooks
->intr_all
);
1997 spin_unlock_irqrestore(&port
->ip_lock
, flags
);
1999 /* Re-enable interrupts before returning from interrupt handler.
2000 * Getting interrupted here is okay. It'll just v() our semaphore, and
2001 * we'll come through the loop again.
2004 write_ireg(port
->ip_ioc4_soft
, port
->ip_ienb
, IOC4_W_IES
,
2005 IOC4_SIO_INTR_TYPE
);
2009 * ioc4_cb_post_ncs - called for some basic errors
2010 * @port: port to use
2013 static void ioc4_cb_post_ncs(struct uart_port
*the_port
, int ncs
)
2015 struct uart_icount
*icount
;
2017 icount
= &the_port
->icount
;
2019 if (ncs
& NCS_BREAK
)
2021 if (ncs
& NCS_FRAMING
)
2023 if (ncs
& NCS_OVERRUN
)
2025 if (ncs
& NCS_PARITY
)
2030 * do_read - Read in bytes from the port. Return the number of bytes
2032 * @the_port: port to use
2033 * @buf: place to put the stuff we read
2034 * @len: how big 'buf' is
2037 static inline int do_read(struct uart_port
*the_port
, unsigned char *buf
,
2040 int prod_ptr
, cons_ptr
, total
;
2041 struct ioc4_port
*port
= get_ioc4_port(the_port
);
2042 struct ring
*inring
;
2043 struct ring_entry
*entry
;
2044 struct hooks
*hooks
= port
->ip_hooks
;
2049 BUG_ON(!(len
>= 0));
2052 /* There is a nasty timing issue in the IOC4. When the rx_timer
2053 * expires or the rx_high condition arises, we take an interrupt.
2054 * At some point while servicing the interrupt, we read bytes from
2055 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2056 * not started until the first byte is received *after* it is armed,
2057 * and any bytes pending in the rx construction buffers are not drained
2058 * to memory until either there are 4 bytes available or the rx_timer
2059 * expires. This leads to a potential situation where data is left
2060 * in the construction buffers forever - 1 to 3 bytes were received
2061 * after the interrupt was generated but before the rx_timer was
2062 * re-armed. At that point as long as no subsequent bytes are received
2063 * the timer will never be started and the bytes will remain in the
2064 * construction buffer forever. The solution is to execute a DRAIN
2065 * command after rearming the timer. This way any bytes received before
2066 * the DRAIN will be drained to memory, and any bytes received after
2067 * the DRAIN will start the TIMER and be drained when it expires.
2068 * Luckily, this only needs to be done when the DMA buffer is empty
2069 * since there is no requirement that this function return all
2070 * available data as long as it returns some.
2072 /* Re-arm the timer */
2073 writel(port
->ip_rx_cons
| IOC4_SRCIR_ARM
,
2074 &port
->ip_serial_regs
->srcir
);
2076 prod_ptr
= readl(&port
->ip_serial_regs
->srpir
) & PROD_CONS_MASK
;
2077 cons_ptr
= port
->ip_rx_cons
;
2079 if (prod_ptr
== cons_ptr
) {
2082 /* Input buffer appears empty, do a flush. */
2084 /* DMA must be enabled for this to work. */
2085 if (!(port
->ip_sscr
& IOC4_SSCR_DMA_EN
)) {
2086 port
->ip_sscr
|= IOC4_SSCR_DMA_EN
;
2090 /* Potential race condition: we must reload the srpir after
2091 * issuing the drain command, otherwise we could think the rx
2092 * buffer is empty, then take a very long interrupt, and when
2093 * we come back it's full and we wait forever for the drain to
2096 writel(port
->ip_sscr
| IOC4_SSCR_RX_DRAIN
,
2097 &port
->ip_serial_regs
->sscr
);
2098 prod_ptr
= readl(&port
->ip_serial_regs
->srpir
)
2101 /* We must not wait for the DRAIN to complete unless there are
2102 * at least 8 bytes (2 ring entries) available to receive the
2103 * data otherwise the DRAIN will never complete and we'll
2105 * In fact, to make things easier, I'll just ignore the flush if
2106 * there is any data at all now available.
2108 if (prod_ptr
== cons_ptr
) {
2110 while (readl(&port
->ip_serial_regs
->sscr
) &
2111 IOC4_SSCR_RX_DRAIN
) {
2113 if (loop_counter
> MAXITER
)
2117 /* SIGH. We have to reload the prod_ptr *again* since
2118 * the drain may have caused it to change
2120 prod_ptr
= readl(&port
->ip_serial_regs
->srpir
)
2124 port
->ip_sscr
&= ~IOC4_SSCR_DMA_EN
;
2125 writel(port
->ip_sscr
, &port
->ip_serial_regs
->sscr
);
2128 inring
= port
->ip_inring
;
2129 port
->ip_flags
&= ~READ_ABORTED
;
2132 loop_counter
= 0xfffff; /* to avoid hangs */
2134 /* Grab bytes from the hardware */
2135 while ((prod_ptr
!= cons_ptr
) && (len
> 0)) {
2136 entry
= (struct ring_entry
*)((caddr_t
)inring
+ cons_ptr
);
2138 if ( loop_counter
-- <= 0 ) {
2139 printk(KERN_WARNING
"IOC4 serial: "
2140 "possible hang condition/"
2141 "port stuck on read.\n");
2145 /* According to the producer pointer, this ring entry
2146 * must contain some data. But if the PIO happened faster
2147 * than the DMA, the data may not be available yet, so let's
2148 * wait until it arrives.
2150 if ((entry
->ring_allsc
& RING_ANY_VALID
) == 0) {
2151 /* Indicate the read is aborted so we don't disable
2152 * the interrupt thinking that the consumer is
2155 port
->ip_flags
|= READ_ABORTED
;
2160 /* Load the bytes/status out of the ring entry */
2161 for (byte_num
= 0; byte_num
< 4 && len
> 0; byte_num
++) {
2162 sc
= &(entry
->ring_sc
[byte_num
]);
2164 /* Check for change in modem state or overrun */
2165 if ((*sc
& IOC4_RXSB_MODEM_VALID
)
2166 && (port
->ip_notify
& N_DDCD
)) {
2167 /* Notify upper layer if DCD dropped */
2169 if ((port
->ip_flags
& DCD_ON
)
2170 && !(*sc
& IOC4_RXSB_DCD
)) {
2172 /* If we have already copied some data,
2173 * return it. We'll pick up the carrier
2174 * drop on the next pass. That way we
2175 * don't throw away the data that has
2176 * already been copied back to
2177 * the caller's buffer.
2183 port
->ip_flags
&= ~DCD_ON
;
2185 /* Turn off this notification so the
2186 * carrier drop protocol won't see it
2187 * again when it does a read.
2189 *sc
&= ~IOC4_RXSB_MODEM_VALID
;
2191 /* To keep things consistent, we need
2192 * to update the consumer pointer so
2193 * the next reader won't come in and
2194 * try to read the same ring entries
2195 * again. This must be done here before
2199 if ((entry
->ring_allsc
& RING_ANY_VALID
)
2201 cons_ptr
+= (int)sizeof
2202 (struct ring_entry
);
2203 cons_ptr
&= PROD_CONS_MASK
;
2206 &port
->ip_serial_regs
->srcir
);
2207 port
->ip_rx_cons
= cons_ptr
;
2209 /* Notify upper layer of carrier drop */
2210 if ((port
->ip_notify
& N_DDCD
)
2212 the_port
->icount
.dcd
= 0;
2213 wake_up_interruptible
2218 /* If we had any data to return, we
2219 * would have returned it above.
2224 if (*sc
& IOC4_RXSB_MODEM_VALID
) {
2225 /* Notify that an input overrun occurred */
2226 if ((*sc
& IOC4_RXSB_OVERRUN
)
2227 && (port
->ip_notify
& N_OVERRUN_ERROR
)) {
2228 ioc4_cb_post_ncs(the_port
, NCS_OVERRUN
);
2230 /* Don't look at this byte again */
2231 *sc
&= ~IOC4_RXSB_MODEM_VALID
;
2234 /* Check for valid data or RX errors */
2235 if ((*sc
& IOC4_RXSB_DATA_VALID
) &&
2236 ((*sc
& (IOC4_RXSB_PAR_ERR
2237 | IOC4_RXSB_FRAME_ERR
2239 && (port
->ip_notify
& (N_PARITY_ERROR
2242 /* There is an error condition on the next byte.
2243 * If we have already transferred some bytes,
2244 * we'll stop here. Otherwise if this is the
2245 * first byte to be read, we'll just transfer
2246 * it alone after notifying the
2247 * upper layer of its status.
2253 if ((*sc
& IOC4_RXSB_PAR_ERR
) &&
2254 (port
->ip_notify
& N_PARITY_ERROR
)) {
2255 ioc4_cb_post_ncs(the_port
,
2258 if ((*sc
& IOC4_RXSB_FRAME_ERR
) &&
2259 (port
->ip_notify
& N_FRAMING_ERROR
)){
2260 ioc4_cb_post_ncs(the_port
,
2263 if ((*sc
& IOC4_RXSB_BREAK
)
2264 && (port
->ip_notify
& N_BREAK
)) {
2272 if (*sc
& IOC4_RXSB_DATA_VALID
) {
2273 *sc
&= ~IOC4_RXSB_DATA_VALID
;
2274 *buf
= entry
->ring_data
[byte_num
];
2281 /* If we used up this entry entirely, go on to the next one,
2282 * otherwise we must have run out of buffer space, so
2283 * leave the consumer pointer here for the next read in case
2284 * there are still unread bytes in this entry.
2286 if ((entry
->ring_allsc
& RING_ANY_VALID
) == 0) {
2287 cons_ptr
+= (int)sizeof(struct ring_entry
);
2288 cons_ptr
&= PROD_CONS_MASK
;
2292 /* Update consumer pointer and re-arm rx timer interrupt */
2293 writel(cons_ptr
, &port
->ip_serial_regs
->srcir
);
2294 port
->ip_rx_cons
= cons_ptr
;
2296 /* If we have now dipped below the rx high water mark and we have
2297 * rx_high interrupt turned off, we can now turn it back on again.
2299 if ((port
->ip_flags
& INPUT_HIGH
) && (((prod_ptr
- cons_ptr
)
2300 & PROD_CONS_MASK
) < ((port
->ip_sscr
&
2301 IOC4_SSCR_RX_THRESHOLD
)
2302 << IOC4_PROD_CONS_PTR_OFF
))) {
2303 port
->ip_flags
&= ~INPUT_HIGH
;
2304 enable_intrs(port
, hooks
->intr_rx_high
);
2309 * receive_chars - upper level read. Called with ip_lock.
2310 * @the_port: port to read from
2312 static void receive_chars(struct uart_port
*the_port
)
2314 struct tty_struct
*tty
;
2315 unsigned char ch
[IOC4_MAX_CHARS
];
2316 int read_count
, request_count
;
2317 struct uart_icount
*icount
;
2318 struct uart_info
*info
= the_port
->info
;
2320 /* Make sure all the pointers are "good" ones */
2328 request_count
= TTY_FLIPBUF_SIZE
- tty
->flip
.count
- 1;
2330 if (request_count
> 0) {
2331 if (request_count
> IOC4_MAX_CHARS
- 2)
2332 request_count
= IOC4_MAX_CHARS
- 2;
2333 icount
= &the_port
->icount
;
2334 read_count
= do_read(the_port
, ch
, request_count
);
2335 if (read_count
> 0) {
2336 memcpy(tty
->flip
.char_buf_ptr
, ch
, read_count
);
2337 memset(tty
->flip
.flag_buf_ptr
, TTY_NORMAL
, read_count
);
2338 tty
->flip
.char_buf_ptr
+= read_count
;
2339 tty
->flip
.flag_buf_ptr
+= read_count
;
2340 tty
->flip
.count
+= read_count
;
2341 icount
->rx
+= read_count
;
2344 tty_flip_buffer_push(tty
);
2348 * ic4_type - What type of console are we?
2349 * @port: Port to operate with (we ignore since we only have one port)
2352 static const char *ic4_type(struct uart_port
*the_port
)
2354 return "SGI IOC4 Serial";
2358 * ic4_tx_empty - Is the transmitter empty? We pretend we're always empty
2359 * @port: Port to operate on (we ignore since we always return 1)
2362 static unsigned int ic4_tx_empty(struct uart_port
*the_port
)
2368 * ic4_stop_tx - stop the transmitter
2369 * @port: Port to operate on
2370 * @tty_stop: Set to 1 if called via uart_stop
2373 static void ic4_stop_tx(struct uart_port
*the_port
, unsigned int tty_stop
)
2378 * null_void_function -
2379 * @port: Port to operate on
2382 static void null_void_function(struct uart_port
*the_port
)
2387 * ic4_shutdown - shut down the port - free irq and disable
2388 * @port: Port to shut down
2391 static void ic4_shutdown(struct uart_port
*the_port
)
2393 unsigned long port_flags
;
2394 struct ioc4_port
*port
;
2395 struct uart_info
*info
;
2397 port
= get_ioc4_port(the_port
);
2401 info
= the_port
->info
;
2403 if (!(info
->flags
& UIF_INITIALIZED
))
2406 wake_up_interruptible(&info
->delta_msr_wait
);
2409 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2411 spin_lock_irqsave(&port
->ip_lock
, port_flags
);
2412 set_notification(port
, N_ALL
, 0);
2413 info
->flags
&= ~UIF_INITIALIZED
;
2414 spin_unlock_irqrestore(&port
->ip_lock
, port_flags
);
2418 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2419 * @port: Port to operate on
2420 * @mctrl: Lines to set/unset
2423 static void ic4_set_mctrl(struct uart_port
*the_port
, unsigned int mctrl
)
2425 unsigned char mcr
= 0;
2427 if (mctrl
& TIOCM_RTS
)
2428 mcr
|= UART_MCR_RTS
;
2429 if (mctrl
& TIOCM_DTR
)
2430 mcr
|= UART_MCR_DTR
;
2431 if (mctrl
& TIOCM_OUT1
)
2432 mcr
|= UART_MCR_OUT1
;
2433 if (mctrl
& TIOCM_OUT2
)
2434 mcr
|= UART_MCR_OUT2
;
2435 if (mctrl
& TIOCM_LOOP
)
2436 mcr
|= UART_MCR_LOOP
;
2438 set_mcr(the_port
, 1, mcr
, IOC4_SHADOW_DTR
);
2442 * ic4_get_mctrl - get control line info
2443 * @port: port to operate on
2446 static unsigned int ic4_get_mctrl(struct uart_port
*the_port
)
2448 struct ioc4_port
*port
= get_ioc4_port(the_port
);
2450 unsigned int ret
= 0;
2455 shadow
= readl(&port
->ip_serial_regs
->shadow
);
2456 if (shadow
& IOC4_SHADOW_DCD
)
2458 if (shadow
& IOC4_SHADOW_DR
)
2460 if (shadow
& IOC4_SHADOW_CTS
)
2466 * ic4_start_tx - Start transmitter, flush any output
2467 * @port: Port to operate on
2468 * @tty_stop: Set to 1 if called via uart_start
2471 static void ic4_start_tx(struct uart_port
*the_port
, unsigned int tty_stop
)
2473 struct ioc4_port
*port
= get_ioc4_port(the_port
);
2474 unsigned long flags
;
2477 spin_lock_irqsave(&port
->ip_lock
, flags
);
2478 transmit_chars(the_port
);
2479 spin_unlock_irqrestore(&port
->ip_lock
, flags
);
2484 * ic4_break_ctl - handle breaks
2485 * @port: Port to operate on
2486 * @break_state: Break state
2489 static void ic4_break_ctl(struct uart_port
*the_port
, int break_state
)
2494 * ic4_startup - Start up the serial port - always return 0 (We're always on)
2495 * @port: Port to operate on
2498 static int ic4_startup(struct uart_port
*the_port
)
2501 struct ioc4_port
*port
;
2502 struct ioc4_control
*control
;
2503 struct uart_info
*info
;
2504 unsigned long port_flags
;
2509 port
= get_ioc4_port(the_port
);
2513 info
= the_port
->info
;
2515 control
= port
->ip_control
;
2520 /* Start up the serial port */
2521 spin_lock_irqsave(&port
->ip_lock
, port_flags
);
2522 retval
= ic4_startup_local(the_port
);
2523 spin_unlock_irqrestore(&port
->ip_lock
, port_flags
);
2528 * ic4_set_termios - set termios stuff
2529 * @port: port to operate on
2530 * @termios: New settings
2535 ic4_set_termios(struct uart_port
*the_port
,
2536 struct termios
*termios
, struct termios
*old_termios
)
2538 struct ioc4_port
*port
= get_ioc4_port(the_port
);
2539 unsigned long port_flags
;
2541 spin_lock_irqsave(&port
->ip_lock
, port_flags
);
2542 ioc4_change_speed(the_port
, termios
, old_termios
);
2543 spin_unlock_irqrestore(&port
->ip_lock
, port_flags
);
2547 * ic4_request_port - allocate resources for port - no op....
2548 * @port: port to operate on
2551 static int ic4_request_port(struct uart_port
*port
)
2556 /* Associate the uart functions above - given to serial core */
2558 static struct uart_ops ioc4_ops
= {
2559 .tx_empty
= ic4_tx_empty
,
2560 .set_mctrl
= ic4_set_mctrl
,
2561 .get_mctrl
= ic4_get_mctrl
,
2562 .stop_tx
= ic4_stop_tx
,
2563 .start_tx
= ic4_start_tx
,
2564 .stop_rx
= null_void_function
,
2565 .enable_ms
= null_void_function
,
2566 .break_ctl
= ic4_break_ctl
,
2567 .startup
= ic4_startup
,
2568 .shutdown
= ic4_shutdown
,
2569 .set_termios
= ic4_set_termios
,
2571 .release_port
= null_void_function
,
2572 .request_port
= ic4_request_port
,
2576 * Boot-time initialization code
2579 static struct uart_driver ioc4_uart
= {
2580 .owner
= THIS_MODULE
,
2581 .driver_name
= "ioc4_serial",
2582 .dev_name
= DEVICE_NAME
,
2583 .major
= DEVICE_MAJOR
,
2584 .minor
= DEVICE_MINOR
,
2585 .nr
= IOC4_NUM_CARDS
* IOC4_NUM_SERIAL_PORTS
,
2589 * ioc4_serial_core_attach - register with serial core
2590 * This is done during pci probing
2591 * @pdev: handle for this card
2594 ioc4_serial_core_attach(struct pci_dev
*pdev
)
2596 struct ioc4_port
*port
;
2597 struct uart_port
*the_port
;
2598 struct ioc4_driver_data
*idd
= pci_get_drvdata(pdev
);
2599 struct ioc4_control
*control
= idd
->idd_serial_data
;
2602 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2603 __FUNCTION__
, pdev
, (void *)control
));
2608 /* once around for each port on this card */
2609 for (ii
= 0; ii
< IOC4_NUM_SERIAL_PORTS
; ii
++) {
2610 the_port
= &control
->ic_port
[ii
].icp_uart_port
;
2611 port
= control
->ic_port
[ii
].icp_port
;
2612 port
->ip_port
= the_port
;
2614 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p\n",
2615 __FUNCTION__
, (void *)the_port
,
2618 spin_lock_init(&the_port
->lock
);
2619 /* membase, iobase and mapbase just need to be non-0 */
2620 the_port
->membase
= (unsigned char __iomem
*)1;
2621 the_port
->line
= the_port
->iobase
= ii
;
2622 the_port
->mapbase
= 1;
2623 the_port
->type
= PORT_16550A
;
2624 the_port
->fifosize
= IOC4_MAX_CHARS
;
2625 the_port
->ops
= &ioc4_ops
;
2626 the_port
->irq
= control
->ic_irq
;
2627 the_port
->dev
= &pdev
->dev
;
2628 if (uart_add_one_port(&ioc4_uart
, the_port
) < 0) {
2630 "%s: unable to add port %d\n",
2631 __FUNCTION__
, the_port
->line
);
2634 ("IOC4 serial driver port %d irq = %d\n",
2635 the_port
->line
, the_port
->irq
));
2637 /* all ports are rs232 for now */
2638 ioc4_set_proto(port
, PROTO_RS232
);
2644 * ioc4_serial_attach_one - register attach function
2645 * called per card found from IOC4 master module.
2646 * @idd: Master module data for this IOC4
2649 ioc4_serial_attach_one(struct ioc4_driver_data
*idd
)
2651 unsigned long tmp_addr1
;
2652 struct ioc4_serial __iomem
*serial
;
2653 struct ioc4_soft
*soft
;
2654 struct ioc4_control
*control
;
2658 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__
, idd
->idd_pdev
, idd
->idd_pci_id
));
2660 /* request serial registers */
2661 tmp_addr1
= idd
->idd_bar0
+ IOC4_SERIAL_OFFSET
;
2663 if (!request_region(tmp_addr1
, sizeof(struct ioc4_serial
),
2666 "ioc4 (%p): unable to get request region for "
2667 "uart space\n", (void *)idd
->idd_pdev
);
2671 serial
= ioremap(tmp_addr1
, sizeof(struct ioc4_serial
));
2674 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2675 (void *)idd
->idd_pdev
);
2679 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2680 __FUNCTION__
, (void *)idd
->idd_misc_regs
, (void *)serial
));
2682 /* Get memory for the new card */
2683 control
= kmalloc(sizeof(struct ioc4_control
) * IOC4_NUM_SERIAL_PORTS
,
2687 printk(KERN_WARNING
"ioc4_attach_one"
2688 ": unable to get memory for the IOC4\n");
2692 memset(control
, 0, sizeof(struct ioc4_control
));
2693 idd
->idd_serial_data
= control
;
2695 /* Allocate the soft structure */
2696 soft
= kmalloc(sizeof(struct ioc4_soft
), GFP_KERNEL
);
2699 "ioc4 (%p): unable to get memory for the soft struct\n",
2700 (void *)idd
->idd_pdev
);
2704 memset(soft
, 0, sizeof(struct ioc4_soft
));
2706 spin_lock_init(&soft
->is_ir_lock
);
2707 soft
->is_ioc4_misc_addr
= idd
->idd_misc_regs
;
2708 soft
->is_ioc4_serial_addr
= serial
;
2711 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT
,
2712 &idd
->idd_misc_regs
->sio_cr
.raw
);
2714 /* Enable serial port mode select generic PIO pins as outputs */
2715 writel(IOC4_GPCR_UART0_MODESEL
| IOC4_GPCR_UART1_MODESEL
2716 | IOC4_GPCR_UART2_MODESEL
| IOC4_GPCR_UART3_MODESEL
,
2717 &idd
->idd_misc_regs
->gpcr_s
.raw
);
2719 /* Clear and disable all serial interrupts */
2720 write_ireg(soft
, ~0, IOC4_W_IEC
, IOC4_SIO_INTR_TYPE
);
2721 writel(~0, &idd
->idd_misc_regs
->sio_ir
.raw
);
2722 write_ireg(soft
, IOC4_OTHER_IR_SER_MEMERR
, IOC4_W_IEC
,
2723 IOC4_OTHER_INTR_TYPE
);
2724 writel(IOC4_OTHER_IR_SER_MEMERR
, &idd
->idd_misc_regs
->other_ir
.raw
);
2725 control
->ic_soft
= soft
;
2727 /* Hook up interrupt handler */
2728 if (!request_irq(idd
->idd_pdev
->irq
, ioc4_intr
, SA_SHIRQ
,
2729 "sgi-ioc4serial", (void *)soft
)) {
2730 control
->ic_irq
= idd
->idd_pdev
->irq
;
2733 "%s : request_irq fails for IRQ 0x%x\n ",
2734 __FUNCTION__
, idd
->idd_pdev
->irq
);
2736 if ((ret
= ioc4_attach_local(idd
->idd_pdev
, control
, soft
,
2737 soft
->is_ioc4_misc_addr
,
2738 soft
->is_ioc4_serial_addr
)))
2741 /* register port with the serial core */
2743 if ((ret
= ioc4_serial_core_attach(idd
->idd_pdev
)))
2748 /* error exits that give back resources */
2754 release_region(tmp_addr1
, sizeof(struct ioc4_serial
));
2762 * ioc4_serial_remove_one - detach function
2764 * @idd: IOC4 master module data for this IOC4
2767 int ioc4_serial_remove_one(struct ioc4_driver_data
*idd
)
2770 struct ioc4_control
*control
;
2771 struct uart_port
*the_port
;
2772 struct ioc4_port
*port
;
2773 struct ioc4_soft
*soft
;
2775 control
= idd
->idd_serial_data
;
2777 for (ii
= 0; ii
< IOC4_NUM_SERIAL_PORTS
; ii
++) {
2778 the_port
= &control
->ic_port
[ii
].icp_uart_port
;
2780 uart_remove_one_port(&ioc4_uart
, the_port
);
2782 port
= control
->ic_port
[ii
].icp_port
;
2783 if (!(ii
& 1) && port
) {
2784 pci_free_consistent(port
->ip_pdev
,
2785 TOTAL_RING_BUF_SIZE
,
2786 (void *)port
->ip_cpu_ringbuf
,
2787 port
->ip_dma_ringbuf
);
2791 soft
= control
->ic_soft
;
2793 free_irq(control
->ic_irq
, (void *)soft
);
2794 if (soft
->is_ioc4_serial_addr
) {
2795 release_region((unsigned long)
2796 soft
->is_ioc4_serial_addr
,
2797 sizeof(struct ioc4_serial
));
2802 idd
->idd_serial_data
= NULL
;
2807 static struct ioc4_submodule ioc4_serial_submodule
= {
2808 .is_name
= "IOC4_serial",
2809 .is_owner
= THIS_MODULE
,
2810 .is_probe
= ioc4_serial_attach_one
,
2811 .is_remove
= ioc4_serial_remove_one
,
2815 * ioc4_serial_init - module init
2817 int ioc4_serial_init(void)
2821 /* register with serial core */
2822 if ((ret
= uart_register_driver(&ioc4_uart
)) < 0) {
2824 "%s: Couldn't register IOC4 serial driver\n",
2829 /* register with IOC4 main module */
2830 return ioc4_register_submodule(&ioc4_serial_submodule
);
2833 static void __devexit
ioc4_serial_exit(void)
2835 ioc4_unregister_submodule(&ioc4_serial_submodule
);
2836 uart_unregister_driver(&ioc4_uart
);
2839 module_init(ioc4_serial_init
);
2840 module_exit(ioc4_serial_exit
);
2842 MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2843 MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2844 MODULE_LICENSE("GPL");