include/asm-powerpc/ppc_asm.h

   1 /*
   2  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3  */
   4 #ifndef _ASM_POWERPC_PPC_ASM_H
   5 #define _ASM_POWERPC_PPC_ASM_H
   6
   7 #include <linux/stringify.h>
   8 #include <linux/config.h>
   9 #include <asm/asm-compat.h>
  10
  11 #ifndef __ASSEMBLY__
  12 #error __FILE__ should only be used in assembler files
  13 #else
  14
  15 #define SZL                     (BITS_PER_LONG/8)
  16
  17 /*
  18  * Macros for storing registers into and loading registers from
  19  * exception frames.
  20  */
  21 #ifdef __powerpc64__
  22 #define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  23 #define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  24 #define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  25 #define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  26 #else
  27 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  28 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  29 #define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
  30                                 SAVE_10GPRS(22, base)
  31 #define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
  32                                 REST_10GPRS(22, base)
  33 #endif
  34
  35
  36 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  37 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  38 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  39 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  40 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  41 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  42 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  43 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  44
  45 #define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
  46 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
  47 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
  48 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
  49 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
  50 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
  51 #define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
  52 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
  53 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
  54 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
  55 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
  56 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
  57
  58 #define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
  59 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
  60 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
  61 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
  62 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
  63 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
  64 #define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
  65 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
  66 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
  67 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
  68 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
  69 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
  70
  71 #define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
  72 #define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
  73 #define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
  74 #define SAVE_8EVRS(n,s,base)    SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
  75 #define SAVE_16EVRS(n,s,base)   SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
  76 #define SAVE_32EVRS(n,s,base)   SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
  77 #define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
  78 #define REST_2EVRS(n,s,base)    REST_EVR(n,s,base); REST_EVR(n+1,s,base)
  79 #define REST_4EVRS(n,s,base)    REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
  80 #define REST_8EVRS(n,s,base)    REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
  81 #define REST_16EVRS(n,s,base)   REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
  82 #define REST_32EVRS(n,s,base)   REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
  83
  84 /* Macros to adjust thread priority for hardware multithreading */
  85 #define HMT_VERY_LOW    or      31,31,31        # very low priority
  86 #define HMT_LOW         or      1,1,1
  87 #define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
  88 #define HMT_MEDIUM      or      2,2,2
  89 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
  90 #define HMT_HIGH        or      3,3,3
  91
  92 /* handle instructions that older assemblers may not know */
  93 #define RFCI            .long 0x4c000066        /* rfci instruction */
  94 #define RFDI            .long 0x4c00004e        /* rfdi instruction */
  95 #define RFMCI           .long 0x4c00004c        /* rfmci instruction */
  96
  97 #ifdef CONFIG_PPC64
  98
  99 #define XGLUE(a,b) a##b
 100 #define GLUE(a,b) XGLUE(a,b)
 101
 102 #define _GLOBAL(name) \
 103         .section ".text"; \
 104         .align 2 ; \
 105         .globl name; \
 106         .globl GLUE(.,name); \
 107         .section ".opd","aw"; \
 108 name: \
 109         .quad GLUE(.,name); \
 110         .quad .TOC.@tocbase; \
 111         .quad 0; \
 112         .previous; \
 113         .type GLUE(.,name),@function; \
 114 GLUE(.,name):
 115
 116 #define _KPROBE(name) \
 117         .section ".kprobes.text","a"; \
 118         .align 2 ; \
 119         .globl name; \
 120         .globl GLUE(.,name); \
 121         .section ".opd","aw"; \
 122 name: \
 123         .quad GLUE(.,name); \
 124         .quad .TOC.@tocbase; \
 125         .quad 0; \
 126         .previous; \
 127         .type GLUE(.,name),@function; \
 128 GLUE(.,name):
 129
 130 #define _STATIC(name) \
 131         .section ".text"; \
 132         .align 2 ; \
 133         .section ".opd","aw"; \
 134 name: \
 135         .quad GLUE(.,name); \
 136         .quad .TOC.@tocbase; \
 137         .quad 0; \
 138         .previous; \
 139         .type GLUE(.,name),@function; \
 140 GLUE(.,name):
 141
 142 #else /* 32-bit */
 143
 144 #define _GLOBAL(n)      \
 145         .text;          \
 146         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 147         .globl n;       \
 148 n:
 149
 150 #define _KPROBE(n)      \
 151         .section ".kprobes.text","a";   \
 152         .globl  n;      \
 153 n:
 154
 155 #endif
 156
 157 /*
 158  * LOADADDR( rn, name )
 159  *   loads the address of 'name' into 'rn'
 160  *
 161  * LOADBASE( rn, name )
 162  *   loads the address (possibly without the low 16 bits) of 'name' into 'rn'
 163  *   suitable for base+disp addressing
 164  */
 165 #ifdef __powerpc64__
 166 #define LOADADDR(rn,name) \
 167         lis     rn,name##@highest;      \
 168         ori     rn,rn,name##@higher;    \
 169         rldicr  rn,rn,32,31;            \
 170         oris    rn,rn,name##@h;         \
 171         ori     rn,rn,name##@l
 172
 173 #define LOADBASE(rn,name)               \
 174         ld      rn,name@got(r2)
 175
 176 #define OFF(name)       0
 177
 178 #define SET_REG_TO_CONST(reg, value)                    \
 179         lis     reg,(((value)>>48)&0xFFFF);             \
 180         ori     reg,reg,(((value)>>32)&0xFFFF);         \
 181         rldicr  reg,reg,32,31;                          \
 182         oris    reg,reg,(((value)>>16)&0xFFFF);         \
 183         ori     reg,reg,((value)&0xFFFF);
 184
 185 #define SET_REG_TO_LABEL(reg, label)                    \
 186         lis     reg,(label)@highest;                    \
 187         ori     reg,reg,(label)@higher;                 \
 188         rldicr  reg,reg,32,31;                          \
 189         oris    reg,reg,(label)@h;                      \
 190         ori     reg,reg,(label)@l;
 191
 192 /* offsets for stack frame layout */
 193 #define LRSAVE  16
 194
 195 #else /* 32-bit */
 196 #define LOADADDR(rn,name) \
 197         lis     rn,name@ha;     \
 198         addi    rn,rn,name@l
 199
 200 #define LOADBASE(rn,name)       \
 201         lis     rn,name@ha
 202
 203 #define OFF(name)       name@l
 204
 205 /* offsets for stack frame layout */
 206 #define LRSAVE  4
 207
 208 #endif
 209
 210 /* various errata or part fixups */
 211 #ifdef CONFIG_PPC601_SYNC_FIX
 212 #define SYNC                            \
 213 BEGIN_FTR_SECTION                       \
 214         sync;                           \
 215         isync;                          \
 216 END_FTR_SECTION_IFSET(CPU_FTR_601)
 217 #define SYNC_601                        \
 218 BEGIN_FTR_SECTION                       \
 219         sync;                           \
 220 END_FTR_SECTION_IFSET(CPU_FTR_601)
 221 #define ISYNC_601                       \
 222 BEGIN_FTR_SECTION                       \
 223         isync;                          \
 224 END_FTR_SECTION_IFSET(CPU_FTR_601)
 225 #else
 226 #define SYNC
 227 #define SYNC_601
 228 #define ISYNC_601
 229 #endif
 230
 231
 232 #ifndef CONFIG_SMP
 233 #define TLBSYNC
 234 #else /* CONFIG_SMP */
 235 /* tlbsync is not implemented on 601 */
 236 #define TLBSYNC                         \
 237 BEGIN_FTR_SECTION                       \
 238         tlbsync;                        \
 239         sync;                           \
 240 END_FTR_SECTION_IFCLR(CPU_FTR_601)
 241 #endif
 242
 243
 244 /*
 245  * This instruction is not implemented on the PPC 603 or 601; however, on
 246  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 247  * All of these instructions exist in the 8xx, they have magical powers,
 248  * and they must be used.
 249  */
 250
 251 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
 252 #define tlbia                                   \
 253         li      r4,1024;                        \
 254         mtctr   r4;                             \
 255         lis     r4,KERNELBASE@h;                \
 256 0:      tlbie   r4;                             \
 257         addi    r4,r4,0x1000;                   \
 258         bdnz    0b
 259 #endif
 260
 261
 262 #ifdef CONFIG_IBM440EP_ERR42
 263 #define PPC440EP_ERR42 isync
 264 #else
 265 #define PPC440EP_ERR42
 266 #endif
 267
 268
 269 #if defined(CONFIG_BOOKE)
 270 #define toreal(rd)
 271 #define fromreal(rd)
 272
 273 #define tophys(rd,rs)                           \
 274         addis   rd,rs,0
 275
 276 #define tovirt(rd,rs)                           \
 277         addis   rd,rs,0
 278
 279 #elif defined(CONFIG_PPC64)
 280 #define toreal(rd)              /* we can access c000... in real mode */
 281 #define fromreal(rd)
 282
 283 #define tophys(rd,rs)                           \
 284         clrldi  rd,rs,2
 285
 286 #define tovirt(rd,rs)                           \
 287         rotldi  rd,rs,16;                       \
 288         ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
 289         rotldi  rd,rd,48
 290 #else
 291 /*
 292  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 293  * physical base address of RAM at compile time.
 294  */
 295 #define toreal(rd)      tophys(rd,rd)
 296 #define fromreal(rd)    tovirt(rd,rd)
 297
 298 #define tophys(rd,rs)                           \
 299 0:      addis   rd,rs,-KERNELBASE@h;            \
 300         .section ".vtop_fixup","aw";            \
 301         .align  1;                              \
 302         .long   0b;                             \
 303         .previous
 304
 305 #define tovirt(rd,rs)                           \
 306 0:      addis   rd,rs,KERNELBASE@h;             \
 307         .section ".ptov_fixup","aw";            \
 308         .align  1;                              \
 309         .long   0b;                             \
 310         .previous
 311 #endif
 312
 313 #ifdef CONFIG_PPC64
 314 #define RFI             rfid
 315 #define MTMSRD(r)       mtmsrd  r
 316
 317 #else
 318 #define FIX_SRR1(ra, rb)
 319 #ifndef CONFIG_40x
 320 #define RFI             rfi
 321 #else
 322 #define RFI             rfi; b .        /* Prevent prefetch past rfi */
 323 #endif
 324 #define MTMSRD(r)       mtmsr   r
 325 #define CLR_TOP32(r)
 326 #endif
 327
 328 /* The boring bits... */
 329
 330 /* Condition Register Bit Fields */
 331
 332 #define cr0     0
 333 #define cr1     1
 334 #define cr2     2
 335 #define cr3     3
 336 #define cr4     4
 337 #define cr5     5
 338 #define cr6     6
 339 #define cr7     7
 340
 341
 342 /* General Purpose Registers (GPRs) */
 343
 344 #define r0      0
 345 #define r1      1
 346 #define r2      2
 347 #define r3      3
 348 #define r4      4
 349 #define r5      5
 350 #define r6      6
 351 #define r7      7
 352 #define r8      8
 353 #define r9      9
 354 #define r10     10
 355 #define r11     11
 356 #define r12     12
 357 #define r13     13
 358 #define r14     14
 359 #define r15     15
 360 #define r16     16
 361 #define r17     17
 362 #define r18     18
 363 #define r19     19
 364 #define r20     20
 365 #define r21     21
 366 #define r22     22
 367 #define r23     23
 368 #define r24     24
 369 #define r25     25
 370 #define r26     26
 371 #define r27     27
 372 #define r28     28
 373 #define r29     29
 374 #define r30     30
 375 #define r31     31
 376
 377
 378 /* Floating Point Registers (FPRs) */
 379
 380 #define fr0     0
 381 #define fr1     1
 382 #define fr2     2
 383 #define fr3     3
 384 #define fr4     4
 385 #define fr5     5
 386 #define fr6     6
 387 #define fr7     7
 388 #define fr8     8
 389 #define fr9     9
 390 #define fr10    10
 391 #define fr11    11
 392 #define fr12    12
 393 #define fr13    13
 394 #define fr14    14
 395 #define fr15    15
 396 #define fr16    16
 397 #define fr17    17
 398 #define fr18    18
 399 #define fr19    19
 400 #define fr20    20
 401 #define fr21    21
 402 #define fr22    22
 403 #define fr23    23
 404 #define fr24    24
 405 #define fr25    25
 406 #define fr26    26
 407 #define fr27    27
 408 #define fr28    28
 409 #define fr29    29
 410 #define fr30    30
 411 #define fr31    31
 412
 413 /* AltiVec Registers (VPRs) */
 414
 415 #define vr0     0
 416 #define vr1     1
 417 #define vr2     2
 418 #define vr3     3
 419 #define vr4     4
 420 #define vr5     5
 421 #define vr6     6
 422 #define vr7     7
 423 #define vr8     8
 424 #define vr9     9
 425 #define vr10    10
 426 #define vr11    11
 427 #define vr12    12
 428 #define vr13    13
 429 #define vr14    14
 430 #define vr15    15
 431 #define vr16    16
 432 #define vr17    17
 433 #define vr18    18
 434 #define vr19    19
 435 #define vr20    20
 436 #define vr21    21
 437 #define vr22    22
 438 #define vr23    23
 439 #define vr24    24
 440 #define vr25    25
 441 #define vr26    26
 442 #define vr27    27
 443 #define vr28    28
 444 #define vr29    29
 445 #define vr30    30
 446 #define vr31    31
 447
 448 /* SPE Registers (EVPRs) */
 449
 450 #define evr0    0
 451 #define evr1    1
 452 #define evr2    2
 453 #define evr3    3
 454 #define evr4    4
 455 #define evr5    5
 456 #define evr6    6
 457 #define evr7    7
 458 #define evr8    8
 459 #define evr9    9
 460 #define evr10   10
 461 #define evr11   11
 462 #define evr12   12
 463 #define evr13   13
 464 #define evr14   14
 465 #define evr15   15
 466 #define evr16   16
 467 #define evr17   17
 468 #define evr18   18
 469 #define evr19   19
 470 #define evr20   20
 471 #define evr21   21
 472 #define evr22   22
 473 #define evr23   23
 474 #define evr24   24
 475 #define evr25   25
 476 #define evr26   26
 477 #define evr27   27
 478 #define evr28   28
 479 #define evr29   29
 480 #define evr30   30
 481 #define evr31   31
 482
 483 /* some stab codes */
 484 #define N_FUN   36
 485 #define N_RSYM  64
 486 #define N_SLINE 68
 487 #define N_SO    100
 488
 489 #endif /*  __ASSEMBLY__ */
 490
 491 #endif /* _ASM_POWERPC_PPC_ASM_H */