drivers/char/rocket.c

   1 /*
   2  * RocketPort device driver for Linux
   3  *
   4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
   5  *
   6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Kernel Synchronization:
  25  *
  26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
  27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
  28  * are not used.
  29  *
  30  * Critical data:
  31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of
  32  *    serial port state information and the xmit_buf circular buffer.  Protected by
  33  *    a per port spinlock.
  34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  35  *    is data to be transmitted.  Protected by atomic bit operations.
  36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
  37  *
  38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  39  * simultaneous access to the same port by more than one process.
  40  */
  41
  42 /****** Defines ******/
  43 #ifdef PCI_NUM_RESOURCES
  44 #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
  45 #else
  46 #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
  47 #endif
  48
  49 #define ROCKET_PARANOIA_CHECK
  50 #define ROCKET_DISABLE_SIMUSAGE
  51
  52 #undef ROCKET_SOFT_FLOW
  53 #undef ROCKET_DEBUG_OPEN
  54 #undef ROCKET_DEBUG_INTR
  55 #undef ROCKET_DEBUG_WRITE
  56 #undef ROCKET_DEBUG_FLOW
  57 #undef ROCKET_DEBUG_THROTTLE
  58 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  59 #undef ROCKET_DEBUG_RECEIVE
  60 #undef ROCKET_DEBUG_HANGUP
  61 #undef REV_PCI_ORDER
  62 #undef ROCKET_DEBUG_IO
  63
  64 #define POLL_PERIOD HZ/100      /*  Polling period .01 seconds (10ms) */
  65
  66 /****** Kernel includes ******/
  67
  68 #ifdef MODVERSIONS
  69 #include <config/modversions.h>
  70 #endif
  71
  72 #include <linux/module.h>
  73 #include <linux/errno.h>
  74 #include <linux/major.h>
  75 #include <linux/kernel.h>
  76 #include <linux/signal.h>
  77 #include <linux/slab.h>
  78 #include <linux/mm.h>
  79 #include <linux/sched.h>
  80 #include <linux/timer.h>
  81 #include <linux/interrupt.h>
  82 #include <linux/tty.h>
  83 #include <linux/tty_driver.h>
  84 #include <linux/tty_flip.h>
  85 #include <linux/string.h>
  86 #include <linux/fcntl.h>
  87 #include <linux/ptrace.h>
  88 #include <linux/ioport.h>
  89 #include <linux/delay.h>
  90 #include <linux/wait.h>
  91 #include <linux/pci.h>
  92 #include <asm/uaccess.h>
  93 #include <asm/atomic.h>
  94 #include <linux/bitops.h>
  95 #include <linux/spinlock.h>
  96 #include <asm/semaphore.h>
  97 #include <linux/init.h>
  98
  99 /****** RocketPort includes ******/
 100
 101 #include "rocket_int.h"
 102 #include "rocket.h"
 103
 104 #define ROCKET_VERSION "2.09"
 105 #define ROCKET_DATE "12-June-2003"
 106
 107 /****** RocketPort Local Variables ******/
 108
 109 static struct tty_driver *rocket_driver;
 110
 111 static struct rocket_version driver_version = {
 112         ROCKET_VERSION, ROCKET_DATE
 113 };
 114
 115 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
 116 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
 117                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
 118 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
 119 static struct timer_list rocket_timer;
 120
 121 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
 122 static unsigned long board2;
 123 static unsigned long board3;
 124 static unsigned long board4;
 125 static unsigned long controller;
 126 static int support_low_speed;
 127 static unsigned long modem1;
 128 static unsigned long modem2;
 129 static unsigned long modem3;
 130 static unsigned long modem4;
 131 static unsigned long pc104_1[8];
 132 static unsigned long pc104_2[8];
 133 static unsigned long pc104_3[8];
 134 static unsigned long pc104_4[8];
 135 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
 136
 137 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
 138 static unsigned long rcktpt_io_addr[NUM_BOARDS];
 139 static int rcktpt_type[NUM_BOARDS];
 140 static int is_PCI[NUM_BOARDS];
 141 static rocketModel_t rocketModel[NUM_BOARDS];
 142 static int max_board;
 143
 144 /*
 145  * The following arrays define the interrupt bits corresponding to each AIOP.
 146  * These bits are different between the ISA and regular PCI boards and the
 147  * Universal PCI boards.
 148  */
 149
 150 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
 151         AIOP_INTR_BIT_0,
 152         AIOP_INTR_BIT_1,
 153         AIOP_INTR_BIT_2,
 154         AIOP_INTR_BIT_3
 155 };
 156
 157 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
 158         UPCI_AIOP_INTR_BIT_0,
 159         UPCI_AIOP_INTR_BIT_1,
 160         UPCI_AIOP_INTR_BIT_2,
 161         UPCI_AIOP_INTR_BIT_3
 162 };
 163
 164 static Byte_t RData[RDATASIZE] = {
 165         0x00, 0x09, 0xf6, 0x82,
 166         0x02, 0x09, 0x86, 0xfb,
 167         0x04, 0x09, 0x00, 0x0a,
 168         0x06, 0x09, 0x01, 0x0a,
 169         0x08, 0x09, 0x8a, 0x13,
 170         0x0a, 0x09, 0xc5, 0x11,
 171         0x0c, 0x09, 0x86, 0x85,
 172         0x0e, 0x09, 0x20, 0x0a,
 173         0x10, 0x09, 0x21, 0x0a,
 174         0x12, 0x09, 0x41, 0xff,
 175         0x14, 0x09, 0x82, 0x00,
 176         0x16, 0x09, 0x82, 0x7b,
 177         0x18, 0x09, 0x8a, 0x7d,
 178         0x1a, 0x09, 0x88, 0x81,
 179         0x1c, 0x09, 0x86, 0x7a,
 180         0x1e, 0x09, 0x84, 0x81,
 181         0x20, 0x09, 0x82, 0x7c,
 182         0x22, 0x09, 0x0a, 0x0a
 183 };
 184
 185 static Byte_t RRegData[RREGDATASIZE] = {
 186         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
 187         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
 188         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
 189         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
 190         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
 191         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
 192         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
 193         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
 194         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
 195         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
 196         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
 197         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
 198         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
 199 };
 200
 201 static CONTROLLER_T sController[CTL_SIZE] = {
 202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 206         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 207          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 208         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 209          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
 210 };
 211
 212 static Byte_t sBitMapClrTbl[8] = {
 213         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
 214 };
 215
 216 static Byte_t sBitMapSetTbl[8] = {
 217         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
 218 };
 219
 220 static int sClockPrescale = 0x14;
 221
 222 /*
 223  *  Line number is the ttySIx number (x), the Minor number.  We
 224  *  assign them sequentially, starting at zero.  The following
 225  *  array keeps track of the line number assigned to a given board/aiop/channel.
 226  */
 227 static unsigned char lineNumbers[MAX_RP_PORTS];
 228 static unsigned long nextLineNumber;
 229
 230 /*****  RocketPort Static Prototypes   *********/
 231 static int __init init_ISA(int i);
 232 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
 233 static void rp_flush_buffer(struct tty_struct *tty);
 234 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
 235 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
 236 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
 237 static void rp_start(struct tty_struct *tty);
 238 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
 239                      int ChanNum);
 240 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
 241 static void sFlushRxFIFO(CHANNEL_T * ChP);
 242 static void sFlushTxFIFO(CHANNEL_T * ChP);
 243 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
 244 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
 245 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
 246 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
 247 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
 248 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
 249                               ByteIO_t * AiopIOList, int AiopIOListSize,
 250                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
 251                               int PeriodicOnly, int altChanRingIndicator,
 252                               int UPCIRingInd);
 253 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
 254                            ByteIO_t * AiopIOList, int AiopIOListSize,
 255                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
 256 static int sReadAiopID(ByteIO_t io);
 257 static int sReadAiopNumChan(WordIO_t io);
 258
 259 MODULE_AUTHOR("Theodore Ts'o");
 260 MODULE_DESCRIPTION("Comtrol RocketPort driver");
 261 module_param(board1, ulong, 0);
 262 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
 263 module_param(board2, ulong, 0);
 264 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
 265 module_param(board3, ulong, 0);
 266 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
 267 module_param(board4, ulong, 0);
 268 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
 269 module_param(controller, ulong, 0);
 270 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
 271 module_param(support_low_speed, bool, 0);
 272 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
 273 module_param(modem1, ulong, 0);
 274 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
 275 module_param(modem2, ulong, 0);
 276 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
 277 module_param(modem3, ulong, 0);
 278 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
 279 module_param(modem4, ulong, 0);
 280 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
 281 module_param_array(pc104_1, ulong, NULL, 0);
 282 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
 283 module_param_array(pc104_2, ulong, NULL, 0);
 284 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
 285 module_param_array(pc104_3, ulong, NULL, 0);
 286 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
 287 module_param_array(pc104_4, ulong, NULL, 0);
 288 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
 289
 290 static int rp_init(void);
 291 static void rp_cleanup_module(void);
 292
 293 module_init(rp_init);
 294 module_exit(rp_cleanup_module);
 295
 296
 297 MODULE_LICENSE("Dual BSD/GPL");
 298
 299 /*************************************************************************/
 300 /*                     Module code starts here                           */
 301
 302 static inline int rocket_paranoia_check(struct r_port *info,
 303                                         const char *routine)
 304 {
 305 #ifdef ROCKET_PARANOIA_CHECK
 306         if (!info)
 307                 return 1;
 308         if (info->magic != RPORT_MAGIC) {
 309                 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
 310                      routine);
 311                 return 1;
 312         }
 313 #endif
 314         return 0;
 315 }
 316
 317
 318 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals
 319  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the
 320  *  tty layer.
 321  */
 322 static void rp_do_receive(struct r_port *info,
 323                           struct tty_struct *tty,
 324                           CHANNEL_t * cp, unsigned int ChanStatus)
 325 {
 326         unsigned int CharNStat;
 327         int ToRecv, wRecv, space = 0, count;
 328         unsigned char *cbuf, *chead;
 329         char *fbuf, *fhead;
 330         struct tty_ldisc *ld;
 331
 332         ld = tty_ldisc_ref(tty);
 333
 334         ToRecv = sGetRxCnt(cp);
 335         space = tty->receive_room;
 336         if (space > 2 * TTY_FLIPBUF_SIZE)
 337                 space = 2 * TTY_FLIPBUF_SIZE;
 338         count = 0;
 339 #ifdef ROCKET_DEBUG_INTR
 340         printk(KERN_INFO "rp_do_receive(%d, %d)...", ToRecv, space);
 341 #endif
 342
 343         /*
 344          * determine how many we can actually read in.  If we can't
 345          * read any in then we have a software overrun condition.
 346          */
 347         if (ToRecv > space)
 348                 ToRecv = space;
 349
 350         ToRecv = tty_prepare_flip_string_flags(tty, &chead, &fhead, ToRecv);
 351         if (ToRecv <= 0)
 352                 goto done;
 353
 354         cbuf = chead;
 355         fbuf = fhead;
 356
 357         /*
 358          * if status indicates there are errored characters in the
 359          * FIFO, then enter status mode (a word in FIFO holds
 360          * character and status).
 361          */
 362         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
 363                 if (!(ChanStatus & STATMODE)) {
 364 #ifdef ROCKET_DEBUG_RECEIVE
 365                         printk(KERN_INFO "Entering STATMODE...");
 366 #endif
 367                         ChanStatus |= STATMODE;
 368                         sEnRxStatusMode(cp);
 369                 }
 370         }
 371
 372         /*
 373          * if we previously entered status mode, then read down the
 374          * FIFO one word at a time, pulling apart the character and
 375          * the status.  Update error counters depending on status
 376          */
 377         if (ChanStatus & STATMODE) {
 378 #ifdef ROCKET_DEBUG_RECEIVE
 379                 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
 380                        info->read_status_mask);
 381 #endif
 382                 while (ToRecv) {
 383                         CharNStat = sInW(sGetTxRxDataIO(cp));
 384 #ifdef ROCKET_DEBUG_RECEIVE
 385                         printk(KERN_INFO "%x...", CharNStat);
 386 #endif
 387                         if (CharNStat & STMBREAKH)
 388                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
 389                         if (CharNStat & info->ignore_status_mask) {
 390                                 ToRecv--;
 391                                 continue;
 392                         }
 393                         CharNStat &= info->read_status_mask;
 394                         if (CharNStat & STMBREAKH)
 395                                 *fbuf++ = TTY_BREAK;
 396                         else if (CharNStat & STMPARITYH)
 397                                 *fbuf++ = TTY_PARITY;
 398                         else if (CharNStat & STMFRAMEH)
 399                                 *fbuf++ = TTY_FRAME;
 400                         else if (CharNStat & STMRCVROVRH)
 401                                 *fbuf++ = TTY_OVERRUN;
 402                         else
 403                                 *fbuf++ = TTY_NORMAL;
 404                         *cbuf++ = CharNStat & 0xff;
 405                         count++;
 406                         ToRecv--;
 407                 }
 408
 409                 /*
 410                  * after we've emptied the FIFO in status mode, turn
 411                  * status mode back off
 412                  */
 413                 if (sGetRxCnt(cp) == 0) {
 414 #ifdef ROCKET_DEBUG_RECEIVE
 415                         printk(KERN_INFO "Status mode off.\n");
 416 #endif
 417                         sDisRxStatusMode(cp);
 418                 }
 419         } else {
 420                 /*
 421                  * we aren't in status mode, so read down the FIFO two
 422                  * characters at time by doing repeated word IO
 423                  * transfer.
 424                  */
 425                 wRecv = ToRecv >> 1;
 426                 if (wRecv)
 427                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
 428                 if (ToRecv & 1)
 429                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
 430                 memset(fbuf, TTY_NORMAL, ToRecv);
 431                 cbuf += ToRecv;
 432                 fbuf += ToRecv;
 433                 count += ToRecv;
 434         }
 435         /*  Push the data up to the tty layer */
 436         ld->receive_buf(tty, chead, fhead, count);
 437 done:
 438         tty_ldisc_deref(ld);
 439 }
 440
 441 /*
 442  *  Serial port transmit data function.  Called from the timer polling loop as a
 443  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
 444  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is
 445  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
 446  */
 447 static void rp_do_transmit(struct r_port *info)
 448 {
 449         int c;
 450         CHANNEL_t *cp = &info->channel;
 451         struct tty_struct *tty;
 452         unsigned long flags;
 453
 454 #ifdef ROCKET_DEBUG_INTR
 455         printk(KERN_INFO "rp_do_transmit ");
 456 #endif
 457         if (!info)
 458                 return;
 459         if (!info->tty) {
 460                 printk(KERN_INFO  "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
 461                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 462                 return;
 463         }
 464
 465         spin_lock_irqsave(&info->slock, flags);
 466         tty = info->tty;
 467         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 468
 469         /*  Loop sending data to FIFO until done or FIFO full */
 470         while (1) {
 471                 if (tty->stopped || tty->hw_stopped)
 472                         break;
 473                 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
 474                 if (c <= 0 || info->xmit_fifo_room <= 0)
 475                         break;
 476                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
 477                 if (c & 1)
 478                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
 479                 info->xmit_tail += c;
 480                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
 481                 info->xmit_cnt -= c;
 482                 info->xmit_fifo_room -= c;
 483 #ifdef ROCKET_DEBUG_INTR
 484                 printk(KERN_INFO "tx %d chars...", c);
 485 #endif
 486         }
 487
 488         if (info->xmit_cnt == 0)
 489                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 490
 491         if (info->xmit_cnt < WAKEUP_CHARS) {
 492                 tty_wakeup(tty);
 493                 wake_up_interruptible(&tty->write_wait);
 494 #ifdef ROCKETPORT_HAVE_POLL_WAIT
 495                 wake_up_interruptible(&tty->poll_wait);
 496 #endif
 497         }
 498
 499         spin_unlock_irqrestore(&info->slock, flags);
 500
 501 #ifdef ROCKET_DEBUG_INTR
 502         printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
 503                info->xmit_tail, info->xmit_fifo_room);
 504 #endif
 505 }
 506
 507 /*
 508  *  Called when a serial port signals it has read data in it's RX FIFO.
 509  *  It checks what interrupts are pending and services them, including
 510  *  receiving serial data.
 511  */
 512 static void rp_handle_port(struct r_port *info)
 513 {
 514         CHANNEL_t *cp;
 515         struct tty_struct *tty;
 516         unsigned int IntMask, ChanStatus;
 517
 518         if (!info)
 519                 return;
 520
 521         if ((info->flags & ROCKET_INITIALIZED) == 0) {
 522                 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
 523                 return;
 524         }
 525         if (!info->tty) {
 526                 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
 527                 return;
 528         }
 529         cp = &info->channel;
 530         tty = info->tty;
 531
 532         IntMask = sGetChanIntID(cp) & info->intmask;
 533 #ifdef ROCKET_DEBUG_INTR
 534         printk(KERN_INFO "rp_interrupt %02x...", IntMask);
 535 #endif
 536         ChanStatus = sGetChanStatus(cp);
 537         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
 538                 rp_do_receive(info, tty, cp, ChanStatus);
 539         }
 540         if (IntMask & DELTA_CD) {       /* CD change  */
 541 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
 542                 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
 543                        (ChanStatus & CD_ACT) ? "on" : "off");
 544 #endif
 545                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
 546 #ifdef ROCKET_DEBUG_HANGUP
 547                         printk(KERN_INFO "CD drop, calling hangup.\n");
 548 #endif
 549                         tty_hangup(tty);
 550                 }
 551                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
 552                 wake_up_interruptible(&info->open_wait);
 553         }
 554 #ifdef ROCKET_DEBUG_INTR
 555         if (IntMask & DELTA_CTS) {      /* CTS change */
 556                 printk(KERN_INFO "CTS change...\n");
 557         }
 558         if (IntMask & DELTA_DSR) {      /* DSR change */
 559                 printk(KERN_INFO "DSR change...\n");
 560         }
 561 #endif
 562 }
 563
 564 /*
 565  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
 566  */
 567 static void rp_do_poll(unsigned long dummy)
 568 {
 569         CONTROLLER_t *ctlp;
 570         int ctrl, aiop, ch, line, i;
 571         unsigned int xmitmask;
 572         unsigned int CtlMask;
 573         unsigned char AiopMask;
 574         Word_t bit;
 575
 576         /*  Walk through all the boards (ctrl's) */
 577         for (ctrl = 0; ctrl < max_board; ctrl++) {
 578                 if (rcktpt_io_addr[ctrl] <= 0)
 579                         continue;
 580
 581                 /*  Get a ptr to the board's control struct */
 582                 ctlp = sCtlNumToCtlPtr(ctrl);
 583
 584                 /*  Get the interupt status from the board */
 585 #ifdef CONFIG_PCI
 586                 if (ctlp->BusType == isPCI)
 587                         CtlMask = sPCIGetControllerIntStatus(ctlp);
 588                 else
 589 #endif
 590                         CtlMask = sGetControllerIntStatus(ctlp);
 591
 592                 /*  Check if any AIOP read bits are set */
 593                 for (aiop = 0; CtlMask; aiop++) {
 594                         bit = ctlp->AiopIntrBits[aiop];
 595                         if (CtlMask & bit) {
 596                                 CtlMask &= ~bit;
 597                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
 598
 599                                 /*  Check if any port read bits are set */
 600                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
 601                                         if (AiopMask & 1) {
 602
 603                                                 /*  Get the line number (/dev/ttyRx number). */
 604                                                 /*  Read the data from the port. */
 605                                                 line = GetLineNumber(ctrl, aiop, ch);
 606                                                 rp_handle_port(rp_table[line]);
 607                                         }
 608                                 }
 609                         }
 610                 }
 611
 612                 xmitmask = xmit_flags[ctrl];
 613
 614                 /*
 615                  *  xmit_flags contains bit-significant flags, indicating there is data
 616                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
 617                  *  1, ... (32 total possible).  The variable i has the aiop and ch
 618                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
 619                  */
 620                 if (xmitmask) {
 621                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
 622                                 if (xmitmask & (1 << i)) {
 623                                         aiop = (i & 0x18) >> 3;
 624                                         ch = i & 0x07;
 625                                         line = GetLineNumber(ctrl, aiop, ch);
 626                                         rp_do_transmit(rp_table[line]);
 627                                 }
 628                         }
 629                 }
 630         }
 631
 632         /*
 633          * Reset the timer so we get called at the next clock tick (10ms).
 634          */
 635         if (atomic_read(&rp_num_ports_open))
 636                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 637 }
 638
 639 /*
 640  *  Initializes the r_port structure for a port, as well as enabling the port on
 641  *  the board.
 642  *  Inputs:  board, aiop, chan numbers
 643  */
 644 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
 645 {
 646         unsigned rocketMode;
 647         struct r_port *info;
 648         int line;
 649         CONTROLLER_T *ctlp;
 650
 651         /*  Get the next available line number */
 652         line = SetLineNumber(board, aiop, chan);
 653
 654         ctlp = sCtlNumToCtlPtr(board);
 655
 656         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
 657         info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
 658         if (!info) {
 659                 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
 660                 return;
 661         }
 662         memset(info, 0, sizeof (struct r_port));
 663
 664         info->magic = RPORT_MAGIC;
 665         info->line = line;
 666         info->ctlp = ctlp;
 667         info->board = board;
 668         info->aiop = aiop;
 669         info->chan = chan;
 670         info->closing_wait = 3000;
 671         info->close_delay = 50;
 672         init_waitqueue_head(&info->open_wait);
 673         init_waitqueue_head(&info->close_wait);
 674         info->flags &= ~ROCKET_MODE_MASK;
 675         switch (pc104[board][line]) {
 676         case 422:
 677                 info->flags |= ROCKET_MODE_RS422;
 678                 break;
 679         case 485:
 680                 info->flags |= ROCKET_MODE_RS485;
 681                 break;
 682         case 232:
 683         default:
 684                 info->flags |= ROCKET_MODE_RS232;
 685                 break;
 686         }
 687
 688         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
 689         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
 690                 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
 691                 kfree(info);
 692                 return;
 693         }
 694
 695         rocketMode = info->flags & ROCKET_MODE_MASK;
 696
 697         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
 698                 sEnRTSToggle(&info->channel);
 699         else
 700                 sDisRTSToggle(&info->channel);
 701
 702         if (ctlp->boardType == ROCKET_TYPE_PC104) {
 703                 switch (rocketMode) {
 704                 case ROCKET_MODE_RS485:
 705                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
 706                         break;
 707                 case ROCKET_MODE_RS422:
 708                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
 709                         break;
 710                 case ROCKET_MODE_RS232:
 711                 default:
 712                         if (info->flags & ROCKET_RTS_TOGGLE)
 713                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
 714                         else
 715                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
 716                         break;
 717                 }
 718         }
 719         spin_lock_init(&info->slock);
 720         sema_init(&info->write_sem, 1);
 721         rp_table[line] = info;
 722         if (pci_dev)
 723                 tty_register_device(rocket_driver, line, &pci_dev->dev);
 724 }
 725
 726 /*
 727  *  Configures a rocketport port according to its termio settings.  Called from
 728  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
 729  */
 730 static void configure_r_port(struct r_port *info,
 731                              struct termios *old_termios)
 732 {
 733         unsigned cflag;
 734         unsigned long flags;
 735         unsigned rocketMode;
 736         int bits, baud, divisor;
 737         CHANNEL_t *cp;
 738
 739         if (!info->tty || !info->tty->termios)
 740                 return;
 741         cp = &info->channel;
 742         cflag = info->tty->termios->c_cflag;
 743
 744         /* Byte size and parity */
 745         if ((cflag & CSIZE) == CS8) {
 746                 sSetData8(cp);
 747                 bits = 10;
 748         } else {
 749                 sSetData7(cp);
 750                 bits = 9;
 751         }
 752         if (cflag & CSTOPB) {
 753                 sSetStop2(cp);
 754                 bits++;
 755         } else {
 756                 sSetStop1(cp);
 757         }
 758
 759         if (cflag & PARENB) {
 760                 sEnParity(cp);
 761                 bits++;
 762                 if (cflag & PARODD) {
 763                         sSetOddParity(cp);
 764                 } else {
 765                         sSetEvenParity(cp);
 766                 }
 767         } else {
 768                 sDisParity(cp);
 769         }
 770
 771         /* baud rate */
 772         baud = tty_get_baud_rate(info->tty);
 773         if (!baud)
 774                 baud = 9600;
 775         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
 776         if ((divisor >= 8192 || divisor < 0) && old_termios) {
 777                 info->tty->termios->c_cflag &= ~CBAUD;
 778                 info->tty->termios->c_cflag |=
 779                     (old_termios->c_cflag & CBAUD);
 780                 baud = tty_get_baud_rate(info->tty);
 781                 if (!baud)
 782                         baud = 9600;
 783                 divisor = (rp_baud_base[info->board] / baud) - 1;
 784         }
 785         if (divisor >= 8192 || divisor < 0) {
 786                 baud = 9600;
 787                 divisor = (rp_baud_base[info->board] / baud) - 1;
 788         }
 789         info->cps = baud / bits;
 790         sSetBaud(cp, divisor);
 791
 792         if (cflag & CRTSCTS) {
 793                 info->intmask |= DELTA_CTS;
 794                 sEnCTSFlowCtl(cp);
 795         } else {
 796                 info->intmask &= ~DELTA_CTS;
 797                 sDisCTSFlowCtl(cp);
 798         }
 799         if (cflag & CLOCAL) {
 800                 info->intmask &= ~DELTA_CD;
 801         } else {
 802                 spin_lock_irqsave(&info->slock, flags);
 803                 if (sGetChanStatus(cp) & CD_ACT)
 804                         info->cd_status = 1;
 805                 else
 806                         info->cd_status = 0;
 807                 info->intmask |= DELTA_CD;
 808                 spin_unlock_irqrestore(&info->slock, flags);
 809         }
 810
 811         /*
 812          * Handle software flow control in the board
 813          */
 814 #ifdef ROCKET_SOFT_FLOW
 815         if (I_IXON(info->tty)) {
 816                 sEnTxSoftFlowCtl(cp);
 817                 if (I_IXANY(info->tty)) {
 818                         sEnIXANY(cp);
 819                 } else {
 820                         sDisIXANY(cp);
 821                 }
 822                 sSetTxXONChar(cp, START_CHAR(info->tty));
 823                 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
 824         } else {
 825                 sDisTxSoftFlowCtl(cp);
 826                 sDisIXANY(cp);
 827                 sClrTxXOFF(cp);
 828         }
 829 #endif
 830
 831         /*
 832          * Set up ignore/read mask words
 833          */
 834         info->read_status_mask = STMRCVROVRH | 0xFF;
 835         if (I_INPCK(info->tty))
 836                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
 837         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
 838                 info->read_status_mask |= STMBREAKH;
 839
 840         /*
 841          * Characters to ignore
 842          */
 843         info->ignore_status_mask = 0;
 844         if (I_IGNPAR(info->tty))
 845                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
 846         if (I_IGNBRK(info->tty)) {
 847                 info->ignore_status_mask |= STMBREAKH;
 848                 /*
 849                  * If we're ignoring parity and break indicators,
 850                  * ignore overruns too.  (For real raw support).
 851                  */
 852                 if (I_IGNPAR(info->tty))
 853                         info->ignore_status_mask |= STMRCVROVRH;
 854         }
 855
 856         rocketMode = info->flags & ROCKET_MODE_MASK;
 857
 858         if ((info->flags & ROCKET_RTS_TOGGLE)
 859             || (rocketMode == ROCKET_MODE_RS485))
 860                 sEnRTSToggle(cp);
 861         else
 862                 sDisRTSToggle(cp);
 863
 864         sSetRTS(&info->channel);
 865
 866         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
 867                 switch (rocketMode) {
 868                 case ROCKET_MODE_RS485:
 869                         sSetInterfaceMode(cp, InterfaceModeRS485);
 870                         break;
 871                 case ROCKET_MODE_RS422:
 872                         sSetInterfaceMode(cp, InterfaceModeRS422);
 873                         break;
 874                 case ROCKET_MODE_RS232:
 875                 default:
 876                         if (info->flags & ROCKET_RTS_TOGGLE)
 877                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
 878                         else
 879                                 sSetInterfaceMode(cp, InterfaceModeRS232);
 880                         break;
 881                 }
 882         }
 883 }
 884
 885 /*  info->count is considered critical, protected by spinlocks.  */
 886 static int block_til_ready(struct tty_struct *tty, struct file *filp,
 887                            struct r_port *info)
 888 {
 889         DECLARE_WAITQUEUE(wait, current);
 890         int retval;
 891         int do_clocal = 0, extra_count = 0;
 892         unsigned long flags;
 893
 894         /*
 895          * If the device is in the middle of being closed, then block
 896          * until it's done, and then try again.
 897          */
 898         if (tty_hung_up_p(filp))
 899                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 900         if (info->flags & ROCKET_CLOSING) {
 901                 interruptible_sleep_on(&info->close_wait);
 902                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 903         }
 904
 905         /*
 906          * If non-blocking mode is set, or the port is not enabled,
 907          * then make the check up front and then exit.
 908          */
 909         if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
 910                 info->flags |= ROCKET_NORMAL_ACTIVE;
 911                 return 0;
 912         }
 913         if (tty->termios->c_cflag & CLOCAL)
 914                 do_clocal = 1;
 915
 916         /*
 917          * Block waiting for the carrier detect and the line to become free.  While we are in
 918          * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
 919          * We restore it upon exit, either normal or abnormal.
 920          */
 921         retval = 0;
 922         add_wait_queue(&info->open_wait, &wait);
 923 #ifdef ROCKET_DEBUG_OPEN
 924         printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
 925 #endif
 926         spin_lock_irqsave(&info->slock, flags);
 927
 928 #ifdef ROCKET_DISABLE_SIMUSAGE
 929         info->flags |= ROCKET_NORMAL_ACTIVE;
 930 #else
 931         if (!tty_hung_up_p(filp)) {
 932                 extra_count = 1;
 933                 info->count--;
 934         }
 935 #endif
 936         info->blocked_open++;
 937
 938         spin_unlock_irqrestore(&info->slock, flags);
 939
 940         while (1) {
 941                 if (tty->termios->c_cflag & CBAUD) {
 942                         sSetDTR(&info->channel);
 943                         sSetRTS(&info->channel);
 944                 }
 945                 set_current_state(TASK_INTERRUPTIBLE);
 946                 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
 947                         if (info->flags & ROCKET_HUP_NOTIFY)
 948                                 retval = -EAGAIN;
 949                         else
 950                                 retval = -ERESTARTSYS;
 951                         break;
 952                 }
 953                 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
 954                         break;
 955                 if (signal_pending(current)) {
 956                         retval = -ERESTARTSYS;
 957                         break;
 958                 }
 959 #ifdef ROCKET_DEBUG_OPEN
 960                 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
 961                      info->line, info->count, info->flags);
 962 #endif
 963                 schedule();     /*  Don't hold spinlock here, will hang PC */
 964         }
 965         current->state = TASK_RUNNING;
 966         remove_wait_queue(&info->open_wait, &wait);
 967
 968         spin_lock_irqsave(&info->slock, flags);
 969
 970         if (extra_count)
 971                 info->count++;
 972         info->blocked_open--;
 973
 974         spin_unlock_irqrestore(&info->slock, flags);
 975
 976 #ifdef ROCKET_DEBUG_OPEN
 977         printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
 978                info->line, info->count);
 979 #endif
 980         if (retval)
 981                 return retval;
 982         info->flags |= ROCKET_NORMAL_ACTIVE;
 983         return 0;
 984 }
 985
 986 /*
 987  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in
 988  *  port's r_port struct.  Initializes the port hardware.
 989  */
 990 static int rp_open(struct tty_struct *tty, struct file *filp)
 991 {
 992         struct r_port *info;
 993         int line = 0, retval;
 994         CHANNEL_t *cp;
 995         unsigned long page;
 996
 997         line = TTY_GET_LINE(tty);
 998         if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
 999                 return -ENXIO;
1000
1001         page = __get_free_page(GFP_KERNEL);
1002         if (!page)
1003                 return -ENOMEM;
1004
1005         if (info->flags & ROCKET_CLOSING) {
1006                 interruptible_sleep_on(&info->close_wait);
1007                 free_page(page);
1008                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1009         }
1010
1011         /*
1012          * We must not sleep from here until the port is marked fully in use.
1013          */
1014         if (info->xmit_buf)
1015                 free_page(page);
1016         else
1017                 info->xmit_buf = (unsigned char *) page;
1018
1019         tty->driver_data = info;
1020         info->tty = tty;
1021
1022         if (info->count++ == 0) {
1023                 atomic_inc(&rp_num_ports_open);
1024
1025 #ifdef ROCKET_DEBUG_OPEN
1026                 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
1027 #endif
1028         }
1029 #ifdef ROCKET_DEBUG_OPEN
1030         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1031 #endif
1032
1033         /*
1034          * Info->count is now 1; so it's safe to sleep now.
1035          */
1036         info->session = current->signal->session;
1037         info->pgrp = process_group(current);
1038
1039         if ((info->flags & ROCKET_INITIALIZED) == 0) {
1040                 cp = &info->channel;
1041                 sSetRxTrigger(cp, TRIG_1);
1042                 if (sGetChanStatus(cp) & CD_ACT)
1043                         info->cd_status = 1;
1044                 else
1045                         info->cd_status = 0;
1046                 sDisRxStatusMode(cp);
1047                 sFlushRxFIFO(cp);
1048                 sFlushTxFIFO(cp);
1049
1050                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1051                 sSetRxTrigger(cp, TRIG_1);
1052
1053                 sGetChanStatus(cp);
1054                 sDisRxStatusMode(cp);
1055                 sClrTxXOFF(cp);
1056
1057                 sDisCTSFlowCtl(cp);
1058                 sDisTxSoftFlowCtl(cp);
1059
1060                 sEnRxFIFO(cp);
1061                 sEnTransmit(cp);
1062
1063                 info->flags |= ROCKET_INITIALIZED;
1064
1065                 /*
1066                  * Set up the tty->alt_speed kludge
1067                  */
1068                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1069                         info->tty->alt_speed = 57600;
1070                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1071                         info->tty->alt_speed = 115200;
1072                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1073                         info->tty->alt_speed = 230400;
1074                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1075                         info->tty->alt_speed = 460800;
1076
1077                 configure_r_port(info, NULL);
1078                 if (tty->termios->c_cflag & CBAUD) {
1079                         sSetDTR(cp);
1080                         sSetRTS(cp);
1081                 }
1082         }
1083         /*  Starts (or resets) the maint polling loop */
1084         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1085
1086         retval = block_til_ready(tty, filp, info);
1087         if (retval) {
1088 #ifdef ROCKET_DEBUG_OPEN
1089                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1090 #endif
1091                 return retval;
1092         }
1093         return 0;
1094 }
1095
1096 /*
1097  *  Exception handler that closes a serial port. info->count is considered critical.
1098  */
1099 static void rp_close(struct tty_struct *tty, struct file *filp)
1100 {
1101         struct r_port *info = (struct r_port *) tty->driver_data;
1102         unsigned long flags;
1103         int timeout;
1104         CHANNEL_t *cp;
1105
1106         if (rocket_paranoia_check(info, "rp_close"))
1107                 return;
1108
1109 #ifdef ROCKET_DEBUG_OPEN
1110         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1111 #endif
1112
1113         if (tty_hung_up_p(filp))
1114                 return;
1115         spin_lock_irqsave(&info->slock, flags);
1116
1117         if ((tty->count == 1) && (info->count != 1)) {
1118                 /*
1119                  * Uh, oh.  tty->count is 1, which means that the tty
1120                  * structure will be freed.  Info->count should always
1121                  * be one in these conditions.  If it's greater than
1122                  * one, we've got real problems, since it means the
1123                  * serial port won't be shutdown.
1124                  */
1125                 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1126                        "info->count is %d\n", info->count);
1127                 info->count = 1;
1128         }
1129         if (--info->count < 0) {
1130                 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1131                        info->line, info->count);
1132                 info->count = 0;
1133         }
1134         if (info->count) {
1135                 spin_unlock_irqrestore(&info->slock, flags);
1136                 return;
1137         }
1138         info->flags |= ROCKET_CLOSING;
1139         spin_unlock_irqrestore(&info->slock, flags);
1140
1141         cp = &info->channel;
1142
1143         /*
1144          * Notify the line discpline to only process XON/XOFF characters
1145          */
1146         tty->closing = 1;
1147
1148         /*
1149          * If transmission was throttled by the application request,
1150          * just flush the xmit buffer.
1151          */
1152         if (tty->flow_stopped)
1153                 rp_flush_buffer(tty);
1154
1155         /*
1156          * Wait for the transmit buffer to clear
1157          */
1158         if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1159                 tty_wait_until_sent(tty, info->closing_wait);
1160         /*
1161          * Before we drop DTR, make sure the UART transmitter
1162          * has completely drained; this is especially
1163          * important if there is a transmit FIFO!
1164          */
1165         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1166         if (timeout == 0)
1167                 timeout = 1;
1168         rp_wait_until_sent(tty, timeout);
1169         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1170
1171         sDisTransmit(cp);
1172         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1173         sDisCTSFlowCtl(cp);
1174         sDisTxSoftFlowCtl(cp);
1175         sClrTxXOFF(cp);
1176         sFlushRxFIFO(cp);
1177         sFlushTxFIFO(cp);
1178         sClrRTS(cp);
1179         if (C_HUPCL(tty))
1180                 sClrDTR(cp);
1181
1182         if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1183                 TTY_DRIVER_FLUSH_BUFFER(tty);
1184
1185         tty_ldisc_flush(tty);
1186
1187         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1188
1189         if (info->blocked_open) {
1190                 if (info->close_delay) {
1191                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
1192                 }
1193                 wake_up_interruptible(&info->open_wait);
1194         } else {
1195                 if (info->xmit_buf) {
1196                         free_page((unsigned long) info->xmit_buf);
1197                         info->xmit_buf = NULL;
1198                 }
1199         }
1200         info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1201         tty->closing = 0;
1202         wake_up_interruptible(&info->close_wait);
1203         atomic_dec(&rp_num_ports_open);
1204
1205 #ifdef ROCKET_DEBUG_OPEN
1206         printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1207         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1208 #endif
1209
1210 }
1211
1212 static void rp_set_termios(struct tty_struct *tty,
1213                            struct termios *old_termios)
1214 {
1215         struct r_port *info = (struct r_port *) tty->driver_data;
1216         CHANNEL_t *cp;
1217         unsigned cflag;
1218
1219         if (rocket_paranoia_check(info, "rp_set_termios"))
1220                 return;
1221
1222         cflag = tty->termios->c_cflag;
1223
1224         if (cflag == old_termios->c_cflag)
1225                 return;
1226
1227         /*
1228          * This driver doesn't support CS5 or CS6
1229          */
1230         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1231                 tty->termios->c_cflag =
1232                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1233
1234         configure_r_port(info, old_termios);
1235
1236         cp = &info->channel;
1237
1238         /* Handle transition to B0 status */
1239         if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1240                 sClrDTR(cp);
1241                 sClrRTS(cp);
1242         }
1243
1244         /* Handle transition away from B0 status */
1245         if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1246                 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1247                         sSetRTS(cp);
1248                 sSetDTR(cp);
1249         }
1250
1251         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1252                 tty->hw_stopped = 0;
1253                 rp_start(tty);
1254         }
1255 }
1256
1257 static void rp_break(struct tty_struct *tty, int break_state)
1258 {
1259         struct r_port *info = (struct r_port *) tty->driver_data;
1260         unsigned long flags;
1261
1262         if (rocket_paranoia_check(info, "rp_break"))
1263                 return;
1264
1265         spin_lock_irqsave(&info->slock, flags);
1266         if (break_state == -1)
1267                 sSendBreak(&info->channel);
1268         else
1269                 sClrBreak(&info->channel);
1270         spin_unlock_irqrestore(&info->slock, flags);
1271 }
1272
1273 /*
1274  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1275  * the UPCI boards was added, it was decided to make this a function because
1276  * the macro was getting too complicated. All cases except the first one
1277  * (UPCIRingInd) are taken directly from the original macro.
1278  */
1279 static int sGetChanRI(CHANNEL_T * ChP)
1280 {
1281         CONTROLLER_t *CtlP = ChP->CtlP;
1282         int ChanNum = ChP->ChanNum;
1283         int RingInd = 0;
1284
1285         if (CtlP->UPCIRingInd)
1286                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1287         else if (CtlP->AltChanRingIndicator)
1288                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1289         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1290                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1291
1292         return RingInd;
1293 }
1294
1295 /********************************************************************************************/
1296 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1297
1298 /*
1299  *  Returns the state of the serial modem control lines.  These next 2 functions
1300  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1301  */
1302 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1303 {
1304         struct r_port *info = (struct r_port *)tty->driver_data;
1305         unsigned int control, result, ChanStatus;
1306
1307         ChanStatus = sGetChanStatusLo(&info->channel);
1308         control = info->channel.TxControl[3];
1309         result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1310                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1311                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1312                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1313                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1314                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1315
1316         return result;
1317 }
1318
1319 /*
1320  *  Sets the modem control lines
1321  */
1322 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1323                     unsigned int set, unsigned int clear)
1324 {
1325         struct r_port *info = (struct r_port *)tty->driver_data;
1326
1327         if (set & TIOCM_RTS)
1328                 info->channel.TxControl[3] |= SET_RTS;
1329         if (set & TIOCM_DTR)
1330                 info->channel.TxControl[3] |= SET_DTR;
1331         if (clear & TIOCM_RTS)
1332                 info->channel.TxControl[3] &= ~SET_RTS;
1333         if (clear & TIOCM_DTR)
1334                 info->channel.TxControl[3] &= ~SET_DTR;
1335
1336         sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1337         return 0;
1338 }
1339
1340 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1341 {
1342         struct rocket_config tmp;
1343
1344         if (!retinfo)
1345                 return -EFAULT;
1346         memset(&tmp, 0, sizeof (tmp));
1347         tmp.line = info->line;
1348         tmp.flags = info->flags;
1349         tmp.close_delay = info->close_delay;
1350         tmp.closing_wait = info->closing_wait;
1351         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1352
1353         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1354                 return -EFAULT;
1355         return 0;
1356 }
1357
1358 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1359 {
1360         struct rocket_config new_serial;
1361
1362         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1363                 return -EFAULT;
1364
1365         if (!capable(CAP_SYS_ADMIN))
1366         {
1367                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1368                         return -EPERM;
1369                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1370                 configure_r_port(info, NULL);
1371                 return 0;
1372         }
1373
1374         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1375         info->close_delay = new_serial.close_delay;
1376         info->closing_wait = new_serial.closing_wait;
1377
1378         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1379                 info->tty->alt_speed = 57600;
1380         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1381                 info->tty->alt_speed = 115200;
1382         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1383                 info->tty->alt_speed = 230400;
1384         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1385                 info->tty->alt_speed = 460800;
1386
1387         configure_r_port(info, NULL);
1388         return 0;
1389 }
1390
1391 /*
1392  *  This function fills in a rocket_ports struct with information
1393  *  about what boards/ports are in the system.  This info is passed
1394  *  to user space.  See setrocket.c where the info is used to create
1395  *  the /dev/ttyRx ports.
1396  */
1397 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1398 {
1399         struct rocket_ports tmp;
1400         int board;
1401
1402         if (!retports)
1403                 return -EFAULT;
1404         memset(&tmp, 0, sizeof (tmp));
1405         tmp.tty_major = rocket_driver->major;
1406
1407         for (board = 0; board < 4; board++) {
1408                 tmp.rocketModel[board].model = rocketModel[board].model;
1409                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1410                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1411                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1412                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1413         }
1414         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1415                 return -EFAULT;
1416         return 0;
1417 }
1418
1419 static int reset_rm2(struct r_port *info, void __user *arg)
1420 {
1421         int reset;
1422
1423         if (copy_from_user(&reset, arg, sizeof (int)))
1424                 return -EFAULT;
1425         if (reset)
1426                 reset = 1;
1427
1428         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1429             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1430                 return -EINVAL;
1431
1432         if (info->ctlp->BusType == isISA)
1433                 sModemReset(info->ctlp, info->chan, reset);
1434         else
1435                 sPCIModemReset(info->ctlp, info->chan, reset);
1436
1437         return 0;
1438 }
1439
1440 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1441 {
1442         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1443                 return -EFAULT;
1444         return 0;
1445 }
1446
1447 /*  IOCTL call handler into the driver */
1448 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1449                     unsigned int cmd, unsigned long arg)
1450 {
1451         struct r_port *info = (struct r_port *) tty->driver_data;
1452         void __user *argp = (void __user *)arg;
1453
1454         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1455                 return -ENXIO;
1456
1457         switch (cmd) {
1458         case RCKP_GET_STRUCT:
1459                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1460                         return -EFAULT;
1461                 return 0;
1462         case RCKP_GET_CONFIG:
1463                 return get_config(info, argp);
1464         case RCKP_SET_CONFIG:
1465                 return set_config(info, argp);
1466         case RCKP_GET_PORTS:
1467                 return get_ports(info, argp);
1468         case RCKP_RESET_RM2:
1469                 return reset_rm2(info, argp);
1470         case RCKP_GET_VERSION:
1471                 return get_version(info, argp);
1472         default:
1473                 return -ENOIOCTLCMD;
1474         }
1475         return 0;
1476 }
1477
1478 static void rp_send_xchar(struct tty_struct *tty, char ch)
1479 {
1480         struct r_port *info = (struct r_port *) tty->driver_data;
1481         CHANNEL_t *cp;
1482
1483         if (rocket_paranoia_check(info, "rp_send_xchar"))
1484                 return;
1485
1486         cp = &info->channel;
1487         if (sGetTxCnt(cp))
1488                 sWriteTxPrioByte(cp, ch);
1489         else
1490                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1491 }
1492
1493 static void rp_throttle(struct tty_struct *tty)
1494 {
1495         struct r_port *info = (struct r_port *) tty->driver_data;
1496         CHANNEL_t *cp;
1497
1498 #ifdef ROCKET_DEBUG_THROTTLE
1499         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1500                tty->ldisc.chars_in_buffer(tty));
1501 #endif
1502
1503         if (rocket_paranoia_check(info, "rp_throttle"))
1504                 return;
1505
1506         cp = &info->channel;
1507         if (I_IXOFF(tty))
1508                 rp_send_xchar(tty, STOP_CHAR(tty));
1509
1510         sClrRTS(&info->channel);
1511 }
1512
1513 static void rp_unthrottle(struct tty_struct *tty)
1514 {
1515         struct r_port *info = (struct r_port *) tty->driver_data;
1516         CHANNEL_t *cp;
1517 #ifdef ROCKET_DEBUG_THROTTLE
1518         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1519                tty->ldisc.chars_in_buffer(tty));
1520 #endif
1521
1522         if (rocket_paranoia_check(info, "rp_throttle"))
1523                 return;
1524
1525         cp = &info->channel;
1526         if (I_IXOFF(tty))
1527                 rp_send_xchar(tty, START_CHAR(tty));
1528
1529         sSetRTS(&info->channel);
1530 }
1531
1532 /*
1533  * ------------------------------------------------------------
1534  * rp_stop() and rp_start()
1535  *
1536  * This routines are called before setting or resetting tty->stopped.
1537  * They enable or disable transmitter interrupts, as necessary.
1538  * ------------------------------------------------------------
1539  */
1540 static void rp_stop(struct tty_struct *tty)
1541 {
1542         struct r_port *info = (struct r_port *) tty->driver_data;
1543
1544 #ifdef ROCKET_DEBUG_FLOW
1545         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1546                info->xmit_cnt, info->xmit_fifo_room);
1547 #endif
1548
1549         if (rocket_paranoia_check(info, "rp_stop"))
1550                 return;
1551
1552         if (sGetTxCnt(&info->channel))
1553                 sDisTransmit(&info->channel);
1554 }
1555
1556 static void rp_start(struct tty_struct *tty)
1557 {
1558         struct r_port *info = (struct r_port *) tty->driver_data;
1559
1560 #ifdef ROCKET_DEBUG_FLOW
1561         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1562                info->xmit_cnt, info->xmit_fifo_room);
1563 #endif
1564
1565         if (rocket_paranoia_check(info, "rp_stop"))
1566                 return;
1567
1568         sEnTransmit(&info->channel);
1569         set_bit((info->aiop * 8) + info->chan,
1570                 (void *) &xmit_flags[info->board]);
1571 }
1572
1573 /*
1574  * rp_wait_until_sent() --- wait until the transmitter is empty
1575  */
1576 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1577 {
1578         struct r_port *info = (struct r_port *) tty->driver_data;
1579         CHANNEL_t *cp;
1580         unsigned long orig_jiffies;
1581         int check_time, exit_time;
1582         int txcnt;
1583
1584         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1585                 return;
1586
1587         cp = &info->channel;
1588
1589         orig_jiffies = jiffies;
1590 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1591         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1592                jiffies);
1593         printk(KERN_INFO "cps=%d...", info->cps);
1594 #endif
1595         while (1) {
1596                 txcnt = sGetTxCnt(cp);
1597                 if (!txcnt) {
1598                         if (sGetChanStatusLo(cp) & TXSHRMT)
1599                                 break;
1600                         check_time = (HZ / info->cps) / 5;
1601                 } else {
1602                         check_time = HZ * txcnt / info->cps;
1603                 }
1604                 if (timeout) {
1605                         exit_time = orig_jiffies + timeout - jiffies;
1606                         if (exit_time <= 0)
1607                                 break;
1608                         if (exit_time < check_time)
1609                                 check_time = exit_time;
1610                 }
1611                 if (check_time == 0)
1612                         check_time = 1;
1613 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1614                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1615 #endif
1616                 msleep_interruptible(jiffies_to_msecs(check_time));
1617                 if (signal_pending(current))
1618                         break;
1619         }
1620         current->state = TASK_RUNNING;
1621 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1622         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1623 #endif
1624 }
1625
1626 /*
1627  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1628  */
1629 static void rp_hangup(struct tty_struct *tty)
1630 {
1631         CHANNEL_t *cp;
1632         struct r_port *info = (struct r_port *) tty->driver_data;
1633
1634         if (rocket_paranoia_check(info, "rp_hangup"))
1635                 return;
1636
1637 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1638         printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1639 #endif
1640         rp_flush_buffer(tty);
1641         if (info->flags & ROCKET_CLOSING)
1642                 return;
1643         if (info->count)
1644                 atomic_dec(&rp_num_ports_open);
1645         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1646
1647         info->count = 0;
1648         info->flags &= ~ROCKET_NORMAL_ACTIVE;
1649         info->tty = NULL;
1650
1651         cp = &info->channel;
1652         sDisRxFIFO(cp);
1653         sDisTransmit(cp);
1654         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1655         sDisCTSFlowCtl(cp);
1656         sDisTxSoftFlowCtl(cp);
1657         sClrTxXOFF(cp);
1658         info->flags &= ~ROCKET_INITIALIZED;
1659
1660         wake_up_interruptible(&info->open_wait);
1661 }
1662
1663 /*
1664  *  Exception handler - write char routine.  The RocketPort driver uses a
1665  *  double-buffering strategy, with the twist that if the in-memory CPU
1666  *  buffer is empty, and there's space in the transmit FIFO, the
1667  *  writing routines will write directly to transmit FIFO.
1668  *  Write buffer and counters protected by spinlocks
1669  */
1670 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1671 {
1672         struct r_port *info = (struct r_port *) tty->driver_data;
1673         CHANNEL_t *cp;
1674         unsigned long flags;
1675
1676         if (rocket_paranoia_check(info, "rp_put_char"))
1677                 return;
1678
1679         /*  Grab the port write semaphore, locking out other processes that try to write to this port */
1680         down(&info->write_sem);
1681
1682 #ifdef ROCKET_DEBUG_WRITE
1683         printk(KERN_INFO "rp_put_char %c...", ch);
1684 #endif
1685
1686         spin_lock_irqsave(&info->slock, flags);
1687         cp = &info->channel;
1688
1689         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1690                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1691
1692         if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1693                 info->xmit_buf[info->xmit_head++] = ch;
1694                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1695                 info->xmit_cnt++;
1696                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1697         } else {
1698                 sOutB(sGetTxRxDataIO(cp), ch);
1699                 info->xmit_fifo_room--;
1700         }
1701         spin_unlock_irqrestore(&info->slock, flags);
1702         up(&info->write_sem);
1703 }
1704
1705 /*
1706  *  Exception handler - write routine, called when user app writes to the device.
1707  *  A per port write semaphore is used to protect from another process writing to
1708  *  this port at the same time.  This other process could be running on the other CPU
1709  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1710  *  Spinlocks protect the info xmit members.
1711  */
1712 static int rp_write(struct tty_struct *tty,
1713                     const unsigned char *buf, int count)
1714 {
1715         struct r_port *info = (struct r_port *) tty->driver_data;
1716         CHANNEL_t *cp;
1717         const unsigned char *b;
1718         int c, retval = 0;
1719         unsigned long flags;
1720
1721         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1722                 return 0;
1723
1724         down_interruptible(&info->write_sem);
1725
1726 #ifdef ROCKET_DEBUG_WRITE
1727         printk(KERN_INFO "rp_write %d chars...", count);
1728 #endif
1729         cp = &info->channel;
1730
1731         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1732                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1733
1734         /*
1735          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes
1736          *  into FIFO.  Use the write queue for temp storage.
1737          */
1738         if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1739                 c = min(count, info->xmit_fifo_room);
1740                 b = buf;
1741
1742                 /*  Push data into FIFO, 2 bytes at a time */
1743                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1744
1745                 /*  If there is a byte remaining, write it */
1746                 if (c & 1)
1747                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1748
1749                 retval += c;
1750                 buf += c;
1751                 count -= c;
1752
1753                 spin_lock_irqsave(&info->slock, flags);
1754                 info->xmit_fifo_room -= c;
1755                 spin_unlock_irqrestore(&info->slock, flags);
1756         }
1757
1758         /* If count is zero, we wrote it all and are done */
1759         if (!count)
1760                 goto end;
1761
1762         /*  Write remaining data into the port's xmit_buf */
1763         while (1) {
1764                 if (info->tty == 0)     /*   Seemingly obligatory check... */
1765                         goto end;
1766
1767                 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1768                 if (c <= 0)
1769                         break;
1770
1771                 b = buf;
1772                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1773
1774                 spin_lock_irqsave(&info->slock, flags);
1775                 info->xmit_head =
1776                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1777                 info->xmit_cnt += c;
1778                 spin_unlock_irqrestore(&info->slock, flags);
1779
1780                 buf += c;
1781                 count -= c;
1782                 retval += c;
1783         }
1784
1785         if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1786                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1787
1788 end:
1789         if (info->xmit_cnt < WAKEUP_CHARS) {
1790                 tty_wakeup(tty);
1791                 wake_up_interruptible(&tty->write_wait);
1792 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1793                 wake_up_interruptible(&tty->poll_wait);
1794 #endif
1795         }
1796         up(&info->write_sem);
1797         return retval;
1798 }
1799
1800 /*
1801  * Return the number of characters that can be sent.  We estimate
1802  * only using the in-memory transmit buffer only, and ignore the
1803  * potential space in the transmit FIFO.
1804  */
1805 static int rp_write_room(struct tty_struct *tty)
1806 {
1807         struct r_port *info = (struct r_port *) tty->driver_data;
1808         int ret;
1809
1810         if (rocket_paranoia_check(info, "rp_write_room"))
1811                 return 0;
1812
1813         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1814         if (ret < 0)
1815                 ret = 0;
1816 #ifdef ROCKET_DEBUG_WRITE
1817         printk(KERN_INFO "rp_write_room returns %d...", ret);
1818 #endif
1819         return ret;
1820 }
1821
1822 /*
1823  * Return the number of characters in the buffer.  Again, this only
1824  * counts those characters in the in-memory transmit buffer.
1825  */
1826 static int rp_chars_in_buffer(struct tty_struct *tty)
1827 {
1828         struct r_port *info = (struct r_port *) tty->driver_data;
1829         CHANNEL_t *cp;
1830
1831         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1832                 return 0;
1833
1834         cp = &info->channel;
1835
1836 #ifdef ROCKET_DEBUG_WRITE
1837         printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1838 #endif
1839         return info->xmit_cnt;
1840 }
1841
1842 /*
1843  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1844  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1845  *  do not call this function if the spinlock is already held.
1846  */
1847 static void rp_flush_buffer(struct tty_struct *tty)
1848 {
1849         struct r_port *info = (struct r_port *) tty->driver_data;
1850         CHANNEL_t *cp;
1851         unsigned long flags;
1852
1853         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1854                 return;
1855
1856         spin_lock_irqsave(&info->slock, flags);
1857         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1858         spin_unlock_irqrestore(&info->slock, flags);
1859
1860         wake_up_interruptible(&tty->write_wait);
1861 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1862         wake_up_interruptible(&tty->poll_wait);
1863 #endif
1864         tty_wakeup(tty);
1865
1866         cp = &info->channel;
1867         sFlushTxFIFO(cp);
1868 }
1869
1870 #ifdef CONFIG_PCI
1871
1872 /*
1873  *  Called when a PCI card is found.  Retrieves and stores model information,
1874  *  init's aiopic and serial port hardware.
1875  *  Inputs:  i is the board number (0-n)
1876  */
1877 static __init int register_PCI(int i, struct pci_dev *dev)
1878 {
1879         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1880         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1881         char *str, *board_type;
1882         CONTROLLER_t *ctlp;
1883
1884         int fast_clock = 0;
1885         int altChanRingIndicator = 0;
1886         int ports_per_aiop = 8;
1887         int ret;
1888         unsigned int class_rev;
1889         WordIO_t ConfigIO = 0;
1890         ByteIO_t UPCIRingInd = 0;
1891
1892         if (!dev || pci_enable_device(dev))
1893                 return 0;
1894
1895         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1896         ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1897
1898         if (ret) {
1899                 printk(KERN_INFO "  Error during register_PCI(), unable to read config dword \n");
1900                 return 0;
1901         }
1902
1903         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1904         rocketModel[i].loadrm2 = 0;
1905         rocketModel[i].startingPortNumber = nextLineNumber;
1906
1907         /*  Depending on the model, set up some config variables */
1908         switch (dev->device) {
1909         case PCI_DEVICE_ID_RP4QUAD:
1910                 str = "Quadcable";
1911                 max_num_aiops = 1;
1912                 ports_per_aiop = 4;
1913                 rocketModel[i].model = MODEL_RP4QUAD;
1914                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1915                 rocketModel[i].numPorts = 4;
1916                 break;
1917         case PCI_DEVICE_ID_RP8OCTA:
1918                 str = "Octacable";
1919                 max_num_aiops = 1;
1920                 rocketModel[i].model = MODEL_RP8OCTA;
1921                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1922                 rocketModel[i].numPorts = 8;
1923                 break;
1924         case PCI_DEVICE_ID_URP8OCTA:
1925                 str = "Octacable";
1926                 max_num_aiops = 1;
1927                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1928                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1929                 rocketModel[i].numPorts = 8;
1930                 break;
1931         case PCI_DEVICE_ID_RP8INTF:
1932                 str = "8";
1933                 max_num_aiops = 1;
1934                 rocketModel[i].model = MODEL_RP8INTF;
1935                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1936                 rocketModel[i].numPorts = 8;
1937                 break;
1938         case PCI_DEVICE_ID_URP8INTF:
1939                 str = "8";
1940                 max_num_aiops = 1;
1941                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1942                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1943                 rocketModel[i].numPorts = 8;
1944                 break;
1945         case PCI_DEVICE_ID_RP8J:
1946                 str = "8J";
1947                 max_num_aiops = 1;
1948                 rocketModel[i].model = MODEL_RP8J;
1949                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1950                 rocketModel[i].numPorts = 8;
1951                 break;
1952         case PCI_DEVICE_ID_RP4J:
1953                 str = "4J";
1954                 max_num_aiops = 1;
1955                 ports_per_aiop = 4;
1956                 rocketModel[i].model = MODEL_RP4J;
1957                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1958                 rocketModel[i].numPorts = 4;
1959                 break;
1960         case PCI_DEVICE_ID_RP8SNI:
1961                 str = "8 (DB78 Custom)";
1962                 max_num_aiops = 1;
1963                 rocketModel[i].model = MODEL_RP8SNI;
1964                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1965                 rocketModel[i].numPorts = 8;
1966                 break;
1967         case PCI_DEVICE_ID_RP16SNI:
1968                 str = "16 (DB78 Custom)";
1969                 max_num_aiops = 2;
1970                 rocketModel[i].model = MODEL_RP16SNI;
1971                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1972                 rocketModel[i].numPorts = 16;
1973                 break;
1974         case PCI_DEVICE_ID_RP16INTF:
1975                 str = "16";
1976                 max_num_aiops = 2;
1977                 rocketModel[i].model = MODEL_RP16INTF;
1978                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1979                 rocketModel[i].numPorts = 16;
1980                 break;
1981         case PCI_DEVICE_ID_URP16INTF:
1982                 str = "16";
1983                 max_num_aiops = 2;
1984                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1985                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1986                 rocketModel[i].numPorts = 16;
1987                 break;
1988         case PCI_DEVICE_ID_CRP16INTF:
1989                 str = "16";
1990                 max_num_aiops = 2;
1991                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1992                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1993                 rocketModel[i].numPorts = 16;
1994                 break;
1995         case PCI_DEVICE_ID_RP32INTF:
1996                 str = "32";
1997                 max_num_aiops = 4;
1998                 rocketModel[i].model = MODEL_RP32INTF;
1999                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2000                 rocketModel[i].numPorts = 32;
2001                 break;
2002         case PCI_DEVICE_ID_URP32INTF:
2003                 str = "32";
2004                 max_num_aiops = 4;
2005                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2006                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2007                 rocketModel[i].numPorts = 32;
2008                 break;
2009         case PCI_DEVICE_ID_RPP4:
2010                 str = "Plus Quadcable";
2011                 max_num_aiops = 1;
2012                 ports_per_aiop = 4;
2013                 altChanRingIndicator++;
2014                 fast_clock++;
2015                 rocketModel[i].model = MODEL_RPP4;
2016                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2017                 rocketModel[i].numPorts = 4;
2018                 break;
2019         case PCI_DEVICE_ID_RPP8:
2020                 str = "Plus Octacable";
2021                 max_num_aiops = 2;
2022                 ports_per_aiop = 4;
2023                 altChanRingIndicator++;
2024                 fast_clock++;
2025                 rocketModel[i].model = MODEL_RPP8;
2026                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2027                 rocketModel[i].numPorts = 8;
2028                 break;
2029         case PCI_DEVICE_ID_RP2_232:
2030                 str = "Plus 2 (RS-232)";
2031                 max_num_aiops = 1;
2032                 ports_per_aiop = 2;
2033                 altChanRingIndicator++;
2034                 fast_clock++;
2035                 rocketModel[i].model = MODEL_RP2_232;
2036                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2037                 rocketModel[i].numPorts = 2;
2038                 break;
2039         case PCI_DEVICE_ID_RP2_422:
2040                 str = "Plus 2 (RS-422)";
2041                 max_num_aiops = 1;
2042                 ports_per_aiop = 2;
2043                 altChanRingIndicator++;
2044                 fast_clock++;
2045                 rocketModel[i].model = MODEL_RP2_422;
2046                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2047                 rocketModel[i].numPorts = 2;
2048                 break;
2049         case PCI_DEVICE_ID_RP6M:
2050
2051                 max_num_aiops = 1;
2052                 ports_per_aiop = 6;
2053                 str = "6-port";
2054
2055                 /*  If class_rev is 1, the rocketmodem flash must be loaded.  If it is 2 it is a "socketed" version. */
2056                 if ((class_rev & 0xFF) == 1) {
2057                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2058                         rocketModel[i].loadrm2 = 1;
2059                 } else {
2060                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2061                 }
2062
2063                 rocketModel[i].model = MODEL_RP6M;
2064                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2065                 rocketModel[i].numPorts = 6;
2066                 break;
2067         case PCI_DEVICE_ID_RP4M:
2068                 max_num_aiops = 1;
2069                 ports_per_aiop = 4;
2070                 str = "4-port";
2071                 if ((class_rev & 0xFF) == 1) {
2072                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2073                         rocketModel[i].loadrm2 = 1;
2074                 } else {
2075                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2076                 }
2077
2078                 rocketModel[i].model = MODEL_RP4M;
2079                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2080                 rocketModel[i].numPorts = 4;
2081                 break;
2082         default:
2083                 str = "(unknown/unsupported)";
2084                 max_num_aiops = 0;
2085                 break;
2086         }
2087
2088         /*
2089          * Check for UPCI boards.
2090          */
2091
2092         switch (dev->device) {
2093         case PCI_DEVICE_ID_URP32INTF:
2094         case PCI_DEVICE_ID_URP8INTF:
2095         case PCI_DEVICE_ID_URP16INTF:
2096         case PCI_DEVICE_ID_CRP16INTF:
2097         case PCI_DEVICE_ID_URP8OCTA:
2098                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2099                 ConfigIO = pci_resource_start(dev, 1);
2100                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2101                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2102
2103                         /*
2104                          * Check for octa or quad cable.
2105                          */
2106                         if (!
2107                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2108                              PCI_GPIO_CTRL_8PORT)) {
2109                                 str = "Quadcable";
2110                                 ports_per_aiop = 4;
2111                                 rocketModel[i].numPorts = 4;
2112                         }
2113                 }
2114                 break;
2115         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2116                 str = "8 ports";
2117                 max_num_aiops = 1;
2118                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2119                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2120                 rocketModel[i].numPorts = 8;
2121                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2122                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2123                 ConfigIO = pci_resource_start(dev, 1);
2124                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2125                 break;
2126         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2127                 str = "4 ports";
2128                 max_num_aiops = 1;
2129                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2130                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2131                 rocketModel[i].numPorts = 4;
2132                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2133                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2134                 ConfigIO = pci_resource_start(dev, 1);
2135                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2136                 break;
2137         default:
2138                 break;
2139         }
2140
2141         switch (rcktpt_type[i]) {
2142         case ROCKET_TYPE_MODEM:
2143                 board_type = "RocketModem";
2144                 break;
2145         case ROCKET_TYPE_MODEMII:
2146                 board_type = "RocketModem II";
2147                 break;
2148         case ROCKET_TYPE_MODEMIII:
2149                 board_type = "RocketModem III";
2150                 break;
2151         default:
2152                 board_type = "RocketPort";
2153                 break;
2154         }
2155
2156         if (fast_clock) {
2157                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2158                 rp_baud_base[i] = 921600;
2159         } else {
2160                 /*
2161                  * If support_low_speed is set, use the slow clock
2162                  * prescale, which supports 50 bps
2163                  */
2164                 if (support_low_speed) {
2165                         /* mod 9 (divide by 10) prescale */
2166                         sClockPrescale = 0x19;
2167                         rp_baud_base[i] = 230400;
2168                 } else {
2169                         /* mod 4 (devide by 5) prescale */
2170                         sClockPrescale = 0x14;
2171                         rp_baud_base[i] = 460800;
2172                 }
2173         }
2174
2175         for (aiop = 0; aiop < max_num_aiops; aiop++)
2176                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2177         ctlp = sCtlNumToCtlPtr(i);
2178         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2179         for (aiop = 0; aiop < max_num_aiops; aiop++)
2180                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2181
2182         printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2183              "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2184              rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2185         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2186                rocketModel[i].modelString,
2187                rocketModel[i].startingPortNumber,
2188                rocketModel[i].startingPortNumber +
2189                rocketModel[i].numPorts - 1);
2190
2191         if (num_aiops <= 0) {
2192                 rcktpt_io_addr[i] = 0;
2193                 return (0);
2194         }
2195         is_PCI[i] = 1;
2196
2197         /*  Reset the AIOPIC, init the serial ports */
2198         for (aiop = 0; aiop < num_aiops; aiop++) {
2199                 sResetAiopByNum(ctlp, aiop);
2200                 num_chan = ports_per_aiop;
2201                 for (chan = 0; chan < num_chan; chan++)
2202                         init_r_port(i, aiop, chan, dev);
2203         }
2204
2205         /*  Rocket modems must be reset */
2206         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2207             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2208             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2209                 num_chan = ports_per_aiop;
2210                 for (chan = 0; chan < num_chan; chan++)
2211                         sPCIModemReset(ctlp, chan, 1);
2212                 mdelay(500);
2213                 for (chan = 0; chan < num_chan; chan++)
2214                         sPCIModemReset(ctlp, chan, 0);
2215                 mdelay(500);
2216                 rmSpeakerReset(ctlp, rocketModel[i].model);
2217         }
2218         return (1);
2219 }
2220
2221 /*
2222  *  Probes for PCI cards, inits them if found
2223  *  Input:   board_found = number of ISA boards already found, or the
2224  *           starting board number
2225  *  Returns: Number of PCI boards found
2226  */
2227 static int __init init_PCI(int boards_found)
2228 {
2229         struct pci_dev *dev = NULL;
2230         int count = 0;
2231
2232         /*  Work through the PCI device list, pulling out ours */
2233         while ((dev = pci_find_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2234                 if (register_PCI(count + boards_found, dev))
2235                         count++;
2236         }
2237         return (count);
2238 }
2239
2240 #endif                          /* CONFIG_PCI */
2241
2242 /*
2243  *  Probes for ISA cards
2244  *  Input:   i = the board number to look for
2245  *  Returns: 1 if board found, 0 else
2246  */
2247 static int __init init_ISA(int i)
2248 {
2249         int num_aiops, num_chan = 0, total_num_chan = 0;
2250         int aiop, chan;
2251         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2252         CONTROLLER_t *ctlp;
2253         char *type_string;
2254
2255         /*  If io_addr is zero, no board configured */
2256         if (rcktpt_io_addr[i] == 0)
2257                 return (0);
2258
2259         /*  Reserve the IO region */
2260         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2261                 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2262                 rcktpt_io_addr[i] = 0;
2263                 return (0);
2264         }
2265
2266         ctlp = sCtlNumToCtlPtr(i);
2267
2268         ctlp->boardType = rcktpt_type[i];
2269
2270         switch (rcktpt_type[i]) {
2271         case ROCKET_TYPE_PC104:
2272                 type_string = "(PC104)";
2273                 break;
2274         case ROCKET_TYPE_MODEM:
2275                 type_string = "(RocketModem)";
2276                 break;
2277         case ROCKET_TYPE_MODEMII:
2278                 type_string = "(RocketModem II)";
2279                 break;
2280         default:
2281                 type_string = "";
2282                 break;
2283         }
2284
2285         /*
2286          * If support_low_speed is set, use the slow clock prescale,
2287          * which supports 50 bps
2288          */
2289         if (support_low_speed) {
2290                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2291                 rp_baud_base[i] = 230400;
2292         } else {
2293                 sClockPrescale = 0x14;  /* mod 4 (devide by 5) prescale */
2294                 rp_baud_base[i] = 460800;
2295         }
2296
2297         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2298                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2299
2300         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2301
2302         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2303                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2304                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2305         }
2306
2307         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2308         if (num_aiops <= 0) {
2309                 release_region(rcktpt_io_addr[i], 64);
2310                 rcktpt_io_addr[i] = 0;
2311                 return (0);
2312         }
2313
2314         rocketModel[i].startingPortNumber = nextLineNumber;
2315
2316         for (aiop = 0; aiop < num_aiops; aiop++) {
2317                 sResetAiopByNum(ctlp, aiop);
2318                 sEnAiop(ctlp, aiop);
2319                 num_chan = sGetAiopNumChan(ctlp, aiop);
2320                 total_num_chan += num_chan;
2321                 for (chan = 0; chan < num_chan; chan++)
2322                         init_r_port(i, aiop, chan, NULL);
2323         }
2324         is_PCI[i] = 0;
2325         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2326                 num_chan = sGetAiopNumChan(ctlp, 0);
2327                 total_num_chan = num_chan;
2328                 for (chan = 0; chan < num_chan; chan++)
2329                         sModemReset(ctlp, chan, 1);
2330                 mdelay(500);
2331                 for (chan = 0; chan < num_chan; chan++)
2332                         sModemReset(ctlp, chan, 0);
2333                 mdelay(500);
2334                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2335         } else {
2336                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2337         }
2338         rocketModel[i].numPorts = total_num_chan;
2339         rocketModel[i].model = MODEL_ISA;
2340
2341         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2342                i, rcktpt_io_addr[i], num_aiops, type_string);
2343
2344         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2345                rocketModel[i].modelString,
2346                rocketModel[i].startingPortNumber,
2347                rocketModel[i].startingPortNumber +
2348                rocketModel[i].numPorts - 1);
2349
2350         return (1);
2351 }
2352
2353 static struct tty_operations rocket_ops = {
2354         .open = rp_open,
2355         .close = rp_close,
2356         .write = rp_write,
2357         .put_char = rp_put_char,
2358         .write_room = rp_write_room,
2359         .chars_in_buffer = rp_chars_in_buffer,
2360         .flush_buffer = rp_flush_buffer,
2361         .ioctl = rp_ioctl,
2362         .throttle = rp_throttle,
2363         .unthrottle = rp_unthrottle,
2364         .set_termios = rp_set_termios,
2365         .stop = rp_stop,
2366         .start = rp_start,
2367         .hangup = rp_hangup,
2368         .break_ctl = rp_break,
2369         .send_xchar = rp_send_xchar,
2370         .wait_until_sent = rp_wait_until_sent,
2371         .tiocmget = rp_tiocmget,
2372         .tiocmset = rp_tiocmset,
2373 };
2374
2375 /*
2376  * The module "startup" routine; it's run when the module is loaded.
2377  */
2378 static int __init rp_init(void)
2379 {
2380         int retval, pci_boards_found, isa_boards_found, i;
2381
2382         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2383                ROCKET_VERSION, ROCKET_DATE);
2384
2385         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2386         if (!rocket_driver)
2387                 return -ENOMEM;
2388
2389         /*
2390          * Set up the timer channel.
2391          */
2392         init_timer(&rocket_timer);
2393         rocket_timer.function = rp_do_poll;
2394
2395         /*
2396          * Initialize the array of pointers to our own internal state
2397          * structures.
2398          */
2399         memset(rp_table, 0, sizeof (rp_table));
2400         memset(xmit_flags, 0, sizeof (xmit_flags));
2401
2402         for (i = 0; i < MAX_RP_PORTS; i++)
2403                 lineNumbers[i] = 0;
2404         nextLineNumber = 0;
2405         memset(rocketModel, 0, sizeof (rocketModel));
2406
2407         /*
2408          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is
2409          *  zero, use the default controller IO address of board1 + 0x40.
2410          */
2411         if (board1) {
2412                 if (controller == 0)
2413                         controller = board1 + 0x40;
2414         } else {
2415                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2416         }
2417
2418         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2419         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2420                 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx.  Driver exiting \n", controller);
2421                 return -EBUSY;
2422         }
2423
2424         /*  Store ISA variable retrieved from command line or .conf file. */
2425         rcktpt_io_addr[0] = board1;
2426         rcktpt_io_addr[1] = board2;
2427         rcktpt_io_addr[2] = board3;
2428         rcktpt_io_addr[3] = board4;
2429
2430         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2431         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2432         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2433         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2434         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2435         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2436         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2437         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2438
2439         /*
2440          * Set up the tty driver structure and then register this
2441          * driver with the tty layer.
2442          */
2443
2444         rocket_driver->owner = THIS_MODULE;
2445         rocket_driver->flags = TTY_DRIVER_NO_DEVFS;
2446         rocket_driver->devfs_name = "tts/R";
2447         rocket_driver->name = "ttyR";
2448         rocket_driver->driver_name = "Comtrol RocketPort";
2449         rocket_driver->major = TTY_ROCKET_MAJOR;
2450         rocket_driver->minor_start = 0;
2451         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2452         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2453         rocket_driver->init_termios = tty_std_termios;
2454         rocket_driver->init_termios.c_cflag =
2455             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2456 #ifdef ROCKET_SOFT_FLOW
2457         rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
2458 #endif
2459         tty_set_operations(rocket_driver, &rocket_ops);
2460
2461         retval = tty_register_driver(rocket_driver);
2462         if (retval < 0) {
2463                 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2464                 put_tty_driver(rocket_driver);
2465                 return -1;
2466         }
2467
2468 #ifdef ROCKET_DEBUG_OPEN
2469         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2470 #endif
2471
2472         /*
2473          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2474          *  will be initialized here.
2475          */
2476         isa_boards_found = 0;
2477         pci_boards_found = 0;
2478
2479         for (i = 0; i < NUM_BOARDS; i++) {
2480                 if (init_ISA(i))
2481                         isa_boards_found++;
2482         }
2483
2484 #ifdef CONFIG_PCI
2485         if (isa_boards_found < NUM_BOARDS)
2486                 pci_boards_found = init_PCI(isa_boards_found);
2487 #endif
2488
2489         max_board = pci_boards_found + isa_boards_found;
2490
2491         if (max_board == 0) {
2492                 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2493                 del_timer_sync(&rocket_timer);
2494                 tty_unregister_driver(rocket_driver);
2495                 put_tty_driver(rocket_driver);
2496                 return -ENXIO;
2497         }
2498
2499         return 0;
2500 }
2501
2502
2503 static void rp_cleanup_module(void)
2504 {
2505         int retval;
2506         int i;
2507
2508         del_timer_sync(&rocket_timer);
2509
2510         retval = tty_unregister_driver(rocket_driver);
2511         if (retval)
2512                 printk(KERN_INFO "Error %d while trying to unregister "
2513                        "rocketport driver\n", -retval);
2514         put_tty_driver(rocket_driver);
2515
2516         for (i = 0; i < MAX_RP_PORTS; i++)
2517                 kfree(rp_table[i]);
2518
2519         for (i = 0; i < NUM_BOARDS; i++) {
2520                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2521                         continue;
2522                 release_region(rcktpt_io_addr[i], 64);
2523         }
2524         if (controller)
2525                 release_region(controller, 4);
2526 }
2527
2528 /***************************************************************************
2529 Function: sInitController
2530 Purpose:  Initialization of controller global registers and controller
2531           structure.
2532 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2533                           IRQNum,Frequency,PeriodicOnly)
2534           CONTROLLER_T *CtlP; Ptr to controller structure
2535           int CtlNum; Controller number
2536           ByteIO_t MudbacIO; Mudbac base I/O address.
2537           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2538              This list must be in the order the AIOPs will be found on the
2539              controller.  Once an AIOP in the list is not found, it is
2540              assumed that there are no more AIOPs on the controller.
2541           int AiopIOListSize; Number of addresses in AiopIOList
2542           int IRQNum; Interrupt Request number.  Can be any of the following:
2543                          0: Disable global interrupts
2544                          3: IRQ 3
2545                          4: IRQ 4
2546                          5: IRQ 5
2547                          9: IRQ 9
2548                          10: IRQ 10
2549                          11: IRQ 11
2550                          12: IRQ 12
2551                          15: IRQ 15
2552           Byte_t Frequency: A flag identifying the frequency
2553                    of the periodic interrupt, can be any one of the following:
2554                       FREQ_DIS - periodic interrupt disabled
2555                       FREQ_137HZ - 137 Hertz
2556                       FREQ_69HZ - 69 Hertz
2557                       FREQ_34HZ - 34 Hertz
2558                       FREQ_17HZ - 17 Hertz
2559                       FREQ_9HZ - 9 Hertz
2560                       FREQ_4HZ - 4 Hertz
2561                    If IRQNum is set to 0 the Frequency parameter is
2562                    overidden, it is forced to a value of FREQ_DIS.
2563           int PeriodicOnly: 1 if all interrupts except the periodic
2564                                interrupt are to be blocked.
2565                             0 is both the periodic interrupt and
2566                                other channel interrupts are allowed.
2567                             If IRQNum is set to 0 the PeriodicOnly parameter is
2568                                overidden, it is forced to a value of 0.
2569 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2570                initialization failed.
2571
2572 Comments:
2573           If periodic interrupts are to be disabled but AIOP interrupts
2574           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2575
2576           If interrupts are to be completely disabled set IRQNum to 0.
2577
2578           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2579           invalid combination.
2580
2581           This function performs initialization of global interrupt modes,
2582           but it does not actually enable global interrupts.  To enable
2583           and disable global interrupts use functions sEnGlobalInt() and
2584           sDisGlobalInt().  Enabling of global interrupts is normally not
2585           done until all other initializations are complete.
2586
2587           Even if interrupts are globally enabled, they must also be
2588           individually enabled for each channel that is to generate
2589           interrupts.
2590
2591 Warnings: No range checking on any of the parameters is done.
2592
2593           No context switches are allowed while executing this function.
2594
2595           After this function all AIOPs on the controller are disabled,
2596           they can be enabled with sEnAiop().
2597 */
2598 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2599                            ByteIO_t * AiopIOList, int AiopIOListSize,
2600                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2601 {
2602         int i;
2603         ByteIO_t io;
2604         int done;
2605
2606         CtlP->AiopIntrBits = aiop_intr_bits;
2607         CtlP->AltChanRingIndicator = 0;
2608         CtlP->CtlNum = CtlNum;
2609         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2610         CtlP->BusType = isISA;
2611         CtlP->MBaseIO = MudbacIO;
2612         CtlP->MReg1IO = MudbacIO + 1;
2613         CtlP->MReg2IO = MudbacIO + 2;
2614         CtlP->MReg3IO = MudbacIO + 3;
2615 #if 1
2616         CtlP->MReg2 = 0;        /* interrupt disable */
2617         CtlP->MReg3 = 0;        /* no periodic interrupts */
2618 #else
2619         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2620                 CtlP->MReg2 = 0;        /* interrupt disable */
2621                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2622         } else {
2623                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2624                 CtlP->MReg3 = Frequency;        /* set frequency */
2625                 if (PeriodicOnly) {     /* periodic interrupt only */
2626                         CtlP->MReg3 |= PERIODIC_ONLY;
2627                 }
2628         }
2629 #endif
2630         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2631         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2632         sControllerEOI(CtlP);   /* clear EOI if warm init */
2633         /* Init AIOPs */
2634         CtlP->NumAiop = 0;
2635         for (i = done = 0; i < AiopIOListSize; i++) {
2636                 io = AiopIOList[i];
2637                 CtlP->AiopIO[i] = (WordIO_t) io;
2638                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2639                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2640                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2641                 if (done)
2642                         continue;
2643                 sEnAiop(CtlP, i);       /* enable the AIOP */
2644                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2645                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2646                         done = 1;       /* done looking for AIOPs */
2647                 else {
2648                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2649                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2650                         sOutB(io + _INDX_DATA, sClockPrescale);
2651                         CtlP->NumAiop++;        /* bump count of AIOPs */
2652                 }
2653                 sDisAiop(CtlP, i);      /* disable AIOP */
2654         }
2655
2656         if (CtlP->NumAiop == 0)
2657                 return (-1);
2658         else
2659                 return (CtlP->NumAiop);
2660 }
2661
2662 /***************************************************************************
2663 Function: sPCIInitController
2664 Purpose:  Initialization of controller global registers and controller
2665           structure.
2666 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2667                           IRQNum,Frequency,PeriodicOnly)
2668           CONTROLLER_T *CtlP; Ptr to controller structure
2669           int CtlNum; Controller number
2670           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2671              This list must be in the order the AIOPs will be found on the
2672              controller.  Once an AIOP in the list is not found, it is
2673              assumed that there are no more AIOPs on the controller.
2674           int AiopIOListSize; Number of addresses in AiopIOList
2675           int IRQNum; Interrupt Request number.  Can be any of the following:
2676                          0: Disable global interrupts
2677                          3: IRQ 3
2678                          4: IRQ 4
2679                          5: IRQ 5
2680                          9: IRQ 9
2681                          10: IRQ 10
2682                          11: IRQ 11
2683                          12: IRQ 12
2684                          15: IRQ 15
2685           Byte_t Frequency: A flag identifying the frequency
2686                    of the periodic interrupt, can be any one of the following:
2687                       FREQ_DIS - periodic interrupt disabled
2688                       FREQ_137HZ - 137 Hertz
2689                       FREQ_69HZ - 69 Hertz
2690                       FREQ_34HZ - 34 Hertz
2691                       FREQ_17HZ - 17 Hertz
2692                       FREQ_9HZ - 9 Hertz
2693                       FREQ_4HZ - 4 Hertz
2694                    If IRQNum is set to 0 the Frequency parameter is
2695                    overidden, it is forced to a value of FREQ_DIS.
2696           int PeriodicOnly: 1 if all interrupts except the periodic
2697                                interrupt are to be blocked.
2698                             0 is both the periodic interrupt and
2699                                other channel interrupts are allowed.
2700                             If IRQNum is set to 0 the PeriodicOnly parameter is
2701                                overidden, it is forced to a value of 0.
2702 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2703                initialization failed.
2704
2705 Comments:
2706           If periodic interrupts are to be disabled but AIOP interrupts
2707           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2708
2709           If interrupts are to be completely disabled set IRQNum to 0.
2710
2711           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2712           invalid combination.
2713
2714           This function performs initialization of global interrupt modes,
2715           but it does not actually enable global interrupts.  To enable
2716           and disable global interrupts use functions sEnGlobalInt() and
2717           sDisGlobalInt().  Enabling of global interrupts is normally not
2718           done until all other initializations are complete.
2719
2720           Even if interrupts are globally enabled, they must also be
2721           individually enabled for each channel that is to generate
2722           interrupts.
2723
2724 Warnings: No range checking on any of the parameters is done.
2725
2726           No context switches are allowed while executing this function.
2727
2728           After this function all AIOPs on the controller are disabled,
2729           they can be enabled with sEnAiop().
2730 */
2731 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2732                               ByteIO_t * AiopIOList, int AiopIOListSize,
2733                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2734                               int PeriodicOnly, int altChanRingIndicator,
2735                               int UPCIRingInd)
2736 {
2737         int i;
2738         ByteIO_t io;
2739
2740         CtlP->AltChanRingIndicator = altChanRingIndicator;
2741         CtlP->UPCIRingInd = UPCIRingInd;
2742         CtlP->CtlNum = CtlNum;
2743         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2744         CtlP->BusType = isPCI;  /* controller release 1 */
2745
2746         if (ConfigIO) {
2747                 CtlP->isUPCI = 1;
2748                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2749                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2750                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2751         } else {
2752                 CtlP->isUPCI = 0;
2753                 CtlP->PCIIO =
2754                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2755                 CtlP->AiopIntrBits = aiop_intr_bits;
2756         }
2757
2758         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
2759         /* Init AIOPs */
2760         CtlP->NumAiop = 0;
2761         for (i = 0; i < AiopIOListSize; i++) {
2762                 io = AiopIOList[i];
2763                 CtlP->AiopIO[i] = (WordIO_t) io;
2764                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2765
2766                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2767                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2768                         break;  /* done looking for AIOPs */
2769
2770                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2771                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2772                 sOutB(io + _INDX_DATA, sClockPrescale);
2773                 CtlP->NumAiop++;        /* bump count of AIOPs */
2774         }
2775
2776         if (CtlP->NumAiop == 0)
2777                 return (-1);
2778         else
2779                 return (CtlP->NumAiop);
2780 }
2781
2782 /***************************************************************************
2783 Function: sReadAiopID
2784 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2785 Call:     sReadAiopID(io)
2786           ByteIO_t io: AIOP base I/O address
2787 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2788                  is replace by an identifying number.
2789           Flag AIOPID_NULL if no valid AIOP is found
2790 Warnings: No context switches are allowed while executing this function.
2791
2792 */
2793 static int sReadAiopID(ByteIO_t io)
2794 {
2795         Byte_t AiopID;          /* ID byte from AIOP */
2796
2797         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2798         sOutB(io + _CMD_REG, 0x0);
2799         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2800         if (AiopID == 0x06)
2801                 return (1);
2802         else                    /* AIOP does not exist */
2803                 return (-1);
2804 }
2805
2806 /***************************************************************************
2807 Function: sReadAiopNumChan
2808 Purpose:  Read the number of channels available in an AIOP directly from
2809           an AIOP.
2810 Call:     sReadAiopNumChan(io)
2811           WordIO_t io: AIOP base I/O address
2812 Return:   int: The number of channels available
2813 Comments: The number of channels is determined by write/reads from identical
2814           offsets within the SRAM address spaces for channels 0 and 4.
2815           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2816           AIOP, otherwise it is an 8 channel.
2817 Warnings: No context switches are allowed while executing this function.
2818 */
2819 static int sReadAiopNumChan(WordIO_t io)
2820 {
2821         Word_t x;
2822         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2823
2824         /* write to chan 0 SRAM */
2825         sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2826         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2827         x = sInW(io + _INDX_DATA);
2828         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2829         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2830                 return (8);
2831         else
2832                 return (4);
2833 }
2834
2835 /***************************************************************************
2836 Function: sInitChan
2837 Purpose:  Initialization of a channel and channel structure
2838 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2839           CONTROLLER_T *CtlP; Ptr to controller structure
2840           CHANNEL_T *ChP; Ptr to channel structure
2841           int AiopNum; AIOP number within controller
2842           int ChanNum; Channel number within AIOP
2843 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2844                number exceeds number of channels available in AIOP.
2845 Comments: This function must be called before a channel can be used.
2846 Warnings: No range checking on any of the parameters is done.
2847
2848           No context switches are allowed while executing this function.
2849 */
2850 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2851                      int ChanNum)
2852 {
2853         int i;
2854         WordIO_t AiopIO;
2855         WordIO_t ChIOOff;
2856         Byte_t *ChR;
2857         Word_t ChOff;
2858         static Byte_t R[4];
2859         int brd9600;
2860
2861         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2862                 return 0;       /* exceeds num chans in AIOP */
2863
2864         /* Channel, AIOP, and controller identifiers */
2865         ChP->CtlP = CtlP;
2866         ChP->ChanID = CtlP->AiopID[AiopNum];
2867         ChP->AiopNum = AiopNum;
2868         ChP->ChanNum = ChanNum;
2869
2870         /* Global direct addresses */
2871         AiopIO = CtlP->AiopIO[AiopNum];
2872         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2873         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2874         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2875         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2876         ChP->IndexData = AiopIO + _INDX_DATA;
2877
2878         /* Channel direct addresses */
2879         ChIOOff = AiopIO + ChP->ChanNum * 2;
2880         ChP->TxRxData = ChIOOff + _TD0;
2881         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2882         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2883         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2884
2885         /* Initialize the channel from the RData array */
2886         for (i = 0; i < RDATASIZE; i += 4) {
2887                 R[0] = RData[i];
2888                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2889                 R[2] = RData[i + 2];
2890                 R[3] = RData[i + 3];
2891                 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2892         }
2893
2894         ChR = ChP->R;
2895         for (i = 0; i < RREGDATASIZE; i += 4) {
2896                 ChR[i] = RRegData[i];
2897                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2898                 ChR[i + 2] = RRegData[i + 2];
2899                 ChR[i + 3] = RRegData[i + 3];
2900         }
2901
2902         /* Indexed registers */
2903         ChOff = (Word_t) ChanNum *0x1000;
2904
2905         if (sClockPrescale == 0x14)
2906                 brd9600 = 47;
2907         else
2908                 brd9600 = 23;
2909
2910         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2911         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2912         ChP->BaudDiv[2] = (Byte_t) brd9600;
2913         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2914         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2915
2916         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2917         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2918         ChP->TxControl[2] = 0;
2919         ChP->TxControl[3] = 0;
2920         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2921
2922         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2923         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2924         ChP->RxControl[2] = 0;
2925         ChP->RxControl[3] = 0;
2926         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2927
2928         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2929         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2930         ChP->TxEnables[2] = 0;
2931         ChP->TxEnables[3] = 0;
2932         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2933
2934         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2935         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2936         ChP->TxCompare[2] = 0;
2937         ChP->TxCompare[3] = 0;
2938         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2939
2940         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2941         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2942         ChP->TxReplace1[2] = 0;
2943         ChP->TxReplace1[3] = 0;
2944         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2945
2946         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2947         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2948         ChP->TxReplace2[2] = 0;
2949         ChP->TxReplace2[3] = 0;
2950         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2951
2952         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2953         ChP->TxFIFO = ChOff + _TX_FIFO;
2954
2955         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2956         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2957         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2958         sOutW(ChP->IndexData, 0);
2959         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2960         ChP->RxFIFO = ChOff + _RX_FIFO;
2961
2962         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2963         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2964         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2965         sOutW(ChP->IndexData, 0);
2966         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2967         sOutW(ChP->IndexData, 0);
2968         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2969         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2970         sOutB(ChP->IndexData, 0);
2971         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2972         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2973         sOutB(ChP->IndexData, 0);
2974         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2975         sEnRxProcessor(ChP);    /* start the Rx processor */
2976
2977         return 1;
2978 }
2979
2980 /***************************************************************************
2981 Function: sStopRxProcessor
2982 Purpose:  Stop the receive processor from processing a channel.
2983 Call:     sStopRxProcessor(ChP)
2984           CHANNEL_T *ChP; Ptr to channel structure
2985
2986 Comments: The receive processor can be started again with sStartRxProcessor().
2987           This function causes the receive processor to skip over the
2988           stopped channel.  It does not stop it from processing other channels.
2989
2990 Warnings: No context switches are allowed while executing this function.
2991
2992           Do not leave the receive processor stopped for more than one
2993           character time.
2994
2995           After calling this function a delay of 4 uS is required to ensure
2996           that the receive processor is no longer processing this channel.
2997 */
2998 static void sStopRxProcessor(CHANNEL_T * ChP)
2999 {
3000         Byte_t R[4];
3001
3002         R[0] = ChP->R[0];
3003         R[1] = ChP->R[1];
3004         R[2] = 0x0a;
3005         R[3] = ChP->R[3];
3006         sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
3007 }
3008
3009 /***************************************************************************
3010 Function: sFlushRxFIFO
3011 Purpose:  Flush the Rx FIFO
3012 Call:     sFlushRxFIFO(ChP)
3013           CHANNEL_T *ChP; Ptr to channel structure
3014 Return:   void
3015 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3016           while it is being flushed the receive processor is stopped
3017           and the transmitter is disabled.  After these operations a
3018           4 uS delay is done before clearing the pointers to allow
3019           the receive processor to stop.  These items are handled inside
3020           this function.
3021 Warnings: No context switches are allowed while executing this function.
3022 */
3023 static void sFlushRxFIFO(CHANNEL_T * ChP)
3024 {
3025         int i;
3026         Byte_t Ch;              /* channel number within AIOP */
3027         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
3028
3029         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
3030                 return;         /* don't need to flush */
3031
3032         RxFIFOEnabled = 0;
3033         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
3034                 RxFIFOEnabled = 1;
3035                 sDisRxFIFO(ChP);        /* disable it */
3036                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
3037                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
3038         }
3039         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
3040         Ch = (Byte_t) sGetChanNum(ChP);
3041         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
3042         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
3043         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
3044         sOutW(ChP->IndexData, 0);
3045         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
3046         sOutW(ChP->IndexData, 0);
3047         if (RxFIFOEnabled)
3048                 sEnRxFIFO(ChP); /* enable Rx FIFO */
3049 }
3050
3051 /***************************************************************************
3052 Function: sFlushTxFIFO
3053 Purpose:  Flush the Tx FIFO
3054 Call:     sFlushTxFIFO(ChP)
3055           CHANNEL_T *ChP; Ptr to channel structure
3056 Return:   void
3057 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3058           while it is being flushed the receive processor is stopped
3059           and the transmitter is disabled.  After these operations a
3060           4 uS delay is done before clearing the pointers to allow
3061           the receive processor to stop.  These items are handled inside
3062           this function.
3063 Warnings: No context switches are allowed while executing this function.
3064 */
3065 static void sFlushTxFIFO(CHANNEL_T * ChP)
3066 {
3067         int i;
3068         Byte_t Ch;              /* channel number within AIOP */
3069         int TxEnabled;          /* 1 if transmitter enabled */
3070
3071         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
3072                 return;         /* don't need to flush */
3073
3074         TxEnabled = 0;
3075         if (ChP->TxControl[3] & TX_ENABLE) {
3076                 TxEnabled = 1;
3077                 sDisTransmit(ChP);      /* disable transmitter */
3078         }
3079         sStopRxProcessor(ChP);  /* stop Rx processor */
3080         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
3081                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
3082         Ch = (Byte_t) sGetChanNum(ChP);
3083         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
3084         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
3085         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
3086         sOutW(ChP->IndexData, 0);
3087         if (TxEnabled)
3088                 sEnTransmit(ChP);       /* enable transmitter */
3089         sStartRxProcessor(ChP); /* restart Rx processor */
3090 }
3091
3092 /***************************************************************************
3093 Function: sWriteTxPrioByte
3094 Purpose:  Write a byte of priority transmit data to a channel
3095 Call:     sWriteTxPrioByte(ChP,Data)
3096           CHANNEL_T *ChP; Ptr to channel structure
3097           Byte_t Data; The transmit data byte
3098
3099 Return:   int: 1 if the bytes is successfully written, otherwise 0.
3100
3101 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3102
3103 Warnings: No context switches are allowed while executing this function.
3104 */
3105 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3106 {
3107         Byte_t DWBuf[4];        /* buffer for double word writes */
3108         Word_t *WordPtr;        /* must be far because Win SS != DS */
3109         register DWordIO_t IndexAddr;
3110
3111         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
3112                 IndexAddr = ChP->IndexAddr;
3113                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
3114                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3115                         return (0);     /* nothing sent */
3116
3117                 WordPtr = (Word_t *) (&DWBuf[0]);
3118                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
3119
3120                 DWBuf[2] = Data;        /* data byte value */
3121                 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0])));  /* write it out */
3122
3123                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
3124
3125                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3126                 DWBuf[3] = 0;   /* priority buffer pointer */
3127                 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0])));  /* write it out */
3128         } else {                /* write it to Tx FIFO */
3129
3130                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3131         }
3132         return (1);             /* 1 byte sent */
3133 }
3134
3135 /***************************************************************************
3136 Function: sEnInterrupts
3137 Purpose:  Enable one or more interrupts for a channel
3138 Call:     sEnInterrupts(ChP,Flags)
3139           CHANNEL_T *ChP; Ptr to channel structure
3140           Word_t Flags: Interrupt enable flags, can be any combination
3141              of the following flags:
3142                 TXINT_EN:   Interrupt on Tx FIFO empty
3143                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3144                             sSetRxTrigger())
3145                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3146                 MCINT_EN:   Interrupt on modem input change
3147                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3148                             Interrupt Channel Register.
3149 Return:   void
3150 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3151           enabled.  If an interrupt enable flag is not set in Flags, that
3152           interrupt will not be changed.  Interrupts can be disabled with
3153           function sDisInterrupts().
3154
3155           This function sets the appropriate bit for the channel in the AIOP's
3156           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3157           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3158
3159           Interrupts must also be globally enabled before channel interrupts
3160           will be passed on to the host.  This is done with function
3161           sEnGlobalInt().
3162
3163           In some cases it may be desirable to disable interrupts globally but
3164           enable channel interrupts.  This would allow the global interrupt
3165           status register to be used to determine which AIOPs need service.
3166 */
3167 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3168 {
3169         Byte_t Mask;            /* Interrupt Mask Register */
3170
3171         ChP->RxControl[2] |=
3172             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3173
3174         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3175
3176         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3177
3178         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3179
3180         if (Flags & CHANINT_EN) {
3181                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3182                 sOutB(ChP->IntMask, Mask);
3183         }
3184 }
3185
3186 /***************************************************************************
3187 Function: sDisInterrupts
3188 Purpose:  Disable one or more interrupts for a channel
3189 Call:     sDisInterrupts(ChP,Flags)
3190           CHANNEL_T *ChP; Ptr to channel structure
3191           Word_t Flags: Interrupt flags, can be any combination
3192              of the following flags:
3193                 TXINT_EN:   Interrupt on Tx FIFO empty
3194                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3195                             sSetRxTrigger())
3196                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3197                 MCINT_EN:   Interrupt on modem input change
3198                 CHANINT_EN: Disable channel interrupt signal to the
3199                             AIOP's Interrupt Channel Register.
3200 Return:   void
3201 Comments: If an interrupt flag is set in Flags, that interrupt will be
3202           disabled.  If an interrupt flag is not set in Flags, that
3203           interrupt will not be changed.  Interrupts can be enabled with
3204           function sEnInterrupts().
3205
3206           This function clears the appropriate bit for the channel in the AIOP's
3207           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3208           this channel's bit from being set in the AIOP's Interrupt Channel
3209           Register.
3210 */
3211 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3212 {
3213         Byte_t Mask;            /* Interrupt Mask Register */
3214
3215         ChP->RxControl[2] &=
3216             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3217         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3218         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3219         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3220
3221         if (Flags & CHANINT_EN) {
3222                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3223                 sOutB(ChP->IntMask, Mask);
3224         }
3225 }
3226
3227 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3228 {
3229         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3230 }
3231
3232 /*
3233  *  Not an official SSCI function, but how to reset RocketModems.
3234  *  ISA bus version
3235  */
3236 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3237 {
3238         ByteIO_t addr;
3239         Byte_t val;
3240
3241         addr = CtlP->AiopIO[0] + 0x400;
3242         val = sInB(CtlP->MReg3IO);
3243         /* if AIOP[1] is not enabled, enable it */
3244         if ((val & 2) == 0) {
3245                 val = sInB(CtlP->MReg2IO);
3246                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3247                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3248         }
3249
3250         sEnAiop(CtlP, 1);
3251         if (!on)
3252                 addr += 8;
3253         sOutB(addr + chan, 0);  /* apply or remove reset */
3254         sDisAiop(CtlP, 1);
3255 }
3256
3257 /*
3258  *  Not an official SSCI function, but how to reset RocketModems.
3259  *  PCI bus version
3260  */
3261 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3262 {
3263         ByteIO_t addr;
3264
3265         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3266         if (!on)
3267                 addr += 8;
3268         sOutB(addr + chan, 0);  /* apply or remove reset */
3269 }
3270
3271 /*  Resets the speaker controller on RocketModem II and III devices */
3272 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3273 {
3274         ByteIO_t addr;
3275
3276         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3277         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3278                 addr = CtlP->AiopIO[0] + 0x4F;
3279                 sOutB(addr, 0);
3280         }
3281
3282         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3283         if ((model == MODEL_UPCI_RM3_8PORT)
3284             || (model == MODEL_UPCI_RM3_4PORT)) {
3285                 addr = CtlP->AiopIO[0] + 0x88;
3286                 sOutB(addr, 0);
3287         }
3288 }
3289
3290 /*  Returns the line number given the controller (board), aiop and channel number */
3291 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3292 {
3293         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3294 }
3295
3296 /*
3297  *  Stores the line number associated with a given controller (board), aiop
3298  *  and channel number.
3299  *  Returns:  The line number assigned
3300  */
3301 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3302 {
3303         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3304         return (nextLineNumber - 1);
3305 }