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igb: Update igb Tx flags to improve code efficiency
[linux-2.6/cjktty.git] / drivers / net / ethernet / intel / igb / igb.h
blobd8fd5b63af9a86afe5ecae7971af4cdc3438856f
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28
29 /* Linux PRO/1000 Ethernet Driver main header file */
30
31 #ifndef _IGB_H_
32 #define _IGB_H_
33
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
36
37 #include <linux/clocksource.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/bitops.h>
41 #include <linux/if_vlan.h>
42
43 struct igb_adapter;
44
45 /* Interrupt defines */
46 #define IGB_START_ITR 648 /* ~6000 ints/sec */
47 #define IGB_4K_ITR 980
48 #define IGB_20K_ITR 196
49 #define IGB_70K_ITR 56
50
51 /* TX/RX descriptor defines */
52 #define IGB_DEFAULT_TXD 256
53 #define IGB_DEFAULT_TX_WORK 128
54 #define IGB_MIN_TXD 80
55 #define IGB_MAX_TXD 4096
56
57 #define IGB_DEFAULT_RXD 256
58 #define IGB_MIN_RXD 80
59 #define IGB_MAX_RXD 4096
60
61 #define IGB_DEFAULT_ITR 3 /* dynamic */
62 #define IGB_MAX_ITR_USECS 10000
63 #define IGB_MIN_ITR_USECS 10
64 #define NON_Q_VECTORS 1
65 #define MAX_Q_VECTORS 8
66
67 /* Transmit and receive queues */
68 #define IGB_MAX_RX_QUEUES 8
69 #define IGB_MAX_RX_QUEUES_82575 4
70 #define IGB_MAX_RX_QUEUES_I211 2
71 #define IGB_MAX_TX_QUEUES 8
72 #define IGB_MAX_VF_MC_ENTRIES 30
73 #define IGB_MAX_VF_FUNCTIONS 8
74 #define IGB_MAX_VFTA_ENTRIES 128
75 #define IGB_82576_VF_DEV_ID 0x10CA
76 #define IGB_I350_VF_DEV_ID 0x1520
77
78 /* NVM version defines */
79 #define IGB_MAJOR_MASK 0xF000
80 #define IGB_MINOR_MASK 0x0FF0
81 #define IGB_BUILD_MASK 0x000F
82 #define IGB_COMB_VER_MASK 0x00FF
83 #define IGB_MAJOR_SHIFT 12
84 #define IGB_MINOR_SHIFT 4
85 #define IGB_COMB_VER_SHFT 8
86 #define IGB_NVM_VER_INVALID 0xFFFF
87 #define IGB_ETRACK_SHIFT 16
88 #define NVM_ETRACK_WORD 0x0042
89 #define NVM_COMB_VER_OFF 0x0083
90 #define NVM_COMB_VER_PTR 0x003d
91
92 struct vf_data_storage {
93 unsigned char vf_mac_addresses[ETH_ALEN];
94 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
95 u16 num_vf_mc_hashes;
96 u16 vlans_enabled;
97 u32 flags;
98 unsigned long last_nack;
99 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
100 u16 pf_qos;
101 u16 tx_rate;
102 };
103
104 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
105 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
106 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
107 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
108
109 /* RX descriptor control thresholds.
110 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
111 * descriptors available in its onboard memory.
112 * Setting this to 0 disables RX descriptor prefetch.
113 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
114 * available in host memory.
115 * If PTHRESH is 0, this should also be 0.
116 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
117 * descriptors until either it has this many to write back, or the
118 * ITR timer expires.
119 */
120 #define IGB_RX_PTHRESH 8
121 #define IGB_RX_HTHRESH 8
122 #define IGB_TX_PTHRESH 8
123 #define IGB_TX_HTHRESH 1
124 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
125 adapter->msix_entries) ? 1 : 4)
126 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
127 adapter->msix_entries) ? 1 : 16)
128
129 /* this is the size past which hardware will drop packets when setting LPE=0 */
130 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
131
132 /* Supported Rx Buffer Sizes */
133 #define IGB_RXBUFFER_256 256
134 #define IGB_RXBUFFER_2048 2048
135 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256
136 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048
137
138 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
139 #define IGB_TX_QUEUE_WAKE 16
140 /* How many Rx Buffers do we bundle into one write to the hardware ? */
141 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
142
143 #define AUTO_ALL_MODES 0
144 #define IGB_EEPROM_APME 0x0400
145
146 #ifndef IGB_MASTER_SLAVE
147 /* Switch to override PHY master/slave setting */
148 #define IGB_MASTER_SLAVE e1000_ms_hw_default
149 #endif
150
151 #define IGB_MNG_VLAN_NONE -1
152
153 enum igb_tx_flags {
154 /* cmd_type flags */
155 IGB_TX_FLAGS_VLAN = 0x01,
156 IGB_TX_FLAGS_TSO = 0x02,
157 IGB_TX_FLAGS_TSTAMP = 0x04,
158
159 /* olinfo flags */
160 IGB_TX_FLAGS_IPV4 = 0x10,
161 IGB_TX_FLAGS_CSUM = 0x20,
162 };
163
164 /* VLAN info */
165 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
166 #define IGB_TX_FLAGS_VLAN_SHIFT 16
167
168 /* wrapper around a pointer to a socket buffer,
169 * so a DMA handle can be stored along with the buffer */
170 struct igb_tx_buffer {
171 union e1000_adv_tx_desc *next_to_watch;
172 unsigned long time_stamp;
173 struct sk_buff *skb;
174 unsigned int bytecount;
175 u16 gso_segs;
176 __be16 protocol;
177 DEFINE_DMA_UNMAP_ADDR(dma);
178 DEFINE_DMA_UNMAP_LEN(len);
179 u32 tx_flags;
180 };
181
182 struct igb_rx_buffer {
183 dma_addr_t dma;
184 struct page *page;
185 unsigned int page_offset;
186 };
187
188 struct igb_tx_queue_stats {
189 u64 packets;
190 u64 bytes;
191 u64 restart_queue;
192 u64 restart_queue2;
193 };
194
195 struct igb_rx_queue_stats {
196 u64 packets;
197 u64 bytes;
198 u64 drops;
199 u64 csum_err;
200 u64 alloc_failed;
201 };
202
203 struct igb_ring_container {
204 struct igb_ring *ring; /* pointer to linked list of rings */
205 unsigned int total_bytes; /* total bytes processed this int */
206 unsigned int total_packets; /* total packets processed this int */
207 u16 work_limit; /* total work allowed per interrupt */
208 u8 count; /* total number of rings in vector */
209 u8 itr; /* current ITR setting for ring */
210 };
211
212 struct igb_ring {
213 struct igb_q_vector *q_vector; /* backlink to q_vector */
214 struct net_device *netdev; /* back pointer to net_device */
215 struct device *dev; /* device pointer for dma mapping */
216 union { /* array of buffer info structs */
217 struct igb_tx_buffer *tx_buffer_info;
218 struct igb_rx_buffer *rx_buffer_info;
219 };
220 void *desc; /* descriptor ring memory */
221 unsigned long flags; /* ring specific flags */
222 void __iomem *tail; /* pointer to ring tail register */
223 dma_addr_t dma; /* phys address of the ring */
224 unsigned int size; /* length of desc. ring in bytes */
225
226 u16 count; /* number of desc. in the ring */
227 u8 queue_index; /* logical index of the ring*/
228 u8 reg_idx; /* physical index of the ring */
229
230 /* everything past this point are written often */
231 u16 next_to_clean;
232 u16 next_to_use;
233 u16 next_to_alloc;
234
235 union {
236 /* TX */
237 struct {
238 struct igb_tx_queue_stats tx_stats;
239 struct u64_stats_sync tx_syncp;
240 struct u64_stats_sync tx_syncp2;
241 };
242 /* RX */
243 struct {
244 struct sk_buff *skb;
245 struct igb_rx_queue_stats rx_stats;
246 struct u64_stats_sync rx_syncp;
247 };
248 };
249 } ____cacheline_internodealigned_in_smp;
250
251 struct igb_q_vector {
252 struct igb_adapter *adapter; /* backlink */
253 int cpu; /* CPU for DCA */
254 u32 eims_value; /* EIMS mask value */
255
256 u16 itr_val;
257 u8 set_itr;
258 void __iomem *itr_register;
259
260 struct igb_ring_container rx, tx;
261
262 struct napi_struct napi;
263 struct rcu_head rcu; /* to avoid race with update stats on free */
264 char name[IFNAMSIZ + 9];
265
266 /* for dynamic allocation of rings associated with this q_vector */
267 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
268 };
269
270 enum e1000_ring_flags_t {
271 IGB_RING_FLAG_RX_SCTP_CSUM,
272 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
273 IGB_RING_FLAG_TX_CTX_IDX,
274 IGB_RING_FLAG_TX_DETECT_HANG
275 };
276
277 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
278
279 #define IGB_RX_DESC(R, i) \
280 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
281 #define IGB_TX_DESC(R, i) \
282 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
283 #define IGB_TX_CTXTDESC(R, i) \
284 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
285
286 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
287 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
288 const u32 stat_err_bits)
289 {
290 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
291 }
292
293 /* igb_desc_unused - calculate if we have unused descriptors */
294 static inline int igb_desc_unused(struct igb_ring *ring)
295 {
296 if (ring->next_to_clean > ring->next_to_use)
297 return ring->next_to_clean - ring->next_to_use - 1;
298
299 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
300 }
301
302 /* board specific private data structure */
303 struct igb_adapter {
304 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
305
306 struct net_device *netdev;
307
308 unsigned long state;
309 unsigned int flags;
310
311 unsigned int num_q_vectors;
312 struct msix_entry *msix_entries;
313
314 /* Interrupt Throttle Rate */
315 u32 rx_itr_setting;
316 u32 tx_itr_setting;
317 u16 tx_itr;
318 u16 rx_itr;
319
320 /* TX */
321 u16 tx_work_limit;
322 u32 tx_timeout_count;
323 int num_tx_queues;
324 struct igb_ring *tx_ring[16];
325
326 /* RX */
327 int num_rx_queues;
328 struct igb_ring *rx_ring[16];
329
330 u32 max_frame_size;
331 u32 min_frame_size;
332
333 struct timer_list watchdog_timer;
334 struct timer_list phy_info_timer;
335
336 u16 mng_vlan_id;
337 u32 bd_number;
338 u32 wol;
339 u32 en_mng_pt;
340 u16 link_speed;
341 u16 link_duplex;
342
343 struct work_struct reset_task;
344 struct work_struct watchdog_task;
345 bool fc_autoneg;
346 u8 tx_timeout_factor;
347 struct timer_list blink_timer;
348 unsigned long led_status;
349
350 /* OS defined structs */
351 struct pci_dev *pdev;
352
353 spinlock_t stats64_lock;
354 struct rtnl_link_stats64 stats64;
355
356 /* structs defined in e1000_hw.h */
357 struct e1000_hw hw;
358 struct e1000_hw_stats stats;
359 struct e1000_phy_info phy_info;
360 struct e1000_phy_stats phy_stats;
361
362 u32 test_icr;
363 struct igb_ring test_tx_ring;
364 struct igb_ring test_rx_ring;
365
366 int msg_enable;
367
368 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
369 u32 eims_enable_mask;
370 u32 eims_other;
371
372 /* to not mess up cache alignment, always add to the bottom */
373 u32 eeprom_wol;
374
375 u16 tx_ring_count;
376 u16 rx_ring_count;
377 unsigned int vfs_allocated_count;
378 struct vf_data_storage *vf_data;
379 int vf_rate_link_speed;
380 u32 rss_queues;
381 u32 wvbr;
382 u32 *shadow_vfta;
383
384 struct ptp_clock *ptp_clock;
385 struct ptp_clock_info ptp_caps;
386 struct delayed_work ptp_overflow_work;
387 struct work_struct ptp_tx_work;
388 struct sk_buff *ptp_tx_skb;
389 spinlock_t tmreg_lock;
390 struct cyclecounter cc;
391 struct timecounter tc;
392
393 char fw_version[32];
394 };
395
396 #define IGB_FLAG_HAS_MSI (1 << 0)
397 #define IGB_FLAG_DCA_ENABLED (1 << 1)
398 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
399 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
400 #define IGB_FLAG_DMAC (1 << 4)
401 #define IGB_FLAG_PTP (1 << 5)
402 #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
403 #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
404
405 /* DMA Coalescing defines */
406 #define IGB_MIN_TXPBSIZE 20408
407 #define IGB_TX_BUF_4096 4096
408 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
409
410 #define IGB_82576_TSYNC_SHIFT 19
411 #define IGB_TS_HDR_LEN 16
412 enum e1000_state_t {
413 __IGB_TESTING,
414 __IGB_RESETTING,
415 __IGB_DOWN
416 };
417
418 enum igb_boards {
419 board_82575,
420 };
421
422 extern char igb_driver_name[];
423 extern char igb_driver_version[];
424
425 extern int igb_up(struct igb_adapter *);
426 extern void igb_down(struct igb_adapter *);
427 extern void igb_reinit_locked(struct igb_adapter *);
428 extern void igb_reset(struct igb_adapter *);
429 extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
430 extern int igb_setup_tx_resources(struct igb_ring *);
431 extern int igb_setup_rx_resources(struct igb_ring *);
432 extern void igb_free_tx_resources(struct igb_ring *);
433 extern void igb_free_rx_resources(struct igb_ring *);
434 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
435 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
436 extern void igb_setup_tctl(struct igb_adapter *);
437 extern void igb_setup_rctl(struct igb_adapter *);
438 extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
439 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
440 struct igb_tx_buffer *);
441 extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
442 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
443 extern bool igb_has_link(struct igb_adapter *adapter);
444 extern void igb_set_ethtool_ops(struct net_device *);
445 extern void igb_power_up_link(struct igb_adapter *);
446 extern void igb_set_fw_version(struct igb_adapter *);
447 extern void igb_ptp_init(struct igb_adapter *adapter);
448 extern void igb_ptp_stop(struct igb_adapter *adapter);
449 extern void igb_ptp_reset(struct igb_adapter *adapter);
450 extern void igb_ptp_tx_work(struct work_struct *work);
451 extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
452 extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
453 struct sk_buff *skb);
454 extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
455 unsigned char *va,
456 struct sk_buff *skb);
457 static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector,
458 union e1000_adv_rx_desc *rx_desc,
459 struct sk_buff *skb)
460 {
461 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
462 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
463 igb_ptp_rx_rgtstamp(q_vector, skb);
464 }
465
466 extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
467 struct ifreq *ifr, int cmd);
468
469 static inline s32 igb_reset_phy(struct e1000_hw *hw)
470 {
471 if (hw->phy.ops.reset)
472 return hw->phy.ops.reset(hw);
473
474 return 0;
475 }
476
477 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
478 {
479 if (hw->phy.ops.read_reg)
480 return hw->phy.ops.read_reg(hw, offset, data);
481
482 return 0;
483 }
484
485 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
486 {
487 if (hw->phy.ops.write_reg)
488 return hw->phy.ops.write_reg(hw, offset, data);
489
490 return 0;
491 }
492
493 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
494 {
495 if (hw->phy.ops.get_phy_info)
496 return hw->phy.ops.get_phy_info(hw);
497
498 return 0;
499 }
500
501 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
502 {
503 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
504 }
505
506 #endif /* _IGB_H_ */
CJK support for tty framebuffer vt