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drivers: net: Remove remaining alloc/OOM messages
[linux-2.6/cjktty.git] / drivers / net / ethernet / freescale / gianfar.c
blobab32bd0be8ff20a1792e5265c1e7ea064659a159
1 /* drivers/net/ethernet/freescale/gianfar.c
2 *
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 *
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65 #define DEBUG
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
83 #include <linux/ip.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
86 #include <linux/in.h>
87 #include <linux/net_tstamp.h>
88
89 #include <asm/io.h>
90 #include <asm/reg.h>
91 #include <asm/irq.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
99 #include <linux/of.h>
100 #include <linux/of_net.h>
101
102 #include "gianfar.h"
103
104 #define TX_TIMEOUT (1*HZ)
105
106 const char gfar_driver_version[] = "1.3";
107
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct platform_device *ofdev);
125 static int gfar_remove(struct platform_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
133 #endif
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
143 const u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
151 dma_addr_t buf)
152 {
153 u32 lstatus;
154
155 bdp->bufPtr = buf;
156
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
160
161 eieio();
162
163 bdp->lstatus = lstatus;
164 }
165
166 static int gfar_init_bds(struct net_device *ndev)
167 {
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
171 struct txbd8 *txbdp;
172 struct rxbd8 *rxbdp;
173 int i, j;
174
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
183
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
187 txbdp->lstatus = 0;
188 txbdp->bufPtr = 0;
189 txbdp++;
190 }
191
192 /* Set the last descriptor in the ring to indicate wrap */
193 txbdp--;
194 txbdp->status |= TXBD_WRAP;
195 }
196
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
202
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
205
206 if (skb) {
207 gfar_init_rxbdp(rx_queue, rxbdp,
208 rxbdp->bufPtr);
209 } else {
210 skb = gfar_new_skb(ndev);
211 if (!skb) {
212 netdev_err(ndev, "Can't allocate RX buffers\n");
213 return -ENOMEM;
214 }
215 rx_queue->rx_skbuff[j] = skb;
216
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
218 }
219
220 rxbdp++;
221 }
222
223 }
224
225 return 0;
226 }
227
228 static int gfar_alloc_skb_resources(struct net_device *ndev)
229 {
230 void *vaddr;
231 dma_addr_t addr;
232 int i, j, k;
233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = &priv->ofdev->dev;
235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
237
238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
241
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
245
246 /* Allocate memory for the buffer descriptors */
247 vaddr = dma_alloc_coherent(dev,
248 sizeof(struct txbd8) * priv->total_tx_ring_size +
249 sizeof(struct rxbd8) * priv->total_rx_ring_size,
250 &addr, GFP_KERNEL);
251 if (!vaddr) {
252 netif_err(priv, ifup, ndev,
253 "Could not allocate buffer descriptors!\n");
254 return -ENOMEM;
255 }
256
257 for (i = 0; i < priv->num_tx_queues; i++) {
258 tx_queue = priv->tx_queue[i];
259 tx_queue->tx_bd_base = vaddr;
260 tx_queue->tx_bd_dma_base = addr;
261 tx_queue->dev = ndev;
262 /* enet DMA only understands physical addresses */
263 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
264 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
265 }
266
267 /* Start the rx descriptor ring where the tx ring leaves off */
268 for (i = 0; i < priv->num_rx_queues; i++) {
269 rx_queue = priv->rx_queue[i];
270 rx_queue->rx_bd_base = vaddr;
271 rx_queue->rx_bd_dma_base = addr;
272 rx_queue->dev = ndev;
273 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
274 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
275 }
276
277 /* Setup the skbuff rings */
278 for (i = 0; i < priv->num_tx_queues; i++) {
279 tx_queue = priv->tx_queue[i];
280 tx_queue->tx_skbuff =
281 kmalloc_array(tx_queue->tx_ring_size,
282 sizeof(*tx_queue->tx_skbuff),
283 GFP_KERNEL);
284 if (!tx_queue->tx_skbuff)
285 goto cleanup;
286
287 for (k = 0; k < tx_queue->tx_ring_size; k++)
288 tx_queue->tx_skbuff[k] = NULL;
289 }
290
291 for (i = 0; i < priv->num_rx_queues; i++) {
292 rx_queue = priv->rx_queue[i];
293 rx_queue->rx_skbuff =
294 kmalloc_array(rx_queue->rx_ring_size,
295 sizeof(*rx_queue->rx_skbuff),
296 GFP_KERNEL);
297 if (!rx_queue->rx_skbuff)
298 goto cleanup;
299
300 for (j = 0; j < rx_queue->rx_ring_size; j++)
301 rx_queue->rx_skbuff[j] = NULL;
302 }
303
304 if (gfar_init_bds(ndev))
305 goto cleanup;
306
307 return 0;
308
309 cleanup:
310 free_skb_resources(priv);
311 return -ENOMEM;
312 }
313
314 static void gfar_init_tx_rx_base(struct gfar_private *priv)
315 {
316 struct gfar __iomem *regs = priv->gfargrp[0].regs;
317 u32 __iomem *baddr;
318 int i;
319
320 baddr = &regs->tbase0;
321 for (i = 0; i < priv->num_tx_queues; i++) {
322 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
323 baddr += 2;
324 }
325
326 baddr = &regs->rbase0;
327 for (i = 0; i < priv->num_rx_queues; i++) {
328 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
329 baddr += 2;
330 }
331 }
332
333 static void gfar_init_mac(struct net_device *ndev)
334 {
335 struct gfar_private *priv = netdev_priv(ndev);
336 struct gfar __iomem *regs = priv->gfargrp[0].regs;
337 u32 rctrl = 0;
338 u32 tctrl = 0;
339 u32 attrs = 0;
340
341 /* write the tx/rx base registers */
342 gfar_init_tx_rx_base(priv);
343
344 /* Configure the coalescing support */
345 gfar_configure_coalescing(priv, 0xFF, 0xFF);
346
347 if (priv->rx_filer_enable) {
348 rctrl |= RCTRL_FILREN;
349 /* Program the RIR0 reg with the required distribution */
350 gfar_write(&regs->rir0, DEFAULT_RIR0);
351 }
352
353 /* Restore PROMISC mode */
354 if (ndev->flags & IFF_PROMISC)
355 rctrl |= RCTRL_PROM;
356
357 if (ndev->features & NETIF_F_RXCSUM)
358 rctrl |= RCTRL_CHECKSUMMING;
359
360 if (priv->extended_hash) {
361 rctrl |= RCTRL_EXTHASH;
362
363 gfar_clear_exact_match(ndev);
364 rctrl |= RCTRL_EMEN;
365 }
366
367 if (priv->padding) {
368 rctrl &= ~RCTRL_PAL_MASK;
369 rctrl |= RCTRL_PADDING(priv->padding);
370 }
371
372 /* Insert receive time stamps into padding alignment bytes */
373 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
374 rctrl &= ~RCTRL_PAL_MASK;
375 rctrl |= RCTRL_PADDING(8);
376 priv->padding = 8;
377 }
378
379 /* Enable HW time stamping if requested from user space */
380 if (priv->hwts_rx_en)
381 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
382
383 if (ndev->features & NETIF_F_HW_VLAN_RX)
384 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
385
386 /* Init rctrl based on our settings */
387 gfar_write(&regs->rctrl, rctrl);
388
389 if (ndev->features & NETIF_F_IP_CSUM)
390 tctrl |= TCTRL_INIT_CSUM;
391
392 if (priv->prio_sched_en)
393 tctrl |= TCTRL_TXSCHED_PRIO;
394 else {
395 tctrl |= TCTRL_TXSCHED_WRRS;
396 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
397 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
398 }
399
400 gfar_write(&regs->tctrl, tctrl);
401
402 /* Set the extraction length and index */
403 attrs = ATTRELI_EL(priv->rx_stash_size) |
404 ATTRELI_EI(priv->rx_stash_index);
405
406 gfar_write(&regs->attreli, attrs);
407
408 /* Start with defaults, and add stashing or locking
409 * depending on the approprate variables
410 */
411 attrs = ATTR_INIT_SETTINGS;
412
413 if (priv->bd_stash_en)
414 attrs |= ATTR_BDSTASH;
415
416 if (priv->rx_stash_size != 0)
417 attrs |= ATTR_BUFSTASH;
418
419 gfar_write(&regs->attr, attrs);
420
421 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
422 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
423 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
424 }
425
426 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
427 {
428 struct gfar_private *priv = netdev_priv(dev);
429 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
430 unsigned long tx_packets = 0, tx_bytes = 0;
431 int i;
432
433 for (i = 0; i < priv->num_rx_queues; i++) {
434 rx_packets += priv->rx_queue[i]->stats.rx_packets;
435 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
436 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
437 }
438
439 dev->stats.rx_packets = rx_packets;
440 dev->stats.rx_bytes = rx_bytes;
441 dev->stats.rx_dropped = rx_dropped;
442
443 for (i = 0; i < priv->num_tx_queues; i++) {
444 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
445 tx_packets += priv->tx_queue[i]->stats.tx_packets;
446 }
447
448 dev->stats.tx_bytes = tx_bytes;
449 dev->stats.tx_packets = tx_packets;
450
451 return &dev->stats;
452 }
453
454 static const struct net_device_ops gfar_netdev_ops = {
455 .ndo_open = gfar_enet_open,
456 .ndo_start_xmit = gfar_start_xmit,
457 .ndo_stop = gfar_close,
458 .ndo_change_mtu = gfar_change_mtu,
459 .ndo_set_features = gfar_set_features,
460 .ndo_set_rx_mode = gfar_set_multi,
461 .ndo_tx_timeout = gfar_timeout,
462 .ndo_do_ioctl = gfar_ioctl,
463 .ndo_get_stats = gfar_get_stats,
464 .ndo_set_mac_address = eth_mac_addr,
465 .ndo_validate_addr = eth_validate_addr,
466 #ifdef CONFIG_NET_POLL_CONTROLLER
467 .ndo_poll_controller = gfar_netpoll,
468 #endif
469 };
470
471 void lock_rx_qs(struct gfar_private *priv)
472 {
473 int i;
474
475 for (i = 0; i < priv->num_rx_queues; i++)
476 spin_lock(&priv->rx_queue[i]->rxlock);
477 }
478
479 void lock_tx_qs(struct gfar_private *priv)
480 {
481 int i;
482
483 for (i = 0; i < priv->num_tx_queues; i++)
484 spin_lock(&priv->tx_queue[i]->txlock);
485 }
486
487 void unlock_rx_qs(struct gfar_private *priv)
488 {
489 int i;
490
491 for (i = 0; i < priv->num_rx_queues; i++)
492 spin_unlock(&priv->rx_queue[i]->rxlock);
493 }
494
495 void unlock_tx_qs(struct gfar_private *priv)
496 {
497 int i;
498
499 for (i = 0; i < priv->num_tx_queues; i++)
500 spin_unlock(&priv->tx_queue[i]->txlock);
501 }
502
503 static bool gfar_is_vlan_on(struct gfar_private *priv)
504 {
505 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
506 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
507 }
508
509 /* Returns 1 if incoming frames use an FCB */
510 static inline int gfar_uses_fcb(struct gfar_private *priv)
511 {
512 return gfar_is_vlan_on(priv) ||
513 (priv->ndev->features & NETIF_F_RXCSUM) ||
514 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
515 }
516
517 static void free_tx_pointers(struct gfar_private *priv)
518 {
519 int i;
520
521 for (i = 0; i < priv->num_tx_queues; i++)
522 kfree(priv->tx_queue[i]);
523 }
524
525 static void free_rx_pointers(struct gfar_private *priv)
526 {
527 int i;
528
529 for (i = 0; i < priv->num_rx_queues; i++)
530 kfree(priv->rx_queue[i]);
531 }
532
533 static void unmap_group_regs(struct gfar_private *priv)
534 {
535 int i;
536
537 for (i = 0; i < MAXGROUPS; i++)
538 if (priv->gfargrp[i].regs)
539 iounmap(priv->gfargrp[i].regs);
540 }
541
542 static void free_gfar_dev(struct gfar_private *priv)
543 {
544 int i, j;
545
546 for (i = 0; i < priv->num_grps; i++)
547 for (j = 0; j < GFAR_NUM_IRQS; j++) {
548 kfree(priv->gfargrp[i].irqinfo[j]);
549 priv->gfargrp[i].irqinfo[j] = NULL;
550 }
551
552 free_netdev(priv->ndev);
553 }
554
555 static void disable_napi(struct gfar_private *priv)
556 {
557 int i;
558
559 for (i = 0; i < priv->num_grps; i++)
560 napi_disable(&priv->gfargrp[i].napi);
561 }
562
563 static void enable_napi(struct gfar_private *priv)
564 {
565 int i;
566
567 for (i = 0; i < priv->num_grps; i++)
568 napi_enable(&priv->gfargrp[i].napi);
569 }
570
571 static int gfar_parse_group(struct device_node *np,
572 struct gfar_private *priv, const char *model)
573 {
574 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
575 u32 *queue_mask;
576 int i;
577
578 for (i = 0; i < GFAR_NUM_IRQS; i++) {
579 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
580 GFP_KERNEL);
581 if (!grp->irqinfo[i])
582 return -ENOMEM;
583 }
584
585 grp->regs = of_iomap(np, 0);
586 if (!grp->regs)
587 return -ENOMEM;
588
589 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
590
591 /* If we aren't the FEC we have multiple interrupts */
592 if (model && strcasecmp(model, "FEC")) {
593 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
594 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
595 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
596 gfar_irq(grp, RX)->irq == NO_IRQ ||
597 gfar_irq(grp, ER)->irq == NO_IRQ)
598 return -EINVAL;
599 }
600
601 grp->grp_id = priv->num_grps;
602 grp->priv = priv;
603 spin_lock_init(&grp->grplock);
604 if (priv->mode == MQ_MG_MODE) {
605 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
606 grp->rx_bit_map = queue_mask ?
607 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
608 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
609 grp->tx_bit_map = queue_mask ?
610 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
611 } else {
612 grp->rx_bit_map = 0xFF;
613 grp->tx_bit_map = 0xFF;
614 }
615 priv->num_grps++;
616
617 return 0;
618 }
619
620 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
621 {
622 const char *model;
623 const char *ctype;
624 const void *mac_addr;
625 int err = 0, i;
626 struct net_device *dev = NULL;
627 struct gfar_private *priv = NULL;
628 struct device_node *np = ofdev->dev.of_node;
629 struct device_node *child = NULL;
630 const u32 *stash;
631 const u32 *stash_len;
632 const u32 *stash_idx;
633 unsigned int num_tx_qs, num_rx_qs;
634 u32 *tx_queues, *rx_queues;
635
636 if (!np || !of_device_is_available(np))
637 return -ENODEV;
638
639 /* parse the num of tx and rx queues */
640 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
641 num_tx_qs = tx_queues ? *tx_queues : 1;
642
643 if (num_tx_qs > MAX_TX_QS) {
644 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
645 num_tx_qs, MAX_TX_QS);
646 pr_err("Cannot do alloc_etherdev, aborting\n");
647 return -EINVAL;
648 }
649
650 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
651 num_rx_qs = rx_queues ? *rx_queues : 1;
652
653 if (num_rx_qs > MAX_RX_QS) {
654 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
655 num_rx_qs, MAX_RX_QS);
656 pr_err("Cannot do alloc_etherdev, aborting\n");
657 return -EINVAL;
658 }
659
660 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
661 dev = *pdev;
662 if (NULL == dev)
663 return -ENOMEM;
664
665 priv = netdev_priv(dev);
666 priv->node = ofdev->dev.of_node;
667 priv->ndev = dev;
668
669 priv->num_tx_queues = num_tx_qs;
670 netif_set_real_num_rx_queues(dev, num_rx_qs);
671 priv->num_rx_queues = num_rx_qs;
672 priv->num_grps = 0x0;
673
674 /* Init Rx queue filer rule set linked list */
675 INIT_LIST_HEAD(&priv->rx_list.list);
676 priv->rx_list.count = 0;
677 mutex_init(&priv->rx_queue_access);
678
679 model = of_get_property(np, "model", NULL);
680
681 for (i = 0; i < MAXGROUPS; i++)
682 priv->gfargrp[i].regs = NULL;
683
684 /* Parse and initialize group specific information */
685 if (of_device_is_compatible(np, "fsl,etsec2")) {
686 priv->mode = MQ_MG_MODE;
687 for_each_child_of_node(np, child) {
688 err = gfar_parse_group(child, priv, model);
689 if (err)
690 goto err_grp_init;
691 }
692 } else {
693 priv->mode = SQ_SG_MODE;
694 err = gfar_parse_group(np, priv, model);
695 if (err)
696 goto err_grp_init;
697 }
698
699 for (i = 0; i < priv->num_tx_queues; i++)
700 priv->tx_queue[i] = NULL;
701 for (i = 0; i < priv->num_rx_queues; i++)
702 priv->rx_queue[i] = NULL;
703
704 for (i = 0; i < priv->num_tx_queues; i++) {
705 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
706 GFP_KERNEL);
707 if (!priv->tx_queue[i]) {
708 err = -ENOMEM;
709 goto tx_alloc_failed;
710 }
711 priv->tx_queue[i]->tx_skbuff = NULL;
712 priv->tx_queue[i]->qindex = i;
713 priv->tx_queue[i]->dev = dev;
714 spin_lock_init(&(priv->tx_queue[i]->txlock));
715 }
716
717 for (i = 0; i < priv->num_rx_queues; i++) {
718 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
719 GFP_KERNEL);
720 if (!priv->rx_queue[i]) {
721 err = -ENOMEM;
722 goto rx_alloc_failed;
723 }
724 priv->rx_queue[i]->rx_skbuff = NULL;
725 priv->rx_queue[i]->qindex = i;
726 priv->rx_queue[i]->dev = dev;
727 spin_lock_init(&(priv->rx_queue[i]->rxlock));
728 }
729
730
731 stash = of_get_property(np, "bd-stash", NULL);
732
733 if (stash) {
734 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
735 priv->bd_stash_en = 1;
736 }
737
738 stash_len = of_get_property(np, "rx-stash-len", NULL);
739
740 if (stash_len)
741 priv->rx_stash_size = *stash_len;
742
743 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
744
745 if (stash_idx)
746 priv->rx_stash_index = *stash_idx;
747
748 if (stash_len || stash_idx)
749 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
750
751 mac_addr = of_get_mac_address(np);
752
753 if (mac_addr)
754 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
755
756 if (model && !strcasecmp(model, "TSEC"))
757 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
758 FSL_GIANFAR_DEV_HAS_COALESCE |
759 FSL_GIANFAR_DEV_HAS_RMON |
760 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
761
762 if (model && !strcasecmp(model, "eTSEC"))
763 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
764 FSL_GIANFAR_DEV_HAS_COALESCE |
765 FSL_GIANFAR_DEV_HAS_RMON |
766 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
767 FSL_GIANFAR_DEV_HAS_PADDING |
768 FSL_GIANFAR_DEV_HAS_CSUM |
769 FSL_GIANFAR_DEV_HAS_VLAN |
770 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
771 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
772 FSL_GIANFAR_DEV_HAS_TIMER;
773
774 ctype = of_get_property(np, "phy-connection-type", NULL);
775
776 /* We only care about rgmii-id. The rest are autodetected */
777 if (ctype && !strcmp(ctype, "rgmii-id"))
778 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
779 else
780 priv->interface = PHY_INTERFACE_MODE_MII;
781
782 if (of_get_property(np, "fsl,magic-packet", NULL))
783 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
784
785 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
786
787 /* Find the TBI PHY. If it's not there, we don't support SGMII */
788 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
789
790 return 0;
791
792 rx_alloc_failed:
793 free_rx_pointers(priv);
794 tx_alloc_failed:
795 free_tx_pointers(priv);
796 err_grp_init:
797 unmap_group_regs(priv);
798 free_gfar_dev(priv);
799 return err;
800 }
801
802 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
803 struct ifreq *ifr, int cmd)
804 {
805 struct hwtstamp_config config;
806 struct gfar_private *priv = netdev_priv(netdev);
807
808 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
809 return -EFAULT;
810
811 /* reserved for future extensions */
812 if (config.flags)
813 return -EINVAL;
814
815 switch (config.tx_type) {
816 case HWTSTAMP_TX_OFF:
817 priv->hwts_tx_en = 0;
818 break;
819 case HWTSTAMP_TX_ON:
820 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
821 return -ERANGE;
822 priv->hwts_tx_en = 1;
823 break;
824 default:
825 return -ERANGE;
826 }
827
828 switch (config.rx_filter) {
829 case HWTSTAMP_FILTER_NONE:
830 if (priv->hwts_rx_en) {
831 stop_gfar(netdev);
832 priv->hwts_rx_en = 0;
833 startup_gfar(netdev);
834 }
835 break;
836 default:
837 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
838 return -ERANGE;
839 if (!priv->hwts_rx_en) {
840 stop_gfar(netdev);
841 priv->hwts_rx_en = 1;
842 startup_gfar(netdev);
843 }
844 config.rx_filter = HWTSTAMP_FILTER_ALL;
845 break;
846 }
847
848 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
849 -EFAULT : 0;
850 }
851
852 /* Ioctl MII Interface */
853 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
854 {
855 struct gfar_private *priv = netdev_priv(dev);
856
857 if (!netif_running(dev))
858 return -EINVAL;
859
860 if (cmd == SIOCSHWTSTAMP)
861 return gfar_hwtstamp_ioctl(dev, rq, cmd);
862
863 if (!priv->phydev)
864 return -ENODEV;
865
866 return phy_mii_ioctl(priv->phydev, rq, cmd);
867 }
868
869 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
870 {
871 unsigned int new_bit_map = 0x0;
872 int mask = 0x1 << (max_qs - 1), i;
873
874 for (i = 0; i < max_qs; i++) {
875 if (bit_map & mask)
876 new_bit_map = new_bit_map + (1 << i);
877 mask = mask >> 0x1;
878 }
879 return new_bit_map;
880 }
881
882 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
883 u32 class)
884 {
885 u32 rqfpr = FPR_FILER_MASK;
886 u32 rqfcr = 0x0;
887
888 rqfar--;
889 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
890 priv->ftp_rqfpr[rqfar] = rqfpr;
891 priv->ftp_rqfcr[rqfar] = rqfcr;
892 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
893
894 rqfar--;
895 rqfcr = RQFCR_CMP_NOMATCH;
896 priv->ftp_rqfpr[rqfar] = rqfpr;
897 priv->ftp_rqfcr[rqfar] = rqfcr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899
900 rqfar--;
901 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
902 rqfpr = class;
903 priv->ftp_rqfcr[rqfar] = rqfcr;
904 priv->ftp_rqfpr[rqfar] = rqfpr;
905 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
906
907 rqfar--;
908 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
909 rqfpr = class;
910 priv->ftp_rqfcr[rqfar] = rqfcr;
911 priv->ftp_rqfpr[rqfar] = rqfpr;
912 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
913
914 return rqfar;
915 }
916
917 static void gfar_init_filer_table(struct gfar_private *priv)
918 {
919 int i = 0x0;
920 u32 rqfar = MAX_FILER_IDX;
921 u32 rqfcr = 0x0;
922 u32 rqfpr = FPR_FILER_MASK;
923
924 /* Default rule */
925 rqfcr = RQFCR_CMP_MATCH;
926 priv->ftp_rqfcr[rqfar] = rqfcr;
927 priv->ftp_rqfpr[rqfar] = rqfpr;
928 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
929
930 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
931 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
932 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
933 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
934 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
935 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
936
937 /* cur_filer_idx indicated the first non-masked rule */
938 priv->cur_filer_idx = rqfar;
939
940 /* Rest are masked rules */
941 rqfcr = RQFCR_CMP_NOMATCH;
942 for (i = 0; i < rqfar; i++) {
943 priv->ftp_rqfcr[i] = rqfcr;
944 priv->ftp_rqfpr[i] = rqfpr;
945 gfar_write_filer(priv, i, rqfcr, rqfpr);
946 }
947 }
948
949 static void gfar_detect_errata(struct gfar_private *priv)
950 {
951 struct device *dev = &priv->ofdev->dev;
952 unsigned int pvr = mfspr(SPRN_PVR);
953 unsigned int svr = mfspr(SPRN_SVR);
954 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
955 unsigned int rev = svr & 0xffff;
956
957 /* MPC8313 Rev 2.0 and higher; All MPC837x */
958 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
959 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
960 priv->errata |= GFAR_ERRATA_74;
961
962 /* MPC8313 and MPC837x all rev */
963 if ((pvr == 0x80850010 && mod == 0x80b0) ||
964 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
965 priv->errata |= GFAR_ERRATA_76;
966
967 /* MPC8313 and MPC837x all rev */
968 if ((pvr == 0x80850010 && mod == 0x80b0) ||
969 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
970 priv->errata |= GFAR_ERRATA_A002;
971
972 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
973 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
974 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
975 priv->errata |= GFAR_ERRATA_12;
976
977 if (priv->errata)
978 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
979 priv->errata);
980 }
981
982 /* Set up the ethernet device structure, private data,
983 * and anything else we need before we start
984 */
985 static int gfar_probe(struct platform_device *ofdev)
986 {
987 u32 tempval;
988 struct net_device *dev = NULL;
989 struct gfar_private *priv = NULL;
990 struct gfar __iomem *regs = NULL;
991 int err = 0, i, grp_idx = 0;
992 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
993 u32 isrg = 0;
994 u32 __iomem *baddr;
995
996 err = gfar_of_init(ofdev, &dev);
997
998 if (err)
999 return err;
1000
1001 priv = netdev_priv(dev);
1002 priv->ndev = dev;
1003 priv->ofdev = ofdev;
1004 priv->node = ofdev->dev.of_node;
1005 SET_NETDEV_DEV(dev, &ofdev->dev);
1006
1007 spin_lock_init(&priv->bflock);
1008 INIT_WORK(&priv->reset_task, gfar_reset_task);
1009
1010 dev_set_drvdata(&ofdev->dev, priv);
1011 regs = priv->gfargrp[0].regs;
1012
1013 gfar_detect_errata(priv);
1014
1015 /* Stop the DMA engine now, in case it was running before
1016 * (The firmware could have used it, and left it running).
1017 */
1018 gfar_halt(dev);
1019
1020 /* Reset MAC layer */
1021 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1022
1023 /* We need to delay at least 3 TX clocks */
1024 udelay(2);
1025
1026 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1027 gfar_write(&regs->maccfg1, tempval);
1028
1029 /* Initialize MACCFG2. */
1030 tempval = MACCFG2_INIT_SETTINGS;
1031 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1032 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1033 gfar_write(&regs->maccfg2, tempval);
1034
1035 /* Initialize ECNTRL */
1036 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1037
1038 /* Set the dev->base_addr to the gfar reg region */
1039 dev->base_addr = (unsigned long) regs;
1040
1041 SET_NETDEV_DEV(dev, &ofdev->dev);
1042
1043 /* Fill in the dev structure */
1044 dev->watchdog_timeo = TX_TIMEOUT;
1045 dev->mtu = 1500;
1046 dev->netdev_ops = &gfar_netdev_ops;
1047 dev->ethtool_ops = &gfar_ethtool_ops;
1048
1049 /* Register for napi ...We are registering NAPI for each grp */
1050 for (i = 0; i < priv->num_grps; i++)
1051 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1052 GFAR_DEV_WEIGHT);
1053
1054 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1055 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1056 NETIF_F_RXCSUM;
1057 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1058 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1059 }
1060
1061 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1062 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1063 dev->features |= NETIF_F_HW_VLAN_RX;
1064 }
1065
1066 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1067 priv->extended_hash = 1;
1068 priv->hash_width = 9;
1069
1070 priv->hash_regs[0] = &regs->igaddr0;
1071 priv->hash_regs[1] = &regs->igaddr1;
1072 priv->hash_regs[2] = &regs->igaddr2;
1073 priv->hash_regs[3] = &regs->igaddr3;
1074 priv->hash_regs[4] = &regs->igaddr4;
1075 priv->hash_regs[5] = &regs->igaddr5;
1076 priv->hash_regs[6] = &regs->igaddr6;
1077 priv->hash_regs[7] = &regs->igaddr7;
1078 priv->hash_regs[8] = &regs->gaddr0;
1079 priv->hash_regs[9] = &regs->gaddr1;
1080 priv->hash_regs[10] = &regs->gaddr2;
1081 priv->hash_regs[11] = &regs->gaddr3;
1082 priv->hash_regs[12] = &regs->gaddr4;
1083 priv->hash_regs[13] = &regs->gaddr5;
1084 priv->hash_regs[14] = &regs->gaddr6;
1085 priv->hash_regs[15] = &regs->gaddr7;
1086
1087 } else {
1088 priv->extended_hash = 0;
1089 priv->hash_width = 8;
1090
1091 priv->hash_regs[0] = &regs->gaddr0;
1092 priv->hash_regs[1] = &regs->gaddr1;
1093 priv->hash_regs[2] = &regs->gaddr2;
1094 priv->hash_regs[3] = &regs->gaddr3;
1095 priv->hash_regs[4] = &regs->gaddr4;
1096 priv->hash_regs[5] = &regs->gaddr5;
1097 priv->hash_regs[6] = &regs->gaddr6;
1098 priv->hash_regs[7] = &regs->gaddr7;
1099 }
1100
1101 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1102 priv->padding = DEFAULT_PADDING;
1103 else
1104 priv->padding = 0;
1105
1106 if (dev->features & NETIF_F_IP_CSUM ||
1107 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1108 dev->needed_headroom = GMAC_FCB_LEN;
1109
1110 /* Program the isrg regs only if number of grps > 1 */
1111 if (priv->num_grps > 1) {
1112 baddr = &regs->isrg0;
1113 for (i = 0; i < priv->num_grps; i++) {
1114 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1115 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1116 gfar_write(baddr, isrg);
1117 baddr++;
1118 isrg = 0x0;
1119 }
1120 }
1121
1122 /* Need to reverse the bit maps as bit_map's MSB is q0
1123 * but, for_each_set_bit parses from right to left, which
1124 * basically reverses the queue numbers
1125 */
1126 for (i = 0; i< priv->num_grps; i++) {
1127 priv->gfargrp[i].tx_bit_map =
1128 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1129 priv->gfargrp[i].rx_bit_map =
1130 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1131 }
1132
1133 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1134 * also assign queues to groups
1135 */
1136 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1137 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1138
1139 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1140 priv->num_rx_queues) {
1141 priv->gfargrp[grp_idx].num_rx_queues++;
1142 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1143 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1144 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1145 }
1146 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1147
1148 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1149 priv->num_tx_queues) {
1150 priv->gfargrp[grp_idx].num_tx_queues++;
1151 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1152 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1153 tqueue = tqueue | (TQUEUE_EN0 >> i);
1154 }
1155 priv->gfargrp[grp_idx].rstat = rstat;
1156 priv->gfargrp[grp_idx].tstat = tstat;
1157 rstat = tstat =0;
1158 }
1159
1160 gfar_write(&regs->rqueue, rqueue);
1161 gfar_write(&regs->tqueue, tqueue);
1162
1163 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1164
1165 /* Initializing some of the rx/tx queue level parameters */
1166 for (i = 0; i < priv->num_tx_queues; i++) {
1167 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1168 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1169 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1170 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1171 }
1172
1173 for (i = 0; i < priv->num_rx_queues; i++) {
1174 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1175 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1176 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1177 }
1178
1179 /* always enable rx filer */
1180 priv->rx_filer_enable = 1;
1181 /* Enable most messages by default */
1182 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1183 /* use pritority h/w tx queue scheduling for single queue devices */
1184 if (priv->num_tx_queues == 1)
1185 priv->prio_sched_en = 1;
1186
1187 /* Carrier starts down, phylib will bring it up */
1188 netif_carrier_off(dev);
1189
1190 err = register_netdev(dev);
1191
1192 if (err) {
1193 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1194 goto register_fail;
1195 }
1196
1197 device_init_wakeup(&dev->dev,
1198 priv->device_flags &
1199 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1200
1201 /* fill out IRQ number and name fields */
1202 for (i = 0; i < priv->num_grps; i++) {
1203 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1204 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1205 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1206 dev->name, "_g", '0' + i, "_tx");
1207 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1208 dev->name, "_g", '0' + i, "_rx");
1209 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1210 dev->name, "_g", '0' + i, "_er");
1211 } else
1212 strcpy(gfar_irq(grp, TX)->name, dev->name);
1213 }
1214
1215 /* Initialize the filer table */
1216 gfar_init_filer_table(priv);
1217
1218 /* Create all the sysfs files */
1219 gfar_init_sysfs(dev);
1220
1221 /* Print out the device info */
1222 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1223
1224 /* Even more device info helps when determining which kernel
1225 * provided which set of benchmarks.
1226 */
1227 netdev_info(dev, "Running with NAPI enabled\n");
1228 for (i = 0; i < priv->num_rx_queues; i++)
1229 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1230 i, priv->rx_queue[i]->rx_ring_size);
1231 for (i = 0; i < priv->num_tx_queues; i++)
1232 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1233 i, priv->tx_queue[i]->tx_ring_size);
1234
1235 return 0;
1236
1237 register_fail:
1238 unmap_group_regs(priv);
1239 free_tx_pointers(priv);
1240 free_rx_pointers(priv);
1241 if (priv->phy_node)
1242 of_node_put(priv->phy_node);
1243 if (priv->tbi_node)
1244 of_node_put(priv->tbi_node);
1245 free_gfar_dev(priv);
1246 return err;
1247 }
1248
1249 static int gfar_remove(struct platform_device *ofdev)
1250 {
1251 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1252
1253 if (priv->phy_node)
1254 of_node_put(priv->phy_node);
1255 if (priv->tbi_node)
1256 of_node_put(priv->tbi_node);
1257
1258 dev_set_drvdata(&ofdev->dev, NULL);
1259
1260 unregister_netdev(priv->ndev);
1261 unmap_group_regs(priv);
1262 free_gfar_dev(priv);
1263
1264 return 0;
1265 }
1266
1267 #ifdef CONFIG_PM
1268
1269 static int gfar_suspend(struct device *dev)
1270 {
1271 struct gfar_private *priv = dev_get_drvdata(dev);
1272 struct net_device *ndev = priv->ndev;
1273 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1274 unsigned long flags;
1275 u32 tempval;
1276
1277 int magic_packet = priv->wol_en &&
1278 (priv->device_flags &
1279 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1280
1281 netif_device_detach(ndev);
1282
1283 if (netif_running(ndev)) {
1284
1285 local_irq_save(flags);
1286 lock_tx_qs(priv);
1287 lock_rx_qs(priv);
1288
1289 gfar_halt_nodisable(ndev);
1290
1291 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1292 tempval = gfar_read(&regs->maccfg1);
1293
1294 tempval &= ~MACCFG1_TX_EN;
1295
1296 if (!magic_packet)
1297 tempval &= ~MACCFG1_RX_EN;
1298
1299 gfar_write(&regs->maccfg1, tempval);
1300
1301 unlock_rx_qs(priv);
1302 unlock_tx_qs(priv);
1303 local_irq_restore(flags);
1304
1305 disable_napi(priv);
1306
1307 if (magic_packet) {
1308 /* Enable interrupt on Magic Packet */
1309 gfar_write(&regs->imask, IMASK_MAG);
1310
1311 /* Enable Magic Packet mode */
1312 tempval = gfar_read(&regs->maccfg2);
1313 tempval |= MACCFG2_MPEN;
1314 gfar_write(&regs->maccfg2, tempval);
1315 } else {
1316 phy_stop(priv->phydev);
1317 }
1318 }
1319
1320 return 0;
1321 }
1322
1323 static int gfar_resume(struct device *dev)
1324 {
1325 struct gfar_private *priv = dev_get_drvdata(dev);
1326 struct net_device *ndev = priv->ndev;
1327 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1328 unsigned long flags;
1329 u32 tempval;
1330 int magic_packet = priv->wol_en &&
1331 (priv->device_flags &
1332 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1333
1334 if (!netif_running(ndev)) {
1335 netif_device_attach(ndev);
1336 return 0;
1337 }
1338
1339 if (!magic_packet && priv->phydev)
1340 phy_start(priv->phydev);
1341
1342 /* Disable Magic Packet mode, in case something
1343 * else woke us up.
1344 */
1345 local_irq_save(flags);
1346 lock_tx_qs(priv);
1347 lock_rx_qs(priv);
1348
1349 tempval = gfar_read(&regs->maccfg2);
1350 tempval &= ~MACCFG2_MPEN;
1351 gfar_write(&regs->maccfg2, tempval);
1352
1353 gfar_start(ndev);
1354
1355 unlock_rx_qs(priv);
1356 unlock_tx_qs(priv);
1357 local_irq_restore(flags);
1358
1359 netif_device_attach(ndev);
1360
1361 enable_napi(priv);
1362
1363 return 0;
1364 }
1365
1366 static int gfar_restore(struct device *dev)
1367 {
1368 struct gfar_private *priv = dev_get_drvdata(dev);
1369 struct net_device *ndev = priv->ndev;
1370
1371 if (!netif_running(ndev)) {
1372 netif_device_attach(ndev);
1373
1374 return 0;
1375 }
1376
1377 if (gfar_init_bds(ndev)) {
1378 free_skb_resources(priv);
1379 return -ENOMEM;
1380 }
1381
1382 init_registers(ndev);
1383 gfar_set_mac_address(ndev);
1384 gfar_init_mac(ndev);
1385 gfar_start(ndev);
1386
1387 priv->oldlink = 0;
1388 priv->oldspeed = 0;
1389 priv->oldduplex = -1;
1390
1391 if (priv->phydev)
1392 phy_start(priv->phydev);
1393
1394 netif_device_attach(ndev);
1395 enable_napi(priv);
1396
1397 return 0;
1398 }
1399
1400 static struct dev_pm_ops gfar_pm_ops = {
1401 .suspend = gfar_suspend,
1402 .resume = gfar_resume,
1403 .freeze = gfar_suspend,
1404 .thaw = gfar_resume,
1405 .restore = gfar_restore,
1406 };
1407
1408 #define GFAR_PM_OPS (&gfar_pm_ops)
1409
1410 #else
1411
1412 #define GFAR_PM_OPS NULL
1413
1414 #endif
1415
1416 /* Reads the controller's registers to determine what interface
1417 * connects it to the PHY.
1418 */
1419 static phy_interface_t gfar_get_interface(struct net_device *dev)
1420 {
1421 struct gfar_private *priv = netdev_priv(dev);
1422 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1423 u32 ecntrl;
1424
1425 ecntrl = gfar_read(&regs->ecntrl);
1426
1427 if (ecntrl & ECNTRL_SGMII_MODE)
1428 return PHY_INTERFACE_MODE_SGMII;
1429
1430 if (ecntrl & ECNTRL_TBI_MODE) {
1431 if (ecntrl & ECNTRL_REDUCED_MODE)
1432 return PHY_INTERFACE_MODE_RTBI;
1433 else
1434 return PHY_INTERFACE_MODE_TBI;
1435 }
1436
1437 if (ecntrl & ECNTRL_REDUCED_MODE) {
1438 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1439 return PHY_INTERFACE_MODE_RMII;
1440 }
1441 else {
1442 phy_interface_t interface = priv->interface;
1443
1444 /* This isn't autodetected right now, so it must
1445 * be set by the device tree or platform code.
1446 */
1447 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1448 return PHY_INTERFACE_MODE_RGMII_ID;
1449
1450 return PHY_INTERFACE_MODE_RGMII;
1451 }
1452 }
1453
1454 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1455 return PHY_INTERFACE_MODE_GMII;
1456
1457 return PHY_INTERFACE_MODE_MII;
1458 }
1459
1460
1461 /* Initializes driver's PHY state, and attaches to the PHY.
1462 * Returns 0 on success.
1463 */
1464 static int init_phy(struct net_device *dev)
1465 {
1466 struct gfar_private *priv = netdev_priv(dev);
1467 uint gigabit_support =
1468 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1469 SUPPORTED_1000baseT_Full : 0;
1470 phy_interface_t interface;
1471
1472 priv->oldlink = 0;
1473 priv->oldspeed = 0;
1474 priv->oldduplex = -1;
1475
1476 interface = gfar_get_interface(dev);
1477
1478 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1479 interface);
1480 if (!priv->phydev)
1481 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1482 interface);
1483 if (!priv->phydev) {
1484 dev_err(&dev->dev, "could not attach to PHY\n");
1485 return -ENODEV;
1486 }
1487
1488 if (interface == PHY_INTERFACE_MODE_SGMII)
1489 gfar_configure_serdes(dev);
1490
1491 /* Remove any features not supported by the controller */
1492 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1493 priv->phydev->advertising = priv->phydev->supported;
1494
1495 return 0;
1496 }
1497
1498 /* Initialize TBI PHY interface for communicating with the
1499 * SERDES lynx PHY on the chip. We communicate with this PHY
1500 * through the MDIO bus on each controller, treating it as a
1501 * "normal" PHY at the address found in the TBIPA register. We assume
1502 * that the TBIPA register is valid. Either the MDIO bus code will set
1503 * it to a value that doesn't conflict with other PHYs on the bus, or the
1504 * value doesn't matter, as there are no other PHYs on the bus.
1505 */
1506 static void gfar_configure_serdes(struct net_device *dev)
1507 {
1508 struct gfar_private *priv = netdev_priv(dev);
1509 struct phy_device *tbiphy;
1510
1511 if (!priv->tbi_node) {
1512 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1513 "device tree specify a tbi-handle\n");
1514 return;
1515 }
1516
1517 tbiphy = of_phy_find_device(priv->tbi_node);
1518 if (!tbiphy) {
1519 dev_err(&dev->dev, "error: Could not get TBI device\n");
1520 return;
1521 }
1522
1523 /* If the link is already up, we must already be ok, and don't need to
1524 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1525 * everything for us? Resetting it takes the link down and requires
1526 * several seconds for it to come back.
1527 */
1528 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1529 return;
1530
1531 /* Single clk mode, mii mode off(for serdes communication) */
1532 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1533
1534 phy_write(tbiphy, MII_ADVERTISE,
1535 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1536 ADVERTISE_1000XPSE_ASYM);
1537
1538 phy_write(tbiphy, MII_BMCR,
1539 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1540 BMCR_SPEED1000);
1541 }
1542
1543 static void init_registers(struct net_device *dev)
1544 {
1545 struct gfar_private *priv = netdev_priv(dev);
1546 struct gfar __iomem *regs = NULL;
1547 int i;
1548
1549 for (i = 0; i < priv->num_grps; i++) {
1550 regs = priv->gfargrp[i].regs;
1551 /* Clear IEVENT */
1552 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1553
1554 /* Initialize IMASK */
1555 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1556 }
1557
1558 regs = priv->gfargrp[0].regs;
1559 /* Init hash registers to zero */
1560 gfar_write(&regs->igaddr0, 0);
1561 gfar_write(&regs->igaddr1, 0);
1562 gfar_write(&regs->igaddr2, 0);
1563 gfar_write(&regs->igaddr3, 0);
1564 gfar_write(&regs->igaddr4, 0);
1565 gfar_write(&regs->igaddr5, 0);
1566 gfar_write(&regs->igaddr6, 0);
1567 gfar_write(&regs->igaddr7, 0);
1568
1569 gfar_write(&regs->gaddr0, 0);
1570 gfar_write(&regs->gaddr1, 0);
1571 gfar_write(&regs->gaddr2, 0);
1572 gfar_write(&regs->gaddr3, 0);
1573 gfar_write(&regs->gaddr4, 0);
1574 gfar_write(&regs->gaddr5, 0);
1575 gfar_write(&regs->gaddr6, 0);
1576 gfar_write(&regs->gaddr7, 0);
1577
1578 /* Zero out the rmon mib registers if it has them */
1579 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1580 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1581
1582 /* Mask off the CAM interrupts */
1583 gfar_write(&regs->rmon.cam1, 0xffffffff);
1584 gfar_write(&regs->rmon.cam2, 0xffffffff);
1585 }
1586
1587 /* Initialize the max receive buffer length */
1588 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1589
1590 /* Initialize the Minimum Frame Length Register */
1591 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1592 }
1593
1594 static int __gfar_is_rx_idle(struct gfar_private *priv)
1595 {
1596 u32 res;
1597
1598 /* Normaly TSEC should not hang on GRS commands, so we should
1599 * actually wait for IEVENT_GRSC flag.
1600 */
1601 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1602 return 0;
1603
1604 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1605 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1606 * and the Rx can be safely reset.
1607 */
1608 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1609 res &= 0x7f807f80;
1610 if ((res & 0xffff) == (res >> 16))
1611 return 1;
1612
1613 return 0;
1614 }
1615
1616 /* Halt the receive and transmit queues */
1617 static void gfar_halt_nodisable(struct net_device *dev)
1618 {
1619 struct gfar_private *priv = netdev_priv(dev);
1620 struct gfar __iomem *regs = NULL;
1621 u32 tempval;
1622 int i;
1623
1624 for (i = 0; i < priv->num_grps; i++) {
1625 regs = priv->gfargrp[i].regs;
1626 /* Mask all interrupts */
1627 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1628
1629 /* Clear all interrupts */
1630 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1631 }
1632
1633 regs = priv->gfargrp[0].regs;
1634 /* Stop the DMA, and wait for it to stop */
1635 tempval = gfar_read(&regs->dmactrl);
1636 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1637 (DMACTRL_GRS | DMACTRL_GTS)) {
1638 int ret;
1639
1640 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1641 gfar_write(&regs->dmactrl, tempval);
1642
1643 do {
1644 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1645 (IEVENT_GRSC | IEVENT_GTSC)) ==
1646 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1647 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1648 ret = __gfar_is_rx_idle(priv);
1649 } while (!ret);
1650 }
1651 }
1652
1653 /* Halt the receive and transmit queues */
1654 void gfar_halt(struct net_device *dev)
1655 {
1656 struct gfar_private *priv = netdev_priv(dev);
1657 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1658 u32 tempval;
1659
1660 gfar_halt_nodisable(dev);
1661
1662 /* Disable Rx and Tx */
1663 tempval = gfar_read(&regs->maccfg1);
1664 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1665 gfar_write(&regs->maccfg1, tempval);
1666 }
1667
1668 static void free_grp_irqs(struct gfar_priv_grp *grp)
1669 {
1670 free_irq(gfar_irq(grp, TX)->irq, grp);
1671 free_irq(gfar_irq(grp, RX)->irq, grp);
1672 free_irq(gfar_irq(grp, ER)->irq, grp);
1673 }
1674
1675 void stop_gfar(struct net_device *dev)
1676 {
1677 struct gfar_private *priv = netdev_priv(dev);
1678 unsigned long flags;
1679 int i;
1680
1681 phy_stop(priv->phydev);
1682
1683
1684 /* Lock it down */
1685 local_irq_save(flags);
1686 lock_tx_qs(priv);
1687 lock_rx_qs(priv);
1688
1689 gfar_halt(dev);
1690
1691 unlock_rx_qs(priv);
1692 unlock_tx_qs(priv);
1693 local_irq_restore(flags);
1694
1695 /* Free the IRQs */
1696 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1697 for (i = 0; i < priv->num_grps; i++)
1698 free_grp_irqs(&priv->gfargrp[i]);
1699 } else {
1700 for (i = 0; i < priv->num_grps; i++)
1701 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1702 &priv->gfargrp[i]);
1703 }
1704
1705 free_skb_resources(priv);
1706 }
1707
1708 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1709 {
1710 struct txbd8 *txbdp;
1711 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1712 int i, j;
1713
1714 txbdp = tx_queue->tx_bd_base;
1715
1716 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1717 if (!tx_queue->tx_skbuff[i])
1718 continue;
1719
1720 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1721 txbdp->length, DMA_TO_DEVICE);
1722 txbdp->lstatus = 0;
1723 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1724 j++) {
1725 txbdp++;
1726 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1727 txbdp->length, DMA_TO_DEVICE);
1728 }
1729 txbdp++;
1730 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1731 tx_queue->tx_skbuff[i] = NULL;
1732 }
1733 kfree(tx_queue->tx_skbuff);
1734 tx_queue->tx_skbuff = NULL;
1735 }
1736
1737 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1738 {
1739 struct rxbd8 *rxbdp;
1740 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1741 int i;
1742
1743 rxbdp = rx_queue->rx_bd_base;
1744
1745 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1746 if (rx_queue->rx_skbuff[i]) {
1747 dma_unmap_single(&priv->ofdev->dev,
1748 rxbdp->bufPtr, priv->rx_buffer_size,
1749 DMA_FROM_DEVICE);
1750 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1751 rx_queue->rx_skbuff[i] = NULL;
1752 }
1753 rxbdp->lstatus = 0;
1754 rxbdp->bufPtr = 0;
1755 rxbdp++;
1756 }
1757 kfree(rx_queue->rx_skbuff);
1758 rx_queue->rx_skbuff = NULL;
1759 }
1760
1761 /* If there are any tx skbs or rx skbs still around, free them.
1762 * Then free tx_skbuff and rx_skbuff
1763 */
1764 static void free_skb_resources(struct gfar_private *priv)
1765 {
1766 struct gfar_priv_tx_q *tx_queue = NULL;
1767 struct gfar_priv_rx_q *rx_queue = NULL;
1768 int i;
1769
1770 /* Go through all the buffer descriptors and free their data buffers */
1771 for (i = 0; i < priv->num_tx_queues; i++) {
1772 struct netdev_queue *txq;
1773
1774 tx_queue = priv->tx_queue[i];
1775 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1776 if (tx_queue->tx_skbuff)
1777 free_skb_tx_queue(tx_queue);
1778 netdev_tx_reset_queue(txq);
1779 }
1780
1781 for (i = 0; i < priv->num_rx_queues; i++) {
1782 rx_queue = priv->rx_queue[i];
1783 if (rx_queue->rx_skbuff)
1784 free_skb_rx_queue(rx_queue);
1785 }
1786
1787 dma_free_coherent(&priv->ofdev->dev,
1788 sizeof(struct txbd8) * priv->total_tx_ring_size +
1789 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1790 priv->tx_queue[0]->tx_bd_base,
1791 priv->tx_queue[0]->tx_bd_dma_base);
1792 }
1793
1794 void gfar_start(struct net_device *dev)
1795 {
1796 struct gfar_private *priv = netdev_priv(dev);
1797 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1798 u32 tempval;
1799 int i = 0;
1800
1801 /* Enable Rx and Tx in MACCFG1 */
1802 tempval = gfar_read(&regs->maccfg1);
1803 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1804 gfar_write(&regs->maccfg1, tempval);
1805
1806 /* Initialize DMACTRL to have WWR and WOP */
1807 tempval = gfar_read(&regs->dmactrl);
1808 tempval |= DMACTRL_INIT_SETTINGS;
1809 gfar_write(&regs->dmactrl, tempval);
1810
1811 /* Make sure we aren't stopped */
1812 tempval = gfar_read(&regs->dmactrl);
1813 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1814 gfar_write(&regs->dmactrl, tempval);
1815
1816 for (i = 0; i < priv->num_grps; i++) {
1817 regs = priv->gfargrp[i].regs;
1818 /* Clear THLT/RHLT, so that the DMA starts polling now */
1819 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1820 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1821 /* Unmask the interrupts we look for */
1822 gfar_write(&regs->imask, IMASK_DEFAULT);
1823 }
1824
1825 dev->trans_start = jiffies; /* prevent tx timeout */
1826 }
1827
1828 void gfar_configure_coalescing(struct gfar_private *priv,
1829 unsigned long tx_mask, unsigned long rx_mask)
1830 {
1831 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1832 u32 __iomem *baddr;
1833 int i = 0;
1834
1835 /* Backward compatible case ---- even if we enable
1836 * multiple queues, there's only single reg to program
1837 */
1838 gfar_write(&regs->txic, 0);
1839 if (likely(priv->tx_queue[0]->txcoalescing))
1840 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1841
1842 gfar_write(&regs->rxic, 0);
1843 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1844 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1845
1846 if (priv->mode == MQ_MG_MODE) {
1847 baddr = &regs->txic0;
1848 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1849 gfar_write(baddr + i, 0);
1850 if (likely(priv->tx_queue[i]->txcoalescing))
1851 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1852 }
1853
1854 baddr = &regs->rxic0;
1855 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1856 gfar_write(baddr + i, 0);
1857 if (likely(priv->rx_queue[i]->rxcoalescing))
1858 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1859 }
1860 }
1861 }
1862
1863 static int register_grp_irqs(struct gfar_priv_grp *grp)
1864 {
1865 struct gfar_private *priv = grp->priv;
1866 struct net_device *dev = priv->ndev;
1867 int err;
1868
1869 /* If the device has multiple interrupts, register for
1870 * them. Otherwise, only register for the one
1871 */
1872 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1873 /* Install our interrupt handlers for Error,
1874 * Transmit, and Receive
1875 */
1876 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1877 gfar_irq(grp, ER)->name, grp);
1878 if (err < 0) {
1879 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1880 gfar_irq(grp, ER)->irq);
1881
1882 goto err_irq_fail;
1883 }
1884 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1885 gfar_irq(grp, TX)->name, grp);
1886 if (err < 0) {
1887 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1888 gfar_irq(grp, TX)->irq);
1889 goto tx_irq_fail;
1890 }
1891 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1892 gfar_irq(grp, RX)->name, grp);
1893 if (err < 0) {
1894 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1895 gfar_irq(grp, RX)->irq);
1896 goto rx_irq_fail;
1897 }
1898 } else {
1899 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1900 gfar_irq(grp, TX)->name, grp);
1901 if (err < 0) {
1902 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1903 gfar_irq(grp, TX)->irq);
1904 goto err_irq_fail;
1905 }
1906 }
1907
1908 return 0;
1909
1910 rx_irq_fail:
1911 free_irq(gfar_irq(grp, TX)->irq, grp);
1912 tx_irq_fail:
1913 free_irq(gfar_irq(grp, ER)->irq, grp);
1914 err_irq_fail:
1915 return err;
1916
1917 }
1918
1919 /* Bring the controller up and running */
1920 int startup_gfar(struct net_device *ndev)
1921 {
1922 struct gfar_private *priv = netdev_priv(ndev);
1923 struct gfar __iomem *regs = NULL;
1924 int err, i, j;
1925
1926 for (i = 0; i < priv->num_grps; i++) {
1927 regs= priv->gfargrp[i].regs;
1928 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1929 }
1930
1931 regs= priv->gfargrp[0].regs;
1932 err = gfar_alloc_skb_resources(ndev);
1933 if (err)
1934 return err;
1935
1936 gfar_init_mac(ndev);
1937
1938 for (i = 0; i < priv->num_grps; i++) {
1939 err = register_grp_irqs(&priv->gfargrp[i]);
1940 if (err) {
1941 for (j = 0; j < i; j++)
1942 free_grp_irqs(&priv->gfargrp[j]);
1943 goto irq_fail;
1944 }
1945 }
1946
1947 /* Start the controller */
1948 gfar_start(ndev);
1949
1950 phy_start(priv->phydev);
1951
1952 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1953
1954 return 0;
1955
1956 irq_fail:
1957 free_skb_resources(priv);
1958 return err;
1959 }
1960
1961 /* Called when something needs to use the ethernet device
1962 * Returns 0 for success.
1963 */
1964 static int gfar_enet_open(struct net_device *dev)
1965 {
1966 struct gfar_private *priv = netdev_priv(dev);
1967 int err;
1968
1969 enable_napi(priv);
1970
1971 /* Initialize a bunch of registers */
1972 init_registers(dev);
1973
1974 gfar_set_mac_address(dev);
1975
1976 err = init_phy(dev);
1977
1978 if (err) {
1979 disable_napi(priv);
1980 return err;
1981 }
1982
1983 err = startup_gfar(dev);
1984 if (err) {
1985 disable_napi(priv);
1986 return err;
1987 }
1988
1989 netif_tx_start_all_queues(dev);
1990
1991 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1992
1993 return err;
1994 }
1995
1996 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1997 {
1998 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1999
2000 memset(fcb, 0, GMAC_FCB_LEN);
2001
2002 return fcb;
2003 }
2004
2005 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2006 int fcb_length)
2007 {
2008 /* If we're here, it's a IP packet with a TCP or UDP
2009 * payload. We set it to checksum, using a pseudo-header
2010 * we provide
2011 */
2012 u8 flags = TXFCB_DEFAULT;
2013
2014 /* Tell the controller what the protocol is
2015 * And provide the already calculated phcs
2016 */
2017 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2018 flags |= TXFCB_UDP;
2019 fcb->phcs = udp_hdr(skb)->check;
2020 } else
2021 fcb->phcs = tcp_hdr(skb)->check;
2022
2023 /* l3os is the distance between the start of the
2024 * frame (skb->data) and the start of the IP hdr.
2025 * l4os is the distance between the start of the
2026 * l3 hdr and the l4 hdr
2027 */
2028 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2029 fcb->l4os = skb_network_header_len(skb);
2030
2031 fcb->flags = flags;
2032 }
2033
2034 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2035 {
2036 fcb->flags |= TXFCB_VLN;
2037 fcb->vlctl = vlan_tx_tag_get(skb);
2038 }
2039
2040 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2041 struct txbd8 *base, int ring_size)
2042 {
2043 struct txbd8 *new_bd = bdp + stride;
2044
2045 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2046 }
2047
2048 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2049 int ring_size)
2050 {
2051 return skip_txbd(bdp, 1, base, ring_size);
2052 }
2053
2054 /* This is called by the kernel when a frame is ready for transmission.
2055 * It is pointed to by the dev->hard_start_xmit function pointer
2056 */
2057 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2058 {
2059 struct gfar_private *priv = netdev_priv(dev);
2060 struct gfar_priv_tx_q *tx_queue = NULL;
2061 struct netdev_queue *txq;
2062 struct gfar __iomem *regs = NULL;
2063 struct txfcb *fcb = NULL;
2064 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2065 u32 lstatus;
2066 int i, rq = 0, do_tstamp = 0;
2067 u32 bufaddr;
2068 unsigned long flags;
2069 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2070
2071 /* TOE=1 frames larger than 2500 bytes may see excess delays
2072 * before start of transmission.
2073 */
2074 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2075 skb->ip_summed == CHECKSUM_PARTIAL &&
2076 skb->len > 2500)) {
2077 int ret;
2078
2079 ret = skb_checksum_help(skb);
2080 if (ret)
2081 return ret;
2082 }
2083
2084 rq = skb->queue_mapping;
2085 tx_queue = priv->tx_queue[rq];
2086 txq = netdev_get_tx_queue(dev, rq);
2087 base = tx_queue->tx_bd_base;
2088 regs = tx_queue->grp->regs;
2089
2090 /* check if time stamp should be generated */
2091 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2092 priv->hwts_tx_en)) {
2093 do_tstamp = 1;
2094 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2095 }
2096
2097 /* make space for additional header when fcb is needed */
2098 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2099 vlan_tx_tag_present(skb) ||
2100 unlikely(do_tstamp)) &&
2101 (skb_headroom(skb) < fcb_length)) {
2102 struct sk_buff *skb_new;
2103
2104 skb_new = skb_realloc_headroom(skb, fcb_length);
2105 if (!skb_new) {
2106 dev->stats.tx_errors++;
2107 kfree_skb(skb);
2108 return NETDEV_TX_OK;
2109 }
2110
2111 if (skb->sk)
2112 skb_set_owner_w(skb_new, skb->sk);
2113 consume_skb(skb);
2114 skb = skb_new;
2115 }
2116
2117 /* total number of fragments in the SKB */
2118 nr_frags = skb_shinfo(skb)->nr_frags;
2119
2120 /* calculate the required number of TxBDs for this skb */
2121 if (unlikely(do_tstamp))
2122 nr_txbds = nr_frags + 2;
2123 else
2124 nr_txbds = nr_frags + 1;
2125
2126 /* check if there is space to queue this packet */
2127 if (nr_txbds > tx_queue->num_txbdfree) {
2128 /* no space, stop the queue */
2129 netif_tx_stop_queue(txq);
2130 dev->stats.tx_fifo_errors++;
2131 return NETDEV_TX_BUSY;
2132 }
2133
2134 /* Update transmit stats */
2135 tx_queue->stats.tx_bytes += skb->len;
2136 tx_queue->stats.tx_packets++;
2137
2138 txbdp = txbdp_start = tx_queue->cur_tx;
2139 lstatus = txbdp->lstatus;
2140
2141 /* Time stamp insertion requires one additional TxBD */
2142 if (unlikely(do_tstamp))
2143 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2144 tx_queue->tx_ring_size);
2145
2146 if (nr_frags == 0) {
2147 if (unlikely(do_tstamp))
2148 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2149 TXBD_INTERRUPT);
2150 else
2151 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2152 } else {
2153 /* Place the fragment addresses and lengths into the TxBDs */
2154 for (i = 0; i < nr_frags; i++) {
2155 /* Point at the next BD, wrapping as needed */
2156 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2157
2158 length = skb_shinfo(skb)->frags[i].size;
2159
2160 lstatus = txbdp->lstatus | length |
2161 BD_LFLAG(TXBD_READY);
2162
2163 /* Handle the last BD specially */
2164 if (i == nr_frags - 1)
2165 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2166
2167 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2168 &skb_shinfo(skb)->frags[i],
2169 0,
2170 length,
2171 DMA_TO_DEVICE);
2172
2173 /* set the TxBD length and buffer pointer */
2174 txbdp->bufPtr = bufaddr;
2175 txbdp->lstatus = lstatus;
2176 }
2177
2178 lstatus = txbdp_start->lstatus;
2179 }
2180
2181 /* Add TxPAL between FCB and frame if required */
2182 if (unlikely(do_tstamp)) {
2183 skb_push(skb, GMAC_TXPAL_LEN);
2184 memset(skb->data, 0, GMAC_TXPAL_LEN);
2185 }
2186
2187 /* Set up checksumming */
2188 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2189 fcb = gfar_add_fcb(skb);
2190 /* as specified by errata */
2191 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2192 ((unsigned long)fcb % 0x20) > 0x18)) {
2193 __skb_pull(skb, GMAC_FCB_LEN);
2194 skb_checksum_help(skb);
2195 } else {
2196 lstatus |= BD_LFLAG(TXBD_TOE);
2197 gfar_tx_checksum(skb, fcb, fcb_length);
2198 }
2199 }
2200
2201 if (vlan_tx_tag_present(skb)) {
2202 if (unlikely(NULL == fcb)) {
2203 fcb = gfar_add_fcb(skb);
2204 lstatus |= BD_LFLAG(TXBD_TOE);
2205 }
2206
2207 gfar_tx_vlan(skb, fcb);
2208 }
2209
2210 /* Setup tx hardware time stamping if requested */
2211 if (unlikely(do_tstamp)) {
2212 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2213 if (fcb == NULL)
2214 fcb = gfar_add_fcb(skb);
2215 fcb->ptp = 1;
2216 lstatus |= BD_LFLAG(TXBD_TOE);
2217 }
2218
2219 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2220 skb_headlen(skb), DMA_TO_DEVICE);
2221
2222 /* If time stamping is requested one additional TxBD must be set up. The
2223 * first TxBD points to the FCB and must have a data length of
2224 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2225 * the full frame length.
2226 */
2227 if (unlikely(do_tstamp)) {
2228 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2229 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2230 (skb_headlen(skb) - fcb_length);
2231 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2232 } else {
2233 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2234 }
2235
2236 netdev_tx_sent_queue(txq, skb->len);
2237
2238 /* We can work in parallel with gfar_clean_tx_ring(), except
2239 * when modifying num_txbdfree. Note that we didn't grab the lock
2240 * when we were reading the num_txbdfree and checking for available
2241 * space, that's because outside of this function it can only grow,
2242 * and once we've got needed space, it cannot suddenly disappear.
2243 *
2244 * The lock also protects us from gfar_error(), which can modify
2245 * regs->tstat and thus retrigger the transfers, which is why we
2246 * also must grab the lock before setting ready bit for the first
2247 * to be transmitted BD.
2248 */
2249 spin_lock_irqsave(&tx_queue->txlock, flags);
2250
2251 /* The powerpc-specific eieio() is used, as wmb() has too strong
2252 * semantics (it requires synchronization between cacheable and
2253 * uncacheable mappings, which eieio doesn't provide and which we
2254 * don't need), thus requiring a more expensive sync instruction. At
2255 * some point, the set of architecture-independent barrier functions
2256 * should be expanded to include weaker barriers.
2257 */
2258 eieio();
2259
2260 txbdp_start->lstatus = lstatus;
2261
2262 eieio(); /* force lstatus write before tx_skbuff */
2263
2264 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2265
2266 /* Update the current skb pointer to the next entry we will use
2267 * (wrapping if necessary)
2268 */
2269 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2270 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2271
2272 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2273
2274 /* reduce TxBD free count */
2275 tx_queue->num_txbdfree -= (nr_txbds);
2276
2277 /* If the next BD still needs to be cleaned up, then the bds
2278 * are full. We need to tell the kernel to stop sending us stuff.
2279 */
2280 if (!tx_queue->num_txbdfree) {
2281 netif_tx_stop_queue(txq);
2282
2283 dev->stats.tx_fifo_errors++;
2284 }
2285
2286 /* Tell the DMA to go go go */
2287 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2288
2289 /* Unlock priv */
2290 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2291
2292 return NETDEV_TX_OK;
2293 }
2294
2295 /* Stops the kernel queue, and halts the controller */
2296 static int gfar_close(struct net_device *dev)
2297 {
2298 struct gfar_private *priv = netdev_priv(dev);
2299
2300 disable_napi(priv);
2301
2302 cancel_work_sync(&priv->reset_task);
2303 stop_gfar(dev);
2304
2305 /* Disconnect from the PHY */
2306 phy_disconnect(priv->phydev);
2307 priv->phydev = NULL;
2308
2309 netif_tx_stop_all_queues(dev);
2310
2311 return 0;
2312 }
2313
2314 /* Changes the mac address if the controller is not running. */
2315 static int gfar_set_mac_address(struct net_device *dev)
2316 {
2317 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2318
2319 return 0;
2320 }
2321
2322 /* Check if rx parser should be activated */
2323 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2324 {
2325 struct gfar __iomem *regs;
2326 u32 tempval;
2327
2328 regs = priv->gfargrp[0].regs;
2329
2330 tempval = gfar_read(&regs->rctrl);
2331 /* If parse is no longer required, then disable parser */
2332 if (tempval & RCTRL_REQ_PARSER)
2333 tempval |= RCTRL_PRSDEP_INIT;
2334 else
2335 tempval &= ~RCTRL_PRSDEP_INIT;
2336 gfar_write(&regs->rctrl, tempval);
2337 }
2338
2339 /* Enables and disables VLAN insertion/extraction */
2340 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2341 {
2342 struct gfar_private *priv = netdev_priv(dev);
2343 struct gfar __iomem *regs = NULL;
2344 unsigned long flags;
2345 u32 tempval;
2346
2347 regs = priv->gfargrp[0].regs;
2348 local_irq_save(flags);
2349 lock_rx_qs(priv);
2350
2351 if (features & NETIF_F_HW_VLAN_TX) {
2352 /* Enable VLAN tag insertion */
2353 tempval = gfar_read(&regs->tctrl);
2354 tempval |= TCTRL_VLINS;
2355 gfar_write(&regs->tctrl, tempval);
2356 } else {
2357 /* Disable VLAN tag insertion */
2358 tempval = gfar_read(&regs->tctrl);
2359 tempval &= ~TCTRL_VLINS;
2360 gfar_write(&regs->tctrl, tempval);
2361 }
2362
2363 if (features & NETIF_F_HW_VLAN_RX) {
2364 /* Enable VLAN tag extraction */
2365 tempval = gfar_read(&regs->rctrl);
2366 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2367 gfar_write(&regs->rctrl, tempval);
2368 } else {
2369 /* Disable VLAN tag extraction */
2370 tempval = gfar_read(&regs->rctrl);
2371 tempval &= ~RCTRL_VLEX;
2372 gfar_write(&regs->rctrl, tempval);
2373
2374 gfar_check_rx_parser_mode(priv);
2375 }
2376
2377 gfar_change_mtu(dev, dev->mtu);
2378
2379 unlock_rx_qs(priv);
2380 local_irq_restore(flags);
2381 }
2382
2383 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2384 {
2385 int tempsize, tempval;
2386 struct gfar_private *priv = netdev_priv(dev);
2387 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2388 int oldsize = priv->rx_buffer_size;
2389 int frame_size = new_mtu + ETH_HLEN;
2390
2391 if (gfar_is_vlan_on(priv))
2392 frame_size += VLAN_HLEN;
2393
2394 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2395 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2396 return -EINVAL;
2397 }
2398
2399 if (gfar_uses_fcb(priv))
2400 frame_size += GMAC_FCB_LEN;
2401
2402 frame_size += priv->padding;
2403
2404 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2405 INCREMENTAL_BUFFER_SIZE;
2406
2407 /* Only stop and start the controller if it isn't already
2408 * stopped, and we changed something
2409 */
2410 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2411 stop_gfar(dev);
2412
2413 priv->rx_buffer_size = tempsize;
2414
2415 dev->mtu = new_mtu;
2416
2417 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2418 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2419
2420 /* If the mtu is larger than the max size for standard
2421 * ethernet frames (ie, a jumbo frame), then set maccfg2
2422 * to allow huge frames, and to check the length
2423 */
2424 tempval = gfar_read(&regs->maccfg2);
2425
2426 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2427 gfar_has_errata(priv, GFAR_ERRATA_74))
2428 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2429 else
2430 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2431
2432 gfar_write(&regs->maccfg2, tempval);
2433
2434 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2435 startup_gfar(dev);
2436
2437 return 0;
2438 }
2439
2440 /* gfar_reset_task gets scheduled when a packet has not been
2441 * transmitted after a set amount of time.
2442 * For now, assume that clearing out all the structures, and
2443 * starting over will fix the problem.
2444 */
2445 static void gfar_reset_task(struct work_struct *work)
2446 {
2447 struct gfar_private *priv = container_of(work, struct gfar_private,
2448 reset_task);
2449 struct net_device *dev = priv->ndev;
2450
2451 if (dev->flags & IFF_UP) {
2452 netif_tx_stop_all_queues(dev);
2453 stop_gfar(dev);
2454 startup_gfar(dev);
2455 netif_tx_start_all_queues(dev);
2456 }
2457
2458 netif_tx_schedule_all(dev);
2459 }
2460
2461 static void gfar_timeout(struct net_device *dev)
2462 {
2463 struct gfar_private *priv = netdev_priv(dev);
2464
2465 dev->stats.tx_errors++;
2466 schedule_work(&priv->reset_task);
2467 }
2468
2469 static void gfar_align_skb(struct sk_buff *skb)
2470 {
2471 /* We need the data buffer to be aligned properly. We will reserve
2472 * as many bytes as needed to align the data properly
2473 */
2474 skb_reserve(skb, RXBUF_ALIGNMENT -
2475 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2476 }
2477
2478 /* Interrupt Handler for Transmit complete */
2479 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2480 {
2481 struct net_device *dev = tx_queue->dev;
2482 struct netdev_queue *txq;
2483 struct gfar_private *priv = netdev_priv(dev);
2484 struct gfar_priv_rx_q *rx_queue = NULL;
2485 struct txbd8 *bdp, *next = NULL;
2486 struct txbd8 *lbdp = NULL;
2487 struct txbd8 *base = tx_queue->tx_bd_base;
2488 struct sk_buff *skb;
2489 int skb_dirtytx;
2490 int tx_ring_size = tx_queue->tx_ring_size;
2491 int frags = 0, nr_txbds = 0;
2492 int i;
2493 int howmany = 0;
2494 int tqi = tx_queue->qindex;
2495 unsigned int bytes_sent = 0;
2496 u32 lstatus;
2497 size_t buflen;
2498
2499 rx_queue = priv->rx_queue[tqi];
2500 txq = netdev_get_tx_queue(dev, tqi);
2501 bdp = tx_queue->dirty_tx;
2502 skb_dirtytx = tx_queue->skb_dirtytx;
2503
2504 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2505 unsigned long flags;
2506
2507 frags = skb_shinfo(skb)->nr_frags;
2508
2509 /* When time stamping, one additional TxBD must be freed.
2510 * Also, we need to dma_unmap_single() the TxPAL.
2511 */
2512 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2513 nr_txbds = frags + 2;
2514 else
2515 nr_txbds = frags + 1;
2516
2517 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2518
2519 lstatus = lbdp->lstatus;
2520
2521 /* Only clean completed frames */
2522 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2523 (lstatus & BD_LENGTH_MASK))
2524 break;
2525
2526 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2527 next = next_txbd(bdp, base, tx_ring_size);
2528 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2529 } else
2530 buflen = bdp->length;
2531
2532 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2533 buflen, DMA_TO_DEVICE);
2534
2535 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2536 struct skb_shared_hwtstamps shhwtstamps;
2537 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2538
2539 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2540 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2541 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2542 skb_tstamp_tx(skb, &shhwtstamps);
2543 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2544 bdp = next;
2545 }
2546
2547 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2548 bdp = next_txbd(bdp, base, tx_ring_size);
2549
2550 for (i = 0; i < frags; i++) {
2551 dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2552 bdp->length, DMA_TO_DEVICE);
2553 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2554 bdp = next_txbd(bdp, base, tx_ring_size);
2555 }
2556
2557 bytes_sent += skb->len;
2558
2559 dev_kfree_skb_any(skb);
2560
2561 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2562
2563 skb_dirtytx = (skb_dirtytx + 1) &
2564 TX_RING_MOD_MASK(tx_ring_size);
2565
2566 howmany++;
2567 spin_lock_irqsave(&tx_queue->txlock, flags);
2568 tx_queue->num_txbdfree += nr_txbds;
2569 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2570 }
2571
2572 /* If we freed a buffer, we can restart transmission, if necessary */
2573 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2574 netif_wake_subqueue(dev, tqi);
2575
2576 /* Update dirty indicators */
2577 tx_queue->skb_dirtytx = skb_dirtytx;
2578 tx_queue->dirty_tx = bdp;
2579
2580 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2581
2582 return howmany;
2583 }
2584
2585 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2586 {
2587 unsigned long flags;
2588
2589 spin_lock_irqsave(&gfargrp->grplock, flags);
2590 if (napi_schedule_prep(&gfargrp->napi)) {
2591 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2592 __napi_schedule(&gfargrp->napi);
2593 } else {
2594 /* Clear IEVENT, so interrupts aren't called again
2595 * because of the packets that have already arrived.
2596 */
2597 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2598 }
2599 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2600
2601 }
2602
2603 /* Interrupt Handler for Transmit complete */
2604 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2605 {
2606 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2607 return IRQ_HANDLED;
2608 }
2609
2610 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2611 struct sk_buff *skb)
2612 {
2613 struct net_device *dev = rx_queue->dev;
2614 struct gfar_private *priv = netdev_priv(dev);
2615 dma_addr_t buf;
2616
2617 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2618 priv->rx_buffer_size, DMA_FROM_DEVICE);
2619 gfar_init_rxbdp(rx_queue, bdp, buf);
2620 }
2621
2622 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2623 {
2624 struct gfar_private *priv = netdev_priv(dev);
2625 struct sk_buff *skb;
2626
2627 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2628 if (!skb)
2629 return NULL;
2630
2631 gfar_align_skb(skb);
2632
2633 return skb;
2634 }
2635
2636 struct sk_buff *gfar_new_skb(struct net_device *dev)
2637 {
2638 return gfar_alloc_skb(dev);
2639 }
2640
2641 static inline void count_errors(unsigned short status, struct net_device *dev)
2642 {
2643 struct gfar_private *priv = netdev_priv(dev);
2644 struct net_device_stats *stats = &dev->stats;
2645 struct gfar_extra_stats *estats = &priv->extra_stats;
2646
2647 /* If the packet was truncated, none of the other errors matter */
2648 if (status & RXBD_TRUNCATED) {
2649 stats->rx_length_errors++;
2650
2651 estats->rx_trunc++;
2652
2653 return;
2654 }
2655 /* Count the errors, if there were any */
2656 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2657 stats->rx_length_errors++;
2658
2659 if (status & RXBD_LARGE)
2660 estats->rx_large++;
2661 else
2662 estats->rx_short++;
2663 }
2664 if (status & RXBD_NONOCTET) {
2665 stats->rx_frame_errors++;
2666 estats->rx_nonoctet++;
2667 }
2668 if (status & RXBD_CRCERR) {
2669 estats->rx_crcerr++;
2670 stats->rx_crc_errors++;
2671 }
2672 if (status & RXBD_OVERRUN) {
2673 estats->rx_overrun++;
2674 stats->rx_crc_errors++;
2675 }
2676 }
2677
2678 irqreturn_t gfar_receive(int irq, void *grp_id)
2679 {
2680 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2681 return IRQ_HANDLED;
2682 }
2683
2684 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2685 {
2686 /* If valid headers were found, and valid sums
2687 * were verified, then we tell the kernel that no
2688 * checksumming is necessary. Otherwise, it is [FIXME]
2689 */
2690 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2691 skb->ip_summed = CHECKSUM_UNNECESSARY;
2692 else
2693 skb_checksum_none_assert(skb);
2694 }
2695
2696
2697 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2698 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2699 int amount_pull, struct napi_struct *napi)
2700 {
2701 struct gfar_private *priv = netdev_priv(dev);
2702 struct rxfcb *fcb = NULL;
2703
2704 gro_result_t ret;
2705
2706 /* fcb is at the beginning if exists */
2707 fcb = (struct rxfcb *)skb->data;
2708
2709 /* Remove the FCB from the skb
2710 * Remove the padded bytes, if there are any
2711 */
2712 if (amount_pull) {
2713 skb_record_rx_queue(skb, fcb->rq);
2714 skb_pull(skb, amount_pull);
2715 }
2716
2717 /* Get receive timestamp from the skb */
2718 if (priv->hwts_rx_en) {
2719 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2720 u64 *ns = (u64 *) skb->data;
2721
2722 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2723 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2724 }
2725
2726 if (priv->padding)
2727 skb_pull(skb, priv->padding);
2728
2729 if (dev->features & NETIF_F_RXCSUM)
2730 gfar_rx_checksum(skb, fcb);
2731
2732 /* Tell the skb what kind of packet this is */
2733 skb->protocol = eth_type_trans(skb, dev);
2734
2735 /* There's need to check for NETIF_F_HW_VLAN_RX here.
2736 * Even if vlan rx accel is disabled, on some chips
2737 * RXFCB_VLN is pseudo randomly set.
2738 */
2739 if (dev->features & NETIF_F_HW_VLAN_RX &&
2740 fcb->flags & RXFCB_VLN)
2741 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2742
2743 /* Send the packet up the stack */
2744 ret = napi_gro_receive(napi, skb);
2745
2746 if (GRO_DROP == ret)
2747 priv->extra_stats.kernel_dropped++;
2748
2749 return 0;
2750 }
2751
2752 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2753 * until the budget/quota has been reached. Returns the number
2754 * of frames handled
2755 */
2756 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2757 {
2758 struct net_device *dev = rx_queue->dev;
2759 struct rxbd8 *bdp, *base;
2760 struct sk_buff *skb;
2761 int pkt_len;
2762 int amount_pull;
2763 int howmany = 0;
2764 struct gfar_private *priv = netdev_priv(dev);
2765
2766 /* Get the first full descriptor */
2767 bdp = rx_queue->cur_rx;
2768 base = rx_queue->rx_bd_base;
2769
2770 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2771
2772 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2773 struct sk_buff *newskb;
2774
2775 rmb();
2776
2777 /* Add another skb for the future */
2778 newskb = gfar_new_skb(dev);
2779
2780 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2781
2782 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2783 priv->rx_buffer_size, DMA_FROM_DEVICE);
2784
2785 if (unlikely(!(bdp->status & RXBD_ERR) &&
2786 bdp->length > priv->rx_buffer_size))
2787 bdp->status = RXBD_LARGE;
2788
2789 /* We drop the frame if we failed to allocate a new buffer */
2790 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2791 bdp->status & RXBD_ERR)) {
2792 count_errors(bdp->status, dev);
2793
2794 if (unlikely(!newskb))
2795 newskb = skb;
2796 else if (skb)
2797 dev_kfree_skb(skb);
2798 } else {
2799 /* Increment the number of packets */
2800 rx_queue->stats.rx_packets++;
2801 howmany++;
2802
2803 if (likely(skb)) {
2804 pkt_len = bdp->length - ETH_FCS_LEN;
2805 /* Remove the FCS from the packet length */
2806 skb_put(skb, pkt_len);
2807 rx_queue->stats.rx_bytes += pkt_len;
2808 skb_record_rx_queue(skb, rx_queue->qindex);
2809 gfar_process_frame(dev, skb, amount_pull,
2810 &rx_queue->grp->napi);
2811
2812 } else {
2813 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2814 rx_queue->stats.rx_dropped++;
2815 priv->extra_stats.rx_skbmissing++;
2816 }
2817
2818 }
2819
2820 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2821
2822 /* Setup the new bdp */
2823 gfar_new_rxbdp(rx_queue, bdp, newskb);
2824
2825 /* Update to the next pointer */
2826 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2827
2828 /* update to point at the next skb */
2829 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2830 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2831 }
2832
2833 /* Update the current rxbd pointer to be the next one */
2834 rx_queue->cur_rx = bdp;
2835
2836 return howmany;
2837 }
2838
2839 static int gfar_poll(struct napi_struct *napi, int budget)
2840 {
2841 struct gfar_priv_grp *gfargrp =
2842 container_of(napi, struct gfar_priv_grp, napi);
2843 struct gfar_private *priv = gfargrp->priv;
2844 struct gfar __iomem *regs = gfargrp->regs;
2845 struct gfar_priv_tx_q *tx_queue = NULL;
2846 struct gfar_priv_rx_q *rx_queue = NULL;
2847 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2848 int tx_cleaned = 0, i, left_over_budget = budget;
2849 unsigned long serviced_queues = 0;
2850 int num_queues = 0;
2851
2852 num_queues = gfargrp->num_rx_queues;
2853 budget_per_queue = budget/num_queues;
2854
2855 /* Clear IEVENT, so interrupts aren't called again
2856 * because of the packets that have already arrived
2857 */
2858 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2859
2860 while (num_queues && left_over_budget) {
2861 budget_per_queue = left_over_budget/num_queues;
2862 left_over_budget = 0;
2863
2864 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2865 if (test_bit(i, &serviced_queues))
2866 continue;
2867 rx_queue = priv->rx_queue[i];
2868 tx_queue = priv->tx_queue[rx_queue->qindex];
2869
2870 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2871 rx_cleaned_per_queue =
2872 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2873 rx_cleaned += rx_cleaned_per_queue;
2874 if (rx_cleaned_per_queue < budget_per_queue) {
2875 left_over_budget = left_over_budget +
2876 (budget_per_queue -
2877 rx_cleaned_per_queue);
2878 set_bit(i, &serviced_queues);
2879 num_queues--;
2880 }
2881 }
2882 }
2883
2884 if (tx_cleaned)
2885 return budget;
2886
2887 if (rx_cleaned < budget) {
2888 napi_complete(napi);
2889
2890 /* Clear the halt bit in RSTAT */
2891 gfar_write(&regs->rstat, gfargrp->rstat);
2892
2893 gfar_write(&regs->imask, IMASK_DEFAULT);
2894
2895 /* If we are coalescing interrupts, update the timer
2896 * Otherwise, clear it
2897 */
2898 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2899 gfargrp->tx_bit_map);
2900 }
2901
2902 return rx_cleaned;
2903 }
2904
2905 #ifdef CONFIG_NET_POLL_CONTROLLER
2906 /* Polling 'interrupt' - used by things like netconsole to send skbs
2907 * without having to re-enable interrupts. It's not called while
2908 * the interrupt routine is executing.
2909 */
2910 static void gfar_netpoll(struct net_device *dev)
2911 {
2912 struct gfar_private *priv = netdev_priv(dev);
2913 int i;
2914
2915 /* If the device has multiple interrupts, run tx/rx */
2916 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2917 for (i = 0; i < priv->num_grps; i++) {
2918 disable_irq(priv->gfargrp[i].interruptTransmit);
2919 disable_irq(priv->gfargrp[i].interruptReceive);
2920 disable_irq(priv->gfargrp[i].interruptError);
2921 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2922 &priv->gfargrp[i]);
2923 enable_irq(priv->gfargrp[i].interruptError);
2924 enable_irq(priv->gfargrp[i].interruptReceive);
2925 enable_irq(priv->gfargrp[i].interruptTransmit);
2926 }
2927 } else {
2928 for (i = 0; i < priv->num_grps; i++) {
2929 disable_irq(priv->gfargrp[i].interruptTransmit);
2930 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2931 &priv->gfargrp[i]);
2932 enable_irq(priv->gfargrp[i].interruptTransmit);
2933 }
2934 }
2935 }
2936 #endif
2937
2938 /* The interrupt handler for devices with one interrupt */
2939 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2940 {
2941 struct gfar_priv_grp *gfargrp = grp_id;
2942
2943 /* Save ievent for future reference */
2944 u32 events = gfar_read(&gfargrp->regs->ievent);
2945
2946 /* Check for reception */
2947 if (events & IEVENT_RX_MASK)
2948 gfar_receive(irq, grp_id);
2949
2950 /* Check for transmit completion */
2951 if (events & IEVENT_TX_MASK)
2952 gfar_transmit(irq, grp_id);
2953
2954 /* Check for errors */
2955 if (events & IEVENT_ERR_MASK)
2956 gfar_error(irq, grp_id);
2957
2958 return IRQ_HANDLED;
2959 }
2960
2961 /* Called every time the controller might need to be made
2962 * aware of new link state. The PHY code conveys this
2963 * information through variables in the phydev structure, and this
2964 * function converts those variables into the appropriate
2965 * register values, and can bring down the device if needed.
2966 */
2967 static void adjust_link(struct net_device *dev)
2968 {
2969 struct gfar_private *priv = netdev_priv(dev);
2970 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2971 unsigned long flags;
2972 struct phy_device *phydev = priv->phydev;
2973 int new_state = 0;
2974
2975 local_irq_save(flags);
2976 lock_tx_qs(priv);
2977
2978 if (phydev->link) {
2979 u32 tempval = gfar_read(&regs->maccfg2);
2980 u32 ecntrl = gfar_read(&regs->ecntrl);
2981
2982 /* Now we make sure that we can be in full duplex mode.
2983 * If not, we operate in half-duplex mode.
2984 */
2985 if (phydev->duplex != priv->oldduplex) {
2986 new_state = 1;
2987 if (!(phydev->duplex))
2988 tempval &= ~(MACCFG2_FULL_DUPLEX);
2989 else
2990 tempval |= MACCFG2_FULL_DUPLEX;
2991
2992 priv->oldduplex = phydev->duplex;
2993 }
2994
2995 if (phydev->speed != priv->oldspeed) {
2996 new_state = 1;
2997 switch (phydev->speed) {
2998 case 1000:
2999 tempval =
3000 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3001
3002 ecntrl &= ~(ECNTRL_R100);
3003 break;
3004 case 100:
3005 case 10:
3006 tempval =
3007 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3008
3009 /* Reduced mode distinguishes
3010 * between 10 and 100
3011 */
3012 if (phydev->speed == SPEED_100)
3013 ecntrl |= ECNTRL_R100;
3014 else
3015 ecntrl &= ~(ECNTRL_R100);
3016 break;
3017 default:
3018 netif_warn(priv, link, dev,
3019 "Ack! Speed (%d) is not 10/100/1000!\n",
3020 phydev->speed);
3021 break;
3022 }
3023
3024 priv->oldspeed = phydev->speed;
3025 }
3026
3027 gfar_write(&regs->maccfg2, tempval);
3028 gfar_write(&regs->ecntrl, ecntrl);
3029
3030 if (!priv->oldlink) {
3031 new_state = 1;
3032 priv->oldlink = 1;
3033 }
3034 } else if (priv->oldlink) {
3035 new_state = 1;
3036 priv->oldlink = 0;
3037 priv->oldspeed = 0;
3038 priv->oldduplex = -1;
3039 }
3040
3041 if (new_state && netif_msg_link(priv))
3042 phy_print_status(phydev);
3043 unlock_tx_qs(priv);
3044 local_irq_restore(flags);
3045 }
3046
3047 /* Update the hash table based on the current list of multicast
3048 * addresses we subscribe to. Also, change the promiscuity of
3049 * the device based on the flags (this function is called
3050 * whenever dev->flags is changed
3051 */
3052 static void gfar_set_multi(struct net_device *dev)
3053 {
3054 struct netdev_hw_addr *ha;
3055 struct gfar_private *priv = netdev_priv(dev);
3056 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3057 u32 tempval;
3058
3059 if (dev->flags & IFF_PROMISC) {
3060 /* Set RCTRL to PROM */
3061 tempval = gfar_read(&regs->rctrl);
3062 tempval |= RCTRL_PROM;
3063 gfar_write(&regs->rctrl, tempval);
3064 } else {
3065 /* Set RCTRL to not PROM */
3066 tempval = gfar_read(&regs->rctrl);
3067 tempval &= ~(RCTRL_PROM);
3068 gfar_write(&regs->rctrl, tempval);
3069 }
3070
3071 if (dev->flags & IFF_ALLMULTI) {
3072 /* Set the hash to rx all multicast frames */
3073 gfar_write(&regs->igaddr0, 0xffffffff);
3074 gfar_write(&regs->igaddr1, 0xffffffff);
3075 gfar_write(&regs->igaddr2, 0xffffffff);
3076 gfar_write(&regs->igaddr3, 0xffffffff);
3077 gfar_write(&regs->igaddr4, 0xffffffff);
3078 gfar_write(&regs->igaddr5, 0xffffffff);
3079 gfar_write(&regs->igaddr6, 0xffffffff);
3080 gfar_write(&regs->igaddr7, 0xffffffff);
3081 gfar_write(&regs->gaddr0, 0xffffffff);
3082 gfar_write(&regs->gaddr1, 0xffffffff);
3083 gfar_write(&regs->gaddr2, 0xffffffff);
3084 gfar_write(&regs->gaddr3, 0xffffffff);
3085 gfar_write(&regs->gaddr4, 0xffffffff);
3086 gfar_write(&regs->gaddr5, 0xffffffff);
3087 gfar_write(&regs->gaddr6, 0xffffffff);
3088 gfar_write(&regs->gaddr7, 0xffffffff);
3089 } else {
3090 int em_num;
3091 int idx;
3092
3093 /* zero out the hash */
3094 gfar_write(&regs->igaddr0, 0x0);
3095 gfar_write(&regs->igaddr1, 0x0);
3096 gfar_write(&regs->igaddr2, 0x0);
3097 gfar_write(&regs->igaddr3, 0x0);
3098 gfar_write(&regs->igaddr4, 0x0);
3099 gfar_write(&regs->igaddr5, 0x0);
3100 gfar_write(&regs->igaddr6, 0x0);
3101 gfar_write(&regs->igaddr7, 0x0);
3102 gfar_write(&regs->gaddr0, 0x0);
3103 gfar_write(&regs->gaddr1, 0x0);
3104 gfar_write(&regs->gaddr2, 0x0);
3105 gfar_write(&regs->gaddr3, 0x0);
3106 gfar_write(&regs->gaddr4, 0x0);
3107 gfar_write(&regs->gaddr5, 0x0);
3108 gfar_write(&regs->gaddr6, 0x0);
3109 gfar_write(&regs->gaddr7, 0x0);
3110
3111 /* If we have extended hash tables, we need to
3112 * clear the exact match registers to prepare for
3113 * setting them
3114 */
3115 if (priv->extended_hash) {
3116 em_num = GFAR_EM_NUM + 1;
3117 gfar_clear_exact_match(dev);
3118 idx = 1;
3119 } else {
3120 idx = 0;
3121 em_num = 0;
3122 }
3123
3124 if (netdev_mc_empty(dev))
3125 return;
3126
3127 /* Parse the list, and set the appropriate bits */
3128 netdev_for_each_mc_addr(ha, dev) {
3129 if (idx < em_num) {
3130 gfar_set_mac_for_addr(dev, idx, ha->addr);
3131 idx++;
3132 } else
3133 gfar_set_hash_for_addr(dev, ha->addr);
3134 }
3135 }
3136 }
3137
3138
3139 /* Clears each of the exact match registers to zero, so they
3140 * don't interfere with normal reception
3141 */
3142 static void gfar_clear_exact_match(struct net_device *dev)
3143 {
3144 int idx;
3145 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3146
3147 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3148 gfar_set_mac_for_addr(dev, idx, zero_arr);
3149 }
3150
3151 /* Set the appropriate hash bit for the given addr */
3152 /* The algorithm works like so:
3153 * 1) Take the Destination Address (ie the multicast address), and
3154 * do a CRC on it (little endian), and reverse the bits of the
3155 * result.
3156 * 2) Use the 8 most significant bits as a hash into a 256-entry
3157 * table. The table is controlled through 8 32-bit registers:
3158 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3159 * gaddr7. This means that the 3 most significant bits in the
3160 * hash index which gaddr register to use, and the 5 other bits
3161 * indicate which bit (assuming an IBM numbering scheme, which
3162 * for PowerPC (tm) is usually the case) in the register holds
3163 * the entry.
3164 */
3165 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3166 {
3167 u32 tempval;
3168 struct gfar_private *priv = netdev_priv(dev);
3169 u32 result = ether_crc(ETH_ALEN, addr);
3170 int width = priv->hash_width;
3171 u8 whichbit = (result >> (32 - width)) & 0x1f;
3172 u8 whichreg = result >> (32 - width + 5);
3173 u32 value = (1 << (31-whichbit));
3174
3175 tempval = gfar_read(priv->hash_regs[whichreg]);
3176 tempval |= value;
3177 gfar_write(priv->hash_regs[whichreg], tempval);
3178 }
3179
3180
3181 /* There are multiple MAC Address register pairs on some controllers
3182 * This function sets the numth pair to a given address
3183 */
3184 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3185 const u8 *addr)
3186 {
3187 struct gfar_private *priv = netdev_priv(dev);
3188 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3189 int idx;
3190 char tmpbuf[ETH_ALEN];
3191 u32 tempval;
3192 u32 __iomem *macptr = &regs->macstnaddr1;
3193
3194 macptr += num*2;
3195
3196 /* Now copy it into the mac registers backwards, cuz
3197 * little endian is silly
3198 */
3199 for (idx = 0; idx < ETH_ALEN; idx++)
3200 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3201
3202 gfar_write(macptr, *((u32 *) (tmpbuf)));
3203
3204 tempval = *((u32 *) (tmpbuf + 4));
3205
3206 gfar_write(macptr+1, tempval);
3207 }
3208
3209 /* GFAR error interrupt handler */
3210 static irqreturn_t gfar_error(int irq, void *grp_id)
3211 {
3212 struct gfar_priv_grp *gfargrp = grp_id;
3213 struct gfar __iomem *regs = gfargrp->regs;
3214 struct gfar_private *priv= gfargrp->priv;
3215 struct net_device *dev = priv->ndev;
3216
3217 /* Save ievent for future reference */
3218 u32 events = gfar_read(&regs->ievent);
3219
3220 /* Clear IEVENT */
3221 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3222
3223 /* Magic Packet is not an error. */
3224 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3225 (events & IEVENT_MAG))
3226 events &= ~IEVENT_MAG;
3227
3228 /* Hmm... */
3229 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3230 netdev_dbg(dev,
3231 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3232 events, gfar_read(&regs->imask));
3233
3234 /* Update the error counters */
3235 if (events & IEVENT_TXE) {
3236 dev->stats.tx_errors++;
3237
3238 if (events & IEVENT_LC)
3239 dev->stats.tx_window_errors++;
3240 if (events & IEVENT_CRL)
3241 dev->stats.tx_aborted_errors++;
3242 if (events & IEVENT_XFUN) {
3243 unsigned long flags;
3244
3245 netif_dbg(priv, tx_err, dev,
3246 "TX FIFO underrun, packet dropped\n");
3247 dev->stats.tx_dropped++;
3248 priv->extra_stats.tx_underrun++;
3249
3250 local_irq_save(flags);
3251 lock_tx_qs(priv);
3252
3253 /* Reactivate the Tx Queues */
3254 gfar_write(&regs->tstat, gfargrp->tstat);
3255
3256 unlock_tx_qs(priv);
3257 local_irq_restore(flags);
3258 }
3259 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3260 }
3261 if (events & IEVENT_BSY) {
3262 dev->stats.rx_errors++;
3263 priv->extra_stats.rx_bsy++;
3264
3265 gfar_receive(irq, grp_id);
3266
3267 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3268 gfar_read(&regs->rstat));
3269 }
3270 if (events & IEVENT_BABR) {
3271 dev->stats.rx_errors++;
3272 priv->extra_stats.rx_babr++;
3273
3274 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3275 }
3276 if (events & IEVENT_EBERR) {
3277 priv->extra_stats.eberr++;
3278 netif_dbg(priv, rx_err, dev, "bus error\n");
3279 }
3280 if (events & IEVENT_RXC)
3281 netif_dbg(priv, rx_status, dev, "control frame\n");
3282
3283 if (events & IEVENT_BABT) {
3284 priv->extra_stats.tx_babt++;
3285 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3286 }
3287 return IRQ_HANDLED;
3288 }
3289
3290 static struct of_device_id gfar_match[] =
3291 {
3292 {
3293 .type = "network",
3294 .compatible = "gianfar",
3295 },
3296 {
3297 .compatible = "fsl,etsec2",
3298 },
3299 {},
3300 };
3301 MODULE_DEVICE_TABLE(of, gfar_match);
3302
3303 /* Structure for a device driver */
3304 static struct platform_driver gfar_driver = {
3305 .driver = {
3306 .name = "fsl-gianfar",
3307 .owner = THIS_MODULE,
3308 .pm = GFAR_PM_OPS,
3309 .of_match_table = gfar_match,
3310 },
3311 .probe = gfar_probe,
3312 .remove = gfar_remove,
3313 };
3314
3315 module_platform_driver(gfar_driver);
CJK support for tty framebuffer vt