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ath9k: Set IEEE80211_TX_CTL_RATE_CTRL_PROBE in rate control for probe rate
[linux-2.6/cjktty.git] / drivers / staging / rt2860 / rt_ate.c
blobf3316ec0b1563c8271e40cee1d2b97383ba2a6d1
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26 */
27
28 #include "rt_config.h"
29
30 #ifdef RALINK_ATE
31 UCHAR TemplateFrame[24] = {0x08/* Data type */,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xAA,0xBB,0x12,0x34,0x56,0x00,0x11,0x22,0xAA,0xBB,0xCC,0x00,0x00}; // 802.11 MAC Header, Type:Data, Length:24bytes
32 extern RTMP_RF_REGS RF2850RegTable[];
33 extern UCHAR NUM_OF_2850_CHNL;
34
35 static CHAR CCKRateTable[] = {0, 1, 2, 3, 8, 9, 10, 11, -1}; /* CCK Mode. */
36 static CHAR OFDMRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, -1}; /* OFDM Mode. */
37 static CHAR HTMIXRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}; /* HT Mix Mode. */
38
39 static INT TxDmaBusy(
40 IN PRTMP_ADAPTER pAd);
41
42 static INT RxDmaBusy(
43 IN PRTMP_ADAPTER pAd);
44
45 static VOID RtmpDmaEnable(
46 IN PRTMP_ADAPTER pAd,
47 IN INT Enable);
48
49 static VOID BbpSoftReset(
50 IN PRTMP_ADAPTER pAd);
51
52 static VOID RtmpRfIoWrite(
53 IN PRTMP_ADAPTER pAd);
54
55 static INT ATESetUpFrame(
56 IN PRTMP_ADAPTER pAd,
57 IN UINT32 TxIdx);
58
59 static INT ATETxPwrHandler(
60 IN PRTMP_ADAPTER pAd,
61 IN char index);
62
63 static INT ATECmdHandler(
64 IN PRTMP_ADAPTER pAd,
65 IN PUCHAR arg);
66
67 static int CheckMCSValid(
68 IN UCHAR Mode,
69 IN UCHAR Mcs);
70
71 #ifdef RT2860
72 static VOID ATEWriteTxWI(
73 IN PRTMP_ADAPTER pAd,
74 IN PTXWI_STRUC pOutTxWI,
75 IN BOOLEAN FRAG,
76 IN BOOLEAN CFACK,
77 IN BOOLEAN InsTimestamp,
78 IN BOOLEAN AMPDU,
79 IN BOOLEAN Ack,
80 IN BOOLEAN NSeq, // HW new a sequence.
81 IN UCHAR BASize,
82 IN UCHAR WCID,
83 IN ULONG Length,
84 IN UCHAR PID,
85 IN UCHAR TID,
86 IN UCHAR TxRate,
87 IN UCHAR Txopmode,
88 IN BOOLEAN CfAck,
89 IN HTTRANSMIT_SETTING *pTransmit);
90 #endif // RT2860 //
91
92
93 static VOID SetJapanFilter(
94 IN PRTMP_ADAPTER pAd);
95
96 /*=========================end of prototype=========================*/
97
98 #ifdef RT2860
99 static INT TxDmaBusy(
100 IN PRTMP_ADAPTER pAd)
101 {
102 INT result;
103 WPDMA_GLO_CFG_STRUC GloCfg;
104
105 RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); // disable DMA
106 if (GloCfg.field.TxDMABusy)
107 result = 1;
108 else
109 result = 0;
110
111 return result;
112 }
113
114 static INT RxDmaBusy(
115 IN PRTMP_ADAPTER pAd)
116 {
117 INT result;
118 WPDMA_GLO_CFG_STRUC GloCfg;
119
120 RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); // disable DMA
121 if (GloCfg.field.RxDMABusy)
122 result = 1;
123 else
124 result = 0;
125
126 return result;
127 }
128
129 static VOID RtmpDmaEnable(
130 IN PRTMP_ADAPTER pAd,
131 IN INT Enable)
132 {
133 BOOLEAN value;
134 ULONG WaitCnt;
135 WPDMA_GLO_CFG_STRUC GloCfg;
136
137 value = Enable > 0 ? 1 : 0;
138
139 // check DMA is in busy mode.
140 WaitCnt = 0;
141 while (TxDmaBusy(pAd) || RxDmaBusy(pAd))
142 {
143 RTMPusecDelay(10);
144 if (WaitCnt++ > 100)
145 break;
146 }
147
148 RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); // disable DMA
149 GloCfg.field.EnableTxDMA = value;
150 GloCfg.field.EnableRxDMA = value;
151 RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); // abort all TX rings
152 RTMPusecDelay(5000);
153
154 return;
155 }
156 #endif // RT2860 //
157
158
159 static VOID BbpSoftReset(
160 IN PRTMP_ADAPTER pAd)
161 {
162 UCHAR BbpData = 0;
163
164 // Soft reset, set BBP R21 bit0=1->0
165 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData);
166 BbpData |= 0x00000001; //set bit0=1
167 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData);
168
169 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData);
170 BbpData &= ~(0x00000001); //set bit0=0
171 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData);
172
173 return;
174 }
175
176 static VOID RtmpRfIoWrite(
177 IN PRTMP_ADAPTER pAd)
178 {
179 // Set RF value 1's set R3[bit2] = [0]
180 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
181 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
182 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
183 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
184
185 RTMPusecDelay(200);
186
187 // Set RF value 2's set R3[bit2] = [1]
188 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
189 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
190 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04));
191 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
192
193 RTMPusecDelay(200);
194
195 // Set RF value 3's set R3[bit2] = [0]
196 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
197 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
198 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
199 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
200
201 return;
202 }
203
204 static int CheckMCSValid(
205 UCHAR Mode,
206 UCHAR Mcs)
207 {
208 int i;
209 PCHAR pRateTab;
210
211 switch(Mode)
212 {
213 case 0:
214 pRateTab = CCKRateTable;
215 break;
216 case 1:
217 pRateTab = OFDMRateTable;
218 break;
219 case 2:
220 case 3:
221 pRateTab = HTMIXRateTable;
222 break;
223 default:
224 ATEDBGPRINT(RT_DEBUG_ERROR, ("unrecognizable Tx Mode %d\n", Mode));
225 return -1;
226 break;
227 }
228
229 i = 0;
230 while(pRateTab[i] != -1)
231 {
232 if (pRateTab[i] == Mcs)
233 return 0;
234 i++;
235 }
236
237 return -1;
238 }
239
240 #if 1
241 static INT ATETxPwrHandler(
242 IN PRTMP_ADAPTER pAd,
243 IN char index)
244 {
245 ULONG R;
246 CHAR TxPower;
247 UCHAR Bbp94 = 0;
248 BOOLEAN bPowerReduce = FALSE;
249
250 #ifdef RALINK_28xx_QA
251 if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
252 {
253 /* When QA is used for Tx, pAd->ate.TxPower0/1 and real tx power
254 ** are not synchronized.
255 */
256 /*
257 pAd->ate.TxPower0 = pAd->LatchRfRegs.xxx;
258 pAd->ate.TxPower1 = pAd->LatchRfRegs.xxx;
259 */
260 return 0;
261 }
262 else
263 #endif // RALINK_28xx_QA //
264 {
265 TxPower = index == 0 ? pAd->ate.TxPower0 : pAd->ate.TxPower1;
266
267 if (pAd->ate.Channel <= 14)
268 {
269 if (TxPower > 31)
270 {
271 //
272 // R3, R4 can't large than 31 (0x24), 31 ~ 36 used by BBP 94
273 //
274 R = 31;
275 if (TxPower <= 36)
276 Bbp94 = BBPR94_DEFAULT + (UCHAR)(TxPower - 31);
277 }
278 else if (TxPower < 0)
279 {
280 //
281 // R3, R4 can't less than 0, -1 ~ -6 used by BBP 94
282 //
283 R = 0;
284 if (TxPower >= -6)
285 Bbp94 = BBPR94_DEFAULT + TxPower;
286 }
287 else
288 {
289 // 0 ~ 31
290 R = (ULONG) TxPower;
291 Bbp94 = BBPR94_DEFAULT;
292 }
293
294 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%ld, BBP_R94=%d)\n", __func__, TxPower, R, Bbp94));
295 }
296 else// 5.5 GHz
297 {
298 if (TxPower > 15)
299 {
300 //
301 // R3, R4 can't large than 15 (0x0F)
302 //
303 R = 15;
304 }
305 else if (TxPower < 0)
306 {
307 //
308 // R3, R4 can't less than 0
309 //
310 // -1 ~ -7
311 ASSERT((TxPower >= -7));
312 R = (ULONG)(TxPower + 7);
313 bPowerReduce = TRUE;
314 }
315 else
316 {
317 // 0 ~ 15
318 R = (ULONG) TxPower;
319 }
320
321 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%lu)\n", __func__, TxPower, R));
322 }
323
324 if (pAd->ate.Channel <= 14)
325 {
326 if (index == 0)
327 {
328 R = R << 9; // shift TX power control to correct RF(R3) register bit position
329 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
330 pAd->LatchRfRegs.R3 = R;
331 }
332 else
333 {
334 R = R << 6; // shift TX power control to correct RF(R4) register bit position
335 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
336 pAd->LatchRfRegs.R4 = R;
337 }
338 }
339 else// 5.5GHz
340 {
341 if (bPowerReduce == FALSE)
342 {
343 if (index == 0)
344 {
345 R = (R << 10) | (1 << 9); // shift TX power control to correct RF(R3) register bit position
346 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
347 pAd->LatchRfRegs.R3 = R;
348 }
349 else
350 {
351 R = (R << 7) | (1 << 6); // shift TX power control to correct RF(R4) register bit position
352 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
353 pAd->LatchRfRegs.R4 = R;
354 }
355 }
356 else
357 {
358 if (index == 0)
359 {
360 R = (R << 10); // shift TX power control to correct RF(R3) register bit position
361 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
362
363 /* Clear bit 9 of R3 to reduce 7dB. */
364 pAd->LatchRfRegs.R3 = (R & (~(1 << 9)));
365 }
366 else
367 {
368 R = (R << 7); // shift TX power control to correct RF(R4) register bit position
369 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
370
371 /* Clear bit 6 of R4 to reduce 7dB. */
372 pAd->LatchRfRegs.R4 = (R & (~(1 << 6)));
373 }
374 }
375 }
376
377 RtmpRfIoWrite(pAd);
378
379 return 0;
380 }
381 }
382 #else// 1 //
383 static INT ATETxPwrHandler(
384 IN PRTMP_ADAPTER pAd,
385 IN char index)
386 {
387 ULONG R;
388 CHAR TxPower;
389 UCHAR Bbp94 = 0;
390
391 #ifdef RALINK_28xx_QA
392 if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
393 {
394 // TODO: how to get current TxPower0/1 from pAd->LatchRfRegs ?
395 /* When QA is used for Tx, pAd->ate.TxPower0/1 and real tx power
396 ** are not synchronized.
397 */
398 /*
399 pAd->ate.TxPower0 = pAd->LatchRfRegs.xxx;
400 pAd->ate.TxPower1 = pAd->LatchRfRegs.xxx;
401 */
402 return 0;
403 }
404 else
405 #endif // RALINK_28xx_QA //
406 {
407 TxPower = index == 0 ? pAd->ate.TxPower0 : pAd->ate.TxPower1;
408
409 if (TxPower > 31)
410 {
411 //
412 // R3, R4 can't large than 36 (0x24), 31 ~ 36 used by BBP 94
413 //
414 R = 31;
415 if (TxPower <= 36)
416 Bbp94 = BBPR94_DEFAULT + (UCHAR)(TxPower - 31);
417 }
418 else if (TxPower < 0)
419 {
420 //
421 // R3, R4 can't less than 0, -1 ~ -6 used by BBP 94
422 //
423 R = 0;
424 if (TxPower >= -6)
425 Bbp94 = BBPR94_DEFAULT + TxPower;
426 }
427 else
428 {
429 // 0 ~ 31
430 R = (ULONG) TxPower;
431 Bbp94 = BBPR94_DEFAULT;
432 }
433
434 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R3=%ld, BBP_R94=%d)\n", __func__, TxPower, R, Bbp94));
435
436 if (pAd->ate.Channel <= 14)
437 {
438 if (index == 0)
439 {
440 R = R << 9; // shift TX power control to correct RF(R3) register bit position
441 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
442 pAd->LatchRfRegs.R3 = R;
443 }
444 else
445 {
446 R = R << 6; // shift TX power control to correct RF(R4) register bit position
447 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
448 pAd->LatchRfRegs.R4 = R;
449 }
450 }
451 else
452 {
453 if (index == 0)
454 {
455 R = (R << 10) | (1 << 9); // shift TX power control to correct RF(R3) register bit position
456 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
457 pAd->LatchRfRegs.R3 = R;
458 }
459 else
460 {
461 R = (R << 7) | (1 << 6); // shift TX power control to correct RF(R4) register bit position
462 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
463 pAd->LatchRfRegs.R4 = R;
464 }
465 }
466
467 RtmpRfIoWrite(pAd);
468
469 return 0;
470 }
471 }
472 #endif // 1 //
473 /*
474 ==========================================================================
475 Description:
476 Set ATE operation mode to
477 0. ATESTART = Start ATE Mode
478 1. ATESTOP = Stop ATE Mode
479 2. TXCONT = Continuous Transmit
480 3. TXCARR = Transmit Carrier
481 4. TXFRAME = Transmit Frames
482 5. RXFRAME = Receive Frames
483 #ifdef RALINK_28xx_QA
484 6. TXSTOP = Stop Any Type of Transmition
485 7. RXSTOP = Stop Receiving Frames
486 #endif // RALINK_28xx_QA //
487 Return:
488 TRUE if all parameters are OK, FALSE otherwise
489 ==========================================================================
490 */
491 #ifdef RT2860
492 static INT ATECmdHandler(
493 IN PRTMP_ADAPTER pAd,
494 IN PUCHAR arg)
495 {
496 UINT32 Value = 0;
497 UCHAR BbpData;
498 UINT32 MacData = 0;
499 PTXD_STRUC pTxD;
500 INT index;
501 UINT i=0, atemode;
502 PRXD_STRUC pRxD;
503 PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
504 #ifndef UCOS
505 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
506 #endif // UCOS //
507 #ifdef RT_BIG_ENDIAN
508 PTXD_STRUC pDestTxD;
509 TXD_STRUC TxD;
510 #endif
511 ATEDBGPRINT(RT_DEBUG_TRACE, ("===> ATECmdHandler()\n"));
512
513 ATEAsicSwitchChannel(pAd);
514 AsicLockChannel(pAd, pAd->ate.Channel);
515
516 RTMPusecDelay(5000);
517
518 // read MAC_SYS_CTRL and backup MAC_SYS_CTRL value.
519 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
520
521 // Default value in BBP R22 is 0x0.
522 BbpData = 0;
523
524 // clean bit4 to stop continuous Tx production test.
525 MacData &= 0xFFFFFFEF;
526
527 if (!strcmp(arg, "ATESTART")) //Enter ATE mode and set Tx/Rx Idle
528 {
529 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: ATESTART\n"));
530
531 #ifndef UCOS
532 // check if we have removed the firmware
533 if (!(ATE_ON(pAd)))
534 {
535 NICEraseFirmware(pAd);
536 }
537 #endif // !UCOS //
538 atemode = pAd->ate.Mode;
539 pAd->ate.Mode = ATE_START;
540 // pAd->ate.TxDoneCount = pAd->ate.TxCount;
541 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
542
543 if (atemode & ATE_TXCARR)
544 {
545 // No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0
546 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
547 BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
548 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
549 }
550 else if (atemode & ATE_TXCARRSUPP)
551 {
552 // No Cont. TX set BBP R22 bit7=0
553 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
554 BbpData &= ~(1 << 7); //set bit7=0
555 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
556
557 // No Carrier Suppression set BBP R24 bit0=0
558 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &BbpData);
559 BbpData &= 0xFFFFFFFE; //clear bit0
560 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, BbpData);
561 }
562 // We should free some resource which was allocated when ATE_TXFRAME , ATE_STOP, and ATE_TXCONT.
563 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
564 {
565 PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
566
567 if (atemode & ATE_TXCONT)
568 {
569 // No Cont. TX set BBP R22 bit7=0
570 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
571 BbpData &= ~(1 << 7); //set bit7=0
572 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
573 }
574 // Abort Tx, Rx DMA.
575 RtmpDmaEnable(pAd, 0);
576 for (i=0; i<TX_RING_SIZE; i++)
577 {
578 PNDIS_PACKET pPacket;
579
580 #ifndef RT_BIG_ENDIAN
581 pTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
582 #else
583 pDestTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
584 TxD = *pDestTxD;
585 pTxD = &TxD;
586 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
587 #endif
588 pTxD->DMADONE = 0;
589 pPacket = pTxRing->Cell[i].pNdisPacket;
590 if (pPacket)
591 {
592 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
593 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
594 }
595 //Always assign pNdisPacket as NULL after clear
596 pTxRing->Cell[i].pNdisPacket = NULL;
597
598 pPacket = pTxRing->Cell[i].pNextNdisPacket;
599 if (pPacket)
600 {
601 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
602 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
603 }
604 //Always assign pNextNdisPacket as NULL after clear
605 pTxRing->Cell[i].pNextNdisPacket = NULL;
606 #ifdef RT_BIG_ENDIAN
607 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
608 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
609 #endif
610 }
611 // Start Tx, RX DMA
612 RtmpDmaEnable(pAd, 1);
613 }
614 // reset Rx statistics.
615 pAd->ate.LastSNR0 = 0;
616 pAd->ate.LastSNR1 = 0;
617 pAd->ate.LastRssi0 = 0;
618 pAd->ate.LastRssi1 = 0;
619 pAd->ate.LastRssi2 = 0;
620 pAd->ate.AvgRssi0 = 0;
621 pAd->ate.AvgRssi1 = 0;
622 pAd->ate.AvgRssi2 = 0;
623 pAd->ate.AvgRssi0X8 = 0;
624 pAd->ate.AvgRssi1X8 = 0;
625 pAd->ate.AvgRssi2X8 = 0;
626 pAd->ate.NumOfAvgRssiSample = 0;
627
628 #ifdef RALINK_28xx_QA
629 // Tx frame
630 pAd->ate.bQATxStart = FALSE;
631 pAd->ate.bQARxStart = FALSE;
632 pAd->ate.seq = 0;
633
634 // counters
635 pAd->ate.U2M = 0;
636 pAd->ate.OtherData = 0;
637 pAd->ate.Beacon = 0;
638 pAd->ate.OtherCount = 0;
639 pAd->ate.TxAc0 = 0;
640 pAd->ate.TxAc1 = 0;
641 pAd->ate.TxAc2 = 0;
642 pAd->ate.TxAc3 = 0;
643 pAd->ate.TxHCCA = 0;
644 pAd->ate.TxMgmt = 0;
645 pAd->ate.RSSI0 = 0;
646 pAd->ate.RSSI1 = 0;
647 pAd->ate.RSSI2 = 0;
648 pAd->ate.SNR0 = 0;
649 pAd->ate.SNR1 = 0;
650
651 // control
652 pAd->ate.TxDoneCount = 0;
653 pAd->ate.TxStatus = 0; // task Tx status // 0 --> task is idle, 1 --> task is running
654 #endif // RALINK_28xx_QA //
655
656 // Soft reset BBP.
657 BbpSoftReset(pAd);
658
659
660 #ifdef CONFIG_STA_SUPPORT
661 //
662 // LinkDown() has "AsicDisableSync();" and "RTMP_BBP_IO_R/W8_BY_REG_ID();" inside.
663 //
664 // LinkDown(pAd, FALSE);
665 // AsicEnableBssSync(pAd);
666 #ifndef UCOS
667 netif_stop_queue(pAd->net_dev);
668 #endif // !UCOS //
669 //
670 // If we skip "LinkDown()", we should disable protection
671 // to prevent from sending out RTS or CTS-to-self.
672 //
673 ATEDisableAsicProtect(pAd);
674 RTMPStationStop(pAd);
675 #endif // CONFIG_STA_SUPPORT //
676
677 /* Disable Tx */
678 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
679 Value &= ~(1 << 2);
680 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
681
682 /* Disable Rx */
683 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
684 Value &= ~(1 << 3);
685 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
686 }
687 else if (!strcmp(arg, "ATESTOP"))
688 {
689 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: ATESTOP\n"));
690
691 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
692 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData); // recover the MAC_SYS_CTRL register back.
693
694 // Disable Tx, Rx
695 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
696 Value &= (0xfffffff3);
697 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
698
699 // Abort Tx, RX DMA.
700 RtmpDmaEnable(pAd, 0);
701
702 #ifndef UCOS
703 pAd->ate.bFWLoading = TRUE;
704 Status = NICLoadFirmware(pAd);
705 if (Status != NDIS_STATUS_SUCCESS)
706 {
707 ATEDBGPRINT(RT_DEBUG_ERROR, ("NICLoadFirmware failed, Status[=0x%08x]\n", Status));
708 return FALSE;
709 }
710 #endif // !UCOS //
711 pAd->ate.Mode = ATE_STOP;
712
713
714 #ifdef CONFIG_STA_SUPPORT
715 //
716 // Even the firmware has been loaded,
717 // we still could use ATE_BBP_IO_READ8_BY_REG_ID().
718 // But this is not suggested.
719 //
720 BbpSoftReset(pAd);
721 #endif // CONFIG_STA_SUPPORT //
722
723 NICDisableInterrupt(pAd);
724
725 NICInitializeAdapter(pAd, TRUE);
726
727
728 // Reinitialize Rx Ring before Rx DMA is enabled.
729 // The nightmare of >>>RxCoherent<<< was gone !
730 for (index = 0; index < RX_RING_SIZE; index++)
731 {
732 pRxD = (PRXD_STRUC) pAd->RxRing.Cell[index].AllocVa;
733 pRxD->DDONE = 0;
734 }
735
736 // We should read EEPROM for all cases.
737 NICReadEEPROMParameters(pAd, NULL);
738 NICInitAsicFromEEPROM(pAd);
739
740 AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
741 AsicLockChannel(pAd, pAd->CommonCfg.Channel);
742
743 //
744 // Enable Interrupt
745 //
746
747 //
748 // These steps are only for APAutoSelectChannel().
749 //
750 #if 0
751 //pAd->bStaFifoTest = TRUE;
752 pAd->int_enable_reg = ((DELAYINTMASK) | (RxINT|TxDataInt|TxMgmtInt)) & ~(0x03);
753 pAd->int_disable_mask = 0;
754 pAd->int_pending = 0;
755 #endif
756 RTMP_IO_WRITE32(pAd, INT_SOURCE_CSR, 0xffffffff); // clear garbage interrupts
757 NICEnableInterrupt(pAd);
758
759
760 /*=========================================================================*/
761 /* restore RX_FILTR_CFG */
762 #ifdef CONFIG_STA_SUPPORT
763 /* restore RX_FILTR_CFG due to that QA maybe set it to 0x3 */
764 RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, STANORMAL);
765 #endif // CONFIG_STA_SUPPORT //
766 /*=========================================================================*/
767
768 // Enable Tx
769 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
770 Value |= (1 << 2);
771 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
772
773 // Enable Tx, Rx DMA.
774 RtmpDmaEnable(pAd, 1);
775
776 // Enable Rx
777 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
778 Value |= (1 << 3);
779 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
780
781
782 #ifdef CONFIG_STA_SUPPORT
783 RTMPStationStart(pAd);
784 #endif // CONFIG_STA_SUPPORT //
785 #ifndef UCOS
786 netif_start_queue(pAd->net_dev);
787 #endif // !UCOS //
788 }
789 else if (!strcmp(arg, "TXCARR")) // Tx Carrier
790 {
791 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXCARR\n"));
792 pAd->ate.Mode |= ATE_TXCARR;
793
794 // QA has done the following steps if it is used.
795 if (pAd->ate.bQATxStart == FALSE)
796 {
797 // Soft reset BBP.
798 BbpSoftReset(pAd);
799
800 // Carrier Test set BBP R22 bit7=1, bit6=1, bit[5~0]=0x01
801 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
802 BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
803 BbpData |= 0x000000C1; //set bit7=1, bit6=1, bit[5~0]=0x01
804 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
805
806 // set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1
807 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
808 Value = Value | 0x00000010;
809 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
810 }
811 }
812 else if (!strcmp(arg, "TXCONT")) // Tx Continue
813 {
814 if (pAd->ate.bQATxStart == TRUE)
815 {
816 /* set MAC_SYS_CTRL(0x1004) bit4(Continuous Tx Production Test)
817 and bit2(MAC TX enable) back to zero. */
818 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
819 MacData &= 0xFFFFFFEB;
820 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
821
822 // set BBP R22 bit7=0
823 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
824 BbpData &= 0xFFFFFF7F; //set bit7=0
825 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
826 }
827
828 /* for TxCont mode.
829 ** Step 1: Send 50 packets first then wait for a moment.
830 ** Step 2: Send more 50 packet then start continue mode.
831 */
832 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXCONT\n"));
833 // Step 1: send 50 packets first.
834 pAd->ate.Mode |= ATE_TXCONT;
835 pAd->ate.TxCount = 50;
836 /* Do it after Tx/Rx DMA is aborted. */
837 // pAd->ate.TxDoneCount = 0;
838
839 // Soft reset BBP.
840 BbpSoftReset(pAd);
841
842 // Abort Tx, RX DMA.
843 RtmpDmaEnable(pAd, 0);
844
845 // Fix can't smooth kick
846 {
847 RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * 0x10, &pTxRing->TxDmaIdx);
848 pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
849 pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
850 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * 0x10, pTxRing->TxCpuIdx);
851 }
852
853 pAd->ate.TxDoneCount = 0;
854
855 /* Only needed if we have to send some normal frames. */
856 SetJapanFilter(pAd);
857
858 for (i = 0; (i < TX_RING_SIZE-1) && (i < pAd->ate.TxCount); i++)
859 {
860 PNDIS_PACKET pPacket;
861 UINT32 TxIdx = pTxRing->TxCpuIdx;
862
863 #ifndef RT_BIG_ENDIAN
864 pTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
865 #else
866 pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
867 TxD = *pDestTxD;
868 pTxD = &TxD;
869 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
870 #endif
871 // Clean current cell.
872 pPacket = pTxRing->Cell[TxIdx].pNdisPacket;
873 if (pPacket)
874 {
875 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
876 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
877 }
878 //Always assign pNdisPacket as NULL after clear
879 pTxRing->Cell[TxIdx].pNdisPacket = NULL;
880
881 pPacket = pTxRing->Cell[TxIdx].pNextNdisPacket;
882 if (pPacket)
883 {
884 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
885 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
886 }
887 //Always assign pNextNdisPacket as NULL after clear
888 pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
889
890 #ifdef RT_BIG_ENDIAN
891 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
892 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
893 #endif
894
895 if (ATESetUpFrame(pAd, TxIdx) != 0)
896 break;
897
898 INC_RING_INDEX(pTxRing->TxCpuIdx, TX_RING_SIZE);
899 }
900
901 // Setup frame format.
902 ATESetUpFrame(pAd, pTxRing->TxCpuIdx);
903
904 // Start Tx, RX DMA.
905 RtmpDmaEnable(pAd, 1);
906
907 // Enable Tx
908 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
909 Value |= (1 << 2);
910 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
911
912 // Disable Rx
913 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
914 Value &= ~(1 << 3);
915 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
916
917 #ifdef RALINK_28xx_QA
918 if (pAd->ate.bQATxStart == TRUE)
919 {
920 pAd->ate.TxStatus = 1;
921 //pAd->ate.Repeat = 0;
922 }
923 #endif // RALINK_28xx_QA //
924
925 // kick Tx-Ring.
926 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * RINGREG_DIFF, pAd->TxRing[QID_AC_BE].TxCpuIdx);
927
928 RTMPusecDelay(5000);
929
930
931 // Step 2: send more 50 packets then start continue mode.
932 // Abort Tx, RX DMA.
933 RtmpDmaEnable(pAd, 0);
934
935 // Cont. TX set BBP R22 bit7=1
936 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
937 BbpData |= 0x00000080; //set bit7=1
938 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
939
940 pAd->ate.TxCount = 50;
941
942 // Fix can't smooth kick
943 {
944 RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * 0x10, &pTxRing->TxDmaIdx);
945 pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
946 pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
947 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * 0x10, pTxRing->TxCpuIdx);
948 }
949
950 pAd->ate.TxDoneCount = 0;
951
952 SetJapanFilter(pAd);
953
954 for (i = 0; (i < TX_RING_SIZE-1) && (i < pAd->ate.TxCount); i++)
955 {
956 PNDIS_PACKET pPacket;
957 UINT32 TxIdx = pTxRing->TxCpuIdx;
958
959 #ifndef RT_BIG_ENDIAN
960 pTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
961 #else
962 pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
963 TxD = *pDestTxD;
964 pTxD = &TxD;
965 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
966 #endif
967 // clean current cell.
968 pPacket = pTxRing->Cell[TxIdx].pNdisPacket;
969 if (pPacket)
970 {
971 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
972 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
973 }
974 //Always assign pNdisPacket as NULL after clear
975 pTxRing->Cell[TxIdx].pNdisPacket = NULL;
976
977 pPacket = pTxRing->Cell[TxIdx].pNextNdisPacket;
978 if (pPacket)
979 {
980 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
981 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
982 }
983 //Always assign pNextNdisPacket as NULL after clear
984 pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
985
986 #ifdef RT_BIG_ENDIAN
987 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
988 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
989 #endif
990
991 if (ATESetUpFrame(pAd, TxIdx) != 0)
992 break;
993
994 INC_RING_INDEX(pTxRing->TxCpuIdx, TX_RING_SIZE);
995 }
996
997 ATESetUpFrame(pAd, pTxRing->TxCpuIdx);
998
999 // Start Tx, RX DMA.
1000 RtmpDmaEnable(pAd, 1);
1001
1002 // Enable Tx
1003 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1004 Value |= (1 << 2);
1005 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1006
1007 // Disable Rx
1008 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1009 Value &= ~(1 << 3);
1010 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1011
1012 #ifdef RALINK_28xx_QA
1013 if (pAd->ate.bQATxStart == TRUE)
1014 {
1015 pAd->ate.TxStatus = 1;
1016 //pAd->ate.Repeat = 0;
1017 }
1018 #endif // RALINK_28xx_QA //
1019
1020 // kick Tx-Ring.
1021 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * RINGREG_DIFF, pAd->TxRing[QID_AC_BE].TxCpuIdx);
1022
1023 RTMPusecDelay(500);
1024
1025 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1026 MacData |= 0x00000010;
1027 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1028 }
1029 else if (!strcmp(arg, "TXFRAME")) // Tx Frames
1030 {
1031 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXFRAME(Count=%d)\n", pAd->ate.TxCount));
1032 pAd->ate.Mode |= ATE_TXFRAME;
1033 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1034
1035 // Soft reset BBP.
1036 BbpSoftReset(pAd);
1037 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1038
1039 // Abort Tx, RX DMA.
1040 RtmpDmaEnable(pAd, 0);
1041
1042 // Fix can't smooth kick
1043 {
1044 RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * 0x10, &pTxRing->TxDmaIdx);
1045 pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
1046 pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
1047 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * 0x10, pTxRing->TxCpuIdx);
1048 }
1049
1050 pAd->ate.TxDoneCount = 0;
1051
1052 SetJapanFilter(pAd);
1053
1054 for (i = 0; (i < TX_RING_SIZE-1) && (i < pAd->ate.TxCount); i++)
1055 {
1056 PNDIS_PACKET pPacket;
1057 UINT32 TxIdx = pTxRing->TxCpuIdx;
1058
1059 #ifndef RT_BIG_ENDIAN
1060 pTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1061 #else
1062 pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1063 TxD = *pDestTxD;
1064 pTxD = &TxD;
1065 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1066 #endif
1067 // Clean current cell.
1068 pPacket = pTxRing->Cell[TxIdx].pNdisPacket;
1069 if (pPacket)
1070 {
1071 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
1072 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1073 }
1074 //Always assign pNdisPacket as NULL after clear
1075 pTxRing->Cell[TxIdx].pNdisPacket = NULL;
1076
1077 pPacket = pTxRing->Cell[TxIdx].pNextNdisPacket;
1078 if (pPacket)
1079 {
1080 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
1081 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1082 }
1083 //Always assign pNextNdisPacket as NULL after clear
1084 pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
1085
1086 #ifdef RT_BIG_ENDIAN
1087 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1088 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
1089 #endif
1090
1091 if (ATESetUpFrame(pAd, TxIdx) != 0)
1092 break;
1093
1094 INC_RING_INDEX(pTxRing->TxCpuIdx, TX_RING_SIZE);
1095
1096 }
1097
1098 ATESetUpFrame(pAd, pTxRing->TxCpuIdx);
1099
1100 // Start Tx, Rx DMA.
1101 RtmpDmaEnable(pAd, 1);
1102
1103 // Enable Tx
1104 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1105 Value |= (1 << 2);
1106 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1107 #ifdef RALINK_28xx_QA
1108 // add this for LoopBack mode
1109 if (pAd->ate.bQARxStart == FALSE)
1110 {
1111 // Disable Rx
1112 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1113 Value &= ~(1 << 3);
1114 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1115 }
1116
1117 if (pAd->ate.bQATxStart == TRUE)
1118 {
1119 pAd->ate.TxStatus = 1;
1120 //pAd->ate.Repeat = 0;
1121 }
1122 #else
1123 // Disable Rx
1124 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1125 Value &= ~(1 << 3);
1126 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1127 #endif // RALINK_28xx_QA //
1128
1129 RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * RINGREG_DIFF, &pAd->TxRing[QID_AC_BE].TxDmaIdx);
1130 // kick Tx-Ring.
1131 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * RINGREG_DIFF, pAd->TxRing[QID_AC_BE].TxCpuIdx);
1132
1133 pAd->RalinkCounters.KickTxCount++;
1134 }
1135 #ifdef RALINK_28xx_QA
1136 else if (!strcmp(arg, "TXSTOP"))
1137 {
1138 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXSTOP\n"));
1139 atemode = pAd->ate.Mode;
1140 pAd->ate.Mode &= ATE_TXSTOP;
1141 pAd->ate.bQATxStart = FALSE;
1142 // pAd->ate.TxDoneCount = pAd->ate.TxCount;
1143
1144 if (atemode & ATE_TXCARR)
1145 {
1146 // No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0
1147 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1148 BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
1149 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1150 }
1151 else if (atemode & ATE_TXCARRSUPP)
1152 {
1153 // No Cont. TX set BBP R22 bit7=0
1154 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1155 BbpData &= ~(1 << 7); //set bit7=0
1156 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1157
1158 // No Carrier Suppression set BBP R24 bit0=0
1159 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &BbpData);
1160 BbpData &= 0xFFFFFFFE; //clear bit0
1161 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, BbpData);
1162 }
1163 // We should free some resource which allocate when ATE_TXFRAME , ATE_STOP, and ATE_TXCONT.
1164 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
1165 {
1166
1167 PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
1168
1169 if (atemode & ATE_TXCONT)
1170 {
1171 // No Cont. TX set BBP R22 bit7=0
1172 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1173 BbpData &= ~(1 << 7); //set bit7=0
1174 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1175 }
1176
1177 // Abort Tx, Rx DMA.
1178 RtmpDmaEnable(pAd, 0);
1179 for (i=0; i<TX_RING_SIZE; i++)
1180 {
1181 PNDIS_PACKET pPacket;
1182
1183 #ifndef RT_BIG_ENDIAN
1184 pTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
1185 #else
1186 pDestTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
1187 TxD = *pDestTxD;
1188 pTxD = &TxD;
1189 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1190 #endif
1191 pTxD->DMADONE = 0;
1192 pPacket = pTxRing->Cell[i].pNdisPacket;
1193 if (pPacket)
1194 {
1195 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
1196 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1197 }
1198 //Always assign pNdisPacket as NULL after clear
1199 pTxRing->Cell[i].pNdisPacket = NULL;
1200
1201 pPacket = pTxRing->Cell[i].pNextNdisPacket;
1202 if (pPacket)
1203 {
1204 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
1205 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1206 }
1207 //Always assign pNextNdisPacket as NULL after clear
1208 pTxRing->Cell[i].pNextNdisPacket = NULL;
1209 #ifdef RT_BIG_ENDIAN
1210 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1211 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
1212 #endif
1213 }
1214 // Enable Tx, Rx DMA
1215 RtmpDmaEnable(pAd, 1);
1216
1217 }
1218
1219 // control
1220 // pAd->ate.TxDoneCount = 0;
1221 pAd->ate.TxStatus = 0; // task Tx status // 0 --> task is idle, 1 --> task is running
1222
1223 // Soft reset BBP.
1224 BbpSoftReset(pAd);
1225
1226 // Disable Tx
1227 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1228 Value &= ~(1 << 2);
1229 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1230 }
1231 else if (!strcmp(arg, "RXSTOP"))
1232 {
1233 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: RXSTOP\n"));
1234 atemode = pAd->ate.Mode;
1235 pAd->ate.Mode &= ATE_RXSTOP;
1236 pAd->ate.bQARxStart = FALSE;
1237 // pAd->ate.TxDoneCount = pAd->ate.TxCount;
1238
1239 if (atemode & ATE_TXCARR)
1240 {
1241 ;
1242 }
1243 else if (atemode & ATE_TXCARRSUPP)
1244 {
1245 ;
1246 }
1247
1248 // We should free some resource which was allocated when ATE_TXFRAME , ATE_STOP, and ATE_TXCONT.
1249 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
1250 {
1251 if (atemode & ATE_TXCONT)
1252 {
1253 ;
1254 }
1255 }
1256
1257 // control
1258 // pAd->ate.TxDoneCount = 0;
1259 // pAd->ate.TxStatus = 0; // task Tx status // 0 --> task is idle, 1 --> task is running
1260
1261 // Soft reset BBP.
1262 BbpSoftReset(pAd);
1263
1264 // Disable Rx
1265 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1266 Value &= ~(1 << 3);
1267 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1268 }
1269 #endif // RALINK_28xx_QA //
1270 else if (!strcmp(arg, "RXFRAME")) // Rx Frames
1271 {
1272 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: RXFRAME\n"));
1273
1274 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1275 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1276
1277 pAd->ate.Mode |= ATE_RXFRAME;
1278
1279 // Disable Tx of MAC block.
1280 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1281 Value &= ~(1 << 2);
1282 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1283
1284 // Enable Rx of MAC block.
1285 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1286 Value |= (1 << 3);
1287 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1288 }
1289 else
1290 {
1291 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: Invalid arg!\n"));
1292 return FALSE;
1293 }
1294 RTMPusecDelay(5000);
1295
1296 ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== ATECmdHandler()\n"));
1297
1298 return TRUE;
1299 }
1300 #endif // RT2860 //
1301 /* */
1302 /* */
1303 /*=======================End of RT2860=======================*/
1304
1305
1306 /*======================Start of RT2870======================*/
1307 /* */
1308 /* */
1309
1310
1311 INT Set_ATE_Proc(
1312 IN PRTMP_ADAPTER pAd,
1313 IN PUCHAR arg)
1314 {
1315 if (ATECmdHandler(pAd, arg))
1316 {
1317 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Proc Success\n"));
1318
1319
1320 return TRUE;
1321 }
1322 else
1323 {
1324 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Proc Failed\n"));
1325 return FALSE;
1326 }
1327 }
1328
1329 /*
1330 ==========================================================================
1331 Description:
1332 Set ATE ADDR1=DA for TxFrame(AP : To DS = 0 ; From DS = 1)
1333 or
1334 Set ATE ADDR3=DA for TxFrame(STA : To DS = 1 ; From DS = 0)
1335
1336 Return:
1337 TRUE if all parameters are OK, FALSE otherwise
1338 ==========================================================================
1339 */
1340 INT Set_ATE_DA_Proc(
1341 IN PRTMP_ADAPTER pAd,
1342 IN PUCHAR arg)
1343 {
1344 CHAR *value;
1345 INT i;
1346
1347 if(strlen(arg) != 17) //Mac address acceptable format 01:02:03:04:05:06 length 17
1348 return FALSE;
1349
1350 for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1351 {
1352 if((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))) )
1353 return FALSE; //Invalid
1354
1355
1356 #ifdef CONFIG_STA_SUPPORT
1357 AtoH(value, &pAd->ate.Addr3[i++], 1);
1358 #endif // CONFIG_STA_SUPPORT //
1359 }
1360
1361 if(i != 6)
1362 return FALSE; //Invalid
1363
1364
1365 #ifdef CONFIG_STA_SUPPORT
1366 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_DA_Proc (DA = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr3[0],
1367 pAd->ate.Addr3[1], pAd->ate.Addr3[2], pAd->ate.Addr3[3], pAd->ate.Addr3[4], pAd->ate.Addr3[5]));
1368 #endif // CONFIG_STA_SUPPORT //
1369
1370 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_DA_Proc Success\n"));
1371
1372 return TRUE;
1373 }
1374
1375 /*
1376 ==========================================================================
1377 Description:
1378 Set ATE ADDR3=SA for TxFrame(AP : To DS = 0 ; From DS = 1)
1379 or
1380 Set ATE ADDR2=SA for TxFrame(STA : To DS = 1 ; From DS = 0)
1381
1382 Return:
1383 TRUE if all parameters are OK, FALSE otherwise
1384 ==========================================================================
1385 */
1386 INT Set_ATE_SA_Proc(
1387 IN PRTMP_ADAPTER pAd,
1388 IN PUCHAR arg)
1389 {
1390 CHAR *value;
1391 INT i;
1392
1393 if(strlen(arg) != 17) //Mac address acceptable format 01:02:03:04:05:06 length 17
1394 return FALSE;
1395
1396 for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1397 {
1398 if((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))) )
1399 return FALSE; //Invalid
1400
1401
1402 #ifdef CONFIG_STA_SUPPORT
1403 AtoH(value, &pAd->ate.Addr2[i++], 1);
1404 #endif // CONFIG_STA_SUPPORT //
1405 }
1406
1407 if(i != 6)
1408 return FALSE; //Invalid
1409
1410
1411 #ifdef CONFIG_STA_SUPPORT
1412 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_SA_Proc (SA = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr2[0],
1413 pAd->ate.Addr2[1], pAd->ate.Addr2[2], pAd->ate.Addr2[3], pAd->ate.Addr2[4], pAd->ate.Addr2[5]));
1414 #endif // CONFIG_STA_SUPPORT //
1415
1416 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_SA_Proc Success\n"));
1417
1418 return TRUE;
1419 }
1420
1421 /*
1422 ==========================================================================
1423 Description:
1424 Set ATE ADDR2=BSSID for TxFrame(AP : To DS = 0 ; From DS = 1)
1425 or
1426 Set ATE ADDR1=BSSID for TxFrame(STA : To DS = 1 ; From DS = 0)
1427
1428 Return:
1429 TRUE if all parameters are OK, FALSE otherwise
1430 ==========================================================================
1431 */
1432 INT Set_ATE_BSSID_Proc(
1433 IN PRTMP_ADAPTER pAd,
1434 IN PUCHAR arg)
1435 {
1436 CHAR *value;
1437 INT i;
1438
1439 if(strlen(arg) != 17) //Mac address acceptable format 01:02:03:04:05:06 length 17
1440 return FALSE;
1441
1442 for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1443 {
1444 if((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))) )
1445 return FALSE; //Invalid
1446
1447
1448 #ifdef CONFIG_STA_SUPPORT
1449 AtoH(value, &pAd->ate.Addr1[i++], 1);
1450 #endif // CONFIG_STA_SUPPORT //
1451 }
1452
1453 if(i != 6)
1454 return FALSE; //Invalid
1455
1456
1457 #ifdef CONFIG_STA_SUPPORT
1458 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_BSSID_Proc (BSSID = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr1[0],
1459 pAd->ate.Addr1[1], pAd->ate.Addr1[2], pAd->ate.Addr1[3], pAd->ate.Addr1[4], pAd->ate.Addr1[5]));
1460 #endif // CONFIG_STA_SUPPORT //
1461
1462 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_BSSID_Proc Success\n"));
1463
1464 return TRUE;
1465 }
1466
1467 /*
1468 ==========================================================================
1469 Description:
1470 Set ATE Tx Channel
1471
1472 Return:
1473 TRUE if all parameters are OK, FALSE otherwise
1474 ==========================================================================
1475 */
1476 INT Set_ATE_CHANNEL_Proc(
1477 IN PRTMP_ADAPTER pAd,
1478 IN PUCHAR arg)
1479 {
1480 UCHAR channel;
1481
1482 channel = simple_strtol(arg, 0, 10);
1483
1484 if ((channel < 1) || (channel > 216))// to allow A band channel : ((channel < 1) || (channel > 14))
1485 {
1486 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_CHANNEL_Proc::Out of range, it should be in range of 1~14.\n"));
1487 return FALSE;
1488 }
1489 pAd->ate.Channel = channel;
1490
1491 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_CHANNEL_Proc (ATE Channel = %d)\n", pAd->ate.Channel));
1492 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_CHANNEL_Proc Success\n"));
1493
1494
1495 return TRUE;
1496 }
1497
1498 /*
1499 ==========================================================================
1500 Description:
1501 Set ATE Tx Power0
1502
1503 Return:
1504 TRUE if all parameters are OK, FALSE otherwise
1505 ==========================================================================
1506 */
1507 INT Set_ATE_TX_POWER0_Proc(
1508 IN PRTMP_ADAPTER pAd,
1509 IN PUCHAR arg)
1510 {
1511 CHAR TxPower;
1512
1513 TxPower = simple_strtol(arg, 0, 10);
1514
1515 if (pAd->ate.Channel <= 14)
1516 {
1517 if ((TxPower > 31) || (TxPower < 0))
1518 {
1519 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER0_Proc::Out of range (Value=%d)\n", TxPower));
1520 return FALSE;
1521 }
1522 }
1523 else// 5.5GHz
1524 {
1525 if ((TxPower > 15) || (TxPower < -7))
1526 {
1527 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER0_Proc::Out of range (Value=%d)\n", TxPower));
1528 return FALSE;
1529 }
1530 }
1531
1532 pAd->ate.TxPower0 = TxPower;
1533 ATETxPwrHandler(pAd, 0);
1534 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER0_Proc Success\n"));
1535
1536
1537 return TRUE;
1538 }
1539
1540 /*
1541 ==========================================================================
1542 Description:
1543 Set ATE Tx Power1
1544
1545 Return:
1546 TRUE if all parameters are OK, FALSE otherwise
1547 ==========================================================================
1548 */
1549 INT Set_ATE_TX_POWER1_Proc(
1550 IN PRTMP_ADAPTER pAd,
1551 IN PUCHAR arg)
1552 {
1553 CHAR TxPower;
1554
1555 TxPower = simple_strtol(arg, 0, 10);
1556
1557 if (pAd->ate.Channel <= 14)
1558 {
1559 if ((TxPower > 31) || (TxPower < 0))
1560 {
1561 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER1_Proc::Out of range (Value=%d)\n", TxPower));
1562 return FALSE;
1563 }
1564 }
1565 else
1566 {
1567 if ((TxPower > 15) || (TxPower < -7))
1568 {
1569 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER1_Proc::Out of range (Value=%d)\n", TxPower));
1570 return FALSE;
1571 }
1572 }
1573
1574 pAd->ate.TxPower1 = TxPower;
1575 ATETxPwrHandler(pAd, 1);
1576 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER1_Proc Success\n"));
1577
1578
1579 return TRUE;
1580 }
1581
1582 /*
1583 ==========================================================================
1584 Description:
1585 Set ATE Tx Antenna
1586
1587 Return:
1588 TRUE if all parameters are OK, FALSE otherwise
1589 ==========================================================================
1590 */
1591 INT Set_ATE_TX_Antenna_Proc(
1592 IN PRTMP_ADAPTER pAd,
1593 IN PUCHAR arg)
1594 {
1595 CHAR value;
1596
1597 value = simple_strtol(arg, 0, 10);
1598
1599 if ((value > 2) || (value < 0))
1600 {
1601 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_Antenna_Proc::Out of range (Value=%d)\n", value));
1602 return FALSE;
1603 }
1604
1605 pAd->ate.TxAntennaSel = value;
1606
1607 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_Antenna_Proc (Antenna = %d)\n", pAd->ate.TxAntennaSel));
1608 ATEDBGPRINT(RT_DEBUG_TRACE,("Ralink: Set_ATE_TX_Antenna_Proc Success\n"));
1609
1610
1611 return TRUE;
1612 }
1613
1614 /*
1615 ==========================================================================
1616 Description:
1617 Set ATE Rx Antenna
1618
1619 Return:
1620 TRUE if all parameters are OK, FALSE otherwise
1621 ==========================================================================
1622 */
1623 INT Set_ATE_RX_Antenna_Proc(
1624 IN PRTMP_ADAPTER pAd,
1625 IN PUCHAR arg)
1626 {
1627 CHAR value;
1628
1629 value = simple_strtol(arg, 0, 10);
1630
1631 if ((value > 3) || (value < 0))
1632 {
1633 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_RX_Antenna_Proc::Out of range (Value=%d)\n", value));
1634 return FALSE;
1635 }
1636
1637 pAd->ate.RxAntennaSel = value;
1638
1639 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_Antenna_Proc (Antenna = %d)\n", pAd->ate.RxAntennaSel));
1640 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_Antenna_Proc Success\n"));
1641
1642
1643 return TRUE;
1644 }
1645
1646 /*
1647 ==========================================================================
1648 Description:
1649 Set ATE RF frequence offset
1650
1651 Return:
1652 TRUE if all parameters are OK, FALSE otherwise
1653 ==========================================================================
1654 */
1655 INT Set_ATE_TX_FREQOFFSET_Proc(
1656 IN PRTMP_ADAPTER pAd,
1657 IN PUCHAR arg)
1658 {
1659 UCHAR RFFreqOffset;
1660 ULONG R4;
1661
1662 RFFreqOffset = simple_strtol(arg, 0, 10);
1663
1664 if(RFFreqOffset >= 64)
1665 {
1666 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_FREQOFFSET_Proc::Out of range, it should be in range of 0~63.\n"));
1667 return FALSE;
1668 }
1669
1670 pAd->ate.RFFreqOffset = RFFreqOffset;
1671 R4 = pAd->ate.RFFreqOffset << 15; // shift TX power control to correct RF register bit position
1672 R4 |= (pAd->LatchRfRegs.R4 & ((~0x001f8000)));
1673 pAd->LatchRfRegs.R4 = R4;
1674
1675 RtmpRfIoWrite(pAd);
1676
1677 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_FREQOFFSET_Proc (RFFreqOffset = %d)\n", pAd->ate.RFFreqOffset));
1678 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_FREQOFFSET_Proc Success\n"));
1679
1680
1681 return TRUE;
1682 }
1683
1684 /*
1685 ==========================================================================
1686 Description:
1687 Set ATE RF BW
1688
1689 Return:
1690 TRUE if all parameters are OK, FALSE otherwise
1691 ==========================================================================
1692 */
1693 INT Set_ATE_TX_BW_Proc(
1694 IN PRTMP_ADAPTER pAd,
1695 IN PUCHAR arg)
1696 {
1697 int i;
1698 UCHAR value = 0;
1699 UCHAR BBPCurrentBW;
1700
1701 BBPCurrentBW = simple_strtol(arg, 0, 10);
1702
1703 if(BBPCurrentBW == 0)
1704 pAd->ate.TxWI.BW = BW_20;
1705 else
1706 pAd->ate.TxWI.BW = BW_40;
1707
1708 if(pAd->ate.TxWI.BW == BW_20)
1709 {
1710 if(pAd->ate.Channel <= 14)
1711 {
1712 for (i=0; i<5; i++)
1713 {
1714 if (pAd->Tx20MPwrCfgGBand[i] != 0xffffffff)
1715 {
1716 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx20MPwrCfgGBand[i]);
1717 RTMPusecDelay(5000);
1718 }
1719 }
1720 }
1721 else
1722 {
1723 for (i=0; i<5; i++)
1724 {
1725 if (pAd->Tx20MPwrCfgABand[i] != 0xffffffff)
1726 {
1727 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx20MPwrCfgABand[i]);
1728 RTMPusecDelay(5000);
1729 }
1730 }
1731 }
1732
1733 //Set BBP R4 bit[4:3]=0:0
1734 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
1735 value &= (~0x18);
1736 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
1737
1738 //Set BBP R66=0x3C
1739 value = 0x3C;
1740 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
1741 //Set BBP R68=0x0B
1742 //to improve Rx sensitivity.
1743 value = 0x0B;
1744 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
1745 //Set BBP R69=0x16
1746 value = 0x16;
1747 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
1748 //Set BBP R70=0x08
1749 value = 0x08;
1750 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
1751 //Set BBP R73=0x11
1752 value = 0x11;
1753 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
1754
1755 // If Channel=14, Bandwidth=20M and Mode=CCK, Set BBP R4 bit5=1
1756 // (Japan filter coefficients)
1757 // This segment of code will only works when ATETXMODE and ATECHANNEL
1758 // were set to MODE_CCK and 14 respectively before ATETXBW is set to 0.
1759 //=====================================================================
1760 if (pAd->ate.Channel == 14)
1761 {
1762 int TxMode = pAd->ate.TxWI.PHYMODE;
1763 if (TxMode == MODE_CCK)
1764 {
1765 // when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1
1766 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
1767 value |= 0x20; //set bit5=1
1768 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
1769 }
1770 }
1771
1772 //=====================================================================
1773 // If bandwidth != 40M, RF Reg4 bit 21 = 0.
1774 pAd->LatchRfRegs.R4 &= ~0x00200000;
1775 RtmpRfIoWrite(pAd);
1776 }
1777 else if(pAd->ate.TxWI.BW == BW_40)
1778 {
1779 if(pAd->ate.Channel <= 14)
1780 {
1781 for (i=0; i<5; i++)
1782 {
1783 if (pAd->Tx40MPwrCfgGBand[i] != 0xffffffff)
1784 {
1785 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx40MPwrCfgGBand[i]);
1786 RTMPusecDelay(5000);
1787 }
1788 }
1789 }
1790 else
1791 {
1792 for (i=0; i<5; i++)
1793 {
1794 if (pAd->Tx40MPwrCfgABand[i] != 0xffffffff)
1795 {
1796 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx40MPwrCfgABand[i]);
1797 RTMPusecDelay(5000);
1798 }
1799 }
1800 #ifdef DOT11_N_SUPPORT
1801 if ((pAd->ate.TxWI.PHYMODE >= MODE_HTMIX) && (pAd->ate.TxWI.MCS == 7))
1802 {
1803 value = 0x28;
1804 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value);
1805 }
1806 #endif // DOT11_N_SUPPORT //
1807 }
1808
1809 //Set BBP R4 bit[4:3]=1:0
1810 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
1811 value &= (~0x18);
1812 value |= 0x10;
1813 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
1814
1815 //Set BBP R66=0x3C
1816 value = 0x3C;
1817 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
1818 //Set BBP R68=0x0C
1819 //to improve Rx sensitivity.
1820 value = 0x0C;
1821 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
1822 //Set BBP R69=0x1A
1823 value = 0x1A;
1824 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
1825 //Set BBP R70=0x0A
1826 value = 0x0A;
1827 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
1828 //Set BBP R73=0x16
1829 value = 0x16;
1830 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
1831
1832 // If bandwidth = 40M, set RF Reg4 bit 21 = 1.
1833 pAd->LatchRfRegs.R4 |= 0x00200000;
1834 RtmpRfIoWrite(pAd);
1835 }
1836
1837 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_BW_Proc (BBPCurrentBW = %d)\n", pAd->ate.TxWI.BW));
1838 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_BW_Proc Success\n"));
1839
1840
1841 return TRUE;
1842 }
1843
1844 /*
1845 ==========================================================================
1846 Description:
1847 Set ATE Tx frame length
1848
1849 Return:
1850 TRUE if all parameters are OK, FALSE otherwise
1851 ==========================================================================
1852 */
1853 INT Set_ATE_TX_LENGTH_Proc(
1854 IN PRTMP_ADAPTER pAd,
1855 IN PUCHAR arg)
1856 {
1857 pAd->ate.TxLength = simple_strtol(arg, 0, 10);
1858
1859 if((pAd->ate.TxLength < 24) || (pAd->ate.TxLength > (MAX_FRAME_SIZE - 34/* == 2312 */)))
1860 {
1861 pAd->ate.TxLength = (MAX_FRAME_SIZE - 34/* == 2312 */);
1862 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_LENGTH_Proc::Out of range, it should be in range of 24~%d.\n", (MAX_FRAME_SIZE - 34/* == 2312 */)));
1863 return FALSE;
1864 }
1865
1866 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_LENGTH_Proc (TxLength = %d)\n", pAd->ate.TxLength));
1867 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_LENGTH_Proc Success\n"));
1868
1869
1870 return TRUE;
1871 }
1872
1873 /*
1874 ==========================================================================
1875 Description:
1876 Set ATE Tx frame count
1877
1878 Return:
1879 TRUE if all parameters are OK, FALSE otherwise
1880 ==========================================================================
1881 */
1882 INT Set_ATE_TX_COUNT_Proc(
1883 IN PRTMP_ADAPTER pAd,
1884 IN PUCHAR arg)
1885 {
1886 pAd->ate.TxCount = simple_strtol(arg, 0, 10);
1887
1888 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_COUNT_Proc (TxCount = %d)\n", pAd->ate.TxCount));
1889 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_COUNT_Proc Success\n"));
1890
1891
1892 return TRUE;
1893 }
1894
1895 /*
1896 ==========================================================================
1897 Description:
1898 Set ATE Tx frame MCS
1899
1900 Return:
1901 TRUE if all parameters are OK, FALSE otherwise
1902 ==========================================================================
1903 */
1904 INT Set_ATE_TX_MCS_Proc(
1905 IN PRTMP_ADAPTER pAd,
1906 IN PUCHAR arg)
1907 {
1908 UCHAR MCS;
1909 int result;
1910
1911 MCS = simple_strtol(arg, 0, 10);
1912 result = CheckMCSValid(pAd->ate.TxWI.PHYMODE, MCS);
1913
1914 if (result != -1)
1915 {
1916 pAd->ate.TxWI.MCS = (UCHAR)MCS;
1917 }
1918 else
1919 {
1920 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MCS_Proc::Out of range, refer to rate table.\n"));
1921 return FALSE;
1922 }
1923
1924 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MCS_Proc (MCS = %d)\n", pAd->ate.TxWI.MCS));
1925 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MCS_Proc Success\n"));
1926
1927
1928 return TRUE;
1929 }
1930
1931 /*
1932 ==========================================================================
1933 Description:
1934 Set ATE Tx frame Mode
1935 0: MODE_CCK
1936 1: MODE_OFDM
1937 2: MODE_HTMIX
1938 3: MODE_HTGREENFIELD
1939
1940 Return:
1941 TRUE if all parameters are OK, FALSE otherwise
1942 ==========================================================================
1943 */
1944 INT Set_ATE_TX_MODE_Proc(
1945 IN PRTMP_ADAPTER pAd,
1946 IN PUCHAR arg)
1947 {
1948 pAd->ate.TxWI.PHYMODE = simple_strtol(arg, 0, 10);
1949
1950 if(pAd->ate.TxWI.PHYMODE > 3)
1951 {
1952 pAd->ate.TxWI.PHYMODE = 0;
1953 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MODE_Proc::Out of range. it should be in range of 0~3\n"));
1954 ATEDBGPRINT(RT_DEBUG_ERROR, ("0: CCK, 1: OFDM, 2: HT_MIX, 3: HT_GREEN_FIELD.\n"));
1955 return FALSE;
1956 }
1957
1958 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MODE_Proc (TxMode = %d)\n", pAd->ate.TxWI.PHYMODE));
1959 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MODE_Proc Success\n"));
1960
1961
1962 return TRUE;
1963 }
1964
1965 /*
1966 ==========================================================================
1967 Description:
1968 Set ATE Tx frame GI
1969
1970 Return:
1971 TRUE if all parameters are OK, FALSE otherwise
1972 ==========================================================================
1973 */
1974 INT Set_ATE_TX_GI_Proc(
1975 IN PRTMP_ADAPTER pAd,
1976 IN PUCHAR arg)
1977 {
1978 pAd->ate.TxWI.ShortGI = simple_strtol(arg, 0, 10);
1979
1980 if(pAd->ate.TxWI.ShortGI > 1)
1981 {
1982 pAd->ate.TxWI.ShortGI = 0;
1983 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_GI_Proc::Out of range\n"));
1984 return FALSE;
1985 }
1986
1987 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_GI_Proc (GI = %d)\n", pAd->ate.TxWI.ShortGI));
1988 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_GI_Proc Success\n"));
1989
1990
1991 return TRUE;
1992 }
1993
1994 /*
1995 ==========================================================================
1996 Description:
1997 ==========================================================================
1998 */
1999 INT Set_ATE_RX_FER_Proc(
2000 IN PRTMP_ADAPTER pAd,
2001 IN PUCHAR arg)
2002 {
2003 pAd->ate.bRxFer = simple_strtol(arg, 0, 10);
2004
2005 if (pAd->ate.bRxFer == 1)
2006 {
2007 pAd->ate.RxCntPerSec = 0;
2008 pAd->ate.RxTotalCnt = 0;
2009 }
2010
2011 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_FER_Proc (bRxFer = %d)\n", pAd->ate.bRxFer));
2012 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_FER_Proc Success\n"));
2013
2014
2015 return TRUE;
2016 }
2017
2018 INT Set_ATE_Read_RF_Proc(
2019 IN PRTMP_ADAPTER pAd,
2020 IN PUCHAR arg)
2021 {
2022 ate_print(KERN_EMERG "R1 = %lx\n", pAd->LatchRfRegs.R1);
2023 ate_print(KERN_EMERG "R2 = %lx\n", pAd->LatchRfRegs.R2);
2024 ate_print(KERN_EMERG "R3 = %lx\n", pAd->LatchRfRegs.R3);
2025 ate_print(KERN_EMERG "R4 = %lx\n", pAd->LatchRfRegs.R4);
2026
2027 return TRUE;
2028 }
2029
2030 INT Set_ATE_Write_RF1_Proc(
2031 IN PRTMP_ADAPTER pAd,
2032 IN PUCHAR arg)
2033 {
2034 UINT32 value = simple_strtol(arg, 0, 16);
2035
2036 pAd->LatchRfRegs.R1 = value;
2037 RtmpRfIoWrite(pAd);
2038
2039 return TRUE;
2040 }
2041
2042 INT Set_ATE_Write_RF2_Proc(
2043 IN PRTMP_ADAPTER pAd,
2044 IN PUCHAR arg)
2045 {
2046 UINT32 value = simple_strtol(arg, 0, 16);
2047
2048 pAd->LatchRfRegs.R2 = value;
2049 RtmpRfIoWrite(pAd);
2050
2051 return TRUE;
2052 }
2053
2054 INT Set_ATE_Write_RF3_Proc(
2055 IN PRTMP_ADAPTER pAd,
2056 IN PUCHAR arg)
2057 {
2058 UINT32 value = simple_strtol(arg, 0, 16);
2059
2060 pAd->LatchRfRegs.R3 = value;
2061 RtmpRfIoWrite(pAd);
2062
2063 return TRUE;
2064 }
2065
2066 INT Set_ATE_Write_RF4_Proc(
2067 IN PRTMP_ADAPTER pAd,
2068 IN PUCHAR arg)
2069 {
2070 UINT32 value = simple_strtol(arg, 0, 16);
2071
2072 pAd->LatchRfRegs.R4 = value;
2073 RtmpRfIoWrite(pAd);
2074
2075 return TRUE;
2076 }
2077
2078 /*
2079 ==========================================================================
2080 Description:
2081 Load and Write EEPROM from a binary file prepared in advance.
2082
2083 Return:
2084 TRUE if all parameters are OK, FALSE otherwise
2085 ==========================================================================
2086 */
2087 #ifndef UCOS
2088 INT Set_ATE_Load_E2P_Proc(
2089 IN PRTMP_ADAPTER pAd,
2090 IN PUCHAR arg)
2091 {
2092 BOOLEAN ret = FALSE;
2093 PUCHAR src = EEPROM_BIN_FILE_NAME;
2094 struct file *srcf;
2095 INT32 retval, orgfsuid, orgfsgid;
2096 mm_segment_t orgfs;
2097 USHORT WriteEEPROM[(EEPROM_SIZE/2)];
2098 UINT32 FileLength = 0;
2099 UINT32 value = simple_strtol(arg, 0, 10);
2100
2101 ATEDBGPRINT(RT_DEBUG_ERROR, ("===> %s (value=%d)\n\n", __func__, value));
2102
2103 if (value > 0)
2104 {
2105 /* zero the e2p buffer */
2106 NdisZeroMemory((PUCHAR)WriteEEPROM, EEPROM_SIZE);
2107
2108 /* save uid and gid used for filesystem access.
2109 ** set user and group to 0 (root)
2110 */
2111 orgfsuid = current->fsuid;
2112 orgfsgid = current->fsgid;
2113 /* as root */
2114 current->fsuid = current->fsgid = 0;
2115 orgfs = get_fs();
2116 set_fs(KERNEL_DS);
2117
2118 do
2119 {
2120 /* open the bin file */
2121 srcf = filp_open(src, O_RDONLY, 0);
2122
2123 if (IS_ERR(srcf))
2124 {
2125 ate_print("%s - Error %ld opening %s\n", __func__, -PTR_ERR(srcf), src);
2126 break;
2127 }
2128
2129 /* the object must have a read method */
2130 if ((srcf->f_op == NULL) || (srcf->f_op->read == NULL))
2131 {
2132 ate_print("%s - %s does not have a read method\n", __func__, src);
2133 break;
2134 }
2135
2136 /* read the firmware from the file *.bin */
2137 FileLength = srcf->f_op->read(srcf,
2138 (PUCHAR)WriteEEPROM,
2139 EEPROM_SIZE,
2140 &srcf->f_pos);
2141
2142 if (FileLength != EEPROM_SIZE)
2143 {
2144 ate_print("%s: error file length (=%d) in e2p.bin\n",
2145 __func__, FileLength);
2146 break;
2147 }
2148 else
2149 {
2150 /* write the content of .bin file to EEPROM */
2151 rt_ee_write_all(pAd, WriteEEPROM);
2152 ret = TRUE;
2153 }
2154 break;
2155 } while(TRUE);
2156
2157 /* close firmware file */
2158 if (IS_ERR(srcf))
2159 {
2160 ;
2161 }
2162 else
2163 {
2164 retval = filp_close(srcf, NULL);
2165 if (retval)
2166 {
2167 ATEDBGPRINT(RT_DEBUG_ERROR, ("--> Error %d closing %s\n", -retval, src));
2168
2169 }
2170 }
2171
2172 /* restore */
2173 set_fs(orgfs);
2174 current->fsuid = orgfsuid;
2175 current->fsgid = orgfsgid;
2176 }
2177 ATEDBGPRINT(RT_DEBUG_ERROR, ("<=== %s (ret=%d)\n", __func__, ret));
2178
2179 return ret;
2180
2181 }
2182 #else
2183 INT Set_ATE_Load_E2P_Proc(
2184 IN PRTMP_ADAPTER pAd,
2185 IN PUCHAR arg)
2186 {
2187 USHORT WriteEEPROM[(EEPROM_SIZE/2)];
2188 struct iwreq *wrq = (struct iwreq *)arg;
2189
2190 ATEDBGPRINT(RT_DEBUG_TRACE, ("===> %s (wrq->u.data.length = %d)\n\n", __func__, wrq->u.data.length));
2191
2192 if (wrq->u.data.length != EEPROM_SIZE)
2193 {
2194 ate_print("%s: error length (=%d) from host\n",
2195 __func__, wrq->u.data.length);
2196 return FALSE;
2197 }
2198 else/* (wrq->u.data.length == EEPROM_SIZE) */
2199 {
2200 /* zero the e2p buffer */
2201 NdisZeroMemory((PUCHAR)WriteEEPROM, EEPROM_SIZE);
2202
2203 /* fill the local buffer */
2204 NdisMoveMemory((PUCHAR)WriteEEPROM, wrq->u.data.pointer, wrq->u.data.length);
2205
2206 do
2207 {
2208 /* write the content of .bin file to EEPROM */
2209 rt_ee_write_all(pAd, WriteEEPROM);
2210
2211 } while(FALSE);
2212 }
2213
2214 ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== %s\n", __func__));
2215
2216 return TRUE;
2217
2218 }
2219 #endif // !UCOS //
2220
2221 INT Set_ATE_Read_E2P_Proc(
2222 IN PRTMP_ADAPTER pAd,
2223 IN PUCHAR arg)
2224 {
2225 USHORT buffer[EEPROM_SIZE/2];
2226 USHORT *p;
2227 int i;
2228
2229 rt_ee_read_all(pAd, (USHORT *)buffer);
2230 p = buffer;
2231 for (i = 0; i < (EEPROM_SIZE/2); i++)
2232 {
2233 ate_print("%4.4x ", *p);
2234 if (((i+1) % 16) == 0)
2235 ate_print("\n");
2236 p++;
2237 }
2238 return TRUE;
2239 }
2240
2241 INT Set_ATE_Show_Proc(
2242 IN PRTMP_ADAPTER pAd,
2243 IN PUCHAR arg)
2244 {
2245 ate_print("Mode=%d\n", pAd->ate.Mode);
2246 ate_print("TxPower0=%d\n", pAd->ate.TxPower0);
2247 ate_print("TxPower1=%d\n", pAd->ate.TxPower1);
2248 ate_print("TxAntennaSel=%d\n", pAd->ate.TxAntennaSel);
2249 ate_print("RxAntennaSel=%d\n", pAd->ate.RxAntennaSel);
2250 ate_print("BBPCurrentBW=%d\n", pAd->ate.TxWI.BW);
2251 ate_print("GI=%d\n", pAd->ate.TxWI.ShortGI);
2252 ate_print("MCS=%d\n", pAd->ate.TxWI.MCS);
2253 ate_print("TxMode=%d\n", pAd->ate.TxWI.PHYMODE);
2254 ate_print("Addr1=%02x:%02x:%02x:%02x:%02x:%02x\n",
2255 pAd->ate.Addr1[0], pAd->ate.Addr1[1], pAd->ate.Addr1[2], pAd->ate.Addr1[3], pAd->ate.Addr1[4], pAd->ate.Addr1[5]);
2256 ate_print("Addr2=%02x:%02x:%02x:%02x:%02x:%02x\n",
2257 pAd->ate.Addr2[0], pAd->ate.Addr2[1], pAd->ate.Addr2[2], pAd->ate.Addr2[3], pAd->ate.Addr2[4], pAd->ate.Addr2[5]);
2258 ate_print("Addr3=%02x:%02x:%02x:%02x:%02x:%02x\n",
2259 pAd->ate.Addr3[0], pAd->ate.Addr3[1], pAd->ate.Addr3[2], pAd->ate.Addr3[3], pAd->ate.Addr3[4], pAd->ate.Addr3[5]);
2260 ate_print("Channel=%d\n", pAd->ate.Channel);
2261 ate_print("TxLength=%d\n", pAd->ate.TxLength);
2262 ate_print("TxCount=%u\n", pAd->ate.TxCount);
2263 ate_print("RFFreqOffset=%d\n", pAd->ate.RFFreqOffset);
2264 ate_print(KERN_EMERG "Set_ATE_Show_Proc Success\n");
2265 return TRUE;
2266 }
2267
2268 INT Set_ATE_Help_Proc(
2269 IN PRTMP_ADAPTER pAd,
2270 IN PUCHAR arg)
2271 {
2272 ate_print("ATE=ATESTART, ATESTOP, TXCONT, TXCARR, TXFRAME, RXFRAME\n");
2273 ate_print("ATEDA\n");
2274 ate_print("ATESA\n");
2275 ate_print("ATEBSSID\n");
2276 ate_print("ATECHANNEL, range:0~14(unless A band !)\n");
2277 ate_print("ATETXPOW0, set power level of antenna 1.\n");
2278 ate_print("ATETXPOW1, set power level of antenna 2.\n");
2279 ate_print("ATETXANT, set TX antenna. 0:all, 1:antenna one, 2:antenna two.\n");
2280 ate_print("ATERXANT, set RX antenna.0:all, 1:antenna one, 2:antenna two, 3:antenna three.\n");
2281 ate_print("ATETXFREQOFFSET, set frequency offset, range 0~63\n");
2282 ate_print("ATETXBW, set BandWidth, 0:20MHz, 1:40MHz.\n");
2283 ate_print("ATETXLEN, set Frame length, range 24~%d\n", (MAX_FRAME_SIZE - 34/* == 2312 */));
2284 ate_print("ATETXCNT, set how many frame going to transmit.\n");
2285 ate_print("ATETXMCS, set MCS, reference to rate table.\n");
2286 ate_print("ATETXMODE, set Mode 0:CCK, 1:OFDM, 2:HT-Mix, 3:GreenField, reference to rate table.\n");
2287 ate_print("ATETXGI, set GI interval, 0:Long, 1:Short\n");
2288 ate_print("ATERXFER, 0:disable Rx Frame error rate. 1:enable Rx Frame error rate.\n");
2289 ate_print("ATERRF, show all RF registers.\n");
2290 ate_print("ATEWRF1, set RF1 register.\n");
2291 ate_print("ATEWRF2, set RF2 register.\n");
2292 ate_print("ATEWRF3, set RF3 register.\n");
2293 ate_print("ATEWRF4, set RF4 register.\n");
2294 ate_print("ATELDE2P, load EEPROM from .bin file.\n");
2295 ate_print("ATERE2P, display all EEPROM content.\n");
2296 ate_print("ATESHOW, display all parameters of ATE.\n");
2297 ate_print("ATEHELP, online help.\n");
2298
2299 return TRUE;
2300 }
2301
2302 /*
2303 ==========================================================================
2304 Description:
2305
2306 AsicSwitchChannel() dedicated for ATE.
2307
2308 ==========================================================================
2309 */
2310 VOID ATEAsicSwitchChannel(
2311 IN PRTMP_ADAPTER pAd)
2312 {
2313 UINT32 R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0, Value = 0;
2314 CHAR TxPwer = 0, TxPwer2 = 0;
2315 UCHAR index, BbpValue = 0, R66 = 0x30;
2316 RTMP_RF_REGS *RFRegTable;
2317 UCHAR Channel;
2318
2319 #ifdef RALINK_28xx_QA
2320 if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
2321 {
2322 if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
2323 {
2324 pAd->ate.Channel = pAd->LatchRfRegs.Channel;
2325 }
2326 return;
2327 }
2328 else
2329 #endif // RALINK_28xx_QA //
2330 Channel = pAd->ate.Channel;
2331
2332 // Select antenna
2333 AsicAntennaSelect(pAd, Channel);
2334
2335 // fill Tx power value
2336 TxPwer = pAd->ate.TxPower0;
2337 TxPwer2 = pAd->ate.TxPower1;
2338
2339 RFRegTable = RF2850RegTable;
2340
2341 switch (pAd->RfIcType)
2342 {
2343 /* But only 2850 and 2750 support 5.5GHz band... */
2344 case RFIC_2820:
2345 case RFIC_2850:
2346 case RFIC_2720:
2347 case RFIC_2750:
2348
2349 for (index = 0; index < NUM_OF_2850_CHNL; index++)
2350 {
2351 if (Channel == RFRegTable[index].Channel)
2352 {
2353 R2 = RFRegTable[index].R2;
2354 if (pAd->Antenna.field.TxPath == 1)
2355 {
2356 R2 |= 0x4000; // If TXpath is 1, bit 14 = 1;
2357 }
2358
2359 if (pAd->Antenna.field.RxPath == 2)
2360 {
2361 switch (pAd->ate.RxAntennaSel)
2362 {
2363 case 1:
2364 R2 |= 0x20040;
2365 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2366 BbpValue &= 0xE4;
2367 BbpValue |= 0x00;
2368 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2369 break;
2370 case 2:
2371 R2 |= 0x10040;
2372 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2373 BbpValue &= 0xE4;
2374 BbpValue |= 0x01;
2375 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2376 break;
2377 default:
2378 R2 |= 0x40;
2379 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2380 BbpValue &= 0xE4;
2381 /* Only enable two Antenna to receive. */
2382 BbpValue |= 0x08;
2383 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2384 break;
2385 }
2386 }
2387 else if (pAd->Antenna.field.RxPath == 1)
2388 {
2389 R2 |= 0x20040; // write 1 to off RxPath
2390 }
2391
2392 if (pAd->Antenna.field.TxPath == 2)
2393 {
2394 if (pAd->ate.TxAntennaSel == 1)
2395 {
2396 R2 |= 0x4000; // If TX Antenna select is 1 , bit 14 = 1; Disable Ant 2
2397 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2398 BbpValue &= 0xE7; //11100111B
2399 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2400 }
2401 else if (pAd->ate.TxAntennaSel == 2)
2402 {
2403 R2 |= 0x8000; // If TX Antenna select is 2 , bit 15 = 1; Disable Ant 1
2404 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2405 BbpValue &= 0xE7;
2406 BbpValue |= 0x08;
2407 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2408 }
2409 else
2410 {
2411 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2412 BbpValue &= 0xE7;
2413 BbpValue |= 0x10;
2414 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2415 }
2416 }
2417 if (pAd->Antenna.field.RxPath == 3)
2418 {
2419 switch (pAd->ate.RxAntennaSel)
2420 {
2421 case 1:
2422 R2 |= 0x20040;
2423 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2424 BbpValue &= 0xE4;
2425 BbpValue |= 0x00;
2426 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2427 break;
2428 case 2:
2429 R2 |= 0x10040;
2430 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2431 BbpValue &= 0xE4;
2432 BbpValue |= 0x01;
2433 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2434 break;
2435 case 3:
2436 R2 |= 0x30000;
2437 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2438 BbpValue &= 0xE4;
2439 BbpValue |= 0x02;
2440 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2441 break;
2442 default:
2443 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2444 BbpValue &= 0xE4;
2445 BbpValue |= 0x10;
2446 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2447 break;
2448 }
2449 }
2450
2451 if (Channel > 14)
2452 {
2453 // initialize R3, R4
2454 R3 = (RFRegTable[index].R3 & 0xffffc1ff);
2455 R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->ate.RFFreqOffset << 15);
2456
2457 // According the Rory's suggestion to solve the middle range issue.
2458 // 5.5G band power range: 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0" means the TX power reduce 7dB
2459 // R3
2460 if ((TxPwer >= -7) && (TxPwer < 0))
2461 {
2462 TxPwer = (7+TxPwer);
2463 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
2464 R3 |= (TxPwer << 10);
2465 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer=%d \n", TxPwer));
2466 }
2467 else
2468 {
2469 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
2470 R3 |= (TxPwer << 10) | (1 << 9);
2471 }
2472
2473 // R4
2474 if ((TxPwer2 >= -7) && (TxPwer2 < 0))
2475 {
2476 TxPwer2 = (7+TxPwer2);
2477 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
2478 R4 |= (TxPwer2 << 7);
2479 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
2480 }
2481 else
2482 {
2483 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
2484 R4 |= (TxPwer2 << 7) | (1 << 6);
2485 }
2486 }
2487 else
2488 {
2489 R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); // set TX power0
2490 R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->ate.RFFreqOffset << 15) | (TxPwer2 <<6);// Set freq offset & TxPwr1
2491 }
2492
2493 // Based on BBP current mode before changing RF channel.
2494 if (pAd->ate.TxWI.BW == BW_40)
2495 {
2496 R4 |=0x200000;
2497 }
2498
2499 // Update variables
2500 pAd->LatchRfRegs.Channel = Channel;
2501 pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
2502 pAd->LatchRfRegs.R2 = R2;
2503 pAd->LatchRfRegs.R3 = R3;
2504 pAd->LatchRfRegs.R4 = R4;
2505
2506 RtmpRfIoWrite(pAd);
2507
2508 break;
2509 }
2510 }
2511 break;
2512
2513 default:
2514 break;
2515 }
2516
2517 // Change BBP setting during switch from a->g, g->a
2518 if (Channel <= 14)
2519 {
2520 ULONG TxPinCfg = 0x00050F0A;// 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A
2521
2522 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
2523 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
2524 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
2525
2526 /* For 1T/2R chip only... */
2527 if (pAd->NicConfig2.field.ExternalLNAForG)
2528 {
2529 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
2530 }
2531 else
2532 {
2533 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
2534 }
2535
2536 // According the Rory's suggestion to solve the middle range issue.
2537 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R86, &BbpValue);
2538 ASSERT((BbpValue == 0x00));
2539 if ((BbpValue != 0x00))
2540 {
2541 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x00);
2542 }
2543
2544 // 5.5GHz band selection PIN, bit1 and bit2 are complement
2545 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
2546 Value &= (~0x6);
2547 Value |= (0x04);
2548 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
2549
2550 // Turn off unused PA or LNA when only 1T or 1R.
2551 if (pAd->Antenna.field.TxPath == 1)
2552 {
2553 TxPinCfg &= 0xFFFFFFF3;
2554 }
2555 if (pAd->Antenna.field.RxPath == 1)
2556 {
2557 TxPinCfg &= 0xFFFFF3FF;
2558 }
2559
2560 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
2561 }
2562 else
2563 {
2564 ULONG TxPinCfg = 0x00050F05;//2007.10.09 by Brian : 0x00050505 ==> 0x00050F05
2565
2566 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
2567 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
2568 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
2569 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
2570
2571 // According the Rory's suggestion to solve the middle range issue.
2572 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R86, &BbpValue);
2573 ASSERT((BbpValue == 0x00));
2574 if ((BbpValue != 0x00))
2575 {
2576 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x00);
2577 }
2578 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
2579 ASSERT((BbpValue == 0x04));
2580
2581 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R92, &BbpValue);
2582 ASSERT((BbpValue == 0x00));
2583
2584 // 5.5GHz band selection PIN, bit1 and bit2 are complement
2585 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
2586 Value &= (~0x6);
2587 Value |= (0x02);
2588 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
2589
2590 // Turn off unused PA or LNA when only 1T or 1R.
2591 if (pAd->Antenna.field.TxPath == 1)
2592 {
2593 TxPinCfg &= 0xFFFFFFF3;
2594 }
2595 if (pAd->Antenna.field.RxPath == 1)
2596 {
2597 TxPinCfg &= 0xFFFFF3FF;
2598 }
2599
2600 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
2601 }
2602
2603 // R66 should be set according to Channel and use 20MHz when scanning
2604 if (Channel <= 14)
2605 {
2606 // BG band
2607 R66 = 0x2E + GET_LNA_GAIN(pAd);
2608 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
2609 }
2610 else
2611 {
2612 // 5.5 GHz band
2613 if (pAd->ate.TxWI.BW == BW_20)
2614 {
2615 R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3);
2616 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
2617 }
2618 else
2619 {
2620 R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3);
2621 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
2622 }
2623 }
2624
2625 //
2626 // On 11A, We should delay and wait RF/BBP to be stable
2627 // and the appropriate time should be 1000 micro seconds
2628 // 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
2629 //
2630 RTMPusecDelay(1000);
2631
2632 if (Channel > 14)
2633 {
2634 // When 5.5GHz band the LSB of TxPwr will be used to reduced 7dB or not.
2635 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
2636 Channel,
2637 pAd->RfIcType,
2638 pAd->Antenna.field.TxPath,
2639 pAd->LatchRfRegs.R1,
2640 pAd->LatchRfRegs.R2,
2641 pAd->LatchRfRegs.R3,
2642 pAd->LatchRfRegs.R4));
2643 }
2644 else
2645 {
2646 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
2647 Channel,
2648 pAd->RfIcType,
2649 (R3 & 0x00003e00) >> 9,
2650 (R4 & 0x000007c0) >> 6,
2651 pAd->Antenna.field.TxPath,
2652 pAd->LatchRfRegs.R1,
2653 pAd->LatchRfRegs.R2,
2654 pAd->LatchRfRegs.R3,
2655 pAd->LatchRfRegs.R4));
2656 }
2657 }
2658
2659 //
2660 // In fact, no one will call this routine so far !
2661 //
2662 /*
2663 ==========================================================================
2664 Description:
2665 Gives CCK TX rate 2 more dB TX power.
2666 This routine works only in ATE mode.
2667
2668 calculate desired Tx power in RF R3.Tx0~5, should consider -
2669 0. if current radio is a noisy environment (pAd->DrsCounters.fNoisyEnvironment)
2670 1. TxPowerPercentage
2671 2. auto calibration based on TSSI feedback
2672 3. extra 2 db for CCK
2673 4. -10 db upon very-short distance (AvgRSSI >= -40db) to AP
2674
2675 NOTE: Since this routine requires the value of (pAd->DrsCounters.fNoisyEnvironment),
2676 it should be called AFTER MlmeDynamicTxRateSwitching()
2677 ==========================================================================
2678 */
2679 VOID ATEAsicAdjustTxPower(
2680 IN PRTMP_ADAPTER pAd)
2681 {
2682 INT i, j;
2683 CHAR DeltaPwr = 0;
2684 BOOLEAN bAutoTxAgc = FALSE;
2685 UCHAR TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep;
2686 UCHAR BbpR49 = 0, idx;
2687 PCHAR pTxAgcCompensate;
2688 ULONG TxPwr[5];
2689 CHAR Value;
2690
2691 /* no one calls this procedure so far */
2692 if (pAd->ate.TxWI.BW == BW_40)
2693 {
2694 if (pAd->ate.Channel > 14)
2695 {
2696 TxPwr[0] = pAd->Tx40MPwrCfgABand[0];
2697 TxPwr[1] = pAd->Tx40MPwrCfgABand[1];
2698 TxPwr[2] = pAd->Tx40MPwrCfgABand[2];
2699 TxPwr[3] = pAd->Tx40MPwrCfgABand[3];
2700 TxPwr[4] = pAd->Tx40MPwrCfgABand[4];
2701 }
2702 else
2703 {
2704 TxPwr[0] = pAd->Tx40MPwrCfgGBand[0];
2705 TxPwr[1] = pAd->Tx40MPwrCfgGBand[1];
2706 TxPwr[2] = pAd->Tx40MPwrCfgGBand[2];
2707 TxPwr[3] = pAd->Tx40MPwrCfgGBand[3];
2708 TxPwr[4] = pAd->Tx40MPwrCfgGBand[4];
2709 }
2710 }
2711 else
2712 {
2713 if (pAd->ate.Channel > 14)
2714 {
2715 TxPwr[0] = pAd->Tx20MPwrCfgABand[0];
2716 TxPwr[1] = pAd->Tx20MPwrCfgABand[1];
2717 TxPwr[2] = pAd->Tx20MPwrCfgABand[2];
2718 TxPwr[3] = pAd->Tx20MPwrCfgABand[3];
2719 TxPwr[4] = pAd->Tx20MPwrCfgABand[4];
2720 }
2721 else
2722 {
2723 TxPwr[0] = pAd->Tx20MPwrCfgGBand[0];
2724 TxPwr[1] = pAd->Tx20MPwrCfgGBand[1];
2725 TxPwr[2] = pAd->Tx20MPwrCfgGBand[2];
2726 TxPwr[3] = pAd->Tx20MPwrCfgGBand[3];
2727 TxPwr[4] = pAd->Tx20MPwrCfgGBand[4];
2728 }
2729 }
2730
2731 // TX power compensation for temperature variation based on TSSI.
2732 // Do it per 4 seconds.
2733 if (pAd->Mlme.OneSecPeriodicRound % 4 == 0)
2734 {
2735 if (pAd->ate.Channel <= 14)
2736 {
2737 /* bg channel */
2738 bAutoTxAgc = pAd->bAutoTxAgcG;
2739 TssiRef = pAd->TssiRefG;
2740 pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0];
2741 pTssiPlusBoundary = &pAd->TssiPlusBoundaryG[0];
2742 TxAgcStep = pAd->TxAgcStepG;
2743 pTxAgcCompensate = &pAd->TxAgcCompensateG;
2744 }
2745 else
2746 {
2747 /* a channel */
2748 bAutoTxAgc = pAd->bAutoTxAgcA;
2749 TssiRef = pAd->TssiRefA;
2750 pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0];
2751 pTssiPlusBoundary = &pAd->TssiPlusBoundaryA[0];
2752 TxAgcStep = pAd->TxAgcStepA;
2753 pTxAgcCompensate = &pAd->TxAgcCompensateA;
2754 }
2755
2756 if (bAutoTxAgc)
2757 {
2758 /* BbpR49 is unsigned char */
2759 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49);
2760
2761 /* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */
2762 /* compensate: +4 +3 +2 +1 0 -1 -2 -3 -4 * steps */
2763 /* step value is defined in pAd->TxAgcStepG for tx power value */
2764
2765 /* [4]+1+[4] p4 p3 p2 p1 o1 m1 m2 m3 m4 */
2766 /* ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
2767 above value are examined in mass factory production */
2768 /* [4] [3] [2] [1] [0] [1] [2] [3] [4] */
2769
2770 /* plus is 0x10 ~ 0x40, minus is 0x60 ~ 0x90 */
2771 /* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */
2772 /* if value is 0x65, tx power will be -= TxAgcStep*(2-1) */
2773
2774 if (BbpR49 > pTssiMinusBoundary[1])
2775 {
2776 // Reading is larger than the reference value.
2777 // Check for how large we need to decrease the Tx power.
2778 for (idx = 1; idx < 5; idx++)
2779 {
2780 if (BbpR49 <= pTssiMinusBoundary[idx]) // Found the range
2781 break;
2782 }
2783 // The index is the step we should decrease, idx = 0 means there is nothing to compensate
2784 // if (R3 > (ULONG) (TxAgcStep * (idx-1)))
2785 *pTxAgcCompensate = -(TxAgcStep * (idx-1));
2786 // else
2787 // *pTxAgcCompensate = -((UCHAR)R3);
2788
2789 DeltaPwr += (*pTxAgcCompensate);
2790 ATEDBGPRINT(RT_DEBUG_TRACE, ("-- Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n",
2791 BbpR49, TssiRef, TxAgcStep, idx-1));
2792 }
2793 else if (BbpR49 < pTssiPlusBoundary[1])
2794 {
2795 // Reading is smaller than the reference value
2796 // check for how large we need to increase the Tx power
2797 for (idx = 1; idx < 5; idx++)
2798 {
2799 if (BbpR49 >= pTssiPlusBoundary[idx]) // Found the range
2800 break;
2801 }
2802 // The index is the step we should increase, idx = 0 means there is nothing to compensate
2803 *pTxAgcCompensate = TxAgcStep * (idx-1);
2804 DeltaPwr += (*pTxAgcCompensate);
2805 ATEDBGPRINT(RT_DEBUG_TRACE, ("++ Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
2806 BbpR49, TssiRef, TxAgcStep, idx-1));
2807 }
2808 else
2809 {
2810 *pTxAgcCompensate = 0;
2811 ATEDBGPRINT(RT_DEBUG_TRACE, (" Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
2812 BbpR49, TssiRef, TxAgcStep, 0));
2813 }
2814 }
2815 }
2816 else
2817 {
2818 if (pAd->ate.Channel <= 14)
2819 {
2820 bAutoTxAgc = pAd->bAutoTxAgcG;
2821 pTxAgcCompensate = &pAd->TxAgcCompensateG;
2822 }
2823 else
2824 {
2825 bAutoTxAgc = pAd->bAutoTxAgcA;
2826 pTxAgcCompensate = &pAd->TxAgcCompensateA;
2827 }
2828
2829 if (bAutoTxAgc)
2830 DeltaPwr += (*pTxAgcCompensate);
2831 }
2832
2833 /* calculate delta power based on the percentage specified from UI */
2834 // E2PROM setting is calibrated for maximum TX power (i.e. 100%)
2835 // We lower TX power here according to the percentage specified from UI
2836 if (pAd->CommonCfg.TxPowerPercentage == 0xffffffff) // AUTO TX POWER control
2837 ;
2838 else if (pAd->CommonCfg.TxPowerPercentage > 90) // 91 ~ 100% & AUTO, treat as 100% in terms of mW
2839 ;
2840 else if (pAd->CommonCfg.TxPowerPercentage > 60) // 61 ~ 90%, treat as 75% in terms of mW
2841 {
2842 DeltaPwr -= 1;
2843 }
2844 else if (pAd->CommonCfg.TxPowerPercentage > 30) // 31 ~ 60%, treat as 50% in terms of mW
2845 {
2846 DeltaPwr -= 3;
2847 }
2848 else if (pAd->CommonCfg.TxPowerPercentage > 15) // 16 ~ 30%, treat as 25% in terms of mW
2849 {
2850 DeltaPwr -= 6;
2851 }
2852 else if (pAd->CommonCfg.TxPowerPercentage > 9) // 10 ~ 15%, treat as 12.5% in terms of mW
2853 {
2854 DeltaPwr -= 9;
2855 }
2856 else // 0 ~ 9 %, treat as MIN(~3%) in terms of mW
2857 {
2858 DeltaPwr -= 12;
2859 }
2860
2861 /* reset different new tx power for different TX rate */
2862 for(i=0; i<5; i++)
2863 {
2864 if (TxPwr[i] != 0xffffffff)
2865 {
2866 for (j=0; j<8; j++)
2867 {
2868 Value = (CHAR)((TxPwr[i] >> j*4) & 0x0F); /* 0 ~ 15 */
2869
2870 if ((Value + DeltaPwr) < 0)
2871 {
2872 Value = 0; /* min */
2873 }
2874 else if ((Value + DeltaPwr) > 0xF)
2875 {
2876 Value = 0xF; /* max */
2877 }
2878 else
2879 {
2880 Value += DeltaPwr; /* temperature compensation */
2881 }
2882
2883 /* fill new value to CSR offset */
2884 TxPwr[i] = (TxPwr[i] & ~(0x0000000F << j*4)) | (Value << j*4);
2885 }
2886
2887 /* write tx power value to CSR */
2888 /* TX_PWR_CFG_0 (8 tx rate) for TX power for OFDM 12M/18M
2889 TX power for OFDM 6M/9M
2890 TX power for CCK5.5M/11M
2891 TX power for CCK1M/2M */
2892 /* TX_PWR_CFG_1 ~ TX_PWR_CFG_4 */
2893 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, TxPwr[i]);
2894
2895
2896 }
2897 }
2898
2899 }
2900
2901 /*
2902 ========================================================================
2903 Routine Description:
2904 Write TxWI for ATE mode.
2905
2906 Return Value:
2907 None
2908 ========================================================================
2909 */
2910 #ifdef RT2860
2911 static VOID ATEWriteTxWI(
2912 IN PRTMP_ADAPTER pAd,
2913 IN PTXWI_STRUC pOutTxWI,
2914 IN BOOLEAN FRAG,
2915 IN BOOLEAN CFACK,
2916 IN BOOLEAN InsTimestamp,
2917 IN BOOLEAN AMPDU,
2918 IN BOOLEAN Ack,
2919 IN BOOLEAN NSeq, // HW new a sequence.
2920 IN UCHAR BASize,
2921 IN UCHAR WCID,
2922 IN ULONG Length,
2923 IN UCHAR PID,
2924 IN UCHAR TID,
2925 IN UCHAR TxRate,
2926 IN UCHAR Txopmode,
2927 IN BOOLEAN CfAck,
2928 IN HTTRANSMIT_SETTING *pTransmit)
2929 {
2930 TXWI_STRUC TxWI;
2931 PTXWI_STRUC pTxWI;
2932
2933 //
2934 // Always use Long preamble before verifiation short preamble functionality works well.
2935 // Todo: remove the following line if short preamble functionality works
2936 //
2937 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
2938 NdisZeroMemory(&TxWI, TXWI_SIZE);
2939 pTxWI = &TxWI;
2940
2941 pTxWI->FRAG= FRAG;
2942
2943 pTxWI->CFACK = CFACK;
2944 pTxWI->TS= InsTimestamp;
2945 pTxWI->AMPDU = AMPDU;
2946 pTxWI->ACK = Ack;
2947 pTxWI->txop= Txopmode;
2948
2949 pTxWI->NSEQ = NSeq;
2950 // John tune the performace with Intel Client in 20 MHz performance
2951 if( BASize >7 )
2952 BASize =7;
2953
2954 pTxWI->BAWinSize = BASize;
2955 pTxWI->WirelessCliID = WCID;
2956 pTxWI->MPDUtotalByteCount = Length;
2957 pTxWI->PacketId = PID;
2958
2959 // If CCK or OFDM, BW must be 20
2960 pTxWI->BW = (pTransmit->field.MODE <= MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
2961 pTxWI->ShortGI = pTransmit->field.ShortGI;
2962 pTxWI->STBC = pTransmit->field.STBC;
2963
2964 pTxWI->MCS = pTransmit->field.MCS;
2965 pTxWI->PHYMODE = pTransmit->field.MODE;
2966 pTxWI->CFACK = CfAck;
2967 pTxWI->MIMOps = 0;
2968 pTxWI->MpduDensity = 0;
2969
2970 pTxWI->PacketId = pTxWI->MCS;
2971 NdisMoveMemory(pOutTxWI, &TxWI, sizeof(TXWI_STRUC));
2972
2973 return;
2974 }
2975 #endif // RT2860 //
2976
2977 /*
2978 ========================================================================
2979
2980 Routine Description:
2981 Disable protection for ATE.
2982 ========================================================================
2983 */
2984 VOID ATEDisableAsicProtect(
2985 IN PRTMP_ADAPTER pAd)
2986 {
2987 PROT_CFG_STRUC ProtCfg, ProtCfg4;
2988 UINT32 Protect[6];
2989 USHORT offset;
2990 UCHAR i;
2991 UINT32 MacReg = 0;
2992
2993 // Config ASIC RTS threshold register
2994 RTMP_IO_READ32(pAd, TX_RTS_CFG, &MacReg);
2995 MacReg &= 0xFF0000FF;
2996 MacReg |= (pAd->CommonCfg.RtsThreshold << 8);
2997 RTMP_IO_WRITE32(pAd, TX_RTS_CFG, MacReg);
2998
2999 // Initial common protection settings
3000 RTMPZeroMemory(Protect, sizeof(Protect));
3001 ProtCfg4.word = 0;
3002 ProtCfg.word = 0;
3003 ProtCfg.field.TxopAllowGF40 = 1;
3004 ProtCfg.field.TxopAllowGF20 = 1;
3005 ProtCfg.field.TxopAllowMM40 = 1;
3006 ProtCfg.field.TxopAllowMM20 = 1;
3007 ProtCfg.field.TxopAllowOfdm = 1;
3008 ProtCfg.field.TxopAllowCck = 1;
3009 ProtCfg.field.RTSThEn = 1;
3010 ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
3011
3012 // Handle legacy(B/G) protection
3013 ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate;
3014 ProtCfg.field.ProtectCtrl = 0;
3015 Protect[0] = ProtCfg.word;
3016 Protect[1] = ProtCfg.word;
3017
3018 // NO PROTECT
3019 // 1.All STAs in the BSS are 20/40 MHz HT
3020 // 2. in ai 20/40MHz BSS
3021 // 3. all STAs are 20MHz in a 20MHz BSS
3022 // Pure HT. no protection.
3023
3024 // MM20_PROT_CFG
3025 // Reserved (31:27)
3026 // PROT_TXOP(25:20) -- 010111
3027 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3028 // PROT_CTRL(17:16) -- 00 (None)
3029 // PROT_RATE(15:0) -- 0x4004 (OFDM 24M)
3030 Protect[2] = 0x01744004;
3031
3032 // MM40_PROT_CFG
3033 // Reserved (31:27)
3034 // PROT_TXOP(25:20) -- 111111
3035 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3036 // PROT_CTRL(17:16) -- 00 (None)
3037 // PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M)
3038 Protect[3] = 0x03f44084;
3039
3040 // CF20_PROT_CFG
3041 // Reserved (31:27)
3042 // PROT_TXOP(25:20) -- 010111
3043 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3044 // PROT_CTRL(17:16) -- 00 (None)
3045 // PROT_RATE(15:0) -- 0x4004 (OFDM 24M)
3046 Protect[4] = 0x01744004;
3047
3048 // CF40_PROT_CFG
3049 // Reserved (31:27)
3050 // PROT_TXOP(25:20) -- 111111
3051 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3052 // PROT_CTRL(17:16) -- 00 (None)
3053 // PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M)
3054 Protect[5] = 0x03f44084;
3055
3056 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
3057
3058 offset = CCK_PROT_CFG;
3059 for (i = 0;i < 6;i++)
3060 RTMP_IO_WRITE32(pAd, offset + i*4, Protect[i]);
3061
3062 }
3063
3064
3065 /* There are two ways to convert Rssi */
3066 #if 1
3067 //
3068 // The way used with GET_LNA_GAIN().
3069 //
3070 CHAR ATEConvertToRssi(
3071 IN PRTMP_ADAPTER pAd,
3072 IN CHAR Rssi,
3073 IN UCHAR RssiNumber)
3074 {
3075 UCHAR RssiOffset, LNAGain;
3076
3077 // Rssi equals to zero should be an invalid value
3078 if (Rssi == 0)
3079 return -99;
3080
3081 LNAGain = GET_LNA_GAIN(pAd);
3082 if (pAd->LatchRfRegs.Channel > 14)
3083 {
3084 if (RssiNumber == 0)
3085 RssiOffset = pAd->ARssiOffset0;
3086 else if (RssiNumber == 1)
3087 RssiOffset = pAd->ARssiOffset1;
3088 else
3089 RssiOffset = pAd->ARssiOffset2;
3090 }
3091 else
3092 {
3093 if (RssiNumber == 0)
3094 RssiOffset = pAd->BGRssiOffset0;
3095 else if (RssiNumber == 1)
3096 RssiOffset = pAd->BGRssiOffset1;
3097 else
3098 RssiOffset = pAd->BGRssiOffset2;
3099 }
3100
3101 return (-12 - RssiOffset - LNAGain - Rssi);
3102 }
3103 #else
3104 //
3105 // The way originally used in ATE of rt2860ap.
3106 //
3107 CHAR ATEConvertToRssi(
3108 IN PRTMP_ADAPTER pAd,
3109 IN CHAR Rssi,
3110 IN UCHAR RssiNumber)
3111 {
3112 UCHAR RssiOffset, LNAGain;
3113
3114 // Rssi equals to zero should be an invalid value
3115 if (Rssi == 0)
3116 return -99;
3117
3118 if (pAd->LatchRfRegs.Channel > 14)
3119 {
3120 LNAGain = pAd->ALNAGain;
3121 if (RssiNumber == 0)
3122 RssiOffset = pAd->ARssiOffset0;
3123 else if (RssiNumber == 1)
3124 RssiOffset = pAd->ARssiOffset1;
3125 else
3126 RssiOffset = pAd->ARssiOffset2;
3127 }
3128 else
3129 {
3130 LNAGain = pAd->BLNAGain;
3131 if (RssiNumber == 0)
3132 RssiOffset = pAd->BGRssiOffset0;
3133 else if (RssiNumber == 1)
3134 RssiOffset = pAd->BGRssiOffset1;
3135 else
3136 RssiOffset = pAd->BGRssiOffset2;
3137 }
3138
3139 return (-32 - RssiOffset + LNAGain - Rssi);
3140 }
3141 #endif /* end of #if 1 */
3142
3143 /*
3144 ========================================================================
3145
3146 Routine Description:
3147 Set Japan filter coefficients if needed.
3148 Note:
3149 This routine should only be called when
3150 entering TXFRAME mode or TXCONT mode.
3151
3152 ========================================================================
3153 */
3154 static VOID SetJapanFilter(
3155 IN PRTMP_ADAPTER pAd)
3156 {
3157 UCHAR BbpData = 0;
3158
3159 //
3160 // If Channel=14 and Bandwidth=20M and Mode=CCK, set BBP R4 bit5=1
3161 // (Japan Tx filter coefficients)when (TXFRAME or TXCONT).
3162 //
3163 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BbpData);
3164
3165 if ((pAd->ate.TxWI.PHYMODE == MODE_CCK) && (pAd->ate.Channel == 14) && (pAd->ate.TxWI.BW == BW_20))
3166 {
3167 BbpData |= 0x20; // turn on
3168 ATEDBGPRINT(RT_DEBUG_TRACE, ("SetJapanFilter!!!\n"));
3169 }
3170 else
3171 {
3172 BbpData &= 0xdf; // turn off
3173 ATEDBGPRINT(RT_DEBUG_TRACE, ("ClearJapanFilter!!!\n"));
3174 }
3175
3176 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData);
3177 }
3178
3179 VOID ATESampleRssi(
3180 IN PRTMP_ADAPTER pAd,
3181 IN PRXWI_STRUC pRxWI)
3182 {
3183 /* There are two ways to collect RSSI. */
3184 #if 1
3185 //pAd->LastRxRate = (USHORT)((pRxWI->MCS) + (pRxWI->BW <<7) + (pRxWI->ShortGI <<8)+ (pRxWI->PHYMODE <<14)) ;
3186 if (pRxWI->RSSI0 != 0)
3187 {
3188 pAd->ate.LastRssi0 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI0, RSSI_0);
3189 pAd->ate.AvgRssi0X8 = (pAd->ate.AvgRssi0X8 - pAd->ate.AvgRssi0) + pAd->ate.LastRssi0;
3190 pAd->ate.AvgRssi0 = pAd->ate.AvgRssi0X8 >> 3;
3191 }
3192 if (pRxWI->RSSI1 != 0)
3193 {
3194 pAd->ate.LastRssi1 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI1, RSSI_1);
3195 pAd->ate.AvgRssi1X8 = (pAd->ate.AvgRssi1X8 - pAd->ate.AvgRssi1) + pAd->ate.LastRssi1;
3196 pAd->ate.AvgRssi1 = pAd->ate.AvgRssi1X8 >> 3;
3197 }
3198 if (pRxWI->RSSI2 != 0)
3199 {
3200 pAd->ate.LastRssi2 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI2, RSSI_2);
3201 pAd->ate.AvgRssi2X8 = (pAd->ate.AvgRssi2X8 - pAd->ate.AvgRssi2) + pAd->ate.LastRssi2;
3202 pAd->ate.AvgRssi2 = pAd->ate.AvgRssi2X8 >> 3;
3203 }
3204
3205 pAd->ate.LastSNR0 = (CHAR)(pRxWI->SNR0);// CHAR ==> UCHAR ?
3206 pAd->ate.LastSNR1 = (CHAR)(pRxWI->SNR1);// CHAR ==> UCHAR ?
3207
3208 pAd->ate.NumOfAvgRssiSample ++;
3209 #else
3210 pAd->ate.LastSNR0 = (CHAR)(pRxWI->SNR0);
3211 pAd->ate.LastSNR1 = (CHAR)(pRxWI->SNR1);
3212 pAd->ate.RxCntPerSec++;
3213 pAd->ate.LastRssi0 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI0, RSSI_0);
3214 pAd->ate.LastRssi1 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI1, RSSI_1);
3215 pAd->ate.LastRssi2 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI2, RSSI_2);
3216 pAd->ate.AvgRssi0X8 = (pAd->ate.AvgRssi0X8 - pAd->ate.AvgRssi0) + pAd->ate.LastRssi0;
3217 pAd->ate.AvgRssi0 = pAd->ate.AvgRssi0X8 >> 3;
3218 pAd->ate.AvgRssi1X8 = (pAd->ate.AvgRssi1X8 - pAd->ate.AvgRssi1) + pAd->ate.LastRssi1;
3219 pAd->ate.AvgRssi1 = pAd->ate.AvgRssi1X8 >> 3;
3220 pAd->ate.AvgRssi2X8 = (pAd->ate.AvgRssi2X8 - pAd->ate.AvgRssi2) + pAd->ate.LastRssi2;
3221 pAd->ate.AvgRssi2 = pAd->ate.AvgRssi2X8 >> 3;
3222 pAd->ate.NumOfAvgRssiSample ++;
3223 #endif
3224 }
3225
3226 #ifdef CONFIG_STA_SUPPORT
3227 VOID RTMPStationStop(
3228 IN PRTMP_ADAPTER pAd)
3229 {
3230 // BOOLEAN Cancelled;
3231
3232 ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStop\n"));
3233
3234 #if 0
3235 RTMPCancelTimer(&pAd->MlmeAux.AssocTimer, &Cancelled);
3236 RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer, &Cancelled);
3237 RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &Cancelled);
3238 RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled);
3239 RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled);
3240 RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled);
3241 #endif
3242 // For rx statistics, we need to keep this timer running.
3243 // RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled);
3244
3245 ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStop\n"));
3246 }
3247
3248 VOID RTMPStationStart(
3249 IN PRTMP_ADAPTER pAd)
3250 {
3251 ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStart\n"));
3252 #ifdef RT2860
3253 pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
3254 //
3255 // We did not cancel this timer when entering ATE mode.
3256 //
3257 // RTMPSetTimer(&pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV);
3258 #endif // RT2860 //
3259 ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStart\n"));
3260 }
3261 #endif // CONFIG_STA_SUPPORT //
3262
3263 /*
3264 ==========================================================================
3265 Description:
3266 Setup Frame format.
3267 NOTE:
3268 This routine should only be used in ATE mode.
3269 ==========================================================================
3270 */
3271 #ifdef RT2860
3272 static INT ATESetUpFrame(
3273 IN PRTMP_ADAPTER pAd,
3274 IN UINT32 TxIdx)
3275 {
3276 UINT j;
3277 PTXD_STRUC pTxD;
3278 #ifdef RT_BIG_ENDIAN
3279 PTXD_STRUC pDestTxD;
3280 TXD_STRUC TxD;
3281 #endif
3282 PNDIS_PACKET pPacket;
3283 PUCHAR pDest;
3284 PVOID AllocVa;
3285 NDIS_PHYSICAL_ADDRESS AllocPa;
3286 HTTRANSMIT_SETTING TxHTPhyMode;
3287
3288 PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
3289 PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
3290 PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
3291
3292 #ifdef RALINK_28xx_QA
3293 PHEADER_802_11 pHeader80211;
3294 #endif // RALINK_28xx_QA //
3295
3296 if (pAd->ate.bQATxStart == TRUE)
3297 {
3298 // always use QID_AC_BE and FIFO_EDCA
3299
3300 // fill TxWI
3301 TxHTPhyMode.field.BW = pAd->ate.TxWI.BW;
3302 TxHTPhyMode.field.ShortGI = pAd->ate.TxWI.ShortGI;
3303 TxHTPhyMode.field.STBC = 0;
3304 TxHTPhyMode.field.MCS = pAd->ate.TxWI.MCS;
3305 TxHTPhyMode.field.MODE = pAd->ate.TxWI.PHYMODE;
3306 ATEWriteTxWI(pAd, pTxWI, pAd->ate.TxWI.FRAG, pAd->ate.TxWI.CFACK, pAd->ate.TxWI.TS, pAd->ate.TxWI.AMPDU, pAd->ate.TxWI.ACK, pAd->ate.TxWI.NSEQ,
3307 pAd->ate.TxWI.BAWinSize, 0, pAd->ate.TxWI.MPDUtotalByteCount, pAd->ate.TxWI.PacketId, 0, 0, pAd->ate.TxWI.txop/*IFS_HTTXOP*/, pAd->ate.TxWI.CFACK/*FALSE*/, &TxHTPhyMode);
3308 }
3309 else
3310 {
3311 TxHTPhyMode.field.BW = pAd->ate.TxWI.BW;
3312 TxHTPhyMode.field.ShortGI = pAd->ate.TxWI.ShortGI;
3313 TxHTPhyMode.field.STBC = 0;
3314 TxHTPhyMode.field.MCS = pAd->ate.TxWI.MCS;
3315 TxHTPhyMode.field.MODE = pAd->ate.TxWI.PHYMODE;
3316 ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
3317 4, 0, pAd->ate.TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
3318 }
3319
3320 // fill 802.11 header.
3321 #ifdef RALINK_28xx_QA
3322 if (pAd->ate.bQATxStart == TRUE)
3323 {
3324 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE, pAd->ate.Header, pAd->ate.HLen);
3325 }
3326 else
3327 #endif // RALINK_28xx_QA //
3328 {
3329 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE, TemplateFrame, LENGTH_802_11);
3330 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE+4, pAd->ate.Addr1, ETH_LENGTH_OF_ADDRESS);
3331 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE+10, pAd->ate.Addr2, ETH_LENGTH_OF_ADDRESS);
3332 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE+16, pAd->ate.Addr3, ETH_LENGTH_OF_ADDRESS);
3333 }
3334
3335 #ifdef RT_BIG_ENDIAN
3336 RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA)+TXWI_SIZE), DIR_READ, FALSE);
3337 #endif // RT_BIG_ENDIAN //
3338
3339 /* alloc buffer for payload */
3340 #ifdef RALINK_28xx_QA
3341 if (pAd->ate.bQATxStart == TRUE)
3342 {
3343 /* Why not use RTMP_AllocateTxPacketBuffer() instead of RTMP_AllocateRxPacketBuffer()? */
3344 pPacket = RTMP_AllocateRxPacketBuffer(pAd, pAd->ate.DLen + 0x100, FALSE, &AllocVa, &AllocPa);
3345 }
3346 else
3347 #endif // RALINK_28xx_QA //
3348 {
3349 /* Why not use RTMP_AllocateTxPacketBuffer() instead of RTMP_AllocateRxPacketBuffer()? */
3350 pPacket = RTMP_AllocateRxPacketBuffer(pAd, pAd->ate.TxLength, FALSE, &AllocVa, &AllocPa);
3351 }
3352
3353 if (pPacket == NULL)
3354 {
3355 pAd->ate.TxCount = 0;
3356 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s fail to alloc packet space.\n", __func__));
3357 return -1;
3358 }
3359 pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
3360
3361 pDest = (PUCHAR) AllocVa;
3362
3363 #ifdef RALINK_28xx_QA
3364 if (pAd->ate.bQATxStart == TRUE)
3365 {
3366 RTPKT_TO_OSPKT(pPacket)->len = pAd->ate.DLen;
3367 }
3368 else
3369 #endif // RALINK_28xx_QA //
3370 {
3371 RTPKT_TO_OSPKT(pPacket)->len = pAd->ate.TxLength - LENGTH_802_11;
3372 }
3373
3374 // Prepare frame payload
3375 #ifdef RALINK_28xx_QA
3376 if (pAd->ate.bQATxStart == TRUE)
3377 {
3378 // copy pattern
3379 if ((pAd->ate.PLen != 0))
3380 {
3381 int j;
3382
3383 for (j = 0; j < pAd->ate.DLen; j+=pAd->ate.PLen)
3384 {
3385 memcpy(RTPKT_TO_OSPKT(pPacket)->data + j, pAd->ate.Pattern, pAd->ate.PLen);
3386 }
3387 }
3388 }
3389 else
3390 #endif // RALINK_28xx_QA //
3391 {
3392 for(j = 0; j < RTPKT_TO_OSPKT(pPacket)->len; j++)
3393 pDest[j] = 0xA5;
3394 }
3395
3396 //
3397 // build Tx Descriptor
3398 //
3399 #ifndef RT_BIG_ENDIAN
3400 pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
3401 #else
3402 pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
3403 TxD = *pDestTxD;
3404 pTxD = &TxD;
3405 #endif // !RT_BIG_ENDIAN //
3406
3407 #ifdef RALINK_28xx_QA
3408 if (pAd->ate.bQATxStart == TRUE)
3409 {
3410 // prepare TxD
3411 NdisZeroMemory(pTxD, TXD_SIZE);
3412 RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
3413 // build TX DESC
3414 pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
3415 pTxD->SDLen0 = TXWI_SIZE + pAd->ate.HLen;
3416 pTxD->LastSec0 = 0;
3417 pTxD->SDPtr1 = AllocPa;
3418 pTxD->SDLen1 = RTPKT_TO_OSPKT(pPacket)->len;
3419 pTxD->LastSec1 = 1;
3420
3421 pDest = (PUCHAR)pTxWI;
3422 pDest += TXWI_SIZE;
3423 pHeader80211 = (PHEADER_802_11)pDest;
3424
3425 // modify sequence number....
3426 if (pAd->ate.TxDoneCount == 0)
3427 {
3428 pAd->ate.seq = pHeader80211->Sequence;
3429 }
3430 else
3431 pHeader80211->Sequence = ++pAd->ate.seq;
3432 }
3433 else
3434 #endif // RALINK_28xx_QA //
3435 {
3436 NdisZeroMemory(pTxD, TXD_SIZE);
3437 RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
3438 // build TX DESC
3439 pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
3440 pTxD->SDLen0 = TXWI_SIZE + LENGTH_802_11;
3441 pTxD->LastSec0 = 0;
3442 pTxD->SDPtr1 = AllocPa;
3443 pTxD->SDLen1 = RTPKT_TO_OSPKT(pPacket)->len;
3444 pTxD->LastSec1 = 1;
3445 }
3446
3447 #ifdef RT_BIG_ENDIAN
3448 RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI);
3449 RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA)+TXWI_SIZE), DIR_WRITE, FALSE);
3450 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
3451 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
3452 #endif // RT_BIG_ENDIAN //
3453 return 0;
3454 }
3455 /* */
3456 /* */
3457 /*=======================End of RT2860=======================*/
3458 #endif // RT2860 //
3459
3460
3461 VOID rt_ee_read_all(PRTMP_ADAPTER pAd, USHORT *Data)
3462 {
3463 USHORT i;
3464 USHORT value;
3465
3466 for (i = 0 ; i < EEPROM_SIZE/2 ; )
3467 {
3468 /* "value" is expecially for some compilers... */
3469 RT28xx_EEPROM_READ16(pAd, i*2, value);
3470 Data[i] = value;
3471 i++;
3472 }
3473 }
3474
3475 VOID rt_ee_write_all(PRTMP_ADAPTER pAd, USHORT *Data)
3476 {
3477 USHORT i;
3478 USHORT value;
3479
3480 for (i = 0 ; i < EEPROM_SIZE/2 ; )
3481 {
3482 /* "value" is expecially for some compilers... */
3483 value = Data[i];
3484 RT28xx_EEPROM_WRITE16(pAd, i*2, value);
3485 i ++;
3486 }
3487 }
3488 #ifdef RALINK_28xx_QA
3489 VOID ATE_QA_Statistics(
3490 IN PRTMP_ADAPTER pAd,
3491 IN PRXWI_STRUC pRxWI,
3492 IN PRT28XX_RXD_STRUC pRxD,
3493 IN PHEADER_802_11 pHeader)
3494 {
3495 // update counter first
3496 if (pHeader != NULL)
3497 {
3498 if (pHeader->FC.Type == BTYPE_DATA)
3499 {
3500 if (pRxD->U2M)
3501 pAd->ate.U2M++;
3502 else
3503 pAd->ate.OtherData++;
3504 }
3505 else if (pHeader->FC.Type == BTYPE_MGMT)
3506 {
3507 if (pHeader->FC.SubType == SUBTYPE_BEACON)
3508 pAd->ate.Beacon++;
3509 else
3510 pAd->ate.OtherCount++;
3511 }
3512 else if (pHeader->FC.Type == BTYPE_CNTL)
3513 {
3514 pAd->ate.OtherCount++;
3515 }
3516 }
3517 pAd->ate.RSSI0 = pRxWI->RSSI0;
3518 pAd->ate.RSSI1 = pRxWI->RSSI1;
3519 pAd->ate.RSSI2 = pRxWI->RSSI2;
3520 pAd->ate.SNR0 = pRxWI->SNR0;
3521 pAd->ate.SNR1 = pRxWI->SNR1;
3522 }
3523
3524 /* command id with Cmd Type == 0x0008(for 28xx)/0x0005(for iNIC) */
3525 #define RACFG_CMD_RF_WRITE_ALL 0x0000
3526 #define RACFG_CMD_E2PROM_READ16 0x0001
3527 #define RACFG_CMD_E2PROM_WRITE16 0x0002
3528 #define RACFG_CMD_E2PROM_READ_ALL 0x0003
3529 #define RACFG_CMD_E2PROM_WRITE_ALL 0x0004
3530 #define RACFG_CMD_IO_READ 0x0005
3531 #define RACFG_CMD_IO_WRITE 0x0006
3532 #define RACFG_CMD_IO_READ_BULK 0x0007
3533 #define RACFG_CMD_BBP_READ8 0x0008
3534 #define RACFG_CMD_BBP_WRITE8 0x0009
3535 #define RACFG_CMD_BBP_READ_ALL 0x000a
3536 #define RACFG_CMD_GET_COUNTER 0x000b
3537 #define RACFG_CMD_CLEAR_COUNTER 0x000c
3538
3539 #define RACFG_CMD_RSV1 0x000d
3540 #define RACFG_CMD_RSV2 0x000e
3541 #define RACFG_CMD_RSV3 0x000f
3542
3543 #define RACFG_CMD_TX_START 0x0010
3544 #define RACFG_CMD_GET_TX_STATUS 0x0011
3545 #define RACFG_CMD_TX_STOP 0x0012
3546 #define RACFG_CMD_RX_START 0x0013
3547 #define RACFG_CMD_RX_STOP 0x0014
3548 #define RACFG_CMD_GET_NOISE_LEVEL 0x0015
3549
3550 #define RACFG_CMD_ATE_START 0x0080
3551 #define RACFG_CMD_ATE_STOP 0x0081
3552
3553 #define RACFG_CMD_ATE_START_TX_CARRIER 0x0100
3554 #define RACFG_CMD_ATE_START_TX_CONT 0x0101
3555 #define RACFG_CMD_ATE_START_TX_FRAME 0x0102
3556 #define RACFG_CMD_ATE_SET_BW 0x0103
3557 #define RACFG_CMD_ATE_SET_TX_POWER0 0x0104
3558 #define RACFG_CMD_ATE_SET_TX_POWER1 0x0105
3559 #define RACFG_CMD_ATE_SET_FREQ_OFFSET 0x0106
3560 #define RACFG_CMD_ATE_GET_STATISTICS 0x0107
3561 #define RACFG_CMD_ATE_RESET_COUNTER 0x0108
3562 #define RACFG_CMD_ATE_SEL_TX_ANTENNA 0x0109
3563 #define RACFG_CMD_ATE_SEL_RX_ANTENNA 0x010a
3564 #define RACFG_CMD_ATE_SET_PREAMBLE 0x010b
3565 #define RACFG_CMD_ATE_SET_CHANNEL 0x010c
3566 #define RACFG_CMD_ATE_SET_ADDR1 0x010d
3567 #define RACFG_CMD_ATE_SET_ADDR2 0x010e
3568 #define RACFG_CMD_ATE_SET_ADDR3 0x010f
3569 #define RACFG_CMD_ATE_SET_RATE 0x0110
3570 #define RACFG_CMD_ATE_SET_TX_FRAME_LEN 0x0111
3571 #define RACFG_CMD_ATE_SET_TX_FRAME_COUNT 0x0112
3572 #define RACFG_CMD_ATE_START_RX_FRAME 0x0113
3573 #define RACFG_CMD_ATE_E2PROM_READ_BULK 0x0114
3574 #define RACFG_CMD_ATE_E2PROM_WRITE_BULK 0x0115
3575 #define RACFG_CMD_ATE_IO_WRITE_BULK 0x0116
3576 #define RACFG_CMD_ATE_BBP_READ_BULK 0x0117
3577 #define RACFG_CMD_ATE_BBP_WRITE_BULK 0x0118
3578 #define RACFG_CMD_ATE_RF_READ_BULK 0x0119
3579 #define RACFG_CMD_ATE_RF_WRITE_BULK 0x011a
3580
3581
3582
3583 #define A2Hex(_X, _p) \
3584 { \
3585 UCHAR *p; \
3586 _X = 0; \
3587 p = _p; \
3588 while (((*p >= 'a') && (*p <= 'f')) || ((*p >= 'A') && (*p <= 'F')) || ((*p >= '0') && (*p <= '9'))) \
3589 { \
3590 if ((*p >= 'a') && (*p <= 'f')) \
3591 _X = _X * 16 + *p - 87; \
3592 else if ((*p >= 'A') && (*p <= 'F')) \
3593 _X = _X * 16 + *p - 55; \
3594 else if ((*p >= '0') && (*p <= '9')) \
3595 _X = _X * 16 + *p - 48; \
3596 p++; \
3597 } \
3598 }
3599
3600
3601 static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len);
3602 static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len);
3603 static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, UINT32 len);
3604
3605 #ifdef UCOS
3606 int ate_copy_to_user(
3607 IN PUCHAR payload,
3608 IN PUCHAR msg,
3609 IN INT len)
3610 {
3611 memmove(payload, msg, len);
3612 return 0;
3613 }
3614
3615 #undef copy_to_user
3616 #define copy_to_user(x,y,z) ate_copy_to_user((PUCHAR)x, (PUCHAR)y, z)
3617 #endif // UCOS //
3618
3619 #define LEN_OF_ARG 16
3620
3621 VOID RtmpDoAte(
3622 IN PRTMP_ADAPTER pAdapter,
3623 IN struct iwreq *wrq)
3624 {
3625 unsigned short Command_Id;
3626 struct ate_racfghdr *pRaCfg;
3627 INT Status = NDIS_STATUS_SUCCESS;
3628
3629
3630
3631 if((pRaCfg = kmalloc(sizeof(struct ate_racfghdr), GFP_KERNEL)) == NULL)
3632 {
3633 Status = -EINVAL;
3634 return;
3635 }
3636
3637 NdisZeroMemory(pRaCfg, sizeof(struct ate_racfghdr));
3638
3639 if (copy_from_user((PUCHAR)pRaCfg, wrq->u.data.pointer, wrq->u.data.length))
3640 {
3641 Status = -EFAULT;
3642 kfree(pRaCfg);
3643 return;
3644 }
3645
3646
3647 Command_Id = ntohs(pRaCfg->command_id);
3648
3649 ATEDBGPRINT(RT_DEBUG_TRACE,("\n%s: Command_Id = 0x%04x !\n", __func__, Command_Id));
3650
3651 switch (Command_Id)
3652 {
3653 // We will get this command when QA starts.
3654 case RACFG_CMD_ATE_START:
3655 {
3656 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START\n"));
3657
3658 // prepare feedback as soon as we can to avoid QA timeout.
3659 pRaCfg->length = htons(2);
3660 pRaCfg->status = htons(0);
3661
3662 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3663 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3664 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3665
3666 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
3667
3668 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3669 {
3670 ATEDBGPRINT(RT_DEBUG_TRACE, ("copy_to_user() fail in case RACFG_CMD_ATE_START\n"));
3671 Status = -EFAULT;
3672 }
3673 else
3674 {
3675 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START is done !\n"));
3676 }
3677 Set_ATE_Proc(pAdapter, "ATESTART");
3678 }
3679 break;
3680
3681 // We will get this command either QA is closed or ated is killed by user.
3682 case RACFG_CMD_ATE_STOP:
3683 {
3684 #ifndef UCOS
3685 INT32 ret;
3686 #endif // !UCOS //
3687
3688 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_STOP\n"));
3689
3690 // Distinguish this command came from QA(via ated)
3691 // or ate daemon according to the existence of pid in payload.
3692 // No need to prepare feedback if this cmd came directly from ate daemon.
3693 pRaCfg->length = ntohs(pRaCfg->length);
3694
3695 if (pRaCfg->length == sizeof(pAdapter->ate.AtePid))
3696 {
3697 // This command came from QA.
3698 // Get the pid of ATE daemon.
3699 memcpy((UCHAR *)&pAdapter->ate.AtePid,
3700 (&pRaCfg->data[0]) - 2/* == &(pRaCfg->status) */,
3701 sizeof(pAdapter->ate.AtePid));
3702
3703 // prepare feedback as soon as we can to avoid QA timeout.
3704 pRaCfg->length = htons(2);
3705 pRaCfg->status = htons(0);
3706
3707 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3708 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3709 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3710
3711 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
3712
3713 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3714 {
3715 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_STOP\n"));
3716 Status = -EFAULT;
3717 }
3718
3719 //
3720 // kill ATE daemon when leaving ATE mode.
3721 // We must kill ATE daemon first before setting ATESTOP,
3722 // or Microsoft will report sth. wrong.
3723 #ifndef UCOS
3724 ret = KILL_THREAD_PID(pAdapter->ate.AtePid, SIGTERM, 1);
3725 if (ret)
3726 {
3727 ATEDBGPRINT(RT_DEBUG_ERROR, ("%s: unable to signal thread\n", pAdapter->net_dev->name));
3728 }
3729 #endif // !UCOS //
3730 }
3731
3732 // AP might have in ATE_STOP mode due to cmd from QA.
3733 if (ATE_ON(pAdapter))
3734 {
3735 // Someone has killed ate daemon while QA GUI is still open.
3736 Set_ATE_Proc(pAdapter, "ATESTOP");
3737 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_AP_START is done !\n"));
3738 }
3739 }
3740 break;
3741
3742 case RACFG_CMD_RF_WRITE_ALL:
3743 {
3744 UINT32 R1, R2, R3, R4;
3745 USHORT channel;
3746
3747 memcpy(&R1, pRaCfg->data-2, 4);
3748 memcpy(&R2, pRaCfg->data+2, 4);
3749 memcpy(&R3, pRaCfg->data+6, 4);
3750 memcpy(&R4, pRaCfg->data+10, 4);
3751 memcpy(&channel, pRaCfg->data+14, 2);
3752
3753 pAdapter->LatchRfRegs.R1 = ntohl(R1);
3754 pAdapter->LatchRfRegs.R2 = ntohl(R2);
3755 pAdapter->LatchRfRegs.R3 = ntohl(R3);
3756 pAdapter->LatchRfRegs.R4 = ntohl(R4);
3757 pAdapter->LatchRfRegs.Channel = ntohs(channel);
3758
3759 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R1);
3760 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R2);
3761 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R3);
3762 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R4);
3763
3764 // prepare feedback
3765 pRaCfg->length = htons(2);
3766 pRaCfg->status = htons(0);
3767
3768 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3769 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3770 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3771
3772 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
3773 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3774 {
3775 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RF_WRITE_ALL\n"));
3776 Status = -EFAULT;
3777 }
3778 else
3779 {
3780 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RF_WRITE_ALL is done !\n"));
3781 }
3782 }
3783 break;
3784
3785 case RACFG_CMD_E2PROM_READ16:
3786 {
3787 USHORT offset, value, tmp;
3788
3789 offset = ntohs(pRaCfg->status);
3790 /* "tmp" is expecially for some compilers... */
3791 RT28xx_EEPROM_READ16(pAdapter, offset, tmp);
3792 value = tmp;
3793 value = htons(value);
3794
3795 ATEDBGPRINT(RT_DEBUG_TRACE,("EEPROM Read offset = 0x%04x, value = 0x%04x\n", offset, value));
3796
3797 // prepare feedback
3798 pRaCfg->length = htons(4);
3799 pRaCfg->status = htons(0);
3800 memcpy(pRaCfg->data, &value, 2);
3801
3802 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3803 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3804 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3805
3806 ATEDBGPRINT(RT_DEBUG_TRACE, ("sizeof(struct ate_racfghdr) = %d\n", sizeof(struct ate_racfghdr)));
3807 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
3808
3809 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3810 {
3811 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_READ16\n"));
3812 Status = -EFAULT;
3813 }
3814 else
3815 {
3816 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_E2PROM_READ16 is done !\n"));
3817 }
3818 }
3819 break;
3820
3821 case RACFG_CMD_E2PROM_WRITE16:
3822 {
3823 USHORT offset, value;
3824
3825 offset = ntohs(pRaCfg->status);
3826 memcpy(&value, pRaCfg->data, 2);
3827 value = ntohs(value);
3828 RT28xx_EEPROM_WRITE16(pAdapter, offset, value);
3829
3830 // prepare feedback
3831 pRaCfg->length = htons(2);
3832 pRaCfg->status = htons(0);
3833 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3834 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3835 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3836
3837 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3838 {
3839 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_WRITE16\n"));
3840 Status = -EFAULT;
3841 }
3842 else
3843 {
3844 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_E2PROM_WRITE16 is done !\n"));
3845 }
3846 }
3847 break;
3848
3849 case RACFG_CMD_E2PROM_READ_ALL:
3850 {
3851 USHORT buffer[EEPROM_SIZE/2];
3852
3853 rt_ee_read_all(pAdapter,(USHORT *)buffer);
3854 memcpy_exs(pAdapter, pRaCfg->data, (UCHAR *)buffer, EEPROM_SIZE);
3855
3856 // prepare feedback
3857 pRaCfg->length = htons(2+EEPROM_SIZE);
3858 pRaCfg->status = htons(0);
3859 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3860 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3861 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3862
3863 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3864 {
3865 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_READ_ALL\n"));
3866 Status = -EFAULT;
3867 }
3868 else
3869 {
3870 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_E2PROM_READ_ALL is done !\n"));
3871 }
3872 }
3873 break;
3874
3875 case RACFG_CMD_E2PROM_WRITE_ALL:
3876 {
3877 USHORT buffer[EEPROM_SIZE/2];
3878
3879 NdisZeroMemory((UCHAR *)buffer, EEPROM_SIZE);
3880 memcpy_exs(pAdapter, (UCHAR *)buffer, (UCHAR *)&pRaCfg->status, EEPROM_SIZE);
3881 rt_ee_write_all(pAdapter,(USHORT *)buffer);
3882
3883 // prepare feedback
3884 pRaCfg->length = htons(2);
3885 pRaCfg->status = htons(0);
3886 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3887 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3888 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3889
3890 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3891 {
3892 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_WRITE_ALL\n"));
3893 Status = -EFAULT;
3894 }
3895 else
3896 {
3897 ATEDBGPRINT(RT_DEBUG_ERROR, ("RACFG_CMD_E2PROM_WRITE_ALL is done !\n"));
3898 }
3899
3900 }
3901 break;
3902
3903 case RACFG_CMD_IO_READ:
3904 {
3905 UINT32 offset;
3906 UINT32 value;
3907
3908 memcpy(&offset, &pRaCfg->status, 4);
3909 offset = ntohl(offset);
3910
3911 // We do not need the base address.
3912 // So just extract the offset out.
3913 offset &= 0x0000FFFF;
3914 RTMP_IO_READ32(pAdapter, offset, &value);
3915 value = htonl(value);
3916
3917 // prepare feedback
3918 pRaCfg->length = htons(6);
3919 pRaCfg->status = htons(0);
3920 memcpy(pRaCfg->data, &value, 4);
3921
3922 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3923 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3924 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3925
3926 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3927 {
3928 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_IO_READ\n"));
3929 Status = -EFAULT;
3930 }
3931 else
3932 {
3933 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_IO_READ is done !\n"));
3934 }
3935 }
3936 break;
3937
3938 case RACFG_CMD_IO_WRITE:
3939 {
3940 UINT32 offset, value;
3941
3942 memcpy(&offset, pRaCfg->data-2, 4);
3943 memcpy(&value, pRaCfg->data+2, 4);
3944
3945 offset = ntohl(offset);
3946
3947 // We do not need the base address.
3948 // So just extract out the offset.
3949 offset &= 0x0000FFFF;
3950 value = ntohl(value);
3951 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_IO_WRITE: offset = %x, value = %x\n", offset, value));
3952 RTMP_IO_WRITE32(pAdapter, offset, value);
3953
3954 // prepare feedback
3955 pRaCfg->length = htons(2);
3956 pRaCfg->status = htons(0);
3957 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
3958 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
3959 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
3960
3961 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
3962 {
3963 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_IO_WRITE\n"));
3964 Status = -EFAULT;
3965 }
3966 else
3967 {
3968 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_IO_WRITE is done !\n"));
3969 }
3970 }
3971 break;
3972
3973 case RACFG_CMD_IO_READ_BULK:
3974 {
3975 UINT32 offset;
3976 USHORT len;
3977
3978 memcpy(&offset, &pRaCfg->status, 4);
3979 offset = ntohl(offset);
3980
3981 // We do not need the base address.
3982 // So just extract the offset.
3983 offset &= 0x0000FFFF;
3984 memcpy(&len, pRaCfg->data+2, 2);
3985 len = ntohs(len);
3986
3987 if (len > 371)
3988 {
3989 ATEDBGPRINT(RT_DEBUG_TRACE,("len is too large, make it smaller\n"));
3990 pRaCfg->length = htons(2);
3991 pRaCfg->status = htons(1);
3992 break;
3993 }
3994
3995 RTMP_IO_READ_BULK(pAdapter, pRaCfg->data, (UCHAR *)offset, len*4);// unit in four bytes
3996
3997 // prepare feedback
3998 pRaCfg->length = htons(2+len*4);// unit in four bytes
3999 pRaCfg->status = htons(0);
4000 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4001 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4002 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4003
4004 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4005 {
4006 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_IO_READ_BULK\n"));
4007 Status = -EFAULT;
4008 }
4009 else
4010 {
4011 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_IO_READ_BULK is done !\n"));
4012 }
4013 }
4014 break;
4015
4016 case RACFG_CMD_BBP_READ8:
4017 {
4018 USHORT offset;
4019 UCHAR value;
4020
4021 value = 0;
4022 offset = ntohs(pRaCfg->status);
4023
4024 if (ATE_ON(pAdapter))
4025 {
4026 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, offset, &value);
4027 }
4028 else
4029 {
4030 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, offset, &value);
4031 }
4032 // prepare feedback
4033 pRaCfg->length = htons(3);
4034 pRaCfg->status = htons(0);
4035 pRaCfg->data[0] = value;
4036
4037 ATEDBGPRINT(RT_DEBUG_TRACE,("BBP value = %x\n", value));
4038
4039 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4040 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4041 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4042
4043 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4044 {
4045 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_BBP_READ8\n"));
4046 Status = -EFAULT;
4047 }
4048 else
4049 {
4050 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_BBP_READ8 is done !\n"));
4051 }
4052 }
4053 break;
4054 case RACFG_CMD_BBP_WRITE8:
4055 {
4056 USHORT offset;
4057 UCHAR value;
4058
4059 offset = ntohs(pRaCfg->status);
4060 memcpy(&value, pRaCfg->data, 1);
4061
4062 if (ATE_ON(pAdapter))
4063 {
4064 ATE_BBP_IO_WRITE8_BY_REG_ID(pAdapter, offset, value);
4065 }
4066 else
4067 {
4068 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, offset, value);
4069 }
4070
4071 if ((offset == BBP_R1) || (offset == BBP_R3))
4072 {
4073 SyncTxRxConfig(pAdapter, offset, value);
4074 }
4075
4076 // prepare feedback
4077 pRaCfg->length = htons(2);
4078 pRaCfg->status = htons(0);
4079 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4080 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4081 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4082
4083 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4084 {
4085 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_BBP_WRITE8\n"));
4086 Status = -EFAULT;
4087 }
4088 else
4089 {
4090 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_BBP_WRITE8 is done !\n"));
4091 }
4092 }
4093 break;
4094
4095 case RACFG_CMD_BBP_READ_ALL:
4096 {
4097 USHORT j;
4098
4099 for (j = 0; j < 137; j++)
4100 {
4101 pRaCfg->data[j] = 0;
4102
4103 if (ATE_ON(pAdapter))
4104 {
4105 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j]);
4106 }
4107 else
4108 {
4109 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j]);
4110 }
4111 }
4112
4113 // prepare feedback
4114 pRaCfg->length = htons(2+137);
4115 pRaCfg->status = htons(0);
4116
4117 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4118 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4119 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4120
4121 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4122 {
4123 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_BBP_READ_ALL\n"));
4124 Status = -EFAULT;
4125 }
4126 else
4127 {
4128 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_BBP_READ_ALL is done !\n"));
4129 }
4130 }
4131
4132 break;
4133
4134 case RACFG_CMD_ATE_E2PROM_READ_BULK:
4135 {
4136 USHORT offset;
4137 USHORT len;
4138 USHORT buffer[EEPROM_SIZE/2];
4139
4140 offset = ntohs(pRaCfg->status);
4141 memcpy(&len, pRaCfg->data, 2);
4142 len = ntohs(len);
4143
4144 rt_ee_read_all(pAdapter,(USHORT *)buffer);
4145 if (offset + len <= EEPROM_SIZE)
4146 memcpy_exs(pAdapter, pRaCfg->data, (UCHAR *)buffer+offset, len);
4147 else
4148 ATEDBGPRINT(RT_DEBUG_ERROR, ("exceed EEPROM size\n"));
4149
4150 // prepare feedback
4151 pRaCfg->length = htons(2+len);
4152 pRaCfg->status = htons(0);
4153 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4154 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4155 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4156
4157 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4158 {
4159 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_E2PROM_READ_BULK\n"));
4160 Status = -EFAULT;
4161 }
4162 else
4163 {
4164 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_E2PROM_READ_BULK is done !\n"));
4165 }
4166
4167 }
4168 break;
4169
4170 case RACFG_CMD_ATE_E2PROM_WRITE_BULK:
4171 {
4172 USHORT offset;
4173 USHORT len;
4174 USHORT buffer[EEPROM_SIZE/2];
4175
4176 offset = ntohs(pRaCfg->status);
4177 memcpy(&len, pRaCfg->data, 2);
4178 len = ntohs(len);
4179
4180 rt_ee_read_all(pAdapter,(USHORT *)buffer);
4181 memcpy_exs(pAdapter, (UCHAR *)buffer + offset, (UCHAR *)pRaCfg->data + 2, len);
4182 rt_ee_write_all(pAdapter,(USHORT *)buffer);
4183
4184 // prepare feedback
4185 pRaCfg->length = htons(2);
4186 pRaCfg->status = htons(0);
4187 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4188 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4189 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4190 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4191 {
4192 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_E2PROM_WRITE_BULK\n"));
4193 Status = -EFAULT;
4194 }
4195 else
4196 {
4197 ATEDBGPRINT(RT_DEBUG_ERROR, ("RACFG_CMD_ATE_E2PROM_WRITE_BULK is done !\n"));
4198 }
4199
4200 }
4201 break;
4202
4203 case RACFG_CMD_ATE_IO_WRITE_BULK:
4204 {
4205 UINT32 offset, i, value;
4206 USHORT len;
4207
4208 memcpy(&offset, &pRaCfg->status, 4);
4209 offset = ntohl(offset);
4210 memcpy(&len, pRaCfg->data+2, 2);
4211 len = ntohs(len);
4212
4213 for (i = 0; i < len; i += 4)
4214 {
4215 memcpy_exl(pAdapter, (UCHAR *)&value, pRaCfg->data+4+i, 4);
4216 printk("Write %x %x\n", offset + i, value);
4217 RTMP_IO_WRITE32(pAdapter, (offset +i) & 0xffff, value);
4218 }
4219
4220 // prepare feedback
4221 pRaCfg->length = htons(2);
4222 pRaCfg->status = htons(0);
4223 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4224 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4225 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4226 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4227 {
4228 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_IO_WRITE_BULK\n"));
4229 Status = -EFAULT;
4230 }
4231 else
4232 {
4233 ATEDBGPRINT(RT_DEBUG_ERROR, ("RACFG_CMD_ATE_IO_WRITE_BULK is done !\n"));
4234 }
4235
4236 }
4237 break;
4238
4239 case RACFG_CMD_ATE_BBP_READ_BULK:
4240 {
4241 USHORT offset;
4242 USHORT len;
4243 USHORT j;
4244
4245 offset = ntohs(pRaCfg->status);
4246 memcpy(&len, pRaCfg->data, 2);
4247 len = ntohs(len);
4248
4249
4250 for (j = offset; j < (offset+len); j++)
4251 {
4252 pRaCfg->data[j - offset] = 0;
4253
4254 if (pAdapter->ate.Mode == ATE_STOP)
4255 {
4256 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j - offset]);
4257 }
4258 else
4259 {
4260 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j - offset]);
4261 }
4262 }
4263
4264 // prepare feedback
4265 pRaCfg->length = htons(2+len);
4266 pRaCfg->status = htons(0);
4267 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4268 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4269 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4270
4271 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4272 {
4273 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_BBP_READ_BULK\n"));
4274 Status = -EFAULT;
4275 }
4276 else
4277 {
4278 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_BBP_READ_BULK is done !\n"));
4279 }
4280
4281 }
4282 break;
4283
4284 case RACFG_CMD_ATE_BBP_WRITE_BULK:
4285 {
4286 USHORT offset;
4287 USHORT len;
4288 USHORT j;
4289 UCHAR *value;
4290
4291 offset = ntohs(pRaCfg->status);
4292 memcpy(&len, pRaCfg->data, 2);
4293 len = ntohs(len);
4294
4295 for (j = offset; j < (offset+len); j++)
4296 {
4297 value = pRaCfg->data + 2 + (j - offset);
4298 if (pAdapter->ate.Mode == ATE_STOP)
4299 {
4300 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, j, *value);
4301 }
4302 else
4303 {
4304 ATE_BBP_IO_WRITE8_BY_REG_ID(pAdapter, j, *value);
4305 }
4306 }
4307
4308 // prepare feedback
4309 pRaCfg->length = htons(2);
4310 pRaCfg->status = htons(0);
4311 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4312 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4313 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4314
4315 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4316 {
4317 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_BBP_WRITE_BULK\n"));
4318 Status = -EFAULT;
4319 }
4320 else
4321 {
4322 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_BBP_WRITE_BULK is done !\n"));
4323 }
4324 }
4325 break;
4326
4327 #ifdef CONFIG_RALINK_RT3052
4328 case RACFG_CMD_ATE_RF_READ_BULK:
4329 {
4330 USHORT offset;
4331 USHORT len;
4332 USHORT j;
4333
4334 offset = ntohs(pRaCfg->status);
4335 memcpy(&len, pRaCfg->data, 2);
4336 len = ntohs(len);
4337
4338 for (j = offset; j < (offset+len); j++)
4339 {
4340 pRaCfg->data[j - offset] = 0;
4341 RT30xxReadRFRegister(pAdapter, j, &pRaCfg->data[j - offset]);
4342 }
4343
4344 // prepare feedback
4345 pRaCfg->length = htons(2+len);
4346 pRaCfg->status = htons(0);
4347 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4348 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4349 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4350
4351 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4352 {
4353 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_RF_READ_BULK\n"));
4354 Status = -EFAULT;
4355 }
4356 else
4357 {
4358 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_RF_READ_BULK is done !\n"));
4359 }
4360
4361 }
4362 break;
4363
4364 case RACFG_CMD_ATE_RF_WRITE_BULK:
4365 {
4366 USHORT offset;
4367 USHORT len;
4368 USHORT j;
4369 UCHAR *value;
4370
4371 offset = ntohs(pRaCfg->status);
4372 memcpy(&len, pRaCfg->data, 2);
4373 len = ntohs(len);
4374
4375 for (j = offset; j < (offset+len); j++)
4376 {
4377 value = pRaCfg->data + 2 + (j - offset);
4378 RT30xxWriteRFRegister(pAdapter, j, *value);
4379 }
4380
4381 // prepare feedback
4382 pRaCfg->length = htons(2);
4383 pRaCfg->status = htons(0);
4384 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4385 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4386 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4387
4388 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4389 {
4390 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_RF_WRITE_BULK\n"));
4391 Status = -EFAULT;
4392 }
4393 else
4394 {
4395 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_RF_WRITE_BULK is done !\n"));
4396 }
4397
4398 }
4399 break;
4400 #endif
4401
4402
4403 case RACFG_CMD_GET_NOISE_LEVEL:
4404 {
4405 UCHAR channel;
4406 INT32 buffer[3][10];/* 3 : RxPath ; 10 : no. of per rssi samples */
4407
4408 channel = (ntohs(pRaCfg->status) & 0x00FF);
4409 CalNoiseLevel(pAdapter, channel, buffer);
4410 memcpy_exl(pAdapter, (UCHAR *)pRaCfg->data, (UCHAR *)&(buffer[0][0]), (sizeof(INT32)*3*10));
4411
4412 // prepare feedback
4413 pRaCfg->length = htons(2 + (sizeof(INT32)*3*10));
4414 pRaCfg->status = htons(0);
4415 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4416 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4417 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4418
4419 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4420 {
4421 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_GET_NOISE_LEVEL\n"));
4422 Status = -EFAULT;
4423 }
4424 else
4425 {
4426 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_GET_NOISE_LEVEL is done !\n"));
4427 }
4428 }
4429 break;
4430
4431 case RACFG_CMD_GET_COUNTER:
4432 {
4433 memcpy_exl(pAdapter, &pRaCfg->data[0], (UCHAR *)&pAdapter->ate.U2M, 4);
4434 memcpy_exl(pAdapter, &pRaCfg->data[4], (UCHAR *)&pAdapter->ate.OtherData, 4);
4435 memcpy_exl(pAdapter, &pRaCfg->data[8], (UCHAR *)&pAdapter->ate.Beacon, 4);
4436 memcpy_exl(pAdapter, &pRaCfg->data[12], (UCHAR *)&pAdapter->ate.OtherCount, 4);
4437 memcpy_exl(pAdapter, &pRaCfg->data[16], (UCHAR *)&pAdapter->ate.TxAc0, 4);
4438 memcpy_exl(pAdapter, &pRaCfg->data[20], (UCHAR *)&pAdapter->ate.TxAc1, 4);
4439 memcpy_exl(pAdapter, &pRaCfg->data[24], (UCHAR *)&pAdapter->ate.TxAc2, 4);
4440 memcpy_exl(pAdapter, &pRaCfg->data[28], (UCHAR *)&pAdapter->ate.TxAc3, 4);
4441 memcpy_exl(pAdapter, &pRaCfg->data[32], (UCHAR *)&pAdapter->ate.TxHCCA, 4);
4442 memcpy_exl(pAdapter, &pRaCfg->data[36], (UCHAR *)&pAdapter->ate.TxMgmt, 4);
4443 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&pAdapter->ate.RSSI0, 4);
4444 memcpy_exl(pAdapter, &pRaCfg->data[44], (UCHAR *)&pAdapter->ate.RSSI1, 4);
4445 memcpy_exl(pAdapter, &pRaCfg->data[48], (UCHAR *)&pAdapter->ate.RSSI2, 4);
4446 memcpy_exl(pAdapter, &pRaCfg->data[52], (UCHAR *)&pAdapter->ate.SNR0, 4);
4447 memcpy_exl(pAdapter, &pRaCfg->data[56], (UCHAR *)&pAdapter->ate.SNR1, 4);
4448
4449 pRaCfg->length = htons(2+60);
4450 pRaCfg->status = htons(0);
4451 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4452 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4453 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4454
4455 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4456 {
4457 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_GET_COUNTER\n"));
4458 Status = -EFAULT;
4459 }
4460 else
4461 {
4462 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_GET_COUNTER is done !\n"));
4463 }
4464 }
4465 break;
4466
4467 case RACFG_CMD_CLEAR_COUNTER:
4468 {
4469 pAdapter->ate.U2M = 0;
4470 pAdapter->ate.OtherData = 0;
4471 pAdapter->ate.Beacon = 0;
4472 pAdapter->ate.OtherCount = 0;
4473 pAdapter->ate.TxAc0 = 0;
4474 pAdapter->ate.TxAc1 = 0;
4475 pAdapter->ate.TxAc2 = 0;
4476 pAdapter->ate.TxAc3 = 0;
4477 pAdapter->ate.TxHCCA = 0;
4478 pAdapter->ate.TxMgmt = 0;
4479 pAdapter->ate.TxDoneCount = 0;
4480
4481 pRaCfg->length = htons(2);
4482 pRaCfg->status = htons(0);
4483
4484 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4485 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4486 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4487
4488 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4489 {
4490 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_CLEAR_COUNTER\n"));
4491 Status = -EFAULT;
4492 }
4493 else
4494 {
4495 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_CLEAR_COUNTER is done !\n"));
4496 }
4497 }
4498
4499 break;
4500
4501 case RACFG_CMD_TX_START:
4502 {
4503 USHORT *p;
4504 USHORT err = 1;
4505 UCHAR Bbp22Value = 0, Bbp24Value = 0;
4506
4507 if ((pAdapter->ate.TxStatus != 0) && (pAdapter->ate.Mode & ATE_TXFRAME))
4508 {
4509 ATEDBGPRINT(RT_DEBUG_TRACE,("Ate Tx is already running, to run next Tx, you must stop it first\n"));
4510 err = 2;
4511 goto TX_START_ERROR;
4512 }
4513 else if ((pAdapter->ate.TxStatus != 0) && !(pAdapter->ate.Mode & ATE_TXFRAME))
4514 {
4515 int i = 0;
4516
4517 while ((i++ < 10) && (pAdapter->ate.TxStatus != 0))
4518 {
4519 RTMPusecDelay(5000);
4520 }
4521
4522 // force it to stop
4523 pAdapter->ate.TxStatus = 0;
4524 pAdapter->ate.TxDoneCount = 0;
4525 //pAdapter->ate.Repeat = 0;
4526 pAdapter->ate.bQATxStart = FALSE;
4527 }
4528
4529 // If pRaCfg->length == 0, this "RACFG_CMD_TX_START" is for Carrier test or Carrier Suppression.
4530 if (ntohs(pRaCfg->length) != 0)
4531 {
4532 // Get frame info
4533
4534 NdisMoveMemory(&pAdapter->ate.TxWI, pRaCfg->data + 2, 16);
4535 #ifdef RT_BIG_ENDIAN
4536 RTMPWIEndianChange((PUCHAR)&pAdapter->ate.TxWI, TYPE_TXWI);
4537 #endif // RT_BIG_ENDIAN //
4538
4539 NdisMoveMemory(&pAdapter->ate.TxCount, pRaCfg->data + 18, 4);
4540 pAdapter->ate.TxCount = ntohl(pAdapter->ate.TxCount);
4541
4542 p = (USHORT *)(&pRaCfg->data[22]);
4543 //p = pRaCfg->data + 22;
4544 // always use QID_AC_BE
4545 pAdapter->ate.QID = 0;
4546 p = (USHORT *)(&pRaCfg->data[24]);
4547 //p = pRaCfg->data + 24;
4548 pAdapter->ate.HLen = ntohs(*p);
4549
4550 if (pAdapter->ate.HLen > 32)
4551 {
4552 ATEDBGPRINT(RT_DEBUG_ERROR,("pAdapter->ate.HLen > 32\n"));
4553 err = 3;
4554 goto TX_START_ERROR;
4555 }
4556
4557 NdisMoveMemory(&pAdapter->ate.Header, pRaCfg->data + 26, pAdapter->ate.HLen);
4558
4559
4560 pAdapter->ate.PLen = ntohs(pRaCfg->length) - (pAdapter->ate.HLen + 28);
4561
4562 if (pAdapter->ate.PLen > 32)
4563 {
4564 ATEDBGPRINT(RT_DEBUG_ERROR,("pAdapter->ate.PLen > 32\n"));
4565 err = 4;
4566 goto TX_START_ERROR;
4567 }
4568
4569 NdisMoveMemory(&pAdapter->ate.Pattern, pRaCfg->data + 26 + pAdapter->ate.HLen, pAdapter->ate.PLen);
4570 pAdapter->ate.DLen = pAdapter->ate.TxWI.MPDUtotalByteCount - pAdapter->ate.HLen;
4571 }
4572
4573 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R22, &Bbp22Value);
4574
4575 switch (Bbp22Value)
4576 {
4577 case BBP22_TXFRAME:
4578 {
4579 if (pAdapter->ate.TxCount == 0)
4580 {
4581 #ifdef RT2860
4582 pAdapter->ate.TxCount = 0xFFFFFFFF;
4583 #endif // RT2860 //
4584 }
4585 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXFRAME\n"));
4586 pAdapter->ate.bQATxStart = TRUE;
4587 Set_ATE_Proc(pAdapter, "TXFRAME");
4588 }
4589 break;
4590
4591 case BBP22_TXCONT_OR_CARRSUPP:
4592 {
4593 ATEDBGPRINT(RT_DEBUG_TRACE,("BBP22_TXCONT_OR_CARRSUPP\n"));
4594 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, 24, &Bbp24Value);
4595
4596 switch (Bbp24Value)
4597 {
4598 case BBP24_TXCONT:
4599 {
4600 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCONT\n"));
4601 pAdapter->ate.bQATxStart = TRUE;
4602 Set_ATE_Proc(pAdapter, "TXCONT");
4603 }
4604 break;
4605
4606 case BBP24_CARRSUPP:
4607 {
4608 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCARRSUPP\n"));
4609 pAdapter->ate.bQATxStart = TRUE;
4610 pAdapter->ate.Mode |= ATE_TXCARRSUPP;
4611 }
4612 break;
4613
4614 default:
4615 {
4616 ATEDBGPRINT(RT_DEBUG_ERROR,("Unknown Start TX subtype !"));
4617 }
4618 break;
4619 }
4620 }
4621 break;
4622
4623 case BBP22_TXCARR:
4624 {
4625 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCARR\n"));
4626 pAdapter->ate.bQATxStart = TRUE;
4627 Set_ATE_Proc(pAdapter, "TXCARR");
4628 }
4629 break;
4630
4631 default:
4632 {
4633 ATEDBGPRINT(RT_DEBUG_ERROR,("Unknown Start TX subtype !"));
4634 }
4635 break;
4636 }
4637
4638 if (pAdapter->ate.bQATxStart == TRUE)
4639 {
4640 // prepare feedback
4641 pRaCfg->length = htons(2);
4642 pRaCfg->status = htons(0);
4643
4644 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4645 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4646 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4647
4648 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4649 {
4650 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() was failed in case RACFG_CMD_TX_START\n"));
4651 Status = -EFAULT;
4652 }
4653 else
4654 {
4655 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_TX_START is done !\n"));
4656 }
4657 break;
4658 }
4659
4660 TX_START_ERROR:
4661 // prepare feedback
4662 pRaCfg->length = htons(2);
4663 pRaCfg->status = htons(err);
4664
4665 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4666 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4667 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4668 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4669 {
4670 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_TX_START\n"));
4671 Status = -EFAULT;
4672 }
4673 else
4674 {
4675 ATEDBGPRINT(RT_DEBUG_TRACE, ("feedback of TX_START_ERROR is done !\n"));
4676 }
4677 }
4678 break;
4679
4680 case RACFG_CMD_GET_TX_STATUS:
4681 {
4682 UINT32 count;
4683
4684 // prepare feedback
4685 pRaCfg->length = htons(6);
4686 pRaCfg->status = htons(0);
4687 count = htonl(pAdapter->ate.TxDoneCount);
4688 NdisMoveMemory(pRaCfg->data, &count, 4);
4689 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4690 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4691 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4692
4693 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4694 {
4695 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_GET_TX_STATUS\n"));
4696 Status = -EFAULT;
4697 }
4698 else
4699 {
4700 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_GET_TX_STATUS is done !\n"));
4701 }
4702 }
4703 break;
4704
4705 case RACFG_CMD_TX_STOP:
4706 {
4707 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_TX_STOP\n"));
4708
4709 Set_ATE_Proc(pAdapter, "TXSTOP");
4710
4711 // prepare feedback
4712 pRaCfg->length = htons(2);
4713 pRaCfg->status = htons(0);
4714 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4715 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4716 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4717
4718 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4719 {
4720 ATEDBGPRINT(RT_DEBUG_TRACE, ("copy_to_user() fail in case RACFG_CMD_TX_STOP\n"));
4721 Status = -EFAULT;
4722 }
4723 else
4724 {
4725 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_TX_STOP is done !\n"));
4726 }
4727 }
4728 break;
4729
4730 case RACFG_CMD_RX_START:
4731 {
4732 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n"));
4733
4734 pAdapter->ate.bQARxStart = TRUE;
4735 Set_ATE_Proc(pAdapter, "RXFRAME");
4736
4737 // prepare feedback
4738 pRaCfg->length = htons(2);
4739 pRaCfg->status = htons(0);
4740 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4741 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4742 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4743
4744 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4745 {
4746 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RX_START\n"));
4747 Status = -EFAULT;
4748 }
4749 else
4750 {
4751 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RX_START is done !\n"));
4752 }
4753 }
4754 break;
4755
4756 case RACFG_CMD_RX_STOP:
4757 {
4758 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_STOP\n"));
4759
4760 Set_ATE_Proc(pAdapter, "RXSTOP");
4761
4762 // prepare feedback
4763 pRaCfg->length = htons(2);
4764 pRaCfg->status = htons(0);
4765 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4766 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4767 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4768
4769 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4770 {
4771 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RX_STOP\n"));
4772 Status = -EFAULT;
4773 }
4774 else
4775 {
4776 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RX_STOP is done !\n"));
4777 }
4778 }
4779 break;
4780
4781 /* The following cases are for new ATE GUI(not QA). */
4782 /*==================================================*/
4783 case RACFG_CMD_ATE_START_TX_CARRIER:
4784 {
4785 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CARRIER\n"));
4786
4787 Set_ATE_Proc(pAdapter, "TXCARR");
4788
4789 pRaCfg->length = htons(2);
4790 pRaCfg->status = htons(0);
4791
4792 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4793 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4794 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4795
4796 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4797
4798 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4799 {
4800 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_START_TX_CARRIER\n"));
4801 Status = -EFAULT;
4802 }
4803 else
4804 {
4805 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START_TX_CARRIER is done !\n"));
4806 }
4807 }
4808 break;
4809
4810 case RACFG_CMD_ATE_START_TX_CONT:
4811 {
4812 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CONT\n"));
4813
4814 Set_ATE_Proc(pAdapter, "TXCONT");
4815
4816 pRaCfg->length = htons(2);
4817 pRaCfg->status = htons(0);
4818
4819 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4820 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4821 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4822
4823 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4824
4825 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4826 {
4827 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_START_TX_CONT\n"));
4828 Status = -EFAULT;
4829 }
4830 else
4831 {
4832 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START_TX_CONT is done !\n"));
4833 }
4834 }
4835 break;
4836
4837 case RACFG_CMD_ATE_START_TX_FRAME:
4838 {
4839 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_FRAME\n"));
4840
4841 Set_ATE_Proc(pAdapter, "TXFRAME");
4842
4843 pRaCfg->length = htons(2);
4844 pRaCfg->status = htons(0);
4845
4846 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4847 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4848 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4849
4850 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4851
4852 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4853 {
4854 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_START_TX_FRAME\n"));
4855 Status = -EFAULT;
4856 }
4857 else
4858 {
4859 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START_TX_FRAME is done !\n"));
4860 }
4861 }
4862 break;
4863
4864 case RACFG_CMD_ATE_SET_BW:
4865 {
4866 SHORT value = 0;
4867 UCHAR str[LEN_OF_ARG];
4868
4869 NdisZeroMemory(str, LEN_OF_ARG);
4870
4871 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_BW\n"));
4872
4873 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
4874 value = ntohs(value);
4875 sprintf((PCHAR)str, "%d", value);
4876
4877 Set_ATE_TX_BW_Proc(pAdapter, str);
4878
4879 // prepare feedback
4880 pRaCfg->length = htons(2);
4881 pRaCfg->status = htons(0);
4882 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4883 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4884 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4885
4886 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4887 {
4888 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_BW\n"));
4889 Status = -EFAULT;
4890 }
4891 else
4892 {
4893 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_BW is done !\n"));
4894 }
4895 }
4896 break;
4897
4898 case RACFG_CMD_ATE_SET_TX_POWER0:
4899 {
4900 SHORT value = 0;
4901 UCHAR str[LEN_OF_ARG];
4902
4903 NdisZeroMemory(str, LEN_OF_ARG);
4904
4905 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER0\n"));
4906
4907 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
4908 value = ntohs(value);
4909 sprintf((PCHAR)str, "%d", value);
4910 Set_ATE_TX_POWER0_Proc(pAdapter, str);
4911
4912 // prepare feedback
4913 pRaCfg->length = htons(2);
4914 pRaCfg->status = htons(0);
4915 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4916 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4917 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4918
4919 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4920 {
4921 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_POWER0\n"));
4922 Status = -EFAULT;
4923 }
4924 else
4925 {
4926 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_POWER0 is done !\n"));
4927 }
4928 }
4929 break;
4930
4931 case RACFG_CMD_ATE_SET_TX_POWER1:
4932 {
4933 SHORT value = 0;
4934 UCHAR str[LEN_OF_ARG];
4935
4936 NdisZeroMemory(str, LEN_OF_ARG);
4937
4938 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER1\n"));
4939
4940 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
4941 value = ntohs(value);
4942 sprintf((PCHAR)str, "%d", value);
4943 Set_ATE_TX_POWER1_Proc(pAdapter, str);
4944
4945 // prepare feedback
4946 pRaCfg->length = htons(2);
4947 pRaCfg->status = htons(0);
4948 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4949 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4950 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4951
4952 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4953 {
4954 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_POWER1\n"));
4955 Status = -EFAULT;
4956 }
4957 else
4958 {
4959 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_POWER1 is done !\n"));
4960 }
4961 }
4962 break;
4963
4964 case RACFG_CMD_ATE_SET_FREQ_OFFSET:
4965 {
4966 SHORT value = 0;
4967 UCHAR str[LEN_OF_ARG];
4968
4969 NdisZeroMemory(str, LEN_OF_ARG);
4970
4971 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_FREQ_OFFSET\n"));
4972
4973 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
4974 value = ntohs(value);
4975 sprintf((PCHAR)str, "%d", value);
4976 Set_ATE_TX_FREQOFFSET_Proc(pAdapter, str);
4977
4978 // prepare feedback
4979 pRaCfg->length = htons(2);
4980 pRaCfg->status = htons(0);
4981 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4982 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4983 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4984
4985 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4986 {
4987 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_FREQ_OFFSET\n"));
4988 Status = -EFAULT;
4989 }
4990 else
4991 {
4992 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_FREQ_OFFSET is done !\n"));
4993 }
4994 }
4995 break;
4996
4997 case RACFG_CMD_ATE_GET_STATISTICS:
4998 {
4999 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_GET_STATISTICS\n"));
5000
5001 memcpy_exl(pAdapter, &pRaCfg->data[0], (UCHAR *)&pAdapter->ate.TxDoneCount, 4);
5002 memcpy_exl(pAdapter, &pRaCfg->data[4], (UCHAR *)&pAdapter->WlanCounters.RetryCount.u.LowPart, 4);
5003 memcpy_exl(pAdapter, &pRaCfg->data[8], (UCHAR *)&pAdapter->WlanCounters.FailedCount.u.LowPart, 4);
5004 memcpy_exl(pAdapter, &pRaCfg->data[12], (UCHAR *)&pAdapter->WlanCounters.RTSSuccessCount.u.LowPart, 4);
5005 memcpy_exl(pAdapter, &pRaCfg->data[16], (UCHAR *)&pAdapter->WlanCounters.RTSFailureCount.u.LowPart, 4);
5006 memcpy_exl(pAdapter, &pRaCfg->data[20], (UCHAR *)&pAdapter->WlanCounters.ReceivedFragmentCount.QuadPart, 4);
5007 memcpy_exl(pAdapter, &pRaCfg->data[24], (UCHAR *)&pAdapter->WlanCounters.FCSErrorCount.u.LowPart, 4);
5008 memcpy_exl(pAdapter, &pRaCfg->data[28], (UCHAR *)&pAdapter->Counters8023.RxNoBuffer, 4);
5009 memcpy_exl(pAdapter, &pRaCfg->data[32], (UCHAR *)&pAdapter->WlanCounters.FrameDuplicateCount.u.LowPart, 4);
5010 memcpy_exl(pAdapter, &pRaCfg->data[36], (UCHAR *)&pAdapter->RalinkCounters.OneSecFalseCCACnt, 4);
5011
5012 if (pAdapter->ate.RxAntennaSel == 0)
5013 {
5014 INT32 RSSI0 = 0;
5015 INT32 RSSI1 = 0;
5016 INT32 RSSI2 = 0;
5017
5018 RSSI0 = (INT32)(pAdapter->ate.LastRssi0 - pAdapter->BbpRssiToDbmDelta);
5019 RSSI1 = (INT32)(pAdapter->ate.LastRssi1 - pAdapter->BbpRssiToDbmDelta);
5020 RSSI2 = (INT32)(pAdapter->ate.LastRssi2 - pAdapter->BbpRssiToDbmDelta);
5021 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4);
5022 memcpy_exl(pAdapter, &pRaCfg->data[44], (UCHAR *)&RSSI1, 4);
5023 memcpy_exl(pAdapter, &pRaCfg->data[48], (UCHAR *)&RSSI2, 4);
5024 pRaCfg->length = htons(2+52);
5025 }
5026 else
5027 {
5028 INT32 RSSI0 = 0;
5029
5030 RSSI0 = (INT32)(pAdapter->ate.LastRssi0 - pAdapter->BbpRssiToDbmDelta);
5031 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4);
5032 pRaCfg->length = htons(2+44);
5033 }
5034 pRaCfg->status = htons(0);
5035 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5036 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5037 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5038
5039 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5040 {
5041 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_GET_STATISTICS\n"));
5042 Status = -EFAULT;
5043 }
5044 else
5045 {
5046 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_GET_STATISTICS is done !\n"));
5047 }
5048 }
5049 break;
5050
5051 case RACFG_CMD_ATE_RESET_COUNTER:
5052 {
5053 SHORT value = 1;
5054 UCHAR str[LEN_OF_ARG];
5055
5056 NdisZeroMemory(str, LEN_OF_ARG);
5057
5058 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_RESET_COUNTER\n"));
5059
5060 sprintf((PCHAR)str, "%d", value);
5061 Set_ResetStatCounter_Proc(pAdapter, str);
5062
5063 pAdapter->ate.TxDoneCount = 0;
5064
5065 pRaCfg->length = htons(2);
5066 pRaCfg->status = htons(0);
5067
5068 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5069 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5070 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5071
5072 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5073 {
5074 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_RESET_COUNTER\n"));
5075 Status = -EFAULT;
5076 }
5077 else
5078 {
5079 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_RESET_COUNTER is done !\n"));
5080 }
5081 }
5082
5083 break;
5084
5085 case RACFG_CMD_ATE_SEL_TX_ANTENNA:
5086 {
5087 SHORT value = 0;
5088 UCHAR str[LEN_OF_ARG];
5089
5090 NdisZeroMemory(str, LEN_OF_ARG);
5091
5092 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_TX_ANTENNA\n"));
5093
5094 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5095 value = ntohs(value);
5096 sprintf((PCHAR)str, "%d", value);
5097 Set_ATE_TX_Antenna_Proc(pAdapter, str);
5098
5099 // prepare feedback
5100 pRaCfg->length = htons(2);
5101 pRaCfg->status = htons(0);
5102 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5103 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5104 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5105
5106 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5107 {
5108 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SEL_TX_ANTENNA\n"));
5109 Status = -EFAULT;
5110 }
5111 else
5112 {
5113 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SEL_TX_ANTENNA is done !\n"));
5114 }
5115 }
5116 break;
5117
5118 case RACFG_CMD_ATE_SEL_RX_ANTENNA:
5119 {
5120 SHORT value = 0;
5121 UCHAR str[LEN_OF_ARG];
5122
5123 NdisZeroMemory(str, LEN_OF_ARG);
5124
5125 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_RX_ANTENNA\n"));
5126
5127 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5128 value = ntohs(value);
5129 sprintf((PCHAR)str, "%d", value);
5130 Set_ATE_RX_Antenna_Proc(pAdapter, str);
5131
5132 // prepare feedback
5133 pRaCfg->length = htons(2);
5134 pRaCfg->status = htons(0);
5135 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5136 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5137 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5138
5139 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5140 {
5141 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SEL_RX_ANTENNA\n"));
5142 Status = -EFAULT;
5143 }
5144 else
5145 {
5146 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SEL_RX_ANTENNA is done !\n"));
5147 }
5148 }
5149 break;
5150
5151 case RACFG_CMD_ATE_SET_PREAMBLE:
5152 {
5153 SHORT value = 0;
5154 UCHAR str[LEN_OF_ARG];
5155
5156 NdisZeroMemory(str, LEN_OF_ARG);
5157
5158 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_PREAMBLE\n"));
5159
5160 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5161 value = ntohs(value);
5162 sprintf((PCHAR)str, "%d", value);
5163 Set_ATE_TX_MODE_Proc(pAdapter, str);
5164
5165 // prepare feedback
5166 pRaCfg->length = htons(2);
5167 pRaCfg->status = htons(0);
5168 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5169 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5170 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5171
5172 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5173 {
5174 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_PREAMBLE\n"));
5175 Status = -EFAULT;
5176 }
5177 else
5178 {
5179 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_PREAMBLE is done !\n"));
5180 }
5181 }
5182 break;
5183
5184 case RACFG_CMD_ATE_SET_CHANNEL:
5185 {
5186 SHORT value = 0;
5187 UCHAR str[LEN_OF_ARG];
5188
5189 NdisZeroMemory(str, LEN_OF_ARG);
5190
5191 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_CHANNEL\n"));
5192
5193 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5194 value = ntohs(value);
5195 sprintf((PCHAR)str, "%d", value);
5196 Set_ATE_CHANNEL_Proc(pAdapter, str);
5197
5198 // prepare feedback
5199 pRaCfg->length = htons(2);
5200 pRaCfg->status = htons(0);
5201 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5202 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5203 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5204
5205 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5206 {
5207 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_CHANNEL\n"));
5208 Status = -EFAULT;
5209 }
5210 else
5211 {
5212 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_CHANNEL is done !\n"));
5213 }
5214 }
5215 break;
5216
5217 case RACFG_CMD_ATE_SET_ADDR1:
5218 {
5219 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR1\n"));
5220
5221 // Addr is an array of UCHAR,
5222 // so no need to perform endian swap.
5223 memcpy(pAdapter->ate.Addr1, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5224
5225 // prepare feedback
5226 pRaCfg->length = htons(2);
5227 pRaCfg->status = htons(0);
5228 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5229 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5230 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5231
5232 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5233 {
5234 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_ADDR1\n"));
5235 Status = -EFAULT;
5236 }
5237 else
5238 {
5239 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_ADDR1 is done !\n (ADDR1 = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAdapter->ate.Addr1[0],
5240 pAdapter->ate.Addr1[1], pAdapter->ate.Addr1[2], pAdapter->ate.Addr1[3], pAdapter->ate.Addr1[4], pAdapter->ate.Addr1[5]));
5241 }
5242 }
5243 break;
5244
5245 case RACFG_CMD_ATE_SET_ADDR2:
5246 {
5247 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR2\n"));
5248
5249 // Addr is an array of UCHAR,
5250 // so no need to perform endian swap.
5251 memcpy(pAdapter->ate.Addr2, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5252
5253 // prepare feedback
5254 pRaCfg->length = htons(2);
5255 pRaCfg->status = htons(0);
5256 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5257 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5258 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5259
5260 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5261 {
5262 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_ADDR2\n"));
5263 Status = -EFAULT;
5264 }
5265 else
5266 {
5267 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_ADDR2 is done !\n (ADDR2 = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAdapter->ate.Addr2[0],
5268 pAdapter->ate.Addr2[1], pAdapter->ate.Addr2[2], pAdapter->ate.Addr2[3], pAdapter->ate.Addr2[4], pAdapter->ate.Addr2[5]));
5269 }
5270 }
5271 break;
5272
5273 case RACFG_CMD_ATE_SET_ADDR3:
5274 {
5275 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR3\n"));
5276
5277 // Addr is an array of UCHAR,
5278 // so no need to perform endian swap.
5279 memcpy(pAdapter->ate.Addr3, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5280
5281 // prepare feedback
5282 pRaCfg->length = htons(2);
5283 pRaCfg->status = htons(0);
5284 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5285 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5286 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5287
5288 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5289 {
5290 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_ADDR3\n"));
5291 Status = -EFAULT;
5292 }
5293 else
5294 {
5295 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_ADDR3 is done !\n (ADDR3 = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAdapter->ate.Addr3[0],
5296 pAdapter->ate.Addr3[1], pAdapter->ate.Addr3[2], pAdapter->ate.Addr3[3], pAdapter->ate.Addr3[4], pAdapter->ate.Addr3[5]));
5297 }
5298 }
5299 break;
5300
5301 case RACFG_CMD_ATE_SET_RATE:
5302 {
5303 SHORT value = 0;
5304 UCHAR str[LEN_OF_ARG];
5305
5306 NdisZeroMemory(str, LEN_OF_ARG);
5307
5308 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_RATE\n"));
5309
5310 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5311 value = ntohs(value);
5312 sprintf((PCHAR)str, "%d", value);
5313 Set_ATE_TX_MCS_Proc(pAdapter, str);
5314
5315 // prepare feedback
5316 pRaCfg->length = htons(2);
5317 pRaCfg->status = htons(0);
5318 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5319 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5320 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5321
5322 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5323 {
5324 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_RATE\n"));
5325 Status = -EFAULT;
5326 }
5327 else
5328 {
5329 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_RATE is done !\n"));
5330 }
5331 }
5332 break;
5333
5334 case RACFG_CMD_ATE_SET_TX_FRAME_LEN:
5335 {
5336 SHORT value = 0;
5337 UCHAR str[LEN_OF_ARG];
5338
5339 NdisZeroMemory(str, LEN_OF_ARG);
5340
5341 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_LEN\n"));
5342
5343 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5344 value = ntohs(value);
5345 sprintf((PCHAR)str, "%d", value);
5346 Set_ATE_TX_LENGTH_Proc(pAdapter, str);
5347
5348 // prepare feedback
5349 pRaCfg->length = htons(2);
5350 pRaCfg->status = htons(0);
5351 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5352 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5353 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5354
5355 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5356 {
5357 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_FRAME_LEN\n"));
5358 Status = -EFAULT;
5359 }
5360 else
5361 {
5362 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_FRAME_LEN is done !\n"));
5363 }
5364 }
5365 break;
5366
5367 case RACFG_CMD_ATE_SET_TX_FRAME_COUNT:
5368 {
5369 USHORT value = 0;
5370 UCHAR str[LEN_OF_ARG];
5371
5372 NdisZeroMemory(str, LEN_OF_ARG);
5373
5374 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_COUNT\n"));
5375
5376 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5377 value = ntohs(value);
5378 #ifdef RT2860
5379 /* TX_FRAME_COUNT == 0 means tx infinitely */
5380 if (value == 0)
5381 {
5382 /* Use TxCount = 0xFFFFFFFF to approximate the infinity. */
5383 pAdapter->ate.TxCount = 0xFFFFFFFF;
5384 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_COUNT_Proc (TxCount = %d)\n", pAdapter->ate.TxCount));
5385 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_COUNT_Proc Success\n"));
5386
5387
5388 }
5389 else
5390 #endif // RT2860 //
5391 {
5392 sprintf((PCHAR)str, "%d", value);
5393 Set_ATE_TX_COUNT_Proc(pAdapter, str);
5394 }
5395
5396 // prepare feedback
5397 pRaCfg->length = htons(2);
5398 pRaCfg->status = htons(0);
5399 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5400 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5401 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5402
5403 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5404 {
5405 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_FRAME_COUNT\n"));
5406 Status = -EFAULT;
5407 }
5408 else
5409 {
5410 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_FRAME_COUNT is done !\n"));
5411 }
5412 }
5413 break;
5414
5415 case RACFG_CMD_ATE_START_RX_FRAME:
5416 {
5417 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n"));
5418
5419 Set_ATE_Proc(pAdapter, "RXFRAME");
5420
5421 // prepare feedback
5422 pRaCfg->length = htons(2);
5423 pRaCfg->status = htons(0);
5424 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5425 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5426 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5427
5428 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5429 {
5430 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RX_START\n"));
5431 Status = -EFAULT;
5432 }
5433 else
5434 {
5435 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RX_START is done !\n"));
5436 }
5437 }
5438 break;
5439 default:
5440 break;
5441 }
5442 ASSERT(pRaCfg != NULL);
5443 if (pRaCfg != NULL)
5444 {
5445 kfree(pRaCfg);
5446 }
5447 return;
5448 }
5449
5450 VOID BubbleSort(INT32 n, INT32 a[])
5451 {
5452 INT32 k, j, temp;
5453
5454 for (k = n-1; k>0; k--)
5455 {
5456 for (j = 0; j<k; j++)
5457 {
5458 if(a[j] > a[j+1])
5459 {
5460 temp = a[j];
5461 a[j]=a[j+1];
5462 a[j+1]=temp;
5463 }
5464 }
5465 }
5466 }
5467
5468 VOID CalNoiseLevel(PRTMP_ADAPTER pAd, UCHAR channel, INT32 RSSI[3][10])
5469 {
5470 INT32 RSSI0, RSSI1, RSSI2;
5471 CHAR Rssi0Offset, Rssi1Offset, Rssi2Offset;
5472 UCHAR BbpR50Rssi0 = 0, BbpR51Rssi1 = 0, BbpR52Rssi2 = 0;
5473 UCHAR Org_BBP66value = 0, Org_BBP69value = 0, Org_BBP70value = 0, data = 0;
5474 USHORT LNA_Gain = 0;
5475 INT32 j = 0;
5476 UCHAR Org_Channel = pAd->ate.Channel;
5477 USHORT GainValue = 0, OffsetValue = 0;
5478
5479 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &Org_BBP66value);
5480 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R69, &Org_BBP69value);
5481 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R70, &Org_BBP70value);
5482
5483 //**********************************************************************
5484 // Read the value of LNA gain and Rssi offset
5485 //**********************************************************************
5486 RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, GainValue);
5487
5488 // for Noise Level
5489 if (channel <= 14)
5490 {
5491 LNA_Gain = GainValue & 0x00FF;
5492
5493 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, OffsetValue);
5494 Rssi0Offset = OffsetValue & 0x00FF;
5495 Rssi1Offset = (OffsetValue & 0xFF00) >> 8;
5496 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_BG_OFFSET + 2)/* 0x48 */, OffsetValue);
5497 Rssi2Offset = OffsetValue & 0x00FF;
5498 }
5499 else
5500 {
5501 LNA_Gain = (GainValue & 0xFF00) >> 8;
5502
5503 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, OffsetValue);
5504 Rssi0Offset = OffsetValue & 0x00FF;
5505 Rssi1Offset = (OffsetValue & 0xFF00) >> 8;
5506 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET + 2)/* 0x4C */, OffsetValue);
5507 Rssi2Offset = OffsetValue & 0x00FF;
5508 }
5509 //**********************************************************************
5510 {
5511 pAd->ate.Channel = channel;
5512 ATEAsicSwitchChannel(pAd);
5513 mdelay(5);
5514
5515 data = 0x10;
5516 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, data);
5517 data = 0x40;
5518 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, data);
5519 data = 0x40;
5520 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, data);
5521 mdelay(5);
5522
5523 // Start Rx
5524 pAd->ate.bQARxStart = TRUE;
5525 Set_ATE_Proc(pAd, "RXFRAME");
5526
5527 mdelay(5);
5528
5529 for (j = 0; j < 10; j++)
5530 {
5531 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R50, &BbpR50Rssi0);
5532 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R51, &BbpR51Rssi1);
5533 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R52, &BbpR52Rssi2);
5534
5535 mdelay(10);
5536
5537 // Calculate RSSI 0
5538 if (BbpR50Rssi0 == 0)
5539 {
5540 RSSI0 = -100;
5541 }
5542 else
5543 {
5544 RSSI0 = (INT32)(-12 - BbpR50Rssi0 - LNA_Gain - Rssi0Offset);
5545 }
5546 RSSI[0][j] = RSSI0;
5547
5548 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
5549 {
5550 // Calculate RSSI 1
5551 if (BbpR51Rssi1 == 0)
5552 {
5553 RSSI1 = -100;
5554 }
5555 else
5556 {
5557 RSSI1 = (INT32)(-12 - BbpR51Rssi1 - LNA_Gain - Rssi1Offset);
5558 }
5559 RSSI[1][j] = RSSI1;
5560 }
5561
5562 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
5563 {
5564 // Calculate RSSI 2
5565 if (BbpR52Rssi2 == 0)
5566 RSSI2 = -100;
5567 else
5568 RSSI2 = (INT32)(-12 - BbpR52Rssi2 - LNA_Gain - Rssi2Offset);
5569
5570 RSSI[2][j] = RSSI2;
5571 }
5572 }
5573
5574 // Stop Rx
5575 Set_ATE_Proc(pAd, "RXSTOP");
5576
5577 mdelay(5);
5578
5579 #if 0// Debug Message................
5580 ate_print("\n**********************************************************\n");
5581 ate_print("Noise Level: Channel %d\n", channel);
5582 ate_print("RSSI0 = %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
5583 RSSI[0][0], RSSI[0][1], RSSI[0][2],
5584 RSSI[0][3], RSSI[0][4], RSSI[0][5],
5585 RSSI[0][6], RSSI[0][7], RSSI[0][8],
5586 RSSI[0][9]);
5587 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
5588 {
5589 ate_print("RSSI1 = %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
5590 RSSI[1][0], RSSI[1][1], RSSI[1][2],
5591 RSSI[1][3], RSSI[1][4], RSSI[1][5],
5592 RSSI[1][6], RSSI[1][7], RSSI[1][8],
5593 RSSI[1][9]);
5594 }
5595 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
5596 {
5597 ate_print("RSSI2 = %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
5598 RSSI[2][0], RSSI[2][1], RSSI[2][2],
5599 RSSI[2][3], RSSI[2][4], RSSI[2][5],
5600 RSSI[2][6], RSSI[2][7], RSSI[2][8],
5601 RSSI[2][9]);
5602 }
5603 #endif // 0 //
5604 BubbleSort(10, RSSI[0]); // 1R
5605
5606 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
5607 {
5608 BubbleSort(10, RSSI[1]);
5609 }
5610
5611 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
5612 {
5613 BubbleSort(10, RSSI[2]);
5614 }
5615
5616 #if 0// Debug Message................
5617 ate_print("\nAfter Sorting....Channel %d\n", channel);
5618 ate_print("RSSI0 = %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
5619 RSSI[0][0], RSSI[0][1], RSSI[0][2],
5620 RSSI[0][3], RSSI[0][4], RSSI[0][5],
5621 RSSI[0][6], RSSI[0][7], RSSI[0][8],
5622 RSSI[0][9]);
5623 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
5624 {
5625 ate_print("RSSI1 = %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
5626 RSSI[1][0], RSSI[1][1], RSSI[1][2],
5627 RSSI[1][3], RSSI[1][4], RSSI[1][5],
5628 RSSI[1][6], RSSI[1][7], RSSI[1][8],
5629 RSSI[1][9]);
5630 }
5631 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
5632 {
5633 ate_print("RSSI2 = %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
5634 RSSI[2][0], RSSI[2][1], RSSI[2][2],
5635 RSSI[2][3], RSSI[2][4], RSSI[2][5],
5636 RSSI[2][6], RSSI[2][7], RSSI[2][8],
5637 RSSI[2][9]);
5638 }
5639 ate_print("**********************************************************\n");
5640 #endif // 0 //
5641 }
5642
5643 pAd->ate.Channel = Org_Channel;
5644 ATEAsicSwitchChannel(pAd);
5645
5646 // Restore original value
5647 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Org_BBP66value);
5648 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, Org_BBP69value);
5649 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, Org_BBP70value);
5650
5651 return;
5652 }
5653
5654 BOOLEAN SyncTxRxConfig(PRTMP_ADAPTER pAd, USHORT offset, UCHAR value)
5655 {
5656 UCHAR tmp = 0, bbp_data = 0;
5657
5658 if (ATE_ON(pAd))
5659 {
5660 ATE_BBP_IO_READ8_BY_REG_ID(pAd, offset, &bbp_data);
5661 }
5662 else
5663 {
5664 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, offset, &bbp_data);
5665 }
5666
5667 /* confirm again */
5668 ASSERT(bbp_data == value);
5669
5670 switch(offset)
5671 {
5672 case BBP_R1:
5673 /* Need to sync. tx configuration with legacy ATE. */
5674 tmp = (bbp_data & ((1 << 4) | (1 << 3))/* 0x18 */) >> 3;
5675 switch(tmp)
5676 {
5677 /* The BBP R1 bit[4:3] = 2 :: Both DACs will be used by QA. */
5678 case 2:
5679 /* All */
5680 pAd->ate.TxAntennaSel = 0;
5681 break;
5682 /* The BBP R1 bit[4:3] = 0 :: DAC 0 will be used by QA. */
5683 case 0:
5684 /* Antenna one */
5685 pAd->ate.TxAntennaSel = 1;
5686 break;
5687 /* The BBP R1 bit[4:3] = 1 :: DAC 1 will be used by QA. */
5688 case 1:
5689 /* Antenna two */
5690 pAd->ate.TxAntennaSel = 2;
5691 break;
5692 default:
5693 DBGPRINT(RT_DEBUG_TRACE, ("%s -- Sth. wrong! : return FALSE; \n", __func__));
5694 return FALSE;
5695 }
5696 break;/* case BBP_R1 */
5697
5698 case BBP_R3:
5699 /* Need to sync. rx configuration with legacy ATE. */
5700 tmp = (bbp_data & ((1 << 1) | (1 << 0))/* 0x03 */);
5701 switch(tmp)
5702 {
5703 /* The BBP R3 bit[1:0] = 3 :: All ADCs will be used by QA. */
5704 case 3:
5705 /* All */
5706 pAd->ate.RxAntennaSel = 0;
5707 break;
5708 /* The BBP R3 bit[1:0] = 0 :: ADC 0 will be used by QA, */
5709 /* unless the BBP R3 bit[4:3] = 2 */
5710 case 0:
5711 /* Antenna one */
5712 pAd->ate.RxAntennaSel = 1;
5713 tmp = ((bbp_data & ((1 << 4) | (1 << 3))/* 0x03 */) >> 3);
5714 if (tmp == 2)// 3R
5715 {
5716 /* Default : All ADCs will be used by QA */
5717 pAd->ate.RxAntennaSel = 0;
5718 }
5719 break;
5720 /* The BBP R3 bit[1:0] = 1 :: ADC 1 will be used by QA. */
5721 case 1:
5722 /* Antenna two */
5723 pAd->ate.RxAntennaSel = 2;
5724 break;
5725 /* The BBP R3 bit[1:0] = 2 :: ADC 2 will be used by QA. */
5726 case 2:
5727 /* Antenna three */
5728 pAd->ate.RxAntennaSel = 3;
5729 break;
5730 default:
5731 DBGPRINT(RT_DEBUG_ERROR, ("%s -- Impossible! : return FALSE; \n", __func__));
5732 return FALSE;
5733 }
5734 break;/* case BBP_R3 */
5735
5736 default:
5737 DBGPRINT(RT_DEBUG_ERROR, ("%s -- Sth. wrong! : return FALSE; \n", __func__));
5738 return FALSE;
5739
5740 }
5741 return TRUE;
5742 }
5743
5744 static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len)
5745 {
5746 ULONG i, Value = 0;
5747 ULONG *pDst, *pSrc;
5748 UCHAR *p8;
5749
5750 p8 = src;
5751 pDst = (ULONG *) dst;
5752 pSrc = (ULONG *) src;
5753
5754 for (i = 0 ; i < (len/4); i++)
5755 {
5756 /* For alignment issue, we need a variable "Value". */
5757 memmove(&Value, pSrc, 4);
5758 Value = htonl(Value);
5759 memmove(pDst, &Value, 4);
5760 pDst++;
5761 pSrc++;
5762 }
5763 if ((len % 4) != 0)
5764 {
5765 /* wish that it will never reach here */
5766 memmove(&Value, pSrc, (len % 4));
5767 Value = htonl(Value);
5768 memmove(pDst, &Value, (len % 4));
5769 }
5770 }
5771
5772 static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len)
5773 {
5774 ULONG i;
5775 UCHAR *pDst, *pSrc;
5776
5777 pDst = dst;
5778 pSrc = src;
5779
5780 for (i = 0; i < (len/2); i++)
5781 {
5782 memmove(pDst, pSrc, 2);
5783 *((USHORT *)pDst) = htons(*((USHORT *)pDst));
5784 pDst+=2;
5785 pSrc+=2;
5786 }
5787
5788 if ((len % 2) != 0)
5789 {
5790 memmove(pDst, pSrc, 1);
5791 }
5792 }
5793
5794 static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, UINT32 len)
5795 {
5796 UINT32 i, Value;
5797 UINT32 *pDst, *pSrc;
5798
5799 pDst = (UINT32 *) dst;
5800 pSrc = (UINT32 *) src;
5801
5802 for (i = 0 ; i < (len/4); i++)
5803 {
5804 RTMP_IO_READ32(pAd, (ULONG)pSrc, &Value);
5805 Value = htonl(Value);
5806 memmove(pDst, &Value, 4);
5807 pDst++;
5808 pSrc++;
5809 }
5810 return;
5811 }
5812
5813 // TODO:
5814 #if 0
5815 /* These work only when RALINK_ATE is defined */
5816 INT Set_TxStart_Proc(
5817 IN PRTMP_ADAPTER pAd,
5818 IN PUCHAR arg)
5819 {
5820 ULONG value = simple_strtol(arg, 0, 10);
5821 UCHAR buffer[26] = {0x88, 0x02, 0x2c, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x00, 0x55, 0x44, 0x33, 0x22, 0x11, 0xc0, 0x22, 0x00, 0x00};
5822 POS_COOKIE pObj;
5823
5824 if (pAd->ate.TxStatus != 0)
5825 return FALSE;
5826
5827 pAd->ate.TxInfo = 0x04000000;
5828 bzero(&pAd->ate.TxWI, sizeof(TXWI_STRUC));
5829 pAd->ate.TxWI.PHYMODE = 0;// MODE_CCK
5830 pAd->ate.TxWI.MPDUtotalByteCount = 1226;
5831 pAd->ate.TxWI.MCS = 3;
5832 //pAd->ate.Mode = ATE_START;
5833 pAd->ate.Mode |= ATE_TXFRAME;
5834 pAd->ate.TxCount = value;
5835 pAd->ate.QID = 0;
5836 pAd->ate.HLen = 26;
5837 pAd->ate.PLen = 0;
5838 pAd->ate.DLen = 1200;
5839 memcpy(pAd->ate.Header, buffer, 26);
5840 pAd->ate.bQATxStart = TRUE;
5841 //pObj = (POS_COOKIE) pAd->OS_Cookie;
5842 //tasklet_hi_schedule(&pObj->AteTxTask);
5843 return TRUE;
5844 }
5845 #endif /* end of #if 0 */
5846
5847 INT Set_TxStop_Proc(
5848 IN PRTMP_ADAPTER pAd,
5849 IN PUCHAR arg)
5850 {
5851 ATEDBGPRINT(RT_DEBUG_TRACE,("Set_TxStop_Proc\n"));
5852
5853 if (Set_ATE_Proc(pAd, "TXSTOP"))
5854 {
5855 return TRUE;
5856 }
5857 else
5858 {
5859 return FALSE;
5860 }
5861 }
5862
5863 INT Set_RxStop_Proc(
5864 IN PRTMP_ADAPTER pAd,
5865 IN PUCHAR arg)
5866 {
5867 ATEDBGPRINT(RT_DEBUG_TRACE,("Set_RxStop_Proc\n"));
5868
5869 if (Set_ATE_Proc(pAd, "RXSTOP"))
5870 {
5871 return TRUE;
5872 }
5873 else
5874 {
5875 return FALSE;
5876 }
5877 }
5878
5879 #if 0
5880 INT Set_EEWrite_Proc(
5881 IN PRTMP_ADAPTER pAd,
5882 IN PUCHAR arg)
5883 {
5884 USHORT offset = 0, value;
5885 PUCHAR p2 = arg;
5886
5887 while((*p2 != ':') && (*p2 != '\0'))
5888 {
5889 p2++;
5890 }
5891
5892 if (*p2 == ':')
5893 {
5894 A2Hex(offset, arg);
5895 A2Hex(value, p2+ 1);
5896 }
5897 else
5898 {
5899 A2Hex(value, arg);
5900 }
5901
5902 if (offset >= EEPROM_SIZE)
5903 {
5904 ate_print("Offset can not exceed EEPROM_SIZE( == 0x%04x)\n", EEPROM_SIZE);
5905 return FALSE;
5906 }
5907
5908 RTMP_EEPROM_WRITE16(pAd, offset, value);
5909
5910 return TRUE;
5911 }
5912
5913 INT Set_BBPRead_Proc(
5914 IN PRTMP_ADAPTER pAd,
5915 IN PUCHAR arg)
5916 {
5917 UCHAR value = 0, offset;
5918
5919 A2Hex(offset, arg);
5920
5921 if (ATE_ON(pAd))
5922 {
5923 ATE_BBP_IO_READ8_BY_REG_ID(pAd, offset, &value);
5924 }
5925 else
5926 {
5927 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, offset, &value);
5928 }
5929
5930 ate_print("%x\n", value);
5931
5932 return TRUE;
5933 }
5934
5935
5936 INT Set_BBPWrite_Proc(
5937 IN PRTMP_ADAPTER pAd,
5938 IN PUCHAR arg)
5939 {
5940 USHORT offset = 0;
5941 PUCHAR p2 = arg;
5942 UCHAR value;
5943
5944 while((*p2 != ':') && (*p2 != '\0'))
5945 {
5946 p2++;
5947 }
5948
5949 if (*p2 == ':')
5950 {
5951 A2Hex(offset, arg);
5952 A2Hex(value, p2+ 1);
5953 }
5954 else
5955 {
5956 A2Hex(value, arg);
5957 }
5958
5959 if (ATE_ON(pAd))
5960 {
5961 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, offset, value);
5962 }
5963 else
5964 {
5965 RTNP_BBP_IO_WRITE8_BY_REG_ID(pAd, offset, value);
5966 }
5967
5968 return TRUE;
5969 }
5970
5971 INT Set_RFWrite_Proc(
5972 IN PRTMP_ADAPTER pAd,
5973 IN PUCHAR arg)
5974 {
5975 PUCHAR p2, p3, p4;
5976 ULONG R1, R2, R3, R4;
5977
5978 p2 = arg;
5979
5980 while((*p2 != ':') && (*p2 != '\0'))
5981 {
5982 p2++;
5983 }
5984
5985 if (*p2 != ':')
5986 return FALSE;
5987
5988 p3 = p2 + 1;
5989
5990 while((*p3 != ':') && (*p3 != '\0'))
5991 {
5992 p3++;
5993 }
5994
5995 if (*p3 != ':')
5996 return FALSE;
5997
5998 p4 = p3 + 1;
5999
6000 while((*p4 != ':') && (*p4 != '\0'))
6001 {
6002 p4++;
6003 }
6004
6005 if (*p4 != ':')
6006 return FALSE;
6007
6008
6009 A2Hex(R1, arg);
6010 A2Hex(R2, p2 + 1);
6011 A2Hex(R3, p3 + 1);
6012 A2Hex(R4, p4 + 1);
6013
6014 RTMP_RF_IO_WRITE32(pAd, R1);
6015 RTMP_RF_IO_WRITE32(pAd, R2);
6016 RTMP_RF_IO_WRITE32(pAd, R3);
6017 RTMP_RF_IO_WRITE32(pAd, R4);
6018
6019 return TRUE;
6020 }
6021 #endif // end of #if 0 //
6022 #endif // RALINK_28xx_QA //
6023
6024 #endif // RALINK_ATE //
6025
CJK support for tty framebuffer vt