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at91: at91sam9g20ek modify dual slot evaluation kit
[linux-2.6/cjktty.git] / arch / arm / plat-omap / gpio.c
blob71ebd7fcfea158afa5d0f6eb14b4d9202f79be5a
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP730 specific GPIO registers
72 */
73 #define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
74 #define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
75 #define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
76 #define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
77 #define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
78 #define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
85
86 /*
87 * OMAP850 specific GPIO registers
88 */
89 #define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90 #define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91 #define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92 #define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93 #define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94 #define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95 #define OMAP850_GPIO_DATA_INPUT 0x00
96 #define OMAP850_GPIO_DATA_OUTPUT 0x04
97 #define OMAP850_GPIO_DIR_CONTROL 0x08
98 #define OMAP850_GPIO_INT_CONTROL 0x0c
99 #define OMAP850_GPIO_INT_MASK 0x10
100 #define OMAP850_GPIO_INT_STATUS 0x14
101
102 #define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103
104 /*
105 * omap24xx specific GPIO registers
106 */
107 #define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000)
108 #define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000)
109 #define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000)
110 #define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000)
111
112 #define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000)
113 #define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000)
114 #define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000)
115 #define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000)
116 #define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000)
117
118 #define OMAP24XX_GPIO_REVISION 0x0000
119 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
120 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
121 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
122 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
123 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
124 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
125 #define OMAP24XX_GPIO_WAKE_EN 0x0020
126 #define OMAP24XX_GPIO_CTRL 0x0030
127 #define OMAP24XX_GPIO_OE 0x0034
128 #define OMAP24XX_GPIO_DATAIN 0x0038
129 #define OMAP24XX_GPIO_DATAOUT 0x003c
130 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
131 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
132 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
133 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
134 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
135 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
136 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
137 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
138 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
139 #define OMAP24XX_GPIO_SETWKUENA 0x0084
140 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
141 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
142
143 #define OMAP4_GPIO_REVISION 0x0000
144 #define OMAP4_GPIO_SYSCONFIG 0x0010
145 #define OMAP4_GPIO_EOI 0x0020
146 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
147 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
148 #define OMAP4_GPIO_IRQSTATUS0 0x002c
149 #define OMAP4_GPIO_IRQSTATUS1 0x0030
150 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
151 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
152 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
153 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
154 #define OMAP4_GPIO_IRQWAKEN0 0x0044
155 #define OMAP4_GPIO_IRQWAKEN1 0x0048
156 #define OMAP4_GPIO_SYSSTATUS 0x0104
157 #define OMAP4_GPIO_CTRL 0x0130
158 #define OMAP4_GPIO_OE 0x0134
159 #define OMAP4_GPIO_DATAIN 0x0138
160 #define OMAP4_GPIO_DATAOUT 0x013c
161 #define OMAP4_GPIO_LEVELDETECT0 0x0140
162 #define OMAP4_GPIO_LEVELDETECT1 0x0144
163 #define OMAP4_GPIO_RISINGDETECT 0x0148
164 #define OMAP4_GPIO_FALLINGDETECT 0x014c
165 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
166 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
167 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
168 #define OMAP4_GPIO_SETDATAOUT 0x0194
169 /*
170 * omap34xx specific GPIO registers
171 */
172
173 #define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000)
174 #define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000)
175 #define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000)
176 #define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000)
177 #define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000)
178 #define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000)
179
180 /*
181 * OMAP44XX specific GPIO registers
182 */
183 #define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000)
184 #define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000)
185 #define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000)
186 #define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000)
187 #define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000)
188 #define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000)
189
190 struct gpio_bank {
191 void __iomem *base;
192 u16 irq;
193 u16 virtual_irq_start;
194 int method;
195 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
196 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
197 u32 suspend_wakeup;
198 u32 saved_wakeup;
199 #endif
200 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
201 defined(CONFIG_ARCH_OMAP4)
202 u32 non_wakeup_gpios;
203 u32 enabled_non_wakeup_gpios;
204
205 u32 saved_datain;
206 u32 saved_fallingdetect;
207 u32 saved_risingdetect;
208 #endif
209 u32 level_mask;
210 spinlock_t lock;
211 struct gpio_chip chip;
212 struct clk *dbck;
213 };
214
215 #define METHOD_MPUIO 0
216 #define METHOD_GPIO_1510 1
217 #define METHOD_GPIO_1610 2
218 #define METHOD_GPIO_730 3
219 #define METHOD_GPIO_850 4
220 #define METHOD_GPIO_24XX 5
221
222 #ifdef CONFIG_ARCH_OMAP16XX
223 static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
228 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
229 };
230 #endif
231
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
236 };
237 #endif
238
239 #ifdef CONFIG_ARCH_OMAP730
240 static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
248 };
249 #endif
250
251 #ifdef CONFIG_ARCH_OMAP850
252 static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
260 };
261 #endif
262
263
264 #ifdef CONFIG_ARCH_OMAP24XX
265
266 static struct gpio_bank gpio_bank_242x[4] = {
267 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
268 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
269 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
270 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
271 };
272
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
275 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
276 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
277 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
278 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
279 };
280
281 #endif
282
283 #ifdef CONFIG_ARCH_OMAP34XX
284 static struct gpio_bank gpio_bank_34xx[6] = {
285 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
291 };
292
293 #endif
294
295 #ifdef CONFIG_ARCH_OMAP4
296 static struct gpio_bank gpio_bank_44xx[6] = {
297 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
298 METHOD_GPIO_24XX },
299 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
300 METHOD_GPIO_24XX },
301 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
302 METHOD_GPIO_24XX },
303 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
304 METHOD_GPIO_24XX },
305 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
306 METHOD_GPIO_24XX },
307 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
308 METHOD_GPIO_24XX },
309 };
310
311 #endif
312
313 static struct gpio_bank *gpio_bank;
314 static int gpio_bank_count;
315
316 static inline struct gpio_bank *get_gpio_bank(int gpio)
317 {
318 if (cpu_is_omap15xx()) {
319 if (OMAP_GPIO_IS_MPUIO(gpio))
320 return &gpio_bank[0];
321 return &gpio_bank[1];
322 }
323 if (cpu_is_omap16xx()) {
324 if (OMAP_GPIO_IS_MPUIO(gpio))
325 return &gpio_bank[0];
326 return &gpio_bank[1 + (gpio >> 4)];
327 }
328 if (cpu_is_omap7xx()) {
329 if (OMAP_GPIO_IS_MPUIO(gpio))
330 return &gpio_bank[0];
331 return &gpio_bank[1 + (gpio >> 5)];
332 }
333 if (cpu_is_omap24xx())
334 return &gpio_bank[gpio >> 5];
335 if (cpu_is_omap34xx() || cpu_is_omap44xx())
336 return &gpio_bank[gpio >> 5];
337 BUG();
338 return NULL;
339 }
340
341 static inline int get_gpio_index(int gpio)
342 {
343 if (cpu_is_omap7xx())
344 return gpio & 0x1f;
345 if (cpu_is_omap24xx())
346 return gpio & 0x1f;
347 if (cpu_is_omap34xx() || cpu_is_omap44xx())
348 return gpio & 0x1f;
349 return gpio & 0x0f;
350 }
351
352 static inline int gpio_valid(int gpio)
353 {
354 if (gpio < 0)
355 return -1;
356 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
357 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
358 return -1;
359 return 0;
360 }
361 if (cpu_is_omap15xx() && gpio < 16)
362 return 0;
363 if ((cpu_is_omap16xx()) && gpio < 64)
364 return 0;
365 if (cpu_is_omap7xx() && gpio < 192)
366 return 0;
367 if (cpu_is_omap24xx() && gpio < 128)
368 return 0;
369 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
370 return 0;
371 return -1;
372 }
373
374 static int check_gpio(int gpio)
375 {
376 if (unlikely(gpio_valid(gpio)) < 0) {
377 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
378 dump_stack();
379 return -1;
380 }
381 return 0;
382 }
383
384 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
385 {
386 void __iomem *reg = bank->base;
387 u32 l;
388
389 switch (bank->method) {
390 #ifdef CONFIG_ARCH_OMAP1
391 case METHOD_MPUIO:
392 reg += OMAP_MPUIO_IO_CNTL;
393 break;
394 #endif
395 #ifdef CONFIG_ARCH_OMAP15XX
396 case METHOD_GPIO_1510:
397 reg += OMAP1510_GPIO_DIR_CONTROL;
398 break;
399 #endif
400 #ifdef CONFIG_ARCH_OMAP16XX
401 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_DIRECTION;
403 break;
404 #endif
405 #ifdef CONFIG_ARCH_OMAP730
406 case METHOD_GPIO_730:
407 reg += OMAP730_GPIO_DIR_CONTROL;
408 break;
409 #endif
410 #ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
413 break;
414 #endif
415 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
416 case METHOD_GPIO_24XX:
417 reg += OMAP24XX_GPIO_OE;
418 break;
419 #endif
420 #if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
423 break;
424 #endif
425 default:
426 WARN_ON(1);
427 return;
428 }
429 l = __raw_readl(reg);
430 if (is_input)
431 l |= 1 << gpio;
432 else
433 l &= ~(1 << gpio);
434 __raw_writel(l, reg);
435 }
436
437 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
438 {
439 void __iomem *reg = bank->base;
440 u32 l = 0;
441
442 switch (bank->method) {
443 #ifdef CONFIG_ARCH_OMAP1
444 case METHOD_MPUIO:
445 reg += OMAP_MPUIO_OUTPUT;
446 l = __raw_readl(reg);
447 if (enable)
448 l |= 1 << gpio;
449 else
450 l &= ~(1 << gpio);
451 break;
452 #endif
453 #ifdef CONFIG_ARCH_OMAP15XX
454 case METHOD_GPIO_1510:
455 reg += OMAP1510_GPIO_DATA_OUTPUT;
456 l = __raw_readl(reg);
457 if (enable)
458 l |= 1 << gpio;
459 else
460 l &= ~(1 << gpio);
461 break;
462 #endif
463 #ifdef CONFIG_ARCH_OMAP16XX
464 case METHOD_GPIO_1610:
465 if (enable)
466 reg += OMAP1610_GPIO_SET_DATAOUT;
467 else
468 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
469 l = 1 << gpio;
470 break;
471 #endif
472 #ifdef CONFIG_ARCH_OMAP730
473 case METHOD_GPIO_730:
474 reg += OMAP730_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
476 if (enable)
477 l |= 1 << gpio;
478 else
479 l &= ~(1 << gpio);
480 break;
481 #endif
482 #ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg);
486 if (enable)
487 l |= 1 << gpio;
488 else
489 l &= ~(1 << gpio);
490 break;
491 #endif
492 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
493 case METHOD_GPIO_24XX:
494 if (enable)
495 reg += OMAP24XX_GPIO_SETDATAOUT;
496 else
497 reg += OMAP24XX_GPIO_CLEARDATAOUT;
498 l = 1 << gpio;
499 break;
500 #endif
501 #ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
503 if (enable)
504 reg += OMAP4_GPIO_SETDATAOUT;
505 else
506 reg += OMAP4_GPIO_CLEARDATAOUT;
507 l = 1 << gpio;
508 break;
509 #endif
510 default:
511 WARN_ON(1);
512 return;
513 }
514 __raw_writel(l, reg);
515 }
516
517 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
518 {
519 void __iomem *reg;
520
521 if (check_gpio(gpio) < 0)
522 return -EINVAL;
523 reg = bank->base;
524 switch (bank->method) {
525 #ifdef CONFIG_ARCH_OMAP1
526 case METHOD_MPUIO:
527 reg += OMAP_MPUIO_INPUT_LATCH;
528 break;
529 #endif
530 #ifdef CONFIG_ARCH_OMAP15XX
531 case METHOD_GPIO_1510:
532 reg += OMAP1510_GPIO_DATA_INPUT;
533 break;
534 #endif
535 #ifdef CONFIG_ARCH_OMAP16XX
536 case METHOD_GPIO_1610:
537 reg += OMAP1610_GPIO_DATAIN;
538 break;
539 #endif
540 #ifdef CONFIG_ARCH_OMAP730
541 case METHOD_GPIO_730:
542 reg += OMAP730_GPIO_DATA_INPUT;
543 break;
544 #endif
545 #ifdef CONFIG_ARCH_OMAP850
546 case METHOD_GPIO_850:
547 reg += OMAP850_GPIO_DATA_INPUT;
548 break;
549 #endif
550 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
551 case METHOD_GPIO_24XX:
552 reg += OMAP24XX_GPIO_DATAIN;
553 break;
554 #endif
555 #ifdef CONFIG_ARCH_OMAP4
556 case METHOD_GPIO_24XX:
557 reg += OMAP4_GPIO_DATAIN;
558 break;
559 #endif
560 default:
561 return -EINVAL;
562 }
563 return (__raw_readl(reg)
564 & (1 << get_gpio_index(gpio))) != 0;
565 }
566
567 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
568 {
569 void __iomem *reg;
570
571 if (check_gpio(gpio) < 0)
572 return -EINVAL;
573 reg = bank->base;
574
575 switch (bank->method) {
576 #ifdef CONFIG_ARCH_OMAP1
577 case METHOD_MPUIO:
578 reg += OMAP_MPUIO_OUTPUT;
579 break;
580 #endif
581 #ifdef CONFIG_ARCH_OMAP15XX
582 case METHOD_GPIO_1510:
583 reg += OMAP1510_GPIO_DATA_OUTPUT;
584 break;
585 #endif
586 #ifdef CONFIG_ARCH_OMAP16XX
587 case METHOD_GPIO_1610:
588 reg += OMAP1610_GPIO_DATAOUT;
589 break;
590 #endif
591 #ifdef CONFIG_ARCH_OMAP730
592 case METHOD_GPIO_730:
593 reg += OMAP730_GPIO_DATA_OUTPUT;
594 break;
595 #endif
596 #ifdef CONFIG_ARCH_OMAP850
597 case METHOD_GPIO_850:
598 reg += OMAP850_GPIO_DATA_OUTPUT;
599 break;
600 #endif
601 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
602 defined(CONFIG_ARCH_OMAP4)
603 case METHOD_GPIO_24XX:
604 reg += OMAP24XX_GPIO_DATAOUT;
605 break;
606 #endif
607 default:
608 return -EINVAL;
609 }
610
611 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
612 }
613
614 #define MOD_REG_BIT(reg, bit_mask, set) \
615 do { \
616 int l = __raw_readl(base + reg); \
617 if (set) l |= bit_mask; \
618 else l &= ~bit_mask; \
619 __raw_writel(l, base + reg); \
620 } while(0)
621
622 void omap_set_gpio_debounce(int gpio, int enable)
623 {
624 struct gpio_bank *bank;
625 void __iomem *reg;
626 unsigned long flags;
627 u32 val, l = 1 << get_gpio_index(gpio);
628
629 if (cpu_class_is_omap1())
630 return;
631
632 bank = get_gpio_bank(gpio);
633 reg = bank->base;
634 #ifdef CONFIG_ARCH_OMAP4
635 reg += OMAP4_GPIO_DEBOUNCENABLE;
636 #else
637 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
638 #endif
639
640 spin_lock_irqsave(&bank->lock, flags);
641 val = __raw_readl(reg);
642
643 if (enable && !(val & l))
644 val |= l;
645 else if (!enable && (val & l))
646 val &= ~l;
647 else
648 goto done;
649
650 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
651 if (enable)
652 clk_enable(bank->dbck);
653 else
654 clk_disable(bank->dbck);
655 }
656
657 __raw_writel(val, reg);
658 done:
659 spin_unlock_irqrestore(&bank->lock, flags);
660 }
661 EXPORT_SYMBOL(omap_set_gpio_debounce);
662
663 void omap_set_gpio_debounce_time(int gpio, int enc_time)
664 {
665 struct gpio_bank *bank;
666 void __iomem *reg;
667
668 if (cpu_class_is_omap1())
669 return;
670
671 bank = get_gpio_bank(gpio);
672 reg = bank->base;
673
674 enc_time &= 0xff;
675 #ifdef CONFIG_ARCH_OMAP4
676 reg += OMAP4_GPIO_DEBOUNCINGTIME;
677 #else
678 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
679 #endif
680 __raw_writel(enc_time, reg);
681 }
682 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
683
684 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
685 defined(CONFIG_ARCH_OMAP4)
686 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
687 int trigger)
688 {
689 void __iomem *base = bank->base;
690 u32 gpio_bit = 1 << gpio;
691 u32 val;
692
693 if (cpu_is_omap44xx()) {
694 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
695 trigger & IRQ_TYPE_LEVEL_LOW);
696 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
697 trigger & IRQ_TYPE_LEVEL_HIGH);
698 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
699 trigger & IRQ_TYPE_EDGE_RISING);
700 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
701 trigger & IRQ_TYPE_EDGE_FALLING);
702 } else {
703 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
704 trigger & IRQ_TYPE_LEVEL_LOW);
705 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
706 trigger & IRQ_TYPE_LEVEL_HIGH);
707 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
708 trigger & IRQ_TYPE_EDGE_RISING);
709 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
710 trigger & IRQ_TYPE_EDGE_FALLING);
711 }
712 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
713 if (cpu_is_omap44xx()) {
714 if (trigger != 0)
715 __raw_writel(1 << gpio, bank->base+
716 OMAP4_GPIO_IRQWAKEN0);
717 else {
718 val = __raw_readl(bank->base +
719 OMAP4_GPIO_IRQWAKEN0);
720 __raw_writel(val & (~(1 << gpio)), bank->base +
721 OMAP4_GPIO_IRQWAKEN0);
722 }
723 } else {
724 if (trigger != 0)
725 __raw_writel(1 << gpio, bank->base
726 + OMAP24XX_GPIO_SETWKUENA);
727 else
728 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_CLEARWKUENA);
730 }
731 } else {
732 if (trigger != 0)
733 bank->enabled_non_wakeup_gpios |= gpio_bit;
734 else
735 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
736 }
737
738 if (cpu_is_omap44xx()) {
739 bank->level_mask =
740 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
741 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
742 } else {
743 bank->level_mask =
744 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
745 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
746 }
747 }
748 #endif
749
750 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
751 {
752 void __iomem *reg = bank->base;
753 u32 l = 0;
754
755 switch (bank->method) {
756 #ifdef CONFIG_ARCH_OMAP1
757 case METHOD_MPUIO:
758 reg += OMAP_MPUIO_GPIO_INT_EDGE;
759 l = __raw_readl(reg);
760 if (trigger & IRQ_TYPE_EDGE_RISING)
761 l |= 1 << gpio;
762 else if (trigger & IRQ_TYPE_EDGE_FALLING)
763 l &= ~(1 << gpio);
764 else
765 goto bad;
766 break;
767 #endif
768 #ifdef CONFIG_ARCH_OMAP15XX
769 case METHOD_GPIO_1510:
770 reg += OMAP1510_GPIO_INT_CONTROL;
771 l = __raw_readl(reg);
772 if (trigger & IRQ_TYPE_EDGE_RISING)
773 l |= 1 << gpio;
774 else if (trigger & IRQ_TYPE_EDGE_FALLING)
775 l &= ~(1 << gpio);
776 else
777 goto bad;
778 break;
779 #endif
780 #ifdef CONFIG_ARCH_OMAP16XX
781 case METHOD_GPIO_1610:
782 if (gpio & 0x08)
783 reg += OMAP1610_GPIO_EDGE_CTRL2;
784 else
785 reg += OMAP1610_GPIO_EDGE_CTRL1;
786 gpio &= 0x07;
787 l = __raw_readl(reg);
788 l &= ~(3 << (gpio << 1));
789 if (trigger & IRQ_TYPE_EDGE_RISING)
790 l |= 2 << (gpio << 1);
791 if (trigger & IRQ_TYPE_EDGE_FALLING)
792 l |= 1 << (gpio << 1);
793 if (trigger)
794 /* Enable wake-up during idle for dynamic tick */
795 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
796 else
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
798 break;
799 #endif
800 #ifdef CONFIG_ARCH_OMAP730
801 case METHOD_GPIO_730:
802 reg += OMAP730_GPIO_INT_CONTROL;
803 l = __raw_readl(reg);
804 if (trigger & IRQ_TYPE_EDGE_RISING)
805 l |= 1 << gpio;
806 else if (trigger & IRQ_TYPE_EDGE_FALLING)
807 l &= ~(1 << gpio);
808 else
809 goto bad;
810 break;
811 #endif
812 #ifdef CONFIG_ARCH_OMAP850
813 case METHOD_GPIO_850:
814 reg += OMAP850_GPIO_INT_CONTROL;
815 l = __raw_readl(reg);
816 if (trigger & IRQ_TYPE_EDGE_RISING)
817 l |= 1 << gpio;
818 else if (trigger & IRQ_TYPE_EDGE_FALLING)
819 l &= ~(1 << gpio);
820 else
821 goto bad;
822 break;
823 #endif
824 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
825 defined(CONFIG_ARCH_OMAP4)
826 case METHOD_GPIO_24XX:
827 set_24xx_gpio_triggering(bank, gpio, trigger);
828 break;
829 #endif
830 default:
831 goto bad;
832 }
833 __raw_writel(l, reg);
834 return 0;
835 bad:
836 return -EINVAL;
837 }
838
839 static int gpio_irq_type(unsigned irq, unsigned type)
840 {
841 struct gpio_bank *bank;
842 unsigned gpio;
843 int retval;
844 unsigned long flags;
845
846 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
847 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
848 else
849 gpio = irq - IH_GPIO_BASE;
850
851 if (check_gpio(gpio) < 0)
852 return -EINVAL;
853
854 if (type & ~IRQ_TYPE_SENSE_MASK)
855 return -EINVAL;
856
857 /* OMAP1 allows only only edge triggering */
858 if (!cpu_class_is_omap2()
859 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
860 return -EINVAL;
861
862 bank = get_irq_chip_data(irq);
863 spin_lock_irqsave(&bank->lock, flags);
864 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
865 if (retval == 0) {
866 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
867 irq_desc[irq].status |= type;
868 }
869 spin_unlock_irqrestore(&bank->lock, flags);
870
871 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
872 __set_irq_handler_unlocked(irq, handle_level_irq);
873 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
874 __set_irq_handler_unlocked(irq, handle_edge_irq);
875
876 return retval;
877 }
878
879 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
880 {
881 void __iomem *reg = bank->base;
882
883 switch (bank->method) {
884 #ifdef CONFIG_ARCH_OMAP1
885 case METHOD_MPUIO:
886 /* MPUIO irqstatus is reset by reading the status register,
887 * so do nothing here */
888 return;
889 #endif
890 #ifdef CONFIG_ARCH_OMAP15XX
891 case METHOD_GPIO_1510:
892 reg += OMAP1510_GPIO_INT_STATUS;
893 break;
894 #endif
895 #ifdef CONFIG_ARCH_OMAP16XX
896 case METHOD_GPIO_1610:
897 reg += OMAP1610_GPIO_IRQSTATUS1;
898 break;
899 #endif
900 #ifdef CONFIG_ARCH_OMAP730
901 case METHOD_GPIO_730:
902 reg += OMAP730_GPIO_INT_STATUS;
903 break;
904 #endif
905 #ifdef CONFIG_ARCH_OMAP850
906 case METHOD_GPIO_850:
907 reg += OMAP850_GPIO_INT_STATUS;
908 break;
909 #endif
910 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
911 case METHOD_GPIO_24XX:
912 reg += OMAP24XX_GPIO_IRQSTATUS1;
913 break;
914 #endif
915 #if defined(CONFIG_ARCH_OMAP4)
916 case METHOD_GPIO_24XX:
917 reg += OMAP4_GPIO_IRQSTATUS0;
918 break;
919 #endif
920 default:
921 WARN_ON(1);
922 return;
923 }
924 __raw_writel(gpio_mask, reg);
925
926 /* Workaround for clearing DSP GPIO interrupts to allow retention */
927 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
928 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
929 #endif
930 #if defined(CONFIG_ARCH_OMAP4)
931 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
932 #endif
933 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
934 __raw_writel(gpio_mask, reg);
935
936 /* Flush posted write for the irq status to avoid spurious interrupts */
937 __raw_readl(reg);
938 }
939 }
940
941 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
942 {
943 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
944 }
945
946 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
947 {
948 void __iomem *reg = bank->base;
949 int inv = 0;
950 u32 l;
951 u32 mask;
952
953 switch (bank->method) {
954 #ifdef CONFIG_ARCH_OMAP1
955 case METHOD_MPUIO:
956 reg += OMAP_MPUIO_GPIO_MASKIT;
957 mask = 0xffff;
958 inv = 1;
959 break;
960 #endif
961 #ifdef CONFIG_ARCH_OMAP15XX
962 case METHOD_GPIO_1510:
963 reg += OMAP1510_GPIO_INT_MASK;
964 mask = 0xffff;
965 inv = 1;
966 break;
967 #endif
968 #ifdef CONFIG_ARCH_OMAP16XX
969 case METHOD_GPIO_1610:
970 reg += OMAP1610_GPIO_IRQENABLE1;
971 mask = 0xffff;
972 break;
973 #endif
974 #ifdef CONFIG_ARCH_OMAP730
975 case METHOD_GPIO_730:
976 reg += OMAP730_GPIO_INT_MASK;
977 mask = 0xffffffff;
978 inv = 1;
979 break;
980 #endif
981 #ifdef CONFIG_ARCH_OMAP850
982 case METHOD_GPIO_850:
983 reg += OMAP850_GPIO_INT_MASK;
984 mask = 0xffffffff;
985 inv = 1;
986 break;
987 #endif
988 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
989 case METHOD_GPIO_24XX:
990 reg += OMAP24XX_GPIO_IRQENABLE1;
991 mask = 0xffffffff;
992 break;
993 #endif
994 #if defined(CONFIG_ARCH_OMAP4)
995 case METHOD_GPIO_24XX:
996 reg += OMAP4_GPIO_IRQSTATUSSET0;
997 mask = 0xffffffff;
998 break;
999 #endif
1000 default:
1001 WARN_ON(1);
1002 return 0;
1003 }
1004
1005 l = __raw_readl(reg);
1006 if (inv)
1007 l = ~l;
1008 l &= mask;
1009 return l;
1010 }
1011
1012 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1013 {
1014 void __iomem *reg = bank->base;
1015 u32 l;
1016
1017 switch (bank->method) {
1018 #ifdef CONFIG_ARCH_OMAP1
1019 case METHOD_MPUIO:
1020 reg += OMAP_MPUIO_GPIO_MASKIT;
1021 l = __raw_readl(reg);
1022 if (enable)
1023 l &= ~(gpio_mask);
1024 else
1025 l |= gpio_mask;
1026 break;
1027 #endif
1028 #ifdef CONFIG_ARCH_OMAP15XX
1029 case METHOD_GPIO_1510:
1030 reg += OMAP1510_GPIO_INT_MASK;
1031 l = __raw_readl(reg);
1032 if (enable)
1033 l &= ~(gpio_mask);
1034 else
1035 l |= gpio_mask;
1036 break;
1037 #endif
1038 #ifdef CONFIG_ARCH_OMAP16XX
1039 case METHOD_GPIO_1610:
1040 if (enable)
1041 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1042 else
1043 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1044 l = gpio_mask;
1045 break;
1046 #endif
1047 #ifdef CONFIG_ARCH_OMAP730
1048 case METHOD_GPIO_730:
1049 reg += OMAP730_GPIO_INT_MASK;
1050 l = __raw_readl(reg);
1051 if (enable)
1052 l &= ~(gpio_mask);
1053 else
1054 l |= gpio_mask;
1055 break;
1056 #endif
1057 #ifdef CONFIG_ARCH_OMAP850
1058 case METHOD_GPIO_850:
1059 reg += OMAP850_GPIO_INT_MASK;
1060 l = __raw_readl(reg);
1061 if (enable)
1062 l &= ~(gpio_mask);
1063 else
1064 l |= gpio_mask;
1065 break;
1066 #endif
1067 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1068 case METHOD_GPIO_24XX:
1069 if (enable)
1070 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1071 else
1072 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1073 l = gpio_mask;
1074 break;
1075 #endif
1076 #ifdef CONFIG_ARCH_OMAP4
1077 case METHOD_GPIO_24XX:
1078 if (enable)
1079 reg += OMAP4_GPIO_IRQSTATUSSET0;
1080 else
1081 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1082 l = gpio_mask;
1083 break;
1084 #endif
1085 default:
1086 WARN_ON(1);
1087 return;
1088 }
1089 __raw_writel(l, reg);
1090 }
1091
1092 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1093 {
1094 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1095 }
1096
1097 /*
1098 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1099 * 1510 does not seem to have a wake-up register. If JTAG is connected
1100 * to the target, system will wake up always on GPIO events. While
1101 * system is running all registered GPIO interrupts need to have wake-up
1102 * enabled. When system is suspended, only selected GPIO interrupts need
1103 * to have wake-up enabled.
1104 */
1105 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1106 {
1107 unsigned long flags;
1108
1109 switch (bank->method) {
1110 #ifdef CONFIG_ARCH_OMAP16XX
1111 case METHOD_MPUIO:
1112 case METHOD_GPIO_1610:
1113 spin_lock_irqsave(&bank->lock, flags);
1114 if (enable)
1115 bank->suspend_wakeup |= (1 << gpio);
1116 else
1117 bank->suspend_wakeup &= ~(1 << gpio);
1118 spin_unlock_irqrestore(&bank->lock, flags);
1119 return 0;
1120 #endif
1121 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1122 defined(CONFIG_ARCH_OMAP4)
1123 case METHOD_GPIO_24XX:
1124 if (bank->non_wakeup_gpios & (1 << gpio)) {
1125 printk(KERN_ERR "Unable to modify wakeup on "
1126 "non-wakeup GPIO%d\n",
1127 (bank - gpio_bank) * 32 + gpio);
1128 return -EINVAL;
1129 }
1130 spin_lock_irqsave(&bank->lock, flags);
1131 if (enable)
1132 bank->suspend_wakeup |= (1 << gpio);
1133 else
1134 bank->suspend_wakeup &= ~(1 << gpio);
1135 spin_unlock_irqrestore(&bank->lock, flags);
1136 return 0;
1137 #endif
1138 default:
1139 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1140 bank->method);
1141 return -EINVAL;
1142 }
1143 }
1144
1145 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1146 {
1147 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1148 _set_gpio_irqenable(bank, gpio, 0);
1149 _clear_gpio_irqstatus(bank, gpio);
1150 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1151 }
1152
1153 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1154 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1155 {
1156 unsigned int gpio = irq - IH_GPIO_BASE;
1157 struct gpio_bank *bank;
1158 int retval;
1159
1160 if (check_gpio(gpio) < 0)
1161 return -ENODEV;
1162 bank = get_irq_chip_data(irq);
1163 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1164
1165 return retval;
1166 }
1167
1168 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1169 {
1170 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1171 unsigned long flags;
1172
1173 spin_lock_irqsave(&bank->lock, flags);
1174
1175 /* Set trigger to none. You need to enable the desired trigger with
1176 * request_irq() or set_irq_type().
1177 */
1178 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1179
1180 #ifdef CONFIG_ARCH_OMAP15XX
1181 if (bank->method == METHOD_GPIO_1510) {
1182 void __iomem *reg;
1183
1184 /* Claim the pin for MPU */
1185 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1186 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1187 }
1188 #endif
1189 spin_unlock_irqrestore(&bank->lock, flags);
1190
1191 return 0;
1192 }
1193
1194 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1195 {
1196 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&bank->lock, flags);
1200 #ifdef CONFIG_ARCH_OMAP16XX
1201 if (bank->method == METHOD_GPIO_1610) {
1202 /* Disable wake-up during idle for dynamic tick */
1203 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1204 __raw_writel(1 << offset, reg);
1205 }
1206 #endif
1207 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1208 defined(CONFIG_ARCH_OMAP4)
1209 if (bank->method == METHOD_GPIO_24XX) {
1210 /* Disable wake-up during idle for dynamic tick */
1211 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1212 __raw_writel(1 << offset, reg);
1213 }
1214 #endif
1215 _reset_gpio(bank, bank->chip.base + offset);
1216 spin_unlock_irqrestore(&bank->lock, flags);
1217 }
1218
1219 /*
1220 * We need to unmask the GPIO bank interrupt as soon as possible to
1221 * avoid missing GPIO interrupts for other lines in the bank.
1222 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1223 * in the bank to avoid missing nested interrupts for a GPIO line.
1224 * If we wait to unmask individual GPIO lines in the bank after the
1225 * line's interrupt handler has been run, we may miss some nested
1226 * interrupts.
1227 */
1228 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1229 {
1230 void __iomem *isr_reg = NULL;
1231 u32 isr;
1232 unsigned int gpio_irq;
1233 struct gpio_bank *bank;
1234 u32 retrigger = 0;
1235 int unmasked = 0;
1236
1237 desc->chip->ack(irq);
1238
1239 bank = get_irq_data(irq);
1240 #ifdef CONFIG_ARCH_OMAP1
1241 if (bank->method == METHOD_MPUIO)
1242 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1243 #endif
1244 #ifdef CONFIG_ARCH_OMAP15XX
1245 if (bank->method == METHOD_GPIO_1510)
1246 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1247 #endif
1248 #if defined(CONFIG_ARCH_OMAP16XX)
1249 if (bank->method == METHOD_GPIO_1610)
1250 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1251 #endif
1252 #ifdef CONFIG_ARCH_OMAP730
1253 if (bank->method == METHOD_GPIO_730)
1254 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1255 #endif
1256 #ifdef CONFIG_ARCH_OMAP850
1257 if (bank->method == METHOD_GPIO_850)
1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1259 #endif
1260 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1261 if (bank->method == METHOD_GPIO_24XX)
1262 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1263 #endif
1264 #if defined(CONFIG_ARCH_OMAP4)
1265 if (bank->method == METHOD_GPIO_24XX)
1266 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1267 #endif
1268 while(1) {
1269 u32 isr_saved, level_mask = 0;
1270 u32 enabled;
1271
1272 enabled = _get_gpio_irqbank_mask(bank);
1273 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1274
1275 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1276 isr &= 0x0000ffff;
1277
1278 if (cpu_class_is_omap2()) {
1279 level_mask = bank->level_mask & enabled;
1280 }
1281
1282 /* clear edge sensitive interrupts before handler(s) are
1283 called so that we don't miss any interrupt occurred while
1284 executing them */
1285 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1286 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1287 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1288
1289 /* if there is only edge sensitive GPIO pin interrupts
1290 configured, we could unmask GPIO bank interrupt immediately */
1291 if (!level_mask && !unmasked) {
1292 unmasked = 1;
1293 desc->chip->unmask(irq);
1294 }
1295
1296 isr |= retrigger;
1297 retrigger = 0;
1298 if (!isr)
1299 break;
1300
1301 gpio_irq = bank->virtual_irq_start;
1302 for (; isr != 0; isr >>= 1, gpio_irq++) {
1303 if (!(isr & 1))
1304 continue;
1305
1306 generic_handle_irq(gpio_irq);
1307 }
1308 }
1309 /* if bank has any level sensitive GPIO pin interrupt
1310 configured, we must unmask the bank interrupt only after
1311 handler(s) are executed in order to avoid spurious bank
1312 interrupt */
1313 if (!unmasked)
1314 desc->chip->unmask(irq);
1315
1316 }
1317
1318 static void gpio_irq_shutdown(unsigned int irq)
1319 {
1320 unsigned int gpio = irq - IH_GPIO_BASE;
1321 struct gpio_bank *bank = get_irq_chip_data(irq);
1322
1323 _reset_gpio(bank, gpio);
1324 }
1325
1326 static void gpio_ack_irq(unsigned int irq)
1327 {
1328 unsigned int gpio = irq - IH_GPIO_BASE;
1329 struct gpio_bank *bank = get_irq_chip_data(irq);
1330
1331 _clear_gpio_irqstatus(bank, gpio);
1332 }
1333
1334 static void gpio_mask_irq(unsigned int irq)
1335 {
1336 unsigned int gpio = irq - IH_GPIO_BASE;
1337 struct gpio_bank *bank = get_irq_chip_data(irq);
1338
1339 _set_gpio_irqenable(bank, gpio, 0);
1340 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1341 }
1342
1343 static void gpio_unmask_irq(unsigned int irq)
1344 {
1345 unsigned int gpio = irq - IH_GPIO_BASE;
1346 struct gpio_bank *bank = get_irq_chip_data(irq);
1347 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1348 struct irq_desc *desc = irq_to_desc(irq);
1349 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1350
1351 if (trigger)
1352 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1353
1354 /* For level-triggered GPIOs, the clearing must be done after
1355 * the HW source is cleared, thus after the handler has run */
1356 if (bank->level_mask & irq_mask) {
1357 _set_gpio_irqenable(bank, gpio, 0);
1358 _clear_gpio_irqstatus(bank, gpio);
1359 }
1360
1361 _set_gpio_irqenable(bank, gpio, 1);
1362 }
1363
1364 static struct irq_chip gpio_irq_chip = {
1365 .name = "GPIO",
1366 .shutdown = gpio_irq_shutdown,
1367 .ack = gpio_ack_irq,
1368 .mask = gpio_mask_irq,
1369 .unmask = gpio_unmask_irq,
1370 .set_type = gpio_irq_type,
1371 .set_wake = gpio_wake_enable,
1372 };
1373
1374 /*---------------------------------------------------------------------*/
1375
1376 #ifdef CONFIG_ARCH_OMAP1
1377
1378 /* MPUIO uses the always-on 32k clock */
1379
1380 static void mpuio_ack_irq(unsigned int irq)
1381 {
1382 /* The ISR is reset automatically, so do nothing here. */
1383 }
1384
1385 static void mpuio_mask_irq(unsigned int irq)
1386 {
1387 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1388 struct gpio_bank *bank = get_irq_chip_data(irq);
1389
1390 _set_gpio_irqenable(bank, gpio, 0);
1391 }
1392
1393 static void mpuio_unmask_irq(unsigned int irq)
1394 {
1395 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1396 struct gpio_bank *bank = get_irq_chip_data(irq);
1397
1398 _set_gpio_irqenable(bank, gpio, 1);
1399 }
1400
1401 static struct irq_chip mpuio_irq_chip = {
1402 .name = "MPUIO",
1403 .ack = mpuio_ack_irq,
1404 .mask = mpuio_mask_irq,
1405 .unmask = mpuio_unmask_irq,
1406 .set_type = gpio_irq_type,
1407 #ifdef CONFIG_ARCH_OMAP16XX
1408 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1409 .set_wake = gpio_wake_enable,
1410 #endif
1411 };
1412
1413
1414 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1415
1416
1417 #ifdef CONFIG_ARCH_OMAP16XX
1418
1419 #include <linux/platform_device.h>
1420
1421 static int omap_mpuio_suspend_noirq(struct device *dev)
1422 {
1423 struct platform_device *pdev = to_platform_device(dev);
1424 struct gpio_bank *bank = platform_get_drvdata(pdev);
1425 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1426 unsigned long flags;
1427
1428 spin_lock_irqsave(&bank->lock, flags);
1429 bank->saved_wakeup = __raw_readl(mask_reg);
1430 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1431 spin_unlock_irqrestore(&bank->lock, flags);
1432
1433 return 0;
1434 }
1435
1436 static int omap_mpuio_resume_noirq(struct device *dev)
1437 {
1438 struct platform_device *pdev = to_platform_device(dev);
1439 struct gpio_bank *bank = platform_get_drvdata(pdev);
1440 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1441 unsigned long flags;
1442
1443 spin_lock_irqsave(&bank->lock, flags);
1444 __raw_writel(bank->saved_wakeup, mask_reg);
1445 spin_unlock_irqrestore(&bank->lock, flags);
1446
1447 return 0;
1448 }
1449
1450 static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1451 .suspend_noirq = omap_mpuio_suspend_noirq,
1452 .resume_noirq = omap_mpuio_resume_noirq,
1453 };
1454
1455 /* use platform_driver for this, now that there's no longer any
1456 * point to sys_device (other than not disturbing old code).
1457 */
1458 static struct platform_driver omap_mpuio_driver = {
1459 .driver = {
1460 .name = "mpuio",
1461 .pm = &omap_mpuio_dev_pm_ops,
1462 },
1463 };
1464
1465 static struct platform_device omap_mpuio_device = {
1466 .name = "mpuio",
1467 .id = -1,
1468 .dev = {
1469 .driver = &omap_mpuio_driver.driver,
1470 }
1471 /* could list the /proc/iomem resources */
1472 };
1473
1474 static inline void mpuio_init(void)
1475 {
1476 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1477
1478 if (platform_driver_register(&omap_mpuio_driver) == 0)
1479 (void) platform_device_register(&omap_mpuio_device);
1480 }
1481
1482 #else
1483 static inline void mpuio_init(void) {}
1484 #endif /* 16xx */
1485
1486 #else
1487
1488 extern struct irq_chip mpuio_irq_chip;
1489
1490 #define bank_is_mpuio(bank) 0
1491 static inline void mpuio_init(void) {}
1492
1493 #endif
1494
1495 /*---------------------------------------------------------------------*/
1496
1497 /* REVISIT these are stupid implementations! replace by ones that
1498 * don't switch on METHOD_* and which mostly avoid spinlocks
1499 */
1500
1501 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1502 {
1503 struct gpio_bank *bank;
1504 unsigned long flags;
1505
1506 bank = container_of(chip, struct gpio_bank, chip);
1507 spin_lock_irqsave(&bank->lock, flags);
1508 _set_gpio_direction(bank, offset, 1);
1509 spin_unlock_irqrestore(&bank->lock, flags);
1510 return 0;
1511 }
1512
1513 static int gpio_is_input(struct gpio_bank *bank, int mask)
1514 {
1515 void __iomem *reg = bank->base;
1516
1517 switch (bank->method) {
1518 case METHOD_MPUIO:
1519 reg += OMAP_MPUIO_IO_CNTL;
1520 break;
1521 case METHOD_GPIO_1510:
1522 reg += OMAP1510_GPIO_DIR_CONTROL;
1523 break;
1524 case METHOD_GPIO_1610:
1525 reg += OMAP1610_GPIO_DIRECTION;
1526 break;
1527 case METHOD_GPIO_730:
1528 reg += OMAP730_GPIO_DIR_CONTROL;
1529 break;
1530 case METHOD_GPIO_850:
1531 reg += OMAP850_GPIO_DIR_CONTROL;
1532 break;
1533 case METHOD_GPIO_24XX:
1534 reg += OMAP24XX_GPIO_OE;
1535 break;
1536 }
1537 return __raw_readl(reg) & mask;
1538 }
1539
1540 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1541 {
1542 struct gpio_bank *bank;
1543 void __iomem *reg;
1544 int gpio;
1545 u32 mask;
1546
1547 gpio = chip->base + offset;
1548 bank = get_gpio_bank(gpio);
1549 reg = bank->base;
1550 mask = 1 << get_gpio_index(gpio);
1551
1552 if (gpio_is_input(bank, mask))
1553 return _get_gpio_datain(bank, gpio);
1554 else
1555 return _get_gpio_dataout(bank, gpio);
1556 }
1557
1558 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1559 {
1560 struct gpio_bank *bank;
1561 unsigned long flags;
1562
1563 bank = container_of(chip, struct gpio_bank, chip);
1564 spin_lock_irqsave(&bank->lock, flags);
1565 _set_gpio_dataout(bank, offset, value);
1566 _set_gpio_direction(bank, offset, 0);
1567 spin_unlock_irqrestore(&bank->lock, flags);
1568 return 0;
1569 }
1570
1571 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1572 {
1573 struct gpio_bank *bank;
1574 unsigned long flags;
1575
1576 bank = container_of(chip, struct gpio_bank, chip);
1577 spin_lock_irqsave(&bank->lock, flags);
1578 _set_gpio_dataout(bank, offset, value);
1579 spin_unlock_irqrestore(&bank->lock, flags);
1580 }
1581
1582 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1583 {
1584 struct gpio_bank *bank;
1585
1586 bank = container_of(chip, struct gpio_bank, chip);
1587 return bank->virtual_irq_start + offset;
1588 }
1589
1590 /*---------------------------------------------------------------------*/
1591
1592 static int initialized;
1593 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1594 static struct clk * gpio_ick;
1595 #endif
1596
1597 #if defined(CONFIG_ARCH_OMAP2)
1598 static struct clk * gpio_fck;
1599 #endif
1600
1601 #if defined(CONFIG_ARCH_OMAP2430)
1602 static struct clk * gpio5_ick;
1603 static struct clk * gpio5_fck;
1604 #endif
1605
1606 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1607 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1608 #endif
1609
1610 /* This lock class tells lockdep that GPIO irqs are in a different
1611 * category than their parents, so it won't report false recursion.
1612 */
1613 static struct lock_class_key gpio_lock_class;
1614
1615 static int __init _omap_gpio_init(void)
1616 {
1617 int i;
1618 int gpio = 0;
1619 struct gpio_bank *bank;
1620 char clk_name[11];
1621
1622 initialized = 1;
1623
1624 #if defined(CONFIG_ARCH_OMAP1)
1625 if (cpu_is_omap15xx()) {
1626 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1627 if (IS_ERR(gpio_ick))
1628 printk("Could not get arm_gpio_ck\n");
1629 else
1630 clk_enable(gpio_ick);
1631 }
1632 #endif
1633 #if defined(CONFIG_ARCH_OMAP2)
1634 if (cpu_class_is_omap2()) {
1635 gpio_ick = clk_get(NULL, "gpios_ick");
1636 if (IS_ERR(gpio_ick))
1637 printk("Could not get gpios_ick\n");
1638 else
1639 clk_enable(gpio_ick);
1640 gpio_fck = clk_get(NULL, "gpios_fck");
1641 if (IS_ERR(gpio_fck))
1642 printk("Could not get gpios_fck\n");
1643 else
1644 clk_enable(gpio_fck);
1645
1646 /*
1647 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1648 */
1649 #if defined(CONFIG_ARCH_OMAP2430)
1650 if (cpu_is_omap2430()) {
1651 gpio5_ick = clk_get(NULL, "gpio5_ick");
1652 if (IS_ERR(gpio5_ick))
1653 printk("Could not get gpio5_ick\n");
1654 else
1655 clk_enable(gpio5_ick);
1656 gpio5_fck = clk_get(NULL, "gpio5_fck");
1657 if (IS_ERR(gpio5_fck))
1658 printk("Could not get gpio5_fck\n");
1659 else
1660 clk_enable(gpio5_fck);
1661 }
1662 #endif
1663 }
1664 #endif
1665
1666 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1667 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1668 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1669 sprintf(clk_name, "gpio%d_ick", i + 1);
1670 gpio_iclks[i] = clk_get(NULL, clk_name);
1671 if (IS_ERR(gpio_iclks[i]))
1672 printk(KERN_ERR "Could not get %s\n", clk_name);
1673 else
1674 clk_enable(gpio_iclks[i]);
1675 }
1676 }
1677 #endif
1678
1679
1680 #ifdef CONFIG_ARCH_OMAP15XX
1681 if (cpu_is_omap15xx()) {
1682 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1683 gpio_bank_count = 2;
1684 gpio_bank = gpio_bank_1510;
1685 }
1686 #endif
1687 #if defined(CONFIG_ARCH_OMAP16XX)
1688 if (cpu_is_omap16xx()) {
1689 u32 rev;
1690
1691 gpio_bank_count = 5;
1692 gpio_bank = gpio_bank_1610;
1693 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1694 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1695 (rev >> 4) & 0x0f, rev & 0x0f);
1696 }
1697 #endif
1698 #ifdef CONFIG_ARCH_OMAP730
1699 if (cpu_is_omap730()) {
1700 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1701 gpio_bank_count = 7;
1702 gpio_bank = gpio_bank_730;
1703 }
1704 #endif
1705 #ifdef CONFIG_ARCH_OMAP850
1706 if (cpu_is_omap850()) {
1707 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1708 gpio_bank_count = 7;
1709 gpio_bank = gpio_bank_850;
1710 }
1711 #endif
1712
1713 #ifdef CONFIG_ARCH_OMAP24XX
1714 if (cpu_is_omap242x()) {
1715 int rev;
1716
1717 gpio_bank_count = 4;
1718 gpio_bank = gpio_bank_242x;
1719 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1720 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1721 (rev >> 4) & 0x0f, rev & 0x0f);
1722 }
1723 if (cpu_is_omap243x()) {
1724 int rev;
1725
1726 gpio_bank_count = 5;
1727 gpio_bank = gpio_bank_243x;
1728 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1729 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1730 (rev >> 4) & 0x0f, rev & 0x0f);
1731 }
1732 #endif
1733 #ifdef CONFIG_ARCH_OMAP34XX
1734 if (cpu_is_omap34xx()) {
1735 int rev;
1736
1737 gpio_bank_count = OMAP34XX_NR_GPIOS;
1738 gpio_bank = gpio_bank_34xx;
1739 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1740 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1741 (rev >> 4) & 0x0f, rev & 0x0f);
1742 }
1743 #endif
1744 #ifdef CONFIG_ARCH_OMAP4
1745 if (cpu_is_omap44xx()) {
1746 int rev;
1747
1748 gpio_bank_count = OMAP34XX_NR_GPIOS;
1749 gpio_bank = gpio_bank_44xx;
1750 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1751 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1752 (rev >> 4) & 0x0f, rev & 0x0f);
1753 }
1754 #endif
1755 for (i = 0; i < gpio_bank_count; i++) {
1756 int j, gpio_count = 16;
1757
1758 bank = &gpio_bank[i];
1759 spin_lock_init(&bank->lock);
1760 if (bank_is_mpuio(bank))
1761 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1762 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1763 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1764 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1765 }
1766 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1767 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1768 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1769 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1770 }
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1772 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1773 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1774
1775 gpio_count = 32; /* 730 has 32-bit GPIOs */
1776 }
1777
1778 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1779 defined(CONFIG_ARCH_OMAP4)
1780 if (bank->method == METHOD_GPIO_24XX) {
1781 static const u32 non_wakeup_gpios[] = {
1782 0xe203ffc0, 0x08700040
1783 };
1784 if (cpu_is_omap44xx()) {
1785 __raw_writel(0xffffffff, bank->base +
1786 OMAP4_GPIO_IRQSTATUSCLR0);
1787 __raw_writew(0x0015, bank->base +
1788 OMAP4_GPIO_SYSCONFIG);
1789 __raw_writel(0x00000000, bank->base +
1790 OMAP4_GPIO_DEBOUNCENABLE);
1791 /* Initialize interface clock ungated, module enabled */
1792 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1793 } else {
1794 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1795 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1796 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1797 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1798
1799 /* Initialize interface clock ungated, module enabled */
1800 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1801 }
1802 if (i < ARRAY_SIZE(non_wakeup_gpios))
1803 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1804 gpio_count = 32;
1805 }
1806 #endif
1807 /* REVISIT eventually switch from OMAP-specific gpio structs
1808 * over to the generic ones
1809 */
1810 bank->chip.request = omap_gpio_request;
1811 bank->chip.free = omap_gpio_free;
1812 bank->chip.direction_input = gpio_input;
1813 bank->chip.get = gpio_get;
1814 bank->chip.direction_output = gpio_output;
1815 bank->chip.set = gpio_set;
1816 bank->chip.to_irq = gpio_2irq;
1817 if (bank_is_mpuio(bank)) {
1818 bank->chip.label = "mpuio";
1819 #ifdef CONFIG_ARCH_OMAP16XX
1820 bank->chip.dev = &omap_mpuio_device.dev;
1821 #endif
1822 bank->chip.base = OMAP_MPUIO(0);
1823 } else {
1824 bank->chip.label = "gpio";
1825 bank->chip.base = gpio;
1826 gpio += gpio_count;
1827 }
1828 bank->chip.ngpio = gpio_count;
1829
1830 gpiochip_add(&bank->chip);
1831
1832 for (j = bank->virtual_irq_start;
1833 j < bank->virtual_irq_start + gpio_count; j++) {
1834 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1835 set_irq_chip_data(j, bank);
1836 if (bank_is_mpuio(bank))
1837 set_irq_chip(j, &mpuio_irq_chip);
1838 else
1839 set_irq_chip(j, &gpio_irq_chip);
1840 set_irq_handler(j, handle_simple_irq);
1841 set_irq_flags(j, IRQF_VALID);
1842 }
1843 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1844 set_irq_data(bank->irq, bank);
1845
1846 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1847 sprintf(clk_name, "gpio%d_dbck", i + 1);
1848 bank->dbck = clk_get(NULL, clk_name);
1849 if (IS_ERR(bank->dbck))
1850 printk(KERN_ERR "Could not get %s\n", clk_name);
1851 }
1852 }
1853
1854 /* Enable system clock for GPIO module.
1855 * The CAM_CLK_CTRL *is* really the right place. */
1856 if (cpu_is_omap16xx())
1857 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1858
1859 /* Enable autoidle for the OCP interface */
1860 if (cpu_is_omap24xx())
1861 omap_writel(1 << 0, 0x48019010);
1862 if (cpu_is_omap34xx())
1863 omap_writel(1 << 0, 0x48306814);
1864
1865 return 0;
1866 }
1867
1868 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1869 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1870 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1871 {
1872 int i;
1873
1874 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1875 return 0;
1876
1877 for (i = 0; i < gpio_bank_count; i++) {
1878 struct gpio_bank *bank = &gpio_bank[i];
1879 void __iomem *wake_status;
1880 void __iomem *wake_clear;
1881 void __iomem *wake_set;
1882 unsigned long flags;
1883
1884 switch (bank->method) {
1885 #ifdef CONFIG_ARCH_OMAP16XX
1886 case METHOD_GPIO_1610:
1887 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1888 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1889 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1890 break;
1891 #endif
1892 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1893 case METHOD_GPIO_24XX:
1894 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1895 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1896 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1897 break;
1898 #endif
1899 #ifdef CONFIG_ARCH_OMAP4
1900 case METHOD_GPIO_24XX:
1901 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1902 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1903 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1904 break;
1905 #endif
1906 default:
1907 continue;
1908 }
1909
1910 spin_lock_irqsave(&bank->lock, flags);
1911 bank->saved_wakeup = __raw_readl(wake_status);
1912 __raw_writel(0xffffffff, wake_clear);
1913 __raw_writel(bank->suspend_wakeup, wake_set);
1914 spin_unlock_irqrestore(&bank->lock, flags);
1915 }
1916
1917 return 0;
1918 }
1919
1920 static int omap_gpio_resume(struct sys_device *dev)
1921 {
1922 int i;
1923
1924 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1925 return 0;
1926
1927 for (i = 0; i < gpio_bank_count; i++) {
1928 struct gpio_bank *bank = &gpio_bank[i];
1929 void __iomem *wake_clear;
1930 void __iomem *wake_set;
1931 unsigned long flags;
1932
1933 switch (bank->method) {
1934 #ifdef CONFIG_ARCH_OMAP16XX
1935 case METHOD_GPIO_1610:
1936 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1937 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1938 break;
1939 #endif
1940 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1941 case METHOD_GPIO_24XX:
1942 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1943 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1944 break;
1945 #endif
1946 #ifdef CONFIG_ARCH_OMAP4
1947 case METHOD_GPIO_24XX:
1948 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1949 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1950 break;
1951 #endif
1952 default:
1953 continue;
1954 }
1955
1956 spin_lock_irqsave(&bank->lock, flags);
1957 __raw_writel(0xffffffff, wake_clear);
1958 __raw_writel(bank->saved_wakeup, wake_set);
1959 spin_unlock_irqrestore(&bank->lock, flags);
1960 }
1961
1962 return 0;
1963 }
1964
1965 static struct sysdev_class omap_gpio_sysclass = {
1966 .name = "gpio",
1967 .suspend = omap_gpio_suspend,
1968 .resume = omap_gpio_resume,
1969 };
1970
1971 static struct sys_device omap_gpio_device = {
1972 .id = 0,
1973 .cls = &omap_gpio_sysclass,
1974 };
1975
1976 #endif
1977
1978 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1979 defined(CONFIG_ARCH_OMAP4)
1980
1981 static int workaround_enabled;
1982
1983 void omap2_gpio_prepare_for_retention(void)
1984 {
1985 int i, c = 0;
1986
1987 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1988 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1989 for (i = 0; i < gpio_bank_count; i++) {
1990 struct gpio_bank *bank = &gpio_bank[i];
1991 u32 l1, l2;
1992
1993 if (!(bank->enabled_non_wakeup_gpios))
1994 continue;
1995 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1996 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1997 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1998 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1999 #endif
2000 #ifdef CONFIG_ARCH_OMAP4
2001 bank->saved_datain = __raw_readl(bank->base +
2002 OMAP4_GPIO_DATAIN);
2003 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
2004 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2005 #endif
2006 bank->saved_fallingdetect = l1;
2007 bank->saved_risingdetect = l2;
2008 l1 &= ~bank->enabled_non_wakeup_gpios;
2009 l2 &= ~bank->enabled_non_wakeup_gpios;
2010 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2011 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2012 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
2013 #endif
2014 #ifdef CONFIG_ARCH_OMAP4
2015 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2016 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2017 #endif
2018 c++;
2019 }
2020 if (!c) {
2021 workaround_enabled = 0;
2022 return;
2023 }
2024 workaround_enabled = 1;
2025 }
2026
2027 void omap2_gpio_resume_after_retention(void)
2028 {
2029 int i;
2030
2031 if (!workaround_enabled)
2032 return;
2033 for (i = 0; i < gpio_bank_count; i++) {
2034 struct gpio_bank *bank = &gpio_bank[i];
2035 u32 l, gen, gen0, gen1;
2036
2037 if (!(bank->enabled_non_wakeup_gpios))
2038 continue;
2039 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2040 __raw_writel(bank->saved_fallingdetect,
2041 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2042 __raw_writel(bank->saved_risingdetect,
2043 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2044 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2045 #endif
2046 #ifdef CONFIG_ARCH_OMAP4
2047 __raw_writel(bank->saved_fallingdetect,
2048 bank->base + OMAP4_GPIO_FALLINGDETECT);
2049 __raw_writel(bank->saved_risingdetect,
2050 bank->base + OMAP4_GPIO_RISINGDETECT);
2051 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2052 #endif
2053 /* Check if any of the non-wakeup interrupt GPIOs have changed
2054 * state. If so, generate an IRQ by software. This is
2055 * horribly racy, but it's the best we can do to work around
2056 * this silicon bug. */
2057 l ^= bank->saved_datain;
2058 l &= bank->non_wakeup_gpios;
2059
2060 /*
2061 * No need to generate IRQs for the rising edge for gpio IRQs
2062 * configured with falling edge only; and vice versa.
2063 */
2064 gen0 = l & bank->saved_fallingdetect;
2065 gen0 &= bank->saved_datain;
2066
2067 gen1 = l & bank->saved_risingdetect;
2068 gen1 &= ~(bank->saved_datain);
2069
2070 /* FIXME: Consider GPIO IRQs with level detections properly! */
2071 gen = l & (~(bank->saved_fallingdetect) &
2072 ~(bank->saved_risingdetect));
2073 /* Consider all GPIO IRQs needed to be updated */
2074 gen |= gen0 | gen1;
2075
2076 if (gen) {
2077 u32 old0, old1;
2078 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2079 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2080 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2081 __raw_writel(old0 | gen, bank->base +
2082 OMAP24XX_GPIO_LEVELDETECT0);
2083 __raw_writel(old1 | gen, bank->base +
2084 OMAP24XX_GPIO_LEVELDETECT1);
2085 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2086 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2087 #endif
2088 #ifdef CONFIG_ARCH_OMAP4
2089 old0 = __raw_readl(bank->base +
2090 OMAP4_GPIO_LEVELDETECT0);
2091 old1 = __raw_readl(bank->base +
2092 OMAP4_GPIO_LEVELDETECT1);
2093 __raw_writel(old0 | l, bank->base +
2094 OMAP4_GPIO_LEVELDETECT0);
2095 __raw_writel(old1 | l, bank->base +
2096 OMAP4_GPIO_LEVELDETECT1);
2097 __raw_writel(old0, bank->base +
2098 OMAP4_GPIO_LEVELDETECT0);
2099 __raw_writel(old1, bank->base +
2100 OMAP4_GPIO_LEVELDETECT1);
2101 #endif
2102 }
2103 }
2104
2105 }
2106
2107 #endif
2108
2109 /*
2110 * This may get called early from board specific init
2111 * for boards that have interrupts routed via FPGA.
2112 */
2113 int __init omap_gpio_init(void)
2114 {
2115 if (!initialized)
2116 return _omap_gpio_init();
2117 else
2118 return 0;
2119 }
2120
2121 static int __init omap_gpio_sysinit(void)
2122 {
2123 int ret = 0;
2124
2125 if (!initialized)
2126 ret = _omap_gpio_init();
2127
2128 mpuio_init();
2129
2130 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2131 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2132 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2133 if (ret == 0) {
2134 ret = sysdev_class_register(&omap_gpio_sysclass);
2135 if (ret == 0)
2136 ret = sysdev_register(&omap_gpio_device);
2137 }
2138 }
2139 #endif
2140
2141 return ret;
2142 }
2143
2144 arch_initcall(omap_gpio_sysinit);
2145
2146
2147 #ifdef CONFIG_DEBUG_FS
2148
2149 #include <linux/debugfs.h>
2150 #include <linux/seq_file.h>
2151
2152 static int dbg_gpio_show(struct seq_file *s, void *unused)
2153 {
2154 unsigned i, j, gpio;
2155
2156 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2157 struct gpio_bank *bank = gpio_bank + i;
2158 unsigned bankwidth = 16;
2159 u32 mask = 1;
2160
2161 if (bank_is_mpuio(bank))
2162 gpio = OMAP_MPUIO(0);
2163 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
2164 cpu_is_omap850())
2165 bankwidth = 32;
2166
2167 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2168 unsigned irq, value, is_in, irqstat;
2169 const char *label;
2170
2171 label = gpiochip_is_requested(&bank->chip, j);
2172 if (!label)
2173 continue;
2174
2175 irq = bank->virtual_irq_start + j;
2176 value = gpio_get_value(gpio);
2177 is_in = gpio_is_input(bank, mask);
2178
2179 if (bank_is_mpuio(bank))
2180 seq_printf(s, "MPUIO %2d ", j);
2181 else
2182 seq_printf(s, "GPIO %3d ", gpio);
2183 seq_printf(s, "(%-20.20s): %s %s",
2184 label,
2185 is_in ? "in " : "out",
2186 value ? "hi" : "lo");
2187
2188 /* FIXME for at least omap2, show pullup/pulldown state */
2189
2190 irqstat = irq_desc[irq].status;
2191 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2192 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2193 if (is_in && ((bank->suspend_wakeup & mask)
2194 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2195 char *trigger = NULL;
2196
2197 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2198 case IRQ_TYPE_EDGE_FALLING:
2199 trigger = "falling";
2200 break;
2201 case IRQ_TYPE_EDGE_RISING:
2202 trigger = "rising";
2203 break;
2204 case IRQ_TYPE_EDGE_BOTH:
2205 trigger = "bothedge";
2206 break;
2207 case IRQ_TYPE_LEVEL_LOW:
2208 trigger = "low";
2209 break;
2210 case IRQ_TYPE_LEVEL_HIGH:
2211 trigger = "high";
2212 break;
2213 case IRQ_TYPE_NONE:
2214 trigger = "(?)";
2215 break;
2216 }
2217 seq_printf(s, ", irq-%d %-8s%s",
2218 irq, trigger,
2219 (bank->suspend_wakeup & mask)
2220 ? " wakeup" : "");
2221 }
2222 #endif
2223 seq_printf(s, "\n");
2224 }
2225
2226 if (bank_is_mpuio(bank)) {
2227 seq_printf(s, "\n");
2228 gpio = 0;
2229 }
2230 }
2231 return 0;
2232 }
2233
2234 static int dbg_gpio_open(struct inode *inode, struct file *file)
2235 {
2236 return single_open(file, dbg_gpio_show, &inode->i_private);
2237 }
2238
2239 static const struct file_operations debug_fops = {
2240 .open = dbg_gpio_open,
2241 .read = seq_read,
2242 .llseek = seq_lseek,
2243 .release = single_release,
2244 };
2245
2246 static int __init omap_gpio_debuginit(void)
2247 {
2248 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2249 NULL, NULL, &debug_fops);
2250 return 0;
2251 }
2252 late_initcall(omap_gpio_debuginit);
2253 #endif
CJK support for tty framebuffer vt