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IB/mlx4: Handle new FW requirement for send request prefetching
[linux-2.6/cjktty.git] / drivers / net / mlx4 / fw.c
blob81fc546a1c44011a4c47bbcbd7ccc6f899dbbe48
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36
37 #include "fw.h"
38 #include "icm.h"
39
40 enum {
41 MLX4_COMMAND_INTERFACE_REV = 2,
42 };
43
44 extern void __buggy_use_of_MLX4_GET(void);
45 extern void __buggy_use_of_MLX4_PUT(void);
46
47 #define MLX4_GET(dest, source, offset) \
48 do { \
49 void *__p = (char *) (source) + (offset); \
50 switch (sizeof (dest)) { \
51 case 1: (dest) = *(u8 *) __p; break; \
52 case 2: (dest) = be16_to_cpup(__p); break; \
53 case 4: (dest) = be32_to_cpup(__p); break; \
54 case 8: (dest) = be64_to_cpup(__p); break; \
55 default: __buggy_use_of_MLX4_GET(); \
56 } \
57 } while (0)
58
59 #define MLX4_PUT(dest, source, offset) \
60 do { \
61 void *__d = ((char *) (dest) + (offset)); \
62 switch (sizeof(source)) { \
63 case 1: *(u8 *) __d = (source); break; \
64 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
65 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
66 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
67 default: __buggy_use_of_MLX4_PUT(); \
68 } \
69 } while (0)
70
71 static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
72 {
73 static const char *fname[] = {
74 [ 0] = "RC transport",
75 [ 1] = "UC transport",
76 [ 2] = "UD transport",
77 [ 3] = "SRC transport",
78 [ 4] = "reliable multicast",
79 [ 5] = "FCoIB support",
80 [ 6] = "SRQ support",
81 [ 7] = "IPoIB checksum offload",
82 [ 8] = "P_Key violation counter",
83 [ 9] = "Q_Key violation counter",
84 [10] = "VMM",
85 [16] = "MW support",
86 [17] = "APM support",
87 [18] = "Atomic ops support",
88 [19] = "Raw multicast support",
89 [20] = "Address vector port checking support",
90 [21] = "UD multicast support",
91 [24] = "Demand paging support",
92 [25] = "Router support"
93 };
94 int i;
95
96 mlx4_dbg(dev, "DEV_CAP flags:\n");
97 for (i = 0; i < ARRAY_SIZE(fname); ++i)
98 if (fname[i] && (flags & (1 << i)))
99 mlx4_dbg(dev, " %s\n", fname[i]);
100 }
101
102 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
103 {
104 struct mlx4_cmd_mailbox *mailbox;
105 u32 *outbox;
106 u8 field;
107 u16 size;
108 u16 stat_rate;
109 int err;
110
111 #define QUERY_DEV_CAP_OUT_SIZE 0x100
112 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
113 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
114 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
115 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
116 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
117 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
118 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
119 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
120 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
121 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
122 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
123 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
124 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
125 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
126 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
127 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
128 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
129 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
130 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
131 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
132 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
133 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
134 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
135 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
136 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
137 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
138 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
139 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
140 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
141 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
142 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
143 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
144 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
145 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
146 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
147 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
148 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
149 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
150 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
151 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
152 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
153 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
154 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
155 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
156 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
157 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
158 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
159 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
160 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
161 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
162 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
163 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
164 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
165 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
166 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
167 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
168 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x97
169 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
170 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
171
172 mailbox = mlx4_alloc_cmd_mailbox(dev);
173 if (IS_ERR(mailbox))
174 return PTR_ERR(mailbox);
175 outbox = mailbox->buf;
176
177 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
178 MLX4_CMD_TIME_CLASS_A);
179
180 if (err)
181 goto out;
182
183 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
184 dev_cap->reserved_qps = 1 << (field & 0xf);
185 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
186 dev_cap->max_qps = 1 << (field & 0x1f);
187 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
188 dev_cap->reserved_srqs = 1 << (field >> 4);
189 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
190 dev_cap->max_srqs = 1 << (field & 0x1f);
191 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
192 dev_cap->max_cq_sz = 1 << field;
193 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
194 dev_cap->reserved_cqs = 1 << (field & 0xf);
195 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
196 dev_cap->max_cqs = 1 << (field & 0x1f);
197 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
198 dev_cap->max_mpts = 1 << (field & 0x3f);
199 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
200 dev_cap->reserved_eqs = 1 << (field & 0xf);
201 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
202 dev_cap->max_eqs = 1 << (field & 0x7);
203 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
204 dev_cap->reserved_mtts = 1 << (field >> 4);
205 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
206 dev_cap->max_mrw_sz = 1 << field;
207 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
208 dev_cap->reserved_mrws = 1 << (field & 0xf);
209 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
210 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
211 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
212 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
213 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
214 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
215 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
216 dev_cap->max_rdma_global = 1 << (field & 0x3f);
217 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
218 dev_cap->local_ca_ack_delay = field & 0x1f;
219 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
220 dev_cap->max_mtu = field >> 4;
221 dev_cap->max_port_width = field & 0xf;
222 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
223 dev_cap->max_vl = field >> 4;
224 dev_cap->num_ports = field & 0xf;
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
226 dev_cap->max_gids = 1 << (field & 0xf);
227 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
228 dev_cap->stat_rate_support = stat_rate;
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
230 dev_cap->max_pkeys = 1 << (field & 0xf);
231 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
232 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
233 dev_cap->reserved_uars = field >> 4;
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
235 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
237 dev_cap->min_page_sz = 1 << field;
238
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
240 if (field & 0x80) {
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
242 dev_cap->bf_reg_size = 1 << (field & 0x1f);
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
244 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
245 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
246 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
247 } else {
248 dev_cap->bf_reg_size = 0;
249 mlx4_dbg(dev, "BlueFlame not available\n");
250 }
251
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
253 dev_cap->max_sq_sg = field;
254 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
255 dev_cap->max_sq_desc_sz = size;
256
257 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
258 dev_cap->max_qp_per_mcg = 1 << field;
259 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
260 dev_cap->reserved_mgms = field & 0xf;
261 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
262 dev_cap->max_mcgs = 1 << field;
263 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
264 dev_cap->reserved_pds = field >> 4;
265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
266 dev_cap->max_pds = 1 << (field & 0x3f);
267
268 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
269 dev_cap->rdmarc_entry_sz = size;
270 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
271 dev_cap->qpc_entry_sz = size;
272 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
273 dev_cap->aux_entry_sz = size;
274 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
275 dev_cap->altc_entry_sz = size;
276 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
277 dev_cap->eqc_entry_sz = size;
278 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
279 dev_cap->cqc_entry_sz = size;
280 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
281 dev_cap->srq_entry_sz = size;
282 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
283 dev_cap->cmpt_entry_sz = size;
284 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
285 dev_cap->mtt_entry_sz = size;
286 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
287 dev_cap->dmpt_entry_sz = size;
288
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
290 dev_cap->max_srq_sz = 1 << field;
291 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
292 dev_cap->max_qp_sz = 1 << field;
293 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
294 dev_cap->resize_srq = field & 1;
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
296 dev_cap->max_rq_sg = field;
297 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
298 dev_cap->max_rq_desc_sz = size;
299
300 MLX4_GET(dev_cap->bmme_flags, outbox,
301 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
302 MLX4_GET(dev_cap->reserved_lkey, outbox,
303 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
304 MLX4_GET(dev_cap->max_icm_sz, outbox,
305 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
306
307 if (dev_cap->bmme_flags & 1)
308 mlx4_dbg(dev, "Base MM extensions: yes "
309 "(flags %d, rsvd L_Key %08x)\n",
310 dev_cap->bmme_flags, dev_cap->reserved_lkey);
311 else
312 mlx4_dbg(dev, "Base MM extensions: no\n");
313
314 /*
315 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
316 * we can't use any EQs whose doorbell falls on that page,
317 * even if the EQ itself isn't reserved.
318 */
319 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
320 dev_cap->reserved_eqs);
321
322 mlx4_dbg(dev, "Max ICM size %lld MB\n",
323 (unsigned long long) dev_cap->max_icm_sz >> 20);
324 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
325 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
326 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
327 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
328 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
329 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
330 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
331 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
332 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
333 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
334 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
335 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
336 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
337 dev_cap->max_pds, dev_cap->reserved_mgms);
338 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
339 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
340 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
341 dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu,
342 dev_cap->max_port_width);
343 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
344 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
345 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
346 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
347
348 dump_dev_cap_flags(dev, dev_cap->flags);
349
350 out:
351 mlx4_free_cmd_mailbox(dev, mailbox);
352 return err;
353 }
354
355 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
356 {
357 struct mlx4_cmd_mailbox *mailbox;
358 struct mlx4_icm_iter iter;
359 __be64 *pages;
360 int lg;
361 int nent = 0;
362 int i;
363 int err = 0;
364 int ts = 0, tc = 0;
365
366 mailbox = mlx4_alloc_cmd_mailbox(dev);
367 if (IS_ERR(mailbox))
368 return PTR_ERR(mailbox);
369 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
370 pages = mailbox->buf;
371
372 for (mlx4_icm_first(icm, &iter);
373 !mlx4_icm_last(&iter);
374 mlx4_icm_next(&iter)) {
375 /*
376 * We have to pass pages that are aligned to their
377 * size, so find the least significant 1 in the
378 * address or size and use that as our log2 size.
379 */
380 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
381 if (lg < MLX4_ICM_PAGE_SHIFT) {
382 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
383 MLX4_ICM_PAGE_SIZE,
384 (unsigned long long) mlx4_icm_addr(&iter),
385 mlx4_icm_size(&iter));
386 err = -EINVAL;
387 goto out;
388 }
389
390 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
391 if (virt != -1) {
392 pages[nent * 2] = cpu_to_be64(virt);
393 virt += 1 << lg;
394 }
395
396 pages[nent * 2 + 1] =
397 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
398 (lg - MLX4_ICM_PAGE_SHIFT));
399 ts += 1 << (lg - 10);
400 ++tc;
401
402 if (++nent == MLX4_MAILBOX_SIZE / 16) {
403 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
404 MLX4_CMD_TIME_CLASS_B);
405 if (err)
406 goto out;
407 nent = 0;
408 }
409 }
410 }
411
412 if (nent)
413 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
414 if (err)
415 goto out;
416
417 switch (op) {
418 case MLX4_CMD_MAP_FA:
419 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
420 break;
421 case MLX4_CMD_MAP_ICM_AUX:
422 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
423 break;
424 case MLX4_CMD_MAP_ICM:
425 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
426 tc, ts, (unsigned long long) virt - (ts << 10));
427 break;
428 }
429
430 out:
431 mlx4_free_cmd_mailbox(dev, mailbox);
432 return err;
433 }
434
435 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
436 {
437 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
438 }
439
440 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
441 {
442 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
443 }
444
445
446 int mlx4_RUN_FW(struct mlx4_dev *dev)
447 {
448 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
449 }
450
451 int mlx4_QUERY_FW(struct mlx4_dev *dev)
452 {
453 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
454 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
455 struct mlx4_cmd_mailbox *mailbox;
456 u32 *outbox;
457 int err = 0;
458 u64 fw_ver;
459 u16 cmd_if_rev;
460 u8 lg;
461
462 #define QUERY_FW_OUT_SIZE 0x100
463 #define QUERY_FW_VER_OFFSET 0x00
464 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
465 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
466 #define QUERY_FW_ERR_START_OFFSET 0x30
467 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
468 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
469
470 #define QUERY_FW_SIZE_OFFSET 0x00
471 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
472 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
473
474 mailbox = mlx4_alloc_cmd_mailbox(dev);
475 if (IS_ERR(mailbox))
476 return PTR_ERR(mailbox);
477 outbox = mailbox->buf;
478
479 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
480 MLX4_CMD_TIME_CLASS_A);
481 if (err)
482 goto out;
483
484 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
485 /*
486 * FW subminor version is at more significant bits than minor
487 * version, so swap here.
488 */
489 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
490 ((fw_ver & 0xffff0000ull) >> 16) |
491 ((fw_ver & 0x0000ffffull) << 16);
492
493 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
494 if (cmd_if_rev != MLX4_COMMAND_INTERFACE_REV) {
495 mlx4_err(dev, "Installed FW has unsupported "
496 "command interface revision %d.\n",
497 cmd_if_rev);
498 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
499 (int) (dev->caps.fw_ver >> 32),
500 (int) (dev->caps.fw_ver >> 16) & 0xffff,
501 (int) dev->caps.fw_ver & 0xffff);
502 mlx4_err(dev, "This driver version supports only revision %d.\n",
503 MLX4_COMMAND_INTERFACE_REV);
504 err = -ENODEV;
505 goto out;
506 }
507
508 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
509 cmd->max_cmds = 1 << lg;
510
511 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
512 (int) (dev->caps.fw_ver >> 32),
513 (int) (dev->caps.fw_ver >> 16) & 0xffff,
514 (int) dev->caps.fw_ver & 0xffff,
515 cmd_if_rev, cmd->max_cmds);
516
517 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
518 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
519 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
520 fw->catas_bar = (fw->catas_bar >> 6) * 2;
521
522 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
523 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
524
525 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
526 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
527 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
528 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
529
530 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
531
532 /*
533 * Round up number of system pages needed in case
534 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
535 */
536 fw->fw_pages =
537 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
538 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
539
540 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
541 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
542
543 out:
544 mlx4_free_cmd_mailbox(dev, mailbox);
545 return err;
546 }
547
548 static void get_board_id(void *vsd, char *board_id)
549 {
550 int i;
551
552 #define VSD_OFFSET_SIG1 0x00
553 #define VSD_OFFSET_SIG2 0xde
554 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
555 #define VSD_OFFSET_TS_BOARD_ID 0x20
556
557 #define VSD_SIGNATURE_TOPSPIN 0x5ad
558
559 memset(board_id, 0, MLX4_BOARD_ID_LEN);
560
561 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
562 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
563 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
564 } else {
565 /*
566 * The board ID is a string but the firmware byte
567 * swaps each 4-byte word before passing it back to
568 * us. Therefore we need to swab it before printing.
569 */
570 for (i = 0; i < 4; ++i)
571 ((u32 *) board_id)[i] =
572 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
573 }
574 }
575
576 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
577 {
578 struct mlx4_cmd_mailbox *mailbox;
579 u32 *outbox;
580 int err;
581
582 #define QUERY_ADAPTER_OUT_SIZE 0x100
583 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
584 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
585 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
586 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
587 #define QUERY_ADAPTER_VSD_OFFSET 0x20
588
589 mailbox = mlx4_alloc_cmd_mailbox(dev);
590 if (IS_ERR(mailbox))
591 return PTR_ERR(mailbox);
592 outbox = mailbox->buf;
593
594 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
595 MLX4_CMD_TIME_CLASS_A);
596 if (err)
597 goto out;
598
599 MLX4_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
600 MLX4_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
601 MLX4_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
602 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
603
604 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
605 adapter->board_id);
606
607 out:
608 mlx4_free_cmd_mailbox(dev, mailbox);
609 return err;
610 }
611
612 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
613 {
614 struct mlx4_cmd_mailbox *mailbox;
615 __be32 *inbox;
616 int err;
617
618 #define INIT_HCA_IN_SIZE 0x200
619 #define INIT_HCA_VERSION_OFFSET 0x000
620 #define INIT_HCA_VERSION 2
621 #define INIT_HCA_FLAGS_OFFSET 0x014
622 #define INIT_HCA_QPC_OFFSET 0x020
623 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
624 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
625 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
626 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
627 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
628 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
629 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
630 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
631 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
632 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
633 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
634 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
635 #define INIT_HCA_MCAST_OFFSET 0x0c0
636 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
637 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
638 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
639 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
640 #define INIT_HCA_TPT_OFFSET 0x0f0
641 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
642 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
643 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
644 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
645 #define INIT_HCA_UAR_OFFSET 0x120
646 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
647 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
648
649 mailbox = mlx4_alloc_cmd_mailbox(dev);
650 if (IS_ERR(mailbox))
651 return PTR_ERR(mailbox);
652 inbox = mailbox->buf;
653
654 memset(inbox, 0, INIT_HCA_IN_SIZE);
655
656 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
657
658 #if defined(__LITTLE_ENDIAN)
659 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
660 #elif defined(__BIG_ENDIAN)
661 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
662 #else
663 #error Host endianness not defined
664 #endif
665 /* Check port for UD address vector: */
666 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
667
668 /* QPC/EEC/CQC/EQC/RDMARC attributes */
669
670 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
671 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
672 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
673 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
674 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
675 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
676 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
677 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
678 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
679 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
680 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
681 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
682
683 /* multicast attributes */
684
685 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
686 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
687 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
688 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
689
690 /* TPT attributes */
691
692 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
693 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
694 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
695 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
696
697 /* UAR attributes */
698
699 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
700 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
701
702 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1000);
703
704 if (err)
705 mlx4_err(dev, "INIT_HCA returns %d\n", err);
706
707 mlx4_free_cmd_mailbox(dev, mailbox);
708 return err;
709 }
710
711 int mlx4_INIT_PORT(struct mlx4_dev *dev, struct mlx4_init_port_param *param, int port)
712 {
713 struct mlx4_cmd_mailbox *mailbox;
714 u32 *inbox;
715 int err;
716 u32 flags;
717
718 #define INIT_PORT_IN_SIZE 256
719 #define INIT_PORT_FLAGS_OFFSET 0x00
720 #define INIT_PORT_FLAG_SIG (1 << 18)
721 #define INIT_PORT_FLAG_NG (1 << 17)
722 #define INIT_PORT_FLAG_G0 (1 << 16)
723 #define INIT_PORT_VL_SHIFT 4
724 #define INIT_PORT_PORT_WIDTH_SHIFT 8
725 #define INIT_PORT_MTU_OFFSET 0x04
726 #define INIT_PORT_MAX_GID_OFFSET 0x06
727 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
728 #define INIT_PORT_GUID0_OFFSET 0x10
729 #define INIT_PORT_NODE_GUID_OFFSET 0x18
730 #define INIT_PORT_SI_GUID_OFFSET 0x20
731
732 mailbox = mlx4_alloc_cmd_mailbox(dev);
733 if (IS_ERR(mailbox))
734 return PTR_ERR(mailbox);
735 inbox = mailbox->buf;
736
737 memset(inbox, 0, INIT_PORT_IN_SIZE);
738
739 flags = 0;
740 flags |= param->set_guid0 ? INIT_PORT_FLAG_G0 : 0;
741 flags |= param->set_node_guid ? INIT_PORT_FLAG_NG : 0;
742 flags |= param->set_si_guid ? INIT_PORT_FLAG_SIG : 0;
743 flags |= (param->vl_cap & 0xf) << INIT_PORT_VL_SHIFT;
744 flags |= (param->port_width_cap & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
745 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
746
747 MLX4_PUT(inbox, param->mtu, INIT_PORT_MTU_OFFSET);
748 MLX4_PUT(inbox, param->max_gid, INIT_PORT_MAX_GID_OFFSET);
749 MLX4_PUT(inbox, param->max_pkey, INIT_PORT_MAX_PKEY_OFFSET);
750 MLX4_PUT(inbox, param->guid0, INIT_PORT_GUID0_OFFSET);
751 MLX4_PUT(inbox, param->node_guid, INIT_PORT_NODE_GUID_OFFSET);
752 MLX4_PUT(inbox, param->si_guid, INIT_PORT_SI_GUID_OFFSET);
753
754 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
755 MLX4_CMD_TIME_CLASS_A);
756
757 mlx4_free_cmd_mailbox(dev, mailbox);
758
759 return err;
760 }
761 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
762
763 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
764 {
765 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
766 }
767 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
768
769 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
770 {
771 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
772 }
773
774 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
775 {
776 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
777 MLX4_CMD_SET_ICM_SIZE,
778 MLX4_CMD_TIME_CLASS_A);
779 if (ret)
780 return ret;
781
782 /*
783 * Round up number of system pages needed in case
784 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
785 */
786 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
787 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
788
789 return 0;
790 }
791
792 int mlx4_NOP(struct mlx4_dev *dev)
793 {
794 /* Input modifier of 0x1f means "finish as soon as possible." */
795 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
796 }
CJK support for tty framebuffer vt