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serial: Fix sh-sci break interrupt/sysrq handling.
[linux-2.6/cjktty.git] / drivers / serial / sh-sci.c
blob46c40bbc4bc6bc6c2972d30504d580fcca8bf8b2
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
37 #include <linux/mm.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42
43 #ifdef CONFIG_CPU_FREQ
44 #include <linux/notifier.h>
45 #include <linux/cpufreq.h>
46 #endif
47
48 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
49 #include <asm/clock.h>
50 #include <asm/sh_bios.h>
51 #include <asm/kgdb.h>
52 #endif
53
54 #include <asm/sci.h>
55 #include "sh-sci.h"
56
57 struct sci_port {
58 struct uart_port port;
59
60 /* Port type */
61 unsigned int type;
62
63 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
64 unsigned int irqs[SCIx_NR_IRQS];
65
66 /* Port pin configuration */
67 void (*init_pins)(struct uart_port *port,
68 unsigned int cflag);
69
70 /* Port enable callback */
71 void (*enable)(struct uart_port *port);
72
73 /* Port disable callback */
74 void (*disable)(struct uart_port *port);
75
76 /* Break timer */
77 struct timer_list break_timer;
78 int break_flag;
79 };
80
81 #ifdef CONFIG_SH_KGDB
82 static struct sci_port *kgdb_sci_port;
83 #endif
84
85 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
86 static struct sci_port *serial_console_port;
87 #endif
88
89 /* Function prototypes */
90 static void sci_stop_tx(struct uart_port *port);
91
92 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
93
94 static struct sci_port sci_ports[SCI_NPORTS];
95 static struct uart_driver sci_uart_driver;
96
97 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
98 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
99 static inline void handle_error(struct uart_port *port)
100 {
101 /* Clear error flags */
102 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
103 }
104
105 static int get_char(struct uart_port *port)
106 {
107 unsigned long flags;
108 unsigned short status;
109 int c;
110
111 spin_lock_irqsave(&port->lock, flags);
112 do {
113 status = sci_in(port, SCxSR);
114 if (status & SCxSR_ERRORS(port)) {
115 handle_error(port);
116 continue;
117 }
118 } while (!(status & SCxSR_RDxF(port)));
119 c = sci_in(port, SCxRDR);
120 sci_in(port, SCxSR); /* Dummy read */
121 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
122 spin_unlock_irqrestore(&port->lock, flags);
123
124 return c;
125 }
126 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
127
128 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
129 static void put_char(struct uart_port *port, char c)
130 {
131 unsigned long flags;
132 unsigned short status;
133
134 spin_lock_irqsave(&port->lock, flags);
135
136 do {
137 status = sci_in(port, SCxSR);
138 } while (!(status & SCxSR_TDxE(port)));
139
140 sci_out(port, SCxTDR, c);
141 sci_in(port, SCxSR); /* Dummy read */
142 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
143
144 spin_unlock_irqrestore(&port->lock, flags);
145 }
146 #endif
147
148 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
149 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
150 {
151 struct uart_port *port = &sci_port->port;
152 const unsigned char *p = buffer;
153 int i;
154
155 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
156 int checksum;
157 int usegdb=0;
158
159 #ifdef CONFIG_SH_STANDARD_BIOS
160 /* This call only does a trap the first time it is
161 * called, and so is safe to do here unconditionally
162 */
163 usegdb |= sh_bios_in_gdb_mode();
164 #endif
165 #ifdef CONFIG_SH_KGDB
166 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
167 #endif
168
169 if (usegdb) {
170 /* $<packet info>#<checksum>. */
171 do {
172 unsigned char c;
173 put_char(port, '$');
174 put_char(port, 'O'); /* 'O'utput to console */
175 checksum = 'O';
176
177 for (i=0; i<count; i++) { /* Don't use run length encoding */
178 int h, l;
179
180 c = *p++;
181 h = highhex(c);
182 l = lowhex(c);
183 put_char(port, h);
184 put_char(port, l);
185 checksum += h + l;
186 }
187 put_char(port, '#');
188 put_char(port, highhex(checksum));
189 put_char(port, lowhex(checksum));
190 } while (get_char(port) != '+');
191 } else
192 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
193 for (i=0; i<count; i++) {
194 if (*p == 10)
195 put_char(port, '\r');
196 put_char(port, *p++);
197 }
198 }
199 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
200
201 #ifdef CONFIG_SH_KGDB
202 static int kgdb_sci_getchar(void)
203 {
204 int c;
205
206 /* Keep trying to read a character, this could be neater */
207 while ((c = get_char(kgdb_sci_port)) < 0)
208 cpu_relax();
209
210 return c;
211 }
212
213 static inline void kgdb_sci_putchar(int c)
214 {
215 put_char(kgdb_sci_port, c);
216 }
217 #endif /* CONFIG_SH_KGDB */
218
219 #if defined(__H8300S__)
220 enum { sci_disable, sci_enable };
221
222 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
223 {
224 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
225 int ch = (port->mapbase - SMR0) >> 3;
226 unsigned char mask = 1 << (ch+1);
227
228 if (ctrl == sci_disable) {
229 *mstpcrl |= mask;
230 } else {
231 *mstpcrl &= ~mask;
232 }
233 }
234
235 static inline void h8300_sci_enable(struct uart_port *port)
236 {
237 h8300_sci_config(port, sci_enable);
238 }
239
240 static inline void h8300_sci_disable(struct uart_port *port)
241 {
242 h8300_sci_config(port, sci_disable);
243 }
244 #endif
245
246 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
247 defined(__H8300H__) || defined(__H8300S__)
248 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
249 {
250 int ch = (port->mapbase - SMR0) >> 3;
251
252 /* set DDR regs */
253 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
254 h8300_sci_pins[ch].rx,
255 H8300_GPIO_INPUT);
256 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
257 h8300_sci_pins[ch].tx,
258 H8300_GPIO_OUTPUT);
259
260 /* tx mark output*/
261 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
262 }
263 #else
264 #define sci_init_pins_sci NULL
265 #endif
266
267 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
268 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
269 {
270 unsigned int fcr_val = 0;
271
272 if (cflag & CRTSCTS)
273 fcr_val |= SCFCR_MCE;
274
275 sci_out(port, SCFCR, fcr_val);
276 }
277 #else
278 #define sci_init_pins_irda NULL
279 #endif
280
281 #ifdef SCI_ONLY
282 #define sci_init_pins_scif NULL
283 #endif
284
285 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
286 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
287 /* SH7300 doesn't use RTS/CTS */
288 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
289 {
290 sci_out(port, SCFCR, 0);
291 }
292 #elif defined(CONFIG_CPU_SH3)
293 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
294 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
295 {
296 unsigned int fcr_val = 0;
297 unsigned short data;
298
299 /* We need to set SCPCR to enable RTS/CTS */
300 data = ctrl_inw(SCPCR);
301 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
302 ctrl_outw(data & 0x0fcf, SCPCR);
303
304 if (cflag & CRTSCTS)
305 fcr_val |= SCFCR_MCE;
306 else {
307 /* We need to set SCPCR to enable RTS/CTS */
308 data = ctrl_inw(SCPCR);
309 /* Clear out SCP7MD1,0, SCP4MD1,0,
310 Set SCP6MD1,0 = {01} (output) */
311 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
312
313 data = ctrl_inb(SCPDR);
314 /* Set /RTS2 (bit6) = 0 */
315 ctrl_outb(data & 0xbf, SCPDR);
316 }
317
318 sci_out(port, SCFCR, fcr_val);
319 }
320 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
321 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
322 {
323 unsigned int fcr_val = 0;
324
325 if (cflag & CRTSCTS) {
326 fcr_val |= SCFCR_MCE;
327
328 ctrl_outw(0x0000, PORT_PSCR);
329 } else {
330 unsigned short data;
331
332 data = ctrl_inw(PORT_PSCR);
333 data &= 0x033f;
334 data |= 0x0400;
335 ctrl_outw(data, PORT_PSCR);
336
337 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
338 }
339
340 sci_out(port, SCFCR, fcr_val);
341 }
342 #else
343 /* For SH7750 */
344 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
345 {
346 unsigned int fcr_val = 0;
347
348 if (cflag & CRTSCTS) {
349 fcr_val |= SCFCR_MCE;
350 } else {
351 #ifdef CONFIG_CPU_SUBTYPE_SH7343
352 /* Nothing */
353 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
354 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
355 #else
356 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
357 #endif
358 }
359 sci_out(port, SCFCR, fcr_val);
360 }
361 #endif
362
363 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
364 static inline int scif_txroom(struct uart_port *port)
365 {
366 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
367 }
368
369 static inline int scif_rxroom(struct uart_port *port)
370 {
371 return sci_in(port, SCRFDR) & 0x7f;
372 }
373 #else
374 static inline int scif_txroom(struct uart_port *port)
375 {
376 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
377 }
378
379 static inline int scif_rxroom(struct uart_port *port)
380 {
381 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
382 }
383 #endif
384 #endif /* SCIF_ONLY || SCI_AND_SCIF */
385
386 static inline int sci_txroom(struct uart_port *port)
387 {
388 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
389 }
390
391 static inline int sci_rxroom(struct uart_port *port)
392 {
393 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
394 }
395
396 /* ********************************************************************** *
397 * the interrupt related routines *
398 * ********************************************************************** */
399
400 static void sci_transmit_chars(struct uart_port *port)
401 {
402 struct circ_buf *xmit = &port->info->xmit;
403 unsigned int stopped = uart_tx_stopped(port);
404 unsigned short status;
405 unsigned short ctrl;
406 int count;
407
408 status = sci_in(port, SCxSR);
409 if (!(status & SCxSR_TDxE(port))) {
410 ctrl = sci_in(port, SCSCR);
411 if (uart_circ_empty(xmit)) {
412 ctrl &= ~SCI_CTRL_FLAGS_TIE;
413 } else {
414 ctrl |= SCI_CTRL_FLAGS_TIE;
415 }
416 sci_out(port, SCSCR, ctrl);
417 return;
418 }
419
420 #ifndef SCI_ONLY
421 if (port->type == PORT_SCIF)
422 count = scif_txroom(port);
423 else
424 #endif
425 count = sci_txroom(port);
426
427 do {
428 unsigned char c;
429
430 if (port->x_char) {
431 c = port->x_char;
432 port->x_char = 0;
433 } else if (!uart_circ_empty(xmit) && !stopped) {
434 c = xmit->buf[xmit->tail];
435 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
436 } else {
437 break;
438 }
439
440 sci_out(port, SCxTDR, c);
441
442 port->icount.tx++;
443 } while (--count > 0);
444
445 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
446
447 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
448 uart_write_wakeup(port);
449 if (uart_circ_empty(xmit)) {
450 sci_stop_tx(port);
451 } else {
452 ctrl = sci_in(port, SCSCR);
453
454 #if !defined(SCI_ONLY)
455 if (port->type == PORT_SCIF) {
456 sci_in(port, SCxSR); /* Dummy read */
457 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
458 }
459 #endif
460
461 ctrl |= SCI_CTRL_FLAGS_TIE;
462 sci_out(port, SCSCR, ctrl);
463 }
464 }
465
466 /* On SH3, SCIF may read end-of-break as a space->mark char */
467 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
468
469 static inline void sci_receive_chars(struct uart_port *port)
470 {
471 struct sci_port *sci_port = (struct sci_port *)port;
472 struct tty_struct *tty = port->info->tty;
473 int i, count, copied = 0;
474 unsigned short status;
475 unsigned char flag;
476
477 status = sci_in(port, SCxSR);
478 if (!(status & SCxSR_RDxF(port)))
479 return;
480
481 while (1) {
482 #if !defined(SCI_ONLY)
483 if (port->type == PORT_SCIF)
484 count = scif_rxroom(port);
485 else
486 #endif
487 count = sci_rxroom(port);
488
489 /* Don't copy more bytes than there is room for in the buffer */
490 count = tty_buffer_request_room(tty, count);
491
492 /* If for any reason we can't copy more data, we're done! */
493 if (count == 0)
494 break;
495
496 if (port->type == PORT_SCI) {
497 char c = sci_in(port, SCxRDR);
498 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
499 count = 0;
500 else {
501 tty_insert_flip_char(tty, c, TTY_NORMAL);
502 }
503 } else {
504 for (i=0; i<count; i++) {
505 char c = sci_in(port, SCxRDR);
506 status = sci_in(port, SCxSR);
507 #if defined(CONFIG_CPU_SH3)
508 /* Skip "chars" during break */
509 if (sci_port->break_flag) {
510 if ((c == 0) &&
511 (status & SCxSR_FER(port))) {
512 count--; i--;
513 continue;
514 }
515
516 /* Nonzero => end-of-break */
517 pr_debug("scif: debounce<%02x>\n", c);
518 sci_port->break_flag = 0;
519
520 if (STEPFN(c)) {
521 count--; i--;
522 continue;
523 }
524 }
525 #endif /* CONFIG_CPU_SH3 */
526 if (uart_handle_sysrq_char(port, c)) {
527 count--; i--;
528 continue;
529 }
530
531 /* Store data and status */
532 if (status&SCxSR_FER(port)) {
533 flag = TTY_FRAME;
534 pr_debug("sci: frame error\n");
535 } else if (status&SCxSR_PER(port)) {
536 flag = TTY_PARITY;
537 pr_debug("sci: parity error\n");
538 } else
539 flag = TTY_NORMAL;
540 tty_insert_flip_char(tty, c, flag);
541 }
542 }
543
544 sci_in(port, SCxSR); /* dummy read */
545 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
546
547 copied += count;
548 port->icount.rx += count;
549 }
550
551 if (copied) {
552 /* Tell the rest of the system the news. New characters! */
553 tty_flip_buffer_push(tty);
554 } else {
555 sci_in(port, SCxSR); /* dummy read */
556 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
557 }
558 }
559
560 #define SCI_BREAK_JIFFIES (HZ/20)
561 /* The sci generates interrupts during the break,
562 * 1 per millisecond or so during the break period, for 9600 baud.
563 * So dont bother disabling interrupts.
564 * But dont want more than 1 break event.
565 * Use a kernel timer to periodically poll the rx line until
566 * the break is finished.
567 */
568 static void sci_schedule_break_timer(struct sci_port *port)
569 {
570 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
571 add_timer(&port->break_timer);
572 }
573 /* Ensure that two consecutive samples find the break over. */
574 static void sci_break_timer(unsigned long data)
575 {
576 struct sci_port *port = (struct sci_port *)data;
577
578 if (sci_rxd_in(&port->port) == 0) {
579 port->break_flag = 1;
580 sci_schedule_break_timer(port);
581 } else if (port->break_flag == 1) {
582 /* break is over. */
583 port->break_flag = 2;
584 sci_schedule_break_timer(port);
585 } else
586 port->break_flag = 0;
587 }
588
589 static inline int sci_handle_errors(struct uart_port *port)
590 {
591 int copied = 0;
592 unsigned short status = sci_in(port, SCxSR);
593 struct tty_struct *tty = port->info->tty;
594
595 if (status & SCxSR_ORER(port)) {
596 /* overrun error */
597 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
598 copied++;
599 pr_debug("sci: overrun error\n");
600 }
601
602 if (status & SCxSR_FER(port)) {
603 if (sci_rxd_in(port) == 0) {
604 /* Notify of BREAK */
605 struct sci_port *sci_port = (struct sci_port *)port;
606
607 if (!sci_port->break_flag) {
608 sci_port->break_flag = 1;
609 sci_schedule_break_timer(sci_port);
610
611 /* Do sysrq handling. */
612 if (uart_handle_break(port))
613 return 0;
614 pr_debug("sci: BREAK detected\n");
615 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
616 copied++;
617 }
618 } else {
619 /* frame error */
620 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
621 copied++;
622 pr_debug("sci: frame error\n");
623 }
624 }
625
626 if (status & SCxSR_PER(port)) {
627 /* parity error */
628 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
629 copied++;
630 pr_debug("sci: parity error\n");
631 }
632
633 if (copied)
634 tty_flip_buffer_push(tty);
635
636 return copied;
637 }
638
639 static inline int sci_handle_breaks(struct uart_port *port)
640 {
641 int copied = 0;
642 unsigned short status = sci_in(port, SCxSR);
643 struct tty_struct *tty = port->info->tty;
644 struct sci_port *s = &sci_ports[port->line];
645
646 if (uart_handle_break(port))
647 return 0;
648
649 if (!s->break_flag && status & SCxSR_BRK(port)) {
650 #if defined(CONFIG_CPU_SH3)
651 /* Debounce break */
652 s->break_flag = 1;
653 #endif
654 /* Notify of BREAK */
655 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
656 copied++;
657 pr_debug("sci: BREAK detected\n");
658 }
659
660 #if defined(SCIF_ORER)
661 /* XXX: Handle SCIF overrun error */
662 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
663 sci_out(port, SCLSR, 0);
664 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
665 copied++;
666 pr_debug("sci: overrun error\n");
667 }
668 }
669 #endif
670
671 if (copied)
672 tty_flip_buffer_push(tty);
673
674 return copied;
675 }
676
677 static irqreturn_t sci_rx_interrupt(int irq, void *port)
678 {
679 /* I think sci_receive_chars has to be called irrespective
680 * of whether the I_IXOFF is set, otherwise, how is the interrupt
681 * to be disabled?
682 */
683 sci_receive_chars(port);
684
685 return IRQ_HANDLED;
686 }
687
688 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
689 {
690 struct uart_port *port = ptr;
691
692 spin_lock_irq(&port->lock);
693 sci_transmit_chars(port);
694 spin_unlock_irq(&port->lock);
695
696 return IRQ_HANDLED;
697 }
698
699 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
700 {
701 struct uart_port *port = ptr;
702
703 /* Handle errors */
704 if (port->type == PORT_SCI) {
705 if (sci_handle_errors(port)) {
706 /* discard character in rx buffer */
707 sci_in(port, SCxSR);
708 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
709 }
710 } else {
711 #if defined(SCIF_ORER)
712 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
713 struct tty_struct *tty = port->info->tty;
714
715 sci_out(port, SCLSR, 0);
716 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
717 tty_flip_buffer_push(tty);
718 pr_debug("scif: overrun error\n");
719 }
720 #endif
721 sci_rx_interrupt(irq, ptr);
722 }
723
724 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
725
726 /* Kick the transmission */
727 sci_tx_interrupt(irq, ptr);
728
729 return IRQ_HANDLED;
730 }
731
732 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
733 {
734 struct uart_port *port = ptr;
735
736 /* Handle BREAKs */
737 sci_handle_breaks(port);
738
739 #ifdef CONFIG_SH_KGDB
740 /* Break into the debugger if a break is detected */
741 BREAKPOINT();
742 #endif
743
744 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
745
746 return IRQ_HANDLED;
747 }
748
749 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
750 {
751 unsigned short ssr_status, scr_status;
752 struct uart_port *port = ptr;
753
754 ssr_status = sci_in(port,SCxSR);
755 scr_status = sci_in(port,SCSCR);
756
757 /* Tx Interrupt */
758 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
759 sci_tx_interrupt(irq, ptr);
760 /* Rx Interrupt */
761 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
762 sci_rx_interrupt(irq, ptr);
763 /* Error Interrupt */
764 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
765 sci_er_interrupt(irq, ptr);
766 /* Break Interrupt */
767 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
768 sci_br_interrupt(irq, ptr);
769
770 return IRQ_HANDLED;
771 }
772
773 #ifdef CONFIG_CPU_FREQ
774 /*
775 * Here we define a transistion notifier so that we can update all of our
776 * ports' baud rate when the peripheral clock changes.
777 */
778 static int sci_notifier(struct notifier_block *self,
779 unsigned long phase, void *p)
780 {
781 struct cpufreq_freqs *freqs = p;
782 int i;
783
784 if ((phase == CPUFREQ_POSTCHANGE) ||
785 (phase == CPUFREQ_RESUMECHANGE)){
786 for (i = 0; i < SCI_NPORTS; i++) {
787 struct uart_port *port = &sci_ports[i].port;
788 struct clk *clk;
789
790 /*
791 * Update the uartclk per-port if frequency has
792 * changed, since it will no longer necessarily be
793 * consistent with the old frequency.
794 *
795 * Really we want to be able to do something like
796 * uart_change_speed() or something along those lines
797 * here to implicitly reset the per-port baud rate..
798 *
799 * Clean this up later..
800 */
801 clk = clk_get(NULL, "module_clk");
802 port->uartclk = clk_get_rate(clk) * 16;
803 clk_put(clk);
804 }
805
806 printk(KERN_INFO "%s: got a postchange notification "
807 "for cpu %d (old %d, new %d)\n",
808 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
809 }
810
811 return NOTIFY_OK;
812 }
813
814 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
815 #endif /* CONFIG_CPU_FREQ */
816
817 static int sci_request_irq(struct sci_port *port)
818 {
819 int i;
820 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
821 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
822 sci_br_interrupt,
823 };
824 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
825 "SCI Transmit Data Empty", "SCI Break" };
826
827 if (port->irqs[0] == port->irqs[1]) {
828 if (!port->irqs[0]) {
829 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
830 return -ENODEV;
831 }
832
833 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
834 IRQF_DISABLED, "sci", port)) {
835 printk(KERN_ERR "sci: Cannot allocate irq.\n");
836 return -ENODEV;
837 }
838 } else {
839 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
840 if (!port->irqs[i])
841 continue;
842 if (request_irq(port->irqs[i], handlers[i],
843 IRQF_DISABLED, desc[i], port)) {
844 printk(KERN_ERR "sci: Cannot allocate irq.\n");
845 return -ENODEV;
846 }
847 }
848 }
849
850 return 0;
851 }
852
853 static void sci_free_irq(struct sci_port *port)
854 {
855 int i;
856
857 if (port->irqs[0] == port->irqs[1]) {
858 if (!port->irqs[0])
859 printk("sci: sci_free_irq error\n");
860 else
861 free_irq(port->irqs[0], port);
862 } else {
863 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
864 if (!port->irqs[i])
865 continue;
866
867 free_irq(port->irqs[i], port);
868 }
869 }
870 }
871
872 static unsigned int sci_tx_empty(struct uart_port *port)
873 {
874 /* Can't detect */
875 return TIOCSER_TEMT;
876 }
877
878 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
879 {
880 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
881 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
882 /* If you have signals for DTR and DCD, please implement here. */
883 }
884
885 static unsigned int sci_get_mctrl(struct uart_port *port)
886 {
887 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
888 and CTS/RTS */
889
890 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
891 }
892
893 static void sci_start_tx(struct uart_port *port)
894 {
895 unsigned short ctrl;
896
897 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
898 ctrl = sci_in(port, SCSCR);
899 ctrl |= SCI_CTRL_FLAGS_TIE;
900 sci_out(port, SCSCR, ctrl);
901 }
902
903 static void sci_stop_tx(struct uart_port *port)
904 {
905 unsigned short ctrl;
906
907 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
908 ctrl = sci_in(port, SCSCR);
909 ctrl &= ~SCI_CTRL_FLAGS_TIE;
910 sci_out(port, SCSCR, ctrl);
911 }
912
913 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
914 {
915 unsigned short ctrl;
916
917 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
918 ctrl = sci_in(port, SCSCR);
919 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
920 sci_out(port, SCSCR, ctrl);
921 }
922
923 static void sci_stop_rx(struct uart_port *port)
924 {
925 unsigned short ctrl;
926
927 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
928 ctrl = sci_in(port, SCSCR);
929 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
930 sci_out(port, SCSCR, ctrl);
931 }
932
933 static void sci_enable_ms(struct uart_port *port)
934 {
935 /* Nothing here yet .. */
936 }
937
938 static void sci_break_ctl(struct uart_port *port, int break_state)
939 {
940 /* Nothing here yet .. */
941 }
942
943 static int sci_startup(struct uart_port *port)
944 {
945 struct sci_port *s = &sci_ports[port->line];
946
947 if (s->enable)
948 s->enable(port);
949
950 sci_request_irq(s);
951 sci_start_tx(port);
952 sci_start_rx(port, 1);
953
954 return 0;
955 }
956
957 static void sci_shutdown(struct uart_port *port)
958 {
959 struct sci_port *s = &sci_ports[port->line];
960
961 sci_stop_rx(port);
962 sci_stop_tx(port);
963 sci_free_irq(s);
964
965 if (s->disable)
966 s->disable(port);
967 }
968
969 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
970 struct ktermios *old)
971 {
972 struct sci_port *s = &sci_ports[port->line];
973 unsigned int status, baud, smr_val;
974 unsigned long flags;
975 int t;
976
977 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
978
979 switch (baud) {
980 case 0:
981 t = -1;
982 break;
983 default:
984 {
985 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
986 struct clk *clk = clk_get(NULL, "module_clk");
987 t = SCBRR_VALUE(baud, clk_get_rate(clk));
988 clk_put(clk);
989 #else
990 t = SCBRR_VALUE(baud);
991 #endif
992 }
993 break;
994 }
995
996 spin_lock_irqsave(&port->lock, flags);
997
998 do {
999 status = sci_in(port, SCxSR);
1000 } while (!(status & SCxSR_TEND(port)));
1001
1002 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1003
1004 #if !defined(SCI_ONLY)
1005 if (port->type == PORT_SCIF)
1006 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1007 #endif
1008
1009 smr_val = sci_in(port, SCSMR) & 3;
1010 if ((termios->c_cflag & CSIZE) == CS7)
1011 smr_val |= 0x40;
1012 if (termios->c_cflag & PARENB)
1013 smr_val |= 0x20;
1014 if (termios->c_cflag & PARODD)
1015 smr_val |= 0x30;
1016 if (termios->c_cflag & CSTOPB)
1017 smr_val |= 0x08;
1018
1019 uart_update_timeout(port, termios->c_cflag, baud);
1020
1021 sci_out(port, SCSMR, smr_val);
1022
1023 if (t > 0) {
1024 if(t >= 256) {
1025 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1026 t >>= 2;
1027 } else {
1028 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1029 }
1030 sci_out(port, SCBRR, t);
1031 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1032 }
1033
1034 if (likely(s->init_pins))
1035 s->init_pins(port, termios->c_cflag);
1036
1037 sci_out(port, SCSCR, SCSCR_INIT(port));
1038
1039 if ((termios->c_cflag & CREAD) != 0)
1040 sci_start_rx(port,0);
1041
1042 spin_unlock_irqrestore(&port->lock, flags);
1043 }
1044
1045 static const char *sci_type(struct uart_port *port)
1046 {
1047 switch (port->type) {
1048 case PORT_SCI: return "sci";
1049 case PORT_SCIF: return "scif";
1050 case PORT_IRDA: return "irda";
1051 }
1052
1053 return 0;
1054 }
1055
1056 static void sci_release_port(struct uart_port *port)
1057 {
1058 /* Nothing here yet .. */
1059 }
1060
1061 static int sci_request_port(struct uart_port *port)
1062 {
1063 /* Nothing here yet .. */
1064 return 0;
1065 }
1066
1067 static void sci_config_port(struct uart_port *port, int flags)
1068 {
1069 struct sci_port *s = &sci_ports[port->line];
1070
1071 port->type = s->type;
1072
1073 switch (port->type) {
1074 case PORT_SCI:
1075 s->init_pins = sci_init_pins_sci;
1076 break;
1077 case PORT_SCIF:
1078 s->init_pins = sci_init_pins_scif;
1079 break;
1080 case PORT_IRDA:
1081 s->init_pins = sci_init_pins_irda;
1082 break;
1083 }
1084
1085 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1086 if (port->mapbase == 0)
1087 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1088
1089 port->membase = (void __iomem *)port->mapbase;
1090 #endif
1091 }
1092
1093 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1094 {
1095 struct sci_port *s = &sci_ports[port->line];
1096
1097 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1098 return -EINVAL;
1099 if (ser->baud_base < 2400)
1100 /* No paper tape reader for Mitch.. */
1101 return -EINVAL;
1102
1103 return 0;
1104 }
1105
1106 static struct uart_ops sci_uart_ops = {
1107 .tx_empty = sci_tx_empty,
1108 .set_mctrl = sci_set_mctrl,
1109 .get_mctrl = sci_get_mctrl,
1110 .start_tx = sci_start_tx,
1111 .stop_tx = sci_stop_tx,
1112 .stop_rx = sci_stop_rx,
1113 .enable_ms = sci_enable_ms,
1114 .break_ctl = sci_break_ctl,
1115 .startup = sci_startup,
1116 .shutdown = sci_shutdown,
1117 .set_termios = sci_set_termios,
1118 .type = sci_type,
1119 .release_port = sci_release_port,
1120 .request_port = sci_request_port,
1121 .config_port = sci_config_port,
1122 .verify_port = sci_verify_port,
1123 };
1124
1125 static void __init sci_init_ports(void)
1126 {
1127 static int first = 1;
1128 int i;
1129
1130 if (!first)
1131 return;
1132
1133 first = 0;
1134
1135 for (i = 0; i < SCI_NPORTS; i++) {
1136 sci_ports[i].port.ops = &sci_uart_ops;
1137 sci_ports[i].port.iotype = UPIO_MEM;
1138 sci_ports[i].port.line = i;
1139 sci_ports[i].port.fifosize = 1;
1140
1141 #if defined(__H8300H__) || defined(__H8300S__)
1142 #ifdef __H8300S__
1143 sci_ports[i].enable = h8300_sci_enable;
1144 sci_ports[i].disable = h8300_sci_disable;
1145 #endif
1146 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1147 #elif defined(CONFIG_SUPERH64)
1148 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1149 #else
1150 /*
1151 * XXX: We should use a proper SCI/SCIF clock
1152 */
1153 {
1154 struct clk *clk = clk_get(NULL, "module_clk");
1155 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1156 clk_put(clk);
1157 }
1158 #endif
1159
1160 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1161 sci_ports[i].break_timer.function = sci_break_timer;
1162
1163 init_timer(&sci_ports[i].break_timer);
1164 }
1165 }
1166
1167 int __init early_sci_setup(struct uart_port *port)
1168 {
1169 if (unlikely(port->line > SCI_NPORTS))
1170 return -ENODEV;
1171
1172 sci_init_ports();
1173
1174 sci_ports[port->line].port.membase = port->membase;
1175 sci_ports[port->line].port.mapbase = port->mapbase;
1176 sci_ports[port->line].port.type = port->type;
1177
1178 return 0;
1179 }
1180
1181 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1182 /*
1183 * Print a string to the serial port trying not to disturb
1184 * any possible real use of the port...
1185 */
1186 static void serial_console_write(struct console *co, const char *s,
1187 unsigned count)
1188 {
1189 put_string(serial_console_port, s, count);
1190 }
1191
1192 static int __init serial_console_setup(struct console *co, char *options)
1193 {
1194 struct uart_port *port;
1195 int baud = 115200;
1196 int bits = 8;
1197 int parity = 'n';
1198 int flow = 'n';
1199 int ret;
1200
1201 /*
1202 * Check whether an invalid uart number has been specified, and
1203 * if so, search for the first available port that does have
1204 * console support.
1205 */
1206 if (co->index >= SCI_NPORTS)
1207 co->index = 0;
1208
1209 serial_console_port = &sci_ports[co->index];
1210 port = &serial_console_port->port;
1211
1212 /*
1213 * Also need to check port->type, we don't actually have any
1214 * UPIO_PORT ports, but uart_report_port() handily misreports
1215 * it anyways if we don't have a port available by the time this is
1216 * called.
1217 */
1218 if (!port->type)
1219 return -ENODEV;
1220 if (!port->membase || !port->mapbase)
1221 return -ENODEV;
1222
1223 spin_lock_init(&port->lock);
1224
1225 port->type = serial_console_port->type;
1226
1227 if (port->flags & UPF_IOREMAP)
1228 sci_config_port(port, 0);
1229
1230 if (serial_console_port->enable)
1231 serial_console_port->enable(port);
1232
1233 if (options)
1234 uart_parse_options(options, &baud, &parity, &bits, &flow);
1235
1236 ret = uart_set_options(port, co, baud, parity, bits, flow);
1237 #if defined(__H8300H__) || defined(__H8300S__)
1238 /* disable rx interrupt */
1239 if (ret == 0)
1240 sci_stop_rx(port);
1241 #endif
1242 return ret;
1243 }
1244
1245 static struct console serial_console = {
1246 .name = "ttySC",
1247 .device = uart_console_device,
1248 .write = serial_console_write,
1249 .setup = serial_console_setup,
1250 .flags = CON_PRINTBUFFER,
1251 .index = -1,
1252 .data = &sci_uart_driver,
1253 };
1254
1255 static int __init sci_console_init(void)
1256 {
1257 sci_init_ports();
1258 register_console(&serial_console);
1259 return 0;
1260 }
1261 console_initcall(sci_console_init);
1262 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1263
1264 #ifdef CONFIG_SH_KGDB
1265 /*
1266 * FIXME: Most of this can go away.. at the moment, we rely on
1267 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1268 * most of that can easily be done here instead.
1269 *
1270 * For the time being, just accept the values that were parsed earlier..
1271 */
1272 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1273 int *parity, int *bits)
1274 {
1275 *baud = kgdb_baud;
1276 *parity = tolower(kgdb_parity);
1277 *bits = kgdb_bits - '0';
1278 }
1279
1280 /*
1281 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1282 * care of the early-on initialization for kgdb, regardless of whether we
1283 * actually use kgdb as a console or not.
1284 *
1285 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1286 */
1287 int __init kgdb_console_setup(struct console *co, char *options)
1288 {
1289 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1290 int baud = 38400;
1291 int bits = 8;
1292 int parity = 'n';
1293 int flow = 'n';
1294
1295 spin_lock_init(&port->lock);
1296
1297 if (co->index != kgdb_portnum)
1298 co->index = kgdb_portnum;
1299
1300 if (options)
1301 uart_parse_options(options, &baud, &parity, &bits, &flow);
1302 else
1303 kgdb_console_get_options(port, &baud, &parity, &bits);
1304
1305 kgdb_getchar = kgdb_sci_getchar;
1306 kgdb_putchar = kgdb_sci_putchar;
1307
1308 return uart_set_options(port, co, baud, parity, bits, flow);
1309 }
1310 #endif /* CONFIG_SH_KGDB */
1311
1312 #ifdef CONFIG_SH_KGDB_CONSOLE
1313 static struct console kgdb_console = {
1314 .name = "ttySC",
1315 .write = kgdb_console_write,
1316 .setup = kgdb_console_setup,
1317 .flags = CON_PRINTBUFFER | CON_ENABLED,
1318 .index = -1,
1319 .data = &sci_uart_driver,
1320 };
1321
1322 /* Register the KGDB console so we get messages (d'oh!) */
1323 static int __init kgdb_console_init(void)
1324 {
1325 sci_init_ports();
1326 register_console(&kgdb_console);
1327 return 0;
1328 }
1329 console_initcall(kgdb_console_init);
1330 #endif /* CONFIG_SH_KGDB_CONSOLE */
1331
1332 #if defined(CONFIG_SH_KGDB_CONSOLE)
1333 #define SCI_CONSOLE &kgdb_console
1334 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1335 #define SCI_CONSOLE &serial_console
1336 #else
1337 #define SCI_CONSOLE 0
1338 #endif
1339
1340 static char banner[] __initdata =
1341 KERN_INFO "SuperH SCI(F) driver initialized\n";
1342
1343 static struct uart_driver sci_uart_driver = {
1344 .owner = THIS_MODULE,
1345 .driver_name = "sci",
1346 .dev_name = "ttySC",
1347 .major = SCI_MAJOR,
1348 .minor = SCI_MINOR_START,
1349 .nr = SCI_NPORTS,
1350 .cons = SCI_CONSOLE,
1351 };
1352
1353 /*
1354 * Register a set of serial devices attached to a platform device. The
1355 * list is terminated with a zero flags entry, which means we expect
1356 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1357 * remapping (such as sh64) should also set UPF_IOREMAP.
1358 */
1359 static int __devinit sci_probe(struct platform_device *dev)
1360 {
1361 struct plat_sci_port *p = dev->dev.platform_data;
1362 int i;
1363
1364 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1365 struct sci_port *sciport = &sci_ports[i];
1366
1367 sciport->port.mapbase = p->mapbase;
1368
1369 /*
1370 * For the simple (and majority of) cases where we don't need
1371 * to do any remapping, just cast the cookie directly.
1372 */
1373 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1374 p->membase = (void __iomem *)p->mapbase;
1375
1376 sciport->port.membase = p->membase;
1377
1378 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1379 sciport->port.flags = p->flags;
1380 sciport->port.dev = &dev->dev;
1381
1382 sciport->type = sciport->port.type = p->type;
1383
1384 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1385
1386 uart_add_one_port(&sci_uart_driver, &sciport->port);
1387 }
1388
1389 #ifdef CONFIG_CPU_FREQ
1390 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1391 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1392 #endif
1393
1394 #ifdef CONFIG_SH_STANDARD_BIOS
1395 sh_bios_gdb_detach();
1396 #endif
1397
1398 return 0;
1399 }
1400
1401 static int __devexit sci_remove(struct platform_device *dev)
1402 {
1403 int i;
1404
1405 for (i = 0; i < SCI_NPORTS; i++)
1406 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1407
1408 return 0;
1409 }
1410
1411 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1412 {
1413 int i;
1414
1415 for (i = 0; i < SCI_NPORTS; i++) {
1416 struct sci_port *p = &sci_ports[i];
1417
1418 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1419 uart_suspend_port(&sci_uart_driver, &p->port);
1420 }
1421
1422 return 0;
1423 }
1424
1425 static int sci_resume(struct platform_device *dev)
1426 {
1427 int i;
1428
1429 for (i = 0; i < SCI_NPORTS; i++) {
1430 struct sci_port *p = &sci_ports[i];
1431
1432 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1433 uart_resume_port(&sci_uart_driver, &p->port);
1434 }
1435
1436 return 0;
1437 }
1438
1439 static struct platform_driver sci_driver = {
1440 .probe = sci_probe,
1441 .remove = __devexit_p(sci_remove),
1442 .suspend = sci_suspend,
1443 .resume = sci_resume,
1444 .driver = {
1445 .name = "sh-sci",
1446 .owner = THIS_MODULE,
1447 },
1448 };
1449
1450 static int __init sci_init(void)
1451 {
1452 int ret;
1453
1454 printk(banner);
1455
1456 sci_init_ports();
1457
1458 ret = uart_register_driver(&sci_uart_driver);
1459 if (likely(ret == 0)) {
1460 ret = platform_driver_register(&sci_driver);
1461 if (unlikely(ret))
1462 uart_unregister_driver(&sci_uart_driver);
1463 }
1464
1465 return ret;
1466 }
1467
1468 static void __exit sci_exit(void)
1469 {
1470 platform_driver_unregister(&sci_driver);
1471 uart_unregister_driver(&sci_uart_driver);
1472 }
1473
1474 module_init(sci_init);
1475 module_exit(sci_exit);
1476
1477 MODULE_LICENSE("GPL");
CJK support for tty framebuffer vt