2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 static int __init
parse_noapic(char *str
)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic
);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list
{
121 struct irq_pin_list
*next
;
124 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
126 struct irq_pin_list
*pin
;
129 node
= cpu_to_node(cpu
);
131 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
137 struct irq_pin_list
*irq_2_pin
;
138 cpumask_var_t domain
;
139 cpumask_var_t old_domain
;
140 unsigned move_cleanup_count
;
142 u8 move_in_progress
: 1;
143 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
144 u8 move_desc_pending
: 1;
148 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
149 #ifdef CONFIG_SPARSE_IRQ
150 static struct irq_cfg irq_cfgx
[] = {
152 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
154 [0] = { .vector
= IRQ0_VECTOR
, },
155 [1] = { .vector
= IRQ1_VECTOR
, },
156 [2] = { .vector
= IRQ2_VECTOR
, },
157 [3] = { .vector
= IRQ3_VECTOR
, },
158 [4] = { .vector
= IRQ4_VECTOR
, },
159 [5] = { .vector
= IRQ5_VECTOR
, },
160 [6] = { .vector
= IRQ6_VECTOR
, },
161 [7] = { .vector
= IRQ7_VECTOR
, },
162 [8] = { .vector
= IRQ8_VECTOR
, },
163 [9] = { .vector
= IRQ9_VECTOR
, },
164 [10] = { .vector
= IRQ10_VECTOR
, },
165 [11] = { .vector
= IRQ11_VECTOR
, },
166 [12] = { .vector
= IRQ12_VECTOR
, },
167 [13] = { .vector
= IRQ13_VECTOR
, },
168 [14] = { .vector
= IRQ14_VECTOR
, },
169 [15] = { .vector
= IRQ15_VECTOR
, },
172 int __init
arch_early_irq_init(void)
175 struct irq_desc
*desc
;
180 count
= ARRAY_SIZE(irq_cfgx
);
182 for (i
= 0; i
< count
; i
++) {
183 desc
= irq_to_desc(i
);
184 desc
->chip_data
= &cfg
[i
];
185 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
186 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
187 if (i
< NR_IRQS_LEGACY
)
188 cpumask_setall(cfg
[i
].domain
);
194 #ifdef CONFIG_SPARSE_IRQ
195 static struct irq_cfg
*irq_cfg(unsigned int irq
)
197 struct irq_cfg
*cfg
= NULL
;
198 struct irq_desc
*desc
;
200 desc
= irq_to_desc(irq
);
202 cfg
= desc
->chip_data
;
207 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
212 node
= cpu_to_node(cpu
);
214 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
216 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
219 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
221 free_cpumask_var(cfg
->domain
);
225 cpumask_clear(cfg
->domain
);
226 cpumask_clear(cfg
->old_domain
);
233 int arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
237 cfg
= desc
->chip_data
;
239 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
240 if (!desc
->chip_data
) {
241 printk(KERN_ERR
"can not alloc irq_cfg\n");
249 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
252 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
254 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
256 cfg
->irq_2_pin
= NULL
;
257 old_entry
= old_cfg
->irq_2_pin
;
261 entry
= get_one_free_irq_2_pin(cpu
);
265 entry
->apic
= old_entry
->apic
;
266 entry
->pin
= old_entry
->pin
;
269 old_entry
= old_entry
->next
;
271 entry
= get_one_free_irq_2_pin(cpu
);
279 /* still use the old one */
282 entry
->apic
= old_entry
->apic
;
283 entry
->pin
= old_entry
->pin
;
286 old_entry
= old_entry
->next
;
290 cfg
->irq_2_pin
= head
;
293 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
295 struct irq_pin_list
*entry
, *next
;
297 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
300 entry
= old_cfg
->irq_2_pin
;
307 old_cfg
->irq_2_pin
= NULL
;
310 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
311 struct irq_desc
*desc
, int cpu
)
314 struct irq_cfg
*old_cfg
;
316 cfg
= get_one_free_irq_cfg(cpu
);
321 desc
->chip_data
= cfg
;
323 old_cfg
= old_desc
->chip_data
;
325 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
327 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
330 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
335 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
337 struct irq_cfg
*old_cfg
, *cfg
;
339 old_cfg
= old_desc
->chip_data
;
340 cfg
= desc
->chip_data
;
346 free_irq_2_pin(old_cfg
, cfg
);
347 free_irq_cfg(old_cfg
);
348 old_desc
->chip_data
= NULL
;
353 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
355 struct irq_cfg
*cfg
= desc
->chip_data
;
357 if (!cfg
->move_in_progress
) {
358 /* it means that domain is not changed */
359 if (!cpumask_intersects(&desc
->affinity
, mask
))
360 cfg
->move_desc_pending
= 1;
366 static struct irq_cfg
*irq_cfg(unsigned int irq
)
368 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
373 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
375 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
382 unsigned int unused
[3];
386 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
388 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
389 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
392 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
394 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
395 writel(reg
, &io_apic
->index
);
396 return readl(&io_apic
->data
);
399 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
401 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
402 writel(reg
, &io_apic
->index
);
403 writel(value
, &io_apic
->data
);
407 * Re-write a value: to be used for read-modify-write
408 * cycles where the read already set up the index register.
410 * Older SiS APIC requires we rewrite the index register
412 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
414 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
417 writel(reg
, &io_apic
->index
);
418 writel(value
, &io_apic
->data
);
421 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
423 struct irq_pin_list
*entry
;
426 spin_lock_irqsave(&ioapic_lock
, flags
);
427 entry
= cfg
->irq_2_pin
;
435 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
436 /* Is the remote IRR bit set? */
437 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
438 spin_unlock_irqrestore(&ioapic_lock
, flags
);
445 spin_unlock_irqrestore(&ioapic_lock
, flags
);
451 struct { u32 w1
, w2
; };
452 struct IO_APIC_route_entry entry
;
455 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
457 union entry_union eu
;
459 spin_lock_irqsave(&ioapic_lock
, flags
);
460 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
461 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
462 spin_unlock_irqrestore(&ioapic_lock
, flags
);
467 * When we write a new IO APIC routing entry, we need to write the high
468 * word first! If the mask bit in the low word is clear, we will enable
469 * the interrupt, and we need to make sure the entry is fully populated
470 * before that happens.
473 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
475 union entry_union eu
;
477 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
478 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
481 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
484 spin_lock_irqsave(&ioapic_lock
, flags
);
485 __ioapic_write_entry(apic
, pin
, e
);
486 spin_unlock_irqrestore(&ioapic_lock
, flags
);
490 * When we mask an IO APIC routing entry, we need to write the low
491 * word first, in order to set the mask bit before we change the
494 static void ioapic_mask_entry(int apic
, int pin
)
497 union entry_union eu
= { .entry
.mask
= 1 };
499 spin_lock_irqsave(&ioapic_lock
, flags
);
500 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
501 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
502 spin_unlock_irqrestore(&ioapic_lock
, flags
);
506 static void send_cleanup_vector(struct irq_cfg
*cfg
)
508 cpumask_var_t cleanup_mask
;
510 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
512 cfg
->move_cleanup_count
= 0;
513 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
514 cfg
->move_cleanup_count
++;
515 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
516 send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
518 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
519 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
520 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
521 free_cpumask_var(cleanup_mask
);
523 cfg
->move_in_progress
= 0;
526 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
529 struct irq_pin_list
*entry
;
530 u8 vector
= cfg
->vector
;
532 entry
= cfg
->irq_2_pin
;
541 #ifdef CONFIG_INTR_REMAP
543 * With interrupt-remapping, destination information comes
544 * from interrupt-remapping table entry.
546 if (!irq_remapped(irq
))
547 io_apic_write(apic
, 0x11 + pin
*2, dest
);
549 io_apic_write(apic
, 0x11 + pin
*2, dest
);
551 reg
= io_apic_read(apic
, 0x10 + pin
*2);
552 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
554 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
562 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
565 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
566 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
569 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
574 if (!cpumask_intersects(mask
, cpu_online_mask
))
578 cfg
= desc
->chip_data
;
579 if (assign_irq_vector(irq
, cfg
, mask
))
582 cpumask_and(&desc
->affinity
, cfg
->domain
, mask
);
583 set_extra_move_desc(desc
, mask
);
584 return cpu_mask_to_apicid_and(&desc
->affinity
, cpu_online_mask
);
588 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
596 cfg
= desc
->chip_data
;
598 spin_lock_irqsave(&ioapic_lock
, flags
);
599 dest
= set_desc_affinity(desc
, mask
);
600 if (dest
!= BAD_APICID
) {
601 /* Only the high 8 bits are valid. */
602 dest
= SET_APIC_LOGICAL_ID(dest
);
603 __target_IO_APIC_irq(irq
, dest
, cfg
);
605 spin_unlock_irqrestore(&ioapic_lock
, flags
);
609 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
611 struct irq_desc
*desc
;
613 desc
= irq_to_desc(irq
);
615 set_ioapic_affinity_irq_desc(desc
, mask
);
617 #endif /* CONFIG_SMP */
620 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
621 * shared ISA-space IRQs, so we have to support them. We are super
622 * fast in the common case, and fast for shared ISA-space IRQs.
624 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
626 struct irq_pin_list
*entry
;
628 entry
= cfg
->irq_2_pin
;
630 entry
= get_one_free_irq_2_pin(cpu
);
632 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
636 cfg
->irq_2_pin
= entry
;
642 while (entry
->next
) {
643 /* not again, please */
644 if (entry
->apic
== apic
&& entry
->pin
== pin
)
650 entry
->next
= get_one_free_irq_2_pin(cpu
);
657 * Reroute an IRQ to a different pin.
659 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
660 int oldapic
, int oldpin
,
661 int newapic
, int newpin
)
663 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
667 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
668 entry
->apic
= newapic
;
671 /* every one is different, right? */
677 /* why? call replace before add? */
679 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
682 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
683 int mask_and
, int mask_or
,
684 void (*final
)(struct irq_pin_list
*entry
))
687 struct irq_pin_list
*entry
;
689 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
692 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
695 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
701 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
703 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
707 static void io_apic_sync(struct irq_pin_list
*entry
)
710 * Synchronize the IO-APIC and the CPU by doing
711 * a dummy read from the IO-APIC
713 struct io_apic __iomem
*io_apic
;
714 io_apic
= io_apic_base(entry
->apic
);
715 readl(&io_apic
->data
);
718 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
720 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
722 #else /* CONFIG_X86_32 */
723 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
725 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
728 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
730 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
731 IO_APIC_REDIR_MASKED
, NULL
);
734 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
736 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
737 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
739 #endif /* CONFIG_X86_32 */
741 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
743 struct irq_cfg
*cfg
= desc
->chip_data
;
748 spin_lock_irqsave(&ioapic_lock
, flags
);
749 __mask_IO_APIC_irq(cfg
);
750 spin_unlock_irqrestore(&ioapic_lock
, flags
);
753 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
755 struct irq_cfg
*cfg
= desc
->chip_data
;
758 spin_lock_irqsave(&ioapic_lock
, flags
);
759 __unmask_IO_APIC_irq(cfg
);
760 spin_unlock_irqrestore(&ioapic_lock
, flags
);
763 static void mask_IO_APIC_irq(unsigned int irq
)
765 struct irq_desc
*desc
= irq_to_desc(irq
);
767 mask_IO_APIC_irq_desc(desc
);
769 static void unmask_IO_APIC_irq(unsigned int irq
)
771 struct irq_desc
*desc
= irq_to_desc(irq
);
773 unmask_IO_APIC_irq_desc(desc
);
776 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
778 struct IO_APIC_route_entry entry
;
780 /* Check delivery_mode to be sure we're not clearing an SMI pin */
781 entry
= ioapic_read_entry(apic
, pin
);
782 if (entry
.delivery_mode
== dest_SMI
)
785 * Disable it in the IO-APIC irq-routing table:
787 ioapic_mask_entry(apic
, pin
);
790 static void clear_IO_APIC (void)
794 for (apic
= 0; apic
< nr_ioapics
; apic
++)
795 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
796 clear_IO_APIC_pin(apic
, pin
);
799 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
800 void send_IPI_self(int vector
)
807 apic_wait_icr_idle();
808 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
810 * Send the IPI. The write to APIC_ICR fires this off.
812 apic_write(APIC_ICR
, cfg
);
814 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
818 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
819 * specific CPU-side IRQs.
823 static int pirq_entries
[MAX_PIRQS
];
824 static int pirqs_enabled
;
826 static int __init
ioapic_pirq_setup(char *str
)
829 int ints
[MAX_PIRQS
+1];
831 get_options(str
, ARRAY_SIZE(ints
), ints
);
833 for (i
= 0; i
< MAX_PIRQS
; i
++)
834 pirq_entries
[i
] = -1;
837 apic_printk(APIC_VERBOSE
, KERN_INFO
838 "PIRQ redirection, working around broken MP-BIOS.\n");
840 if (ints
[0] < MAX_PIRQS
)
843 for (i
= 0; i
< max
; i
++) {
844 apic_printk(APIC_VERBOSE
, KERN_DEBUG
845 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
847 * PIRQs are mapped upside down, usually.
849 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
854 __setup("pirq=", ioapic_pirq_setup
);
855 #endif /* CONFIG_X86_32 */
857 #ifdef CONFIG_INTR_REMAP
858 /* I/O APIC RTE contents at the OS boot up */
859 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
862 * Saves and masks all the unmasked IO-APIC RTE's
864 int save_mask_IO_APIC_setup(void)
866 union IO_APIC_reg_01 reg_01
;
871 * The number of IO-APIC IRQ registers (== #pins):
873 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
874 spin_lock_irqsave(&ioapic_lock
, flags
);
875 reg_01
.raw
= io_apic_read(apic
, 1);
876 spin_unlock_irqrestore(&ioapic_lock
, flags
);
877 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
880 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
881 early_ioapic_entries
[apic
] =
882 kzalloc(sizeof(struct IO_APIC_route_entry
) *
883 nr_ioapic_registers
[apic
], GFP_KERNEL
);
884 if (!early_ioapic_entries
[apic
])
888 for (apic
= 0; apic
< nr_ioapics
; apic
++)
889 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
890 struct IO_APIC_route_entry entry
;
892 entry
= early_ioapic_entries
[apic
][pin
] =
893 ioapic_read_entry(apic
, pin
);
896 ioapic_write_entry(apic
, pin
, entry
);
904 kfree(early_ioapic_entries
[apic
--]);
905 memset(early_ioapic_entries
, 0,
906 ARRAY_SIZE(early_ioapic_entries
));
911 void restore_IO_APIC_setup(void)
915 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
916 if (!early_ioapic_entries
[apic
])
918 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
919 ioapic_write_entry(apic
, pin
,
920 early_ioapic_entries
[apic
][pin
]);
921 kfree(early_ioapic_entries
[apic
]);
922 early_ioapic_entries
[apic
] = NULL
;
926 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
929 * for now plain restore of previous settings.
930 * TBD: In the case of OS enabling interrupt-remapping,
931 * IO-APIC RTE's need to be setup to point to interrupt-remapping
932 * table entries. for now, do a plain restore, and wait for
933 * the setup_IO_APIC_irqs() to do proper initialization.
935 restore_IO_APIC_setup();
940 * Find the IRQ entry number of a certain pin.
942 static int find_irq_entry(int apic
, int pin
, int type
)
946 for (i
= 0; i
< mp_irq_entries
; i
++)
947 if (mp_irqs
[i
].mp_irqtype
== type
&&
948 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
949 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
950 mp_irqs
[i
].mp_dstirq
== pin
)
957 * Find the pin to which IRQ[irq] (ISA) is connected
959 static int __init
find_isa_irq_pin(int irq
, int type
)
963 for (i
= 0; i
< mp_irq_entries
; i
++) {
964 int lbus
= mp_irqs
[i
].mp_srcbus
;
966 if (test_bit(lbus
, mp_bus_not_pci
) &&
967 (mp_irqs
[i
].mp_irqtype
== type
) &&
968 (mp_irqs
[i
].mp_srcbusirq
== irq
))
970 return mp_irqs
[i
].mp_dstirq
;
975 static int __init
find_isa_irq_apic(int irq
, int type
)
979 for (i
= 0; i
< mp_irq_entries
; i
++) {
980 int lbus
= mp_irqs
[i
].mp_srcbus
;
982 if (test_bit(lbus
, mp_bus_not_pci
) &&
983 (mp_irqs
[i
].mp_irqtype
== type
) &&
984 (mp_irqs
[i
].mp_srcbusirq
== irq
))
987 if (i
< mp_irq_entries
) {
989 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
990 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
999 * Find a specific PCI IRQ entry.
1000 * Not an __init, possibly needed by modules
1002 static int pin_2_irq(int idx
, int apic
, int pin
);
1004 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1006 int apic
, i
, best_guess
= -1;
1008 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1010 if (test_bit(bus
, mp_bus_not_pci
)) {
1011 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1014 for (i
= 0; i
< mp_irq_entries
; i
++) {
1015 int lbus
= mp_irqs
[i
].mp_srcbus
;
1017 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1018 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
1019 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
1022 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1023 !mp_irqs
[i
].mp_irqtype
&&
1025 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
1026 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
1028 if (!(apic
|| IO_APIC_IRQ(irq
)))
1031 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
1034 * Use the first all-but-pin matching entry as a
1035 * best-guess fuzzy result for broken mptables.
1044 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1046 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1048 * EISA Edge/Level control register, ELCR
1050 static int EISA_ELCR(unsigned int irq
)
1052 if (irq
< NR_IRQS_LEGACY
) {
1053 unsigned int port
= 0x4d0 + (irq
>> 3);
1054 return (inb(port
) >> (irq
& 7)) & 1;
1056 apic_printk(APIC_VERBOSE
, KERN_INFO
1057 "Broken MPtable reports ISA irq %d\n", irq
);
1063 /* ISA interrupts are always polarity zero edge triggered,
1064 * when listed as conforming in the MP table. */
1066 #define default_ISA_trigger(idx) (0)
1067 #define default_ISA_polarity(idx) (0)
1069 /* EISA interrupts are always polarity zero and can be edge or level
1070 * trigger depending on the ELCR value. If an interrupt is listed as
1071 * EISA conforming in the MP table, that means its trigger type must
1072 * be read in from the ELCR */
1074 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1075 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1077 /* PCI interrupts are always polarity one level triggered,
1078 * when listed as conforming in the MP table. */
1080 #define default_PCI_trigger(idx) (1)
1081 #define default_PCI_polarity(idx) (1)
1083 /* MCA interrupts are always polarity zero level triggered,
1084 * when listed as conforming in the MP table. */
1086 #define default_MCA_trigger(idx) (1)
1087 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1089 static int MPBIOS_polarity(int idx
)
1091 int bus
= mp_irqs
[idx
].mp_srcbus
;
1095 * Determine IRQ line polarity (high active or low active):
1097 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1099 case 0: /* conforms, ie. bus-type dependent polarity */
1100 if (test_bit(bus
, mp_bus_not_pci
))
1101 polarity
= default_ISA_polarity(idx
);
1103 polarity
= default_PCI_polarity(idx
);
1105 case 1: /* high active */
1110 case 2: /* reserved */
1112 printk(KERN_WARNING
"broken BIOS!!\n");
1116 case 3: /* low active */
1121 default: /* invalid */
1123 printk(KERN_WARNING
"broken BIOS!!\n");
1131 static int MPBIOS_trigger(int idx
)
1133 int bus
= mp_irqs
[idx
].mp_srcbus
;
1137 * Determine IRQ trigger mode (edge or level sensitive):
1139 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1141 case 0: /* conforms, ie. bus-type dependent */
1142 if (test_bit(bus
, mp_bus_not_pci
))
1143 trigger
= default_ISA_trigger(idx
);
1145 trigger
= default_PCI_trigger(idx
);
1146 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1147 switch (mp_bus_id_to_type
[bus
]) {
1148 case MP_BUS_ISA
: /* ISA pin */
1150 /* set before the switch */
1153 case MP_BUS_EISA
: /* EISA pin */
1155 trigger
= default_EISA_trigger(idx
);
1158 case MP_BUS_PCI
: /* PCI pin */
1160 /* set before the switch */
1163 case MP_BUS_MCA
: /* MCA pin */
1165 trigger
= default_MCA_trigger(idx
);
1170 printk(KERN_WARNING
"broken BIOS!!\n");
1182 case 2: /* reserved */
1184 printk(KERN_WARNING
"broken BIOS!!\n");
1193 default: /* invalid */
1195 printk(KERN_WARNING
"broken BIOS!!\n");
1203 static inline int irq_polarity(int idx
)
1205 return MPBIOS_polarity(idx
);
1208 static inline int irq_trigger(int idx
)
1210 return MPBIOS_trigger(idx
);
1213 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1214 static int pin_2_irq(int idx
, int apic
, int pin
)
1217 int bus
= mp_irqs
[idx
].mp_srcbus
;
1220 * Debugging check, we are in big trouble if this message pops up!
1222 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1223 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1225 if (test_bit(bus
, mp_bus_not_pci
)) {
1226 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1229 * PCI IRQs are mapped in order
1233 irq
+= nr_ioapic_registers
[i
++];
1236 * For MPS mode, so far only needed by ES7000 platform
1238 if (ioapic_renumber_irq
)
1239 irq
= ioapic_renumber_irq(apic
, irq
);
1242 #ifdef CONFIG_X86_32
1244 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1246 if ((pin
>= 16) && (pin
<= 23)) {
1247 if (pirq_entries
[pin
-16] != -1) {
1248 if (!pirq_entries
[pin
-16]) {
1249 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1250 "disabling PIRQ%d\n", pin
-16);
1252 irq
= pirq_entries
[pin
-16];
1253 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1254 "using PIRQ%d -> IRQ %d\n",
1264 void lock_vector_lock(void)
1266 /* Used to the online set of cpus does not change
1267 * during assign_irq_vector.
1269 spin_lock(&vector_lock
);
1272 void unlock_vector_lock(void)
1274 spin_unlock(&vector_lock
);
1278 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1281 * NOTE! The local APIC isn't very good at handling
1282 * multiple interrupts at the same interrupt level.
1283 * As the interrupt level is determined by taking the
1284 * vector number and shifting that right by 4, we
1285 * want to spread these out a bit so that they don't
1286 * all fall in the same interrupt level.
1288 * Also, we've got to be careful not to trash gate
1289 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1291 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1292 unsigned int old_vector
;
1294 cpumask_var_t tmp_mask
;
1296 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1299 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1302 old_vector
= cfg
->vector
;
1304 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1305 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1306 if (!cpumask_empty(tmp_mask
)) {
1307 free_cpumask_var(tmp_mask
);
1312 /* Only try and allocate irqs on cpus that are present */
1314 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1318 vector_allocation_domain(cpu
, tmp_mask
);
1320 vector
= current_vector
;
1321 offset
= current_offset
;
1324 if (vector
>= first_system_vector
) {
1325 /* If out of vectors on large boxen, must share them. */
1326 offset
= (offset
+ 1) % 8;
1327 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1329 if (unlikely(current_vector
== vector
))
1332 if (test_bit(vector
, used_vectors
))
1335 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1336 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1339 current_vector
= vector
;
1340 current_offset
= offset
;
1342 cfg
->move_in_progress
= 1;
1343 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1345 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1346 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1347 cfg
->vector
= vector
;
1348 cpumask_copy(cfg
->domain
, tmp_mask
);
1352 free_cpumask_var(tmp_mask
);
1357 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1360 unsigned long flags
;
1362 spin_lock_irqsave(&vector_lock
, flags
);
1363 err
= __assign_irq_vector(irq
, cfg
, mask
);
1364 spin_unlock_irqrestore(&vector_lock
, flags
);
1368 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1372 BUG_ON(!cfg
->vector
);
1374 vector
= cfg
->vector
;
1375 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1376 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1379 cpumask_clear(cfg
->domain
);
1381 if (likely(!cfg
->move_in_progress
))
1383 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1384 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1386 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1388 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1392 cfg
->move_in_progress
= 0;
1395 void __setup_vector_irq(int cpu
)
1397 /* Initialize vector_irq on a new cpu */
1398 /* This function must be called with vector_lock held */
1400 struct irq_cfg
*cfg
;
1401 struct irq_desc
*desc
;
1403 /* Mark the inuse vectors */
1404 for_each_irq_desc(irq
, desc
) {
1405 cfg
= desc
->chip_data
;
1406 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1408 vector
= cfg
->vector
;
1409 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1411 /* Mark the free vectors */
1412 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1413 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1418 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1419 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1423 static struct irq_chip ioapic_chip
;
1424 #ifdef CONFIG_INTR_REMAP
1425 static struct irq_chip ir_ioapic_chip
;
1428 #define IOAPIC_AUTO -1
1429 #define IOAPIC_EDGE 0
1430 #define IOAPIC_LEVEL 1
1432 #ifdef CONFIG_X86_32
1433 static inline int IO_APIC_irq_trigger(int irq
)
1437 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1438 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1439 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1440 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1441 return irq_trigger(idx
);
1445 * nonexistent IRQs are edge default
1450 static inline int IO_APIC_irq_trigger(int irq
)
1456 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1459 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1460 trigger
== IOAPIC_LEVEL
)
1461 desc
->status
|= IRQ_LEVEL
;
1463 desc
->status
&= ~IRQ_LEVEL
;
1465 #ifdef CONFIG_INTR_REMAP
1466 if (irq_remapped(irq
)) {
1467 desc
->status
|= IRQ_MOVE_PCNTXT
;
1469 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1473 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1474 handle_edge_irq
, "edge");
1478 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1479 trigger
== IOAPIC_LEVEL
)
1480 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1484 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1485 handle_edge_irq
, "edge");
1488 static int setup_ioapic_entry(int apic
, int irq
,
1489 struct IO_APIC_route_entry
*entry
,
1490 unsigned int destination
, int trigger
,
1491 int polarity
, int vector
)
1494 * add it to the IO-APIC irq-routing table:
1496 memset(entry
,0,sizeof(*entry
));
1498 #ifdef CONFIG_INTR_REMAP
1499 if (intr_remapping_enabled
) {
1500 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1502 struct IR_IO_APIC_route_entry
*ir_entry
=
1503 (struct IR_IO_APIC_route_entry
*) entry
;
1507 panic("No mapping iommu for ioapic %d\n", apic
);
1509 index
= alloc_irte(iommu
, irq
, 1);
1511 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1513 memset(&irte
, 0, sizeof(irte
));
1516 irte
.dst_mode
= INT_DEST_MODE
;
1517 irte
.trigger_mode
= trigger
;
1518 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1519 irte
.vector
= vector
;
1520 irte
.dest_id
= IRTE_DEST(destination
);
1522 modify_irte(irq
, &irte
);
1524 ir_entry
->index2
= (index
>> 15) & 0x1;
1526 ir_entry
->format
= 1;
1527 ir_entry
->index
= (index
& 0x7fff);
1531 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1532 entry
->dest_mode
= INT_DEST_MODE
;
1533 entry
->dest
= destination
;
1536 entry
->mask
= 0; /* enable IRQ */
1537 entry
->trigger
= trigger
;
1538 entry
->polarity
= polarity
;
1539 entry
->vector
= vector
;
1541 /* Mask level triggered irqs.
1542 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1549 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1550 int trigger
, int polarity
)
1552 struct irq_cfg
*cfg
;
1553 struct IO_APIC_route_entry entry
;
1556 if (!IO_APIC_IRQ(irq
))
1559 cfg
= desc
->chip_data
;
1561 if (assign_irq_vector(irq
, cfg
, TARGET_CPUS
))
1564 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
1566 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1567 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1568 "IRQ %d Mode:%i Active:%i)\n",
1569 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1570 irq
, trigger
, polarity
);
1573 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1574 dest
, trigger
, polarity
, cfg
->vector
)) {
1575 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1576 mp_ioapics
[apic
].mp_apicid
, pin
);
1577 __clear_irq_vector(irq
, cfg
);
1581 ioapic_register_intr(irq
, desc
, trigger
);
1582 if (irq
< NR_IRQS_LEGACY
)
1583 disable_8259A_irq(irq
);
1585 ioapic_write_entry(apic
, pin
, entry
);
1588 static void __init
setup_IO_APIC_irqs(void)
1590 int apic
, pin
, idx
, irq
;
1592 struct irq_desc
*desc
;
1593 struct irq_cfg
*cfg
;
1594 int cpu
= boot_cpu_id
;
1596 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1598 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1599 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1601 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1605 apic_printk(APIC_VERBOSE
,
1606 KERN_DEBUG
" %d-%d",
1607 mp_ioapics
[apic
].mp_apicid
,
1610 apic_printk(APIC_VERBOSE
, " %d-%d",
1611 mp_ioapics
[apic
].mp_apicid
,
1616 apic_printk(APIC_VERBOSE
,
1617 " (apicid-pin) not connected\n");
1621 irq
= pin_2_irq(idx
, apic
, pin
);
1622 #ifdef CONFIG_X86_32
1623 if (multi_timer_check(apic
, irq
))
1626 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1628 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1631 cfg
= desc
->chip_data
;
1632 add_pin_to_irq_cpu(cfg
, cpu
, apic
, pin
);
1634 setup_IO_APIC_irq(apic
, pin
, irq
, desc
,
1635 irq_trigger(idx
), irq_polarity(idx
));
1640 apic_printk(APIC_VERBOSE
,
1641 " (apicid-pin) not connected\n");
1645 * Set up the timer pin, possibly with the 8259A-master behind.
1647 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1650 struct IO_APIC_route_entry entry
;
1652 #ifdef CONFIG_INTR_REMAP
1653 if (intr_remapping_enabled
)
1657 memset(&entry
, 0, sizeof(entry
));
1660 * We use logical delivery to get the timer IRQ
1663 entry
.dest_mode
= INT_DEST_MODE
;
1664 entry
.mask
= 1; /* mask IRQ now */
1665 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1666 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1669 entry
.vector
= vector
;
1672 * The timer IRQ doesn't have to know that behind the
1673 * scene we may have a 8259A-master in AEOI mode ...
1675 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1678 * Add it to the IO-APIC irq-routing table:
1680 ioapic_write_entry(apic
, pin
, entry
);
1684 __apicdebuginit(void) print_IO_APIC(void)
1687 union IO_APIC_reg_00 reg_00
;
1688 union IO_APIC_reg_01 reg_01
;
1689 union IO_APIC_reg_02 reg_02
;
1690 union IO_APIC_reg_03 reg_03
;
1691 unsigned long flags
;
1692 struct irq_cfg
*cfg
;
1693 struct irq_desc
*desc
;
1696 if (apic_verbosity
== APIC_QUIET
)
1699 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1700 for (i
= 0; i
< nr_ioapics
; i
++)
1701 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1702 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1705 * We are a bit conservative about what we expect. We have to
1706 * know about every hardware change ASAP.
1708 printk(KERN_INFO
"testing the IO APIC.......................\n");
1710 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1712 spin_lock_irqsave(&ioapic_lock
, flags
);
1713 reg_00
.raw
= io_apic_read(apic
, 0);
1714 reg_01
.raw
= io_apic_read(apic
, 1);
1715 if (reg_01
.bits
.version
>= 0x10)
1716 reg_02
.raw
= io_apic_read(apic
, 2);
1717 if (reg_01
.bits
.version
>= 0x20)
1718 reg_03
.raw
= io_apic_read(apic
, 3);
1719 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1722 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1723 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1724 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1725 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1726 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1728 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1729 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1731 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1732 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1735 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1736 * but the value of reg_02 is read as the previous read register
1737 * value, so ignore it if reg_02 == reg_01.
1739 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1740 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1741 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1745 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1746 * or reg_03, but the value of reg_0[23] is read as the previous read
1747 * register value, so ignore it if reg_03 == reg_0[12].
1749 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1750 reg_03
.raw
!= reg_01
.raw
) {
1751 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1752 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1755 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1757 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1758 " Stat Dmod Deli Vect: \n");
1760 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1761 struct IO_APIC_route_entry entry
;
1763 entry
= ioapic_read_entry(apic
, i
);
1765 printk(KERN_DEBUG
" %02x %03X ",
1770 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1775 entry
.delivery_status
,
1777 entry
.delivery_mode
,
1782 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1783 for_each_irq_desc(irq
, desc
) {
1784 struct irq_pin_list
*entry
;
1786 cfg
= desc
->chip_data
;
1787 entry
= cfg
->irq_2_pin
;
1790 printk(KERN_DEBUG
"IRQ%d ", irq
);
1792 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1795 entry
= entry
->next
;
1800 printk(KERN_INFO
".................................... done.\n");
1805 __apicdebuginit(void) print_APIC_bitfield(int base
)
1810 if (apic_verbosity
== APIC_QUIET
)
1813 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1814 for (i
= 0; i
< 8; i
++) {
1815 v
= apic_read(base
+ i
*0x10);
1816 for (j
= 0; j
< 32; j
++) {
1826 __apicdebuginit(void) print_local_APIC(void *dummy
)
1828 unsigned int v
, ver
, maxlvt
;
1831 if (apic_verbosity
== APIC_QUIET
)
1834 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1835 smp_processor_id(), hard_smp_processor_id());
1836 v
= apic_read(APIC_ID
);
1837 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1838 v
= apic_read(APIC_LVR
);
1839 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1840 ver
= GET_APIC_VERSION(v
);
1841 maxlvt
= lapic_get_maxlvt();
1843 v
= apic_read(APIC_TASKPRI
);
1844 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1846 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1847 if (!APIC_XAPIC(ver
)) {
1848 v
= apic_read(APIC_ARBPRI
);
1849 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1850 v
& APIC_ARBPRI_MASK
);
1852 v
= apic_read(APIC_PROCPRI
);
1853 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1857 * Remote read supported only in the 82489DX and local APIC for
1858 * Pentium processors.
1860 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1861 v
= apic_read(APIC_RRR
);
1862 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1865 v
= apic_read(APIC_LDR
);
1866 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1867 if (!x2apic_enabled()) {
1868 v
= apic_read(APIC_DFR
);
1869 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1871 v
= apic_read(APIC_SPIV
);
1872 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1874 printk(KERN_DEBUG
"... APIC ISR field:\n");
1875 print_APIC_bitfield(APIC_ISR
);
1876 printk(KERN_DEBUG
"... APIC TMR field:\n");
1877 print_APIC_bitfield(APIC_TMR
);
1878 printk(KERN_DEBUG
"... APIC IRR field:\n");
1879 print_APIC_bitfield(APIC_IRR
);
1881 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1882 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1883 apic_write(APIC_ESR
, 0);
1885 v
= apic_read(APIC_ESR
);
1886 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1889 icr
= apic_icr_read();
1890 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1891 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1893 v
= apic_read(APIC_LVTT
);
1894 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1896 if (maxlvt
> 3) { /* PC is LVT#4. */
1897 v
= apic_read(APIC_LVTPC
);
1898 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1900 v
= apic_read(APIC_LVT0
);
1901 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1902 v
= apic_read(APIC_LVT1
);
1903 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1905 if (maxlvt
> 2) { /* ERR is LVT#3. */
1906 v
= apic_read(APIC_LVTERR
);
1907 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1910 v
= apic_read(APIC_TMICT
);
1911 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1912 v
= apic_read(APIC_TMCCT
);
1913 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1914 v
= apic_read(APIC_TDCR
);
1915 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1919 __apicdebuginit(void) print_all_local_APICs(void)
1924 for_each_online_cpu(cpu
)
1925 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1929 __apicdebuginit(void) print_PIC(void)
1932 unsigned long flags
;
1934 if (apic_verbosity
== APIC_QUIET
)
1937 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1939 spin_lock_irqsave(&i8259A_lock
, flags
);
1941 v
= inb(0xa1) << 8 | inb(0x21);
1942 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1944 v
= inb(0xa0) << 8 | inb(0x20);
1945 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1949 v
= inb(0xa0) << 8 | inb(0x20);
1953 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1955 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1957 v
= inb(0x4d1) << 8 | inb(0x4d0);
1958 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1961 __apicdebuginit(int) print_all_ICs(void)
1964 print_all_local_APICs();
1970 fs_initcall(print_all_ICs
);
1973 /* Where if anywhere is the i8259 connect in external int mode */
1974 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1976 void __init
enable_IO_APIC(void)
1978 union IO_APIC_reg_01 reg_01
;
1979 int i8259_apic
, i8259_pin
;
1981 unsigned long flags
;
1983 #ifdef CONFIG_X86_32
1986 for (i
= 0; i
< MAX_PIRQS
; i
++)
1987 pirq_entries
[i
] = -1;
1991 * The number of IO-APIC IRQ registers (== #pins):
1993 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1994 spin_lock_irqsave(&ioapic_lock
, flags
);
1995 reg_01
.raw
= io_apic_read(apic
, 1);
1996 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1997 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1999 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2001 /* See if any of the pins is in ExtINT mode */
2002 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2003 struct IO_APIC_route_entry entry
;
2004 entry
= ioapic_read_entry(apic
, pin
);
2006 /* If the interrupt line is enabled and in ExtInt mode
2007 * I have found the pin where the i8259 is connected.
2009 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2010 ioapic_i8259
.apic
= apic
;
2011 ioapic_i8259
.pin
= pin
;
2017 /* Look to see what if the MP table has reported the ExtINT */
2018 /* If we could not find the appropriate pin by looking at the ioapic
2019 * the i8259 probably is not connected the ioapic but give the
2020 * mptable a chance anyway.
2022 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2023 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2024 /* Trust the MP table if nothing is setup in the hardware */
2025 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2026 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2027 ioapic_i8259
.pin
= i8259_pin
;
2028 ioapic_i8259
.apic
= i8259_apic
;
2030 /* Complain if the MP table and the hardware disagree */
2031 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2032 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2034 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2038 * Do not trust the IO-APIC being empty at bootup
2044 * Not an __init, needed by the reboot code
2046 void disable_IO_APIC(void)
2049 * Clear the IO-APIC before rebooting:
2054 * If the i8259 is routed through an IOAPIC
2055 * Put that IOAPIC in virtual wire mode
2056 * so legacy interrupts can be delivered.
2058 if (ioapic_i8259
.pin
!= -1) {
2059 struct IO_APIC_route_entry entry
;
2061 memset(&entry
, 0, sizeof(entry
));
2062 entry
.mask
= 0; /* Enabled */
2063 entry
.trigger
= 0; /* Edge */
2065 entry
.polarity
= 0; /* High */
2066 entry
.delivery_status
= 0;
2067 entry
.dest_mode
= 0; /* Physical */
2068 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2070 entry
.dest
= read_apic_id();
2073 * Add it to the IO-APIC irq-routing table:
2075 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2078 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
2081 #ifdef CONFIG_X86_32
2083 * function to set the IO-APIC physical IDs based on the
2084 * values stored in the MPC table.
2086 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2089 static void __init
setup_ioapic_ids_from_mpc(void)
2091 union IO_APIC_reg_00 reg_00
;
2092 physid_mask_t phys_id_present_map
;
2095 unsigned char old_id
;
2096 unsigned long flags
;
2098 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2102 * Don't check I/O APIC IDs for xAPIC systems. They have
2103 * no meaning without the serial APIC bus.
2105 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2106 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2109 * This is broken; anything with a real cpu count has to
2110 * circumvent this idiocy regardless.
2112 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2115 * Set the IOAPIC ID to the value stored in the MPC table.
2117 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2119 /* Read the register 0 value */
2120 spin_lock_irqsave(&ioapic_lock
, flags
);
2121 reg_00
.raw
= io_apic_read(apic
, 0);
2122 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2124 old_id
= mp_ioapics
[apic
].mp_apicid
;
2126 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2127 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2128 apic
, mp_ioapics
[apic
].mp_apicid
);
2129 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2131 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2135 * Sanity check, is the ID really free? Every APIC in a
2136 * system must have a unique ID or we get lots of nice
2137 * 'stuck on smp_invalidate_needed IPI wait' messages.
2139 if (check_apicid_used(phys_id_present_map
,
2140 mp_ioapics
[apic
].mp_apicid
)) {
2141 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2142 apic
, mp_ioapics
[apic
].mp_apicid
);
2143 for (i
= 0; i
< get_physical_broadcast(); i
++)
2144 if (!physid_isset(i
, phys_id_present_map
))
2146 if (i
>= get_physical_broadcast())
2147 panic("Max APIC ID exceeded!\n");
2148 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2150 physid_set(i
, phys_id_present_map
);
2151 mp_ioapics
[apic
].mp_apicid
= i
;
2154 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2155 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2156 "phys_id_present_map\n",
2157 mp_ioapics
[apic
].mp_apicid
);
2158 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2163 * We need to adjust the IRQ routing table
2164 * if the ID changed.
2166 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2167 for (i
= 0; i
< mp_irq_entries
; i
++)
2168 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2169 mp_irqs
[i
].mp_dstapic
2170 = mp_ioapics
[apic
].mp_apicid
;
2173 * Read the right value from the MPC table and
2174 * write it into the ID register.
2176 apic_printk(APIC_VERBOSE
, KERN_INFO
2177 "...changing IO-APIC physical APIC ID to %d ...",
2178 mp_ioapics
[apic
].mp_apicid
);
2180 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2181 spin_lock_irqsave(&ioapic_lock
, flags
);
2182 io_apic_write(apic
, 0, reg_00
.raw
);
2183 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2188 spin_lock_irqsave(&ioapic_lock
, flags
);
2189 reg_00
.raw
= io_apic_read(apic
, 0);
2190 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2191 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2192 printk("could not set ID!\n");
2194 apic_printk(APIC_VERBOSE
, " ok.\n");
2199 int no_timer_check __initdata
;
2201 static int __init
notimercheck(char *s
)
2206 __setup("no_timer_check", notimercheck
);
2209 * There is a nasty bug in some older SMP boards, their mptable lies
2210 * about the timer IRQ. We do the following to work around the situation:
2212 * - timer IRQ defaults to IO-APIC IRQ
2213 * - if this function detects that timer IRQs are defunct, then we fall
2214 * back to ISA timer IRQs
2216 static int __init
timer_irq_works(void)
2218 unsigned long t1
= jiffies
;
2219 unsigned long flags
;
2224 local_save_flags(flags
);
2226 /* Let ten ticks pass... */
2227 mdelay((10 * 1000) / HZ
);
2228 local_irq_restore(flags
);
2231 * Expect a few ticks at least, to be sure some possible
2232 * glue logic does not lock up after one or two first
2233 * ticks in a non-ExtINT mode. Also the local APIC
2234 * might have cached one ExtINT interrupt. Finally, at
2235 * least one tick may be lost due to delays.
2239 if (time_after(jiffies
, t1
+ 4))
2245 * In the SMP+IOAPIC case it might happen that there are an unspecified
2246 * number of pending IRQ events unhandled. These cases are very rare,
2247 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2248 * better to do it this way as thus we do not have to be aware of
2249 * 'pending' interrupts in the IRQ path, except at this point.
2252 * Edge triggered needs to resend any interrupt
2253 * that was delayed but this is now handled in the device
2258 * Starting up a edge-triggered IO-APIC interrupt is
2259 * nasty - we need to make sure that we get the edge.
2260 * If it is already asserted for some reason, we need
2261 * return 1 to indicate that is was pending.
2263 * This is not complete - we should be able to fake
2264 * an edge even if it isn't on the 8259A...
2267 static unsigned int startup_ioapic_irq(unsigned int irq
)
2269 int was_pending
= 0;
2270 unsigned long flags
;
2271 struct irq_cfg
*cfg
;
2273 spin_lock_irqsave(&ioapic_lock
, flags
);
2274 if (irq
< NR_IRQS_LEGACY
) {
2275 disable_8259A_irq(irq
);
2276 if (i8259A_irq_pending(irq
))
2280 __unmask_IO_APIC_irq(cfg
);
2281 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2286 #ifdef CONFIG_X86_64
2287 static int ioapic_retrigger_irq(unsigned int irq
)
2290 struct irq_cfg
*cfg
= irq_cfg(irq
);
2291 unsigned long flags
;
2293 spin_lock_irqsave(&vector_lock
, flags
);
2294 send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2295 spin_unlock_irqrestore(&vector_lock
, flags
);
2300 static int ioapic_retrigger_irq(unsigned int irq
)
2302 send_IPI_self(irq_cfg(irq
)->vector
);
2309 * Level and edge triggered IO-APIC interrupts need different handling,
2310 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2311 * handled with the level-triggered descriptor, but that one has slightly
2312 * more overhead. Level-triggered interrupts cannot be handled with the
2313 * edge-triggered handler, without risking IRQ storms and other ugly
2319 #ifdef CONFIG_INTR_REMAP
2320 static void ir_irq_migration(struct work_struct
*work
);
2322 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2325 * Migrate the IO-APIC irq in the presence of intr-remapping.
2327 * For edge triggered, irq migration is a simple atomic update(of vector
2328 * and cpu destination) of IRTE and flush the hardware cache.
2330 * For level triggered, we need to modify the io-apic RTE aswell with the update
2331 * vector information, along with modifying IRTE with vector and destination.
2332 * So irq migration for level triggered is little bit more complex compared to
2333 * edge triggered migration. But the good news is, we use the same algorithm
2334 * for level triggered migration as we have today, only difference being,
2335 * we now initiate the irq migration from process context instead of the
2336 * interrupt context.
2338 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2339 * suppression) to the IO-APIC, level triggered irq migration will also be
2340 * as simple as edge triggered migration and we can do the irq migration
2341 * with a simple atomic update to IO-APIC RTE.
2344 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2346 struct irq_cfg
*cfg
;
2348 int modify_ioapic_rte
;
2350 unsigned long flags
;
2353 if (!cpumask_intersects(mask
, cpu_online_mask
))
2357 if (get_irte(irq
, &irte
))
2360 cfg
= desc
->chip_data
;
2361 if (assign_irq_vector(irq
, cfg
, mask
))
2364 set_extra_move_desc(desc
, mask
);
2366 dest
= cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2368 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2369 if (modify_ioapic_rte
) {
2370 spin_lock_irqsave(&ioapic_lock
, flags
);
2371 __target_IO_APIC_irq(irq
, dest
, cfg
);
2372 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2375 irte
.vector
= cfg
->vector
;
2376 irte
.dest_id
= IRTE_DEST(dest
);
2379 * Modified the IRTE and flushes the Interrupt entry cache.
2381 modify_irte(irq
, &irte
);
2383 if (cfg
->move_in_progress
)
2384 send_cleanup_vector(cfg
);
2386 cpumask_copy(&desc
->affinity
, mask
);
2389 static int migrate_irq_remapped_level_desc(struct irq_desc
*desc
)
2392 struct irq_cfg
*cfg
= desc
->chip_data
;
2394 mask_IO_APIC_irq_desc(desc
);
2396 if (io_apic_level_ack_pending(cfg
)) {
2398 * Interrupt in progress. Migrating irq now will change the
2399 * vector information in the IO-APIC RTE and that will confuse
2400 * the EOI broadcast performed by cpu.
2401 * So, delay the irq migration to the next instance.
2403 schedule_delayed_work(&ir_migration_work
, 1);
2407 /* everthing is clear. we have right of way */
2408 migrate_ioapic_irq_desc(desc
, &desc
->pending_mask
);
2411 desc
->status
&= ~IRQ_MOVE_PENDING
;
2412 cpumask_clear(&desc
->pending_mask
);
2415 unmask_IO_APIC_irq_desc(desc
);
2420 static void ir_irq_migration(struct work_struct
*work
)
2423 struct irq_desc
*desc
;
2425 for_each_irq_desc(irq
, desc
) {
2426 if (desc
->status
& IRQ_MOVE_PENDING
) {
2427 unsigned long flags
;
2429 spin_lock_irqsave(&desc
->lock
, flags
);
2430 if (!desc
->chip
->set_affinity
||
2431 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2432 desc
->status
&= ~IRQ_MOVE_PENDING
;
2433 spin_unlock_irqrestore(&desc
->lock
, flags
);
2437 desc
->chip
->set_affinity(irq
, &desc
->pending_mask
);
2438 spin_unlock_irqrestore(&desc
->lock
, flags
);
2444 * Migrates the IRQ destination in the process context.
2446 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2447 const struct cpumask
*mask
)
2449 if (desc
->status
& IRQ_LEVEL
) {
2450 desc
->status
|= IRQ_MOVE_PENDING
;
2451 cpumask_copy(&desc
->pending_mask
, mask
);
2452 migrate_irq_remapped_level_desc(desc
);
2456 migrate_ioapic_irq_desc(desc
, mask
);
2458 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2459 const struct cpumask
*mask
)
2461 struct irq_desc
*desc
= irq_to_desc(irq
);
2463 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2467 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2469 unsigned vector
, me
;
2475 me
= smp_processor_id();
2476 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2478 struct irq_desc
*desc
;
2479 struct irq_cfg
*cfg
;
2480 irq
= __get_cpu_var(vector_irq
)[vector
];
2485 desc
= irq_to_desc(irq
);
2490 spin_lock(&desc
->lock
);
2491 if (!cfg
->move_cleanup_count
)
2494 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2497 __get_cpu_var(vector_irq
)[vector
] = -1;
2498 cfg
->move_cleanup_count
--;
2500 spin_unlock(&desc
->lock
);
2506 static void irq_complete_move(struct irq_desc
**descp
)
2508 struct irq_desc
*desc
= *descp
;
2509 struct irq_cfg
*cfg
= desc
->chip_data
;
2510 unsigned vector
, me
;
2512 if (likely(!cfg
->move_in_progress
)) {
2513 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2514 if (likely(!cfg
->move_desc_pending
))
2517 /* domain has not changed, but affinity did */
2518 me
= smp_processor_id();
2519 if (cpu_isset(me
, desc
->affinity
)) {
2520 *descp
= desc
= move_irq_desc(desc
, me
);
2521 /* get the new one */
2522 cfg
= desc
->chip_data
;
2523 cfg
->move_desc_pending
= 0;
2529 vector
= ~get_irq_regs()->orig_ax
;
2530 me
= smp_processor_id();
2531 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2532 *descp
= desc
= move_irq_desc(desc
, me
);
2533 /* get the new one */
2534 cfg
= desc
->chip_data
;
2537 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2538 send_cleanup_vector(cfg
);
2541 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2544 #ifdef CONFIG_INTR_REMAP
2545 static void ack_x2apic_level(unsigned int irq
)
2550 static void ack_x2apic_edge(unsigned int irq
)
2557 static void ack_apic_edge(unsigned int irq
)
2559 struct irq_desc
*desc
= irq_to_desc(irq
);
2561 irq_complete_move(&desc
);
2562 move_native_irq(irq
);
2566 atomic_t irq_mis_count
;
2568 static void ack_apic_level(unsigned int irq
)
2570 struct irq_desc
*desc
= irq_to_desc(irq
);
2572 #ifdef CONFIG_X86_32
2576 struct irq_cfg
*cfg
;
2577 int do_unmask_irq
= 0;
2579 irq_complete_move(&desc
);
2580 #ifdef CONFIG_GENERIC_PENDING_IRQ
2581 /* If we are moving the irq we need to mask it */
2582 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2584 mask_IO_APIC_irq_desc(desc
);
2588 #ifdef CONFIG_X86_32
2590 * It appears there is an erratum which affects at least version 0x11
2591 * of I/O APIC (that's the 82093AA and cores integrated into various
2592 * chipsets). Under certain conditions a level-triggered interrupt is
2593 * erroneously delivered as edge-triggered one but the respective IRR
2594 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2595 * message but it will never arrive and further interrupts are blocked
2596 * from the source. The exact reason is so far unknown, but the
2597 * phenomenon was observed when two consecutive interrupt requests
2598 * from a given source get delivered to the same CPU and the source is
2599 * temporarily disabled in between.
2601 * A workaround is to simulate an EOI message manually. We achieve it
2602 * by setting the trigger mode to edge and then to level when the edge
2603 * trigger mode gets detected in the TMR of a local APIC for a
2604 * level-triggered interrupt. We mask the source for the time of the
2605 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2606 * The idea is from Manfred Spraul. --macro
2608 cfg
= desc
->chip_data
;
2611 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2615 * We must acknowledge the irq before we move it or the acknowledge will
2616 * not propagate properly.
2620 /* Now we can move and renable the irq */
2621 if (unlikely(do_unmask_irq
)) {
2622 /* Only migrate the irq if the ack has been received.
2624 * On rare occasions the broadcast level triggered ack gets
2625 * delayed going to ioapics, and if we reprogram the
2626 * vector while Remote IRR is still set the irq will never
2629 * To prevent this scenario we read the Remote IRR bit
2630 * of the ioapic. This has two effects.
2631 * - On any sane system the read of the ioapic will
2632 * flush writes (and acks) going to the ioapic from
2634 * - We get to see if the ACK has actually been delivered.
2636 * Based on failed experiments of reprogramming the
2637 * ioapic entry from outside of irq context starting
2638 * with masking the ioapic entry and then polling until
2639 * Remote IRR was clear before reprogramming the
2640 * ioapic I don't trust the Remote IRR bit to be
2641 * completey accurate.
2643 * However there appears to be no other way to plug
2644 * this race, so if the Remote IRR bit is not
2645 * accurate and is causing problems then it is a hardware bug
2646 * and you can go talk to the chipset vendor about it.
2648 cfg
= desc
->chip_data
;
2649 if (!io_apic_level_ack_pending(cfg
))
2650 move_masked_irq(irq
);
2651 unmask_IO_APIC_irq_desc(desc
);
2654 #ifdef CONFIG_X86_32
2655 if (!(v
& (1 << (i
& 0x1f)))) {
2656 atomic_inc(&irq_mis_count
);
2657 spin_lock(&ioapic_lock
);
2658 __mask_and_edge_IO_APIC_irq(cfg
);
2659 __unmask_and_level_IO_APIC_irq(cfg
);
2660 spin_unlock(&ioapic_lock
);
2665 static struct irq_chip ioapic_chip __read_mostly
= {
2667 .startup
= startup_ioapic_irq
,
2668 .mask
= mask_IO_APIC_irq
,
2669 .unmask
= unmask_IO_APIC_irq
,
2670 .ack
= ack_apic_edge
,
2671 .eoi
= ack_apic_level
,
2673 .set_affinity
= set_ioapic_affinity_irq
,
2675 .retrigger
= ioapic_retrigger_irq
,
2678 #ifdef CONFIG_INTR_REMAP
2679 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2680 .name
= "IR-IO-APIC",
2681 .startup
= startup_ioapic_irq
,
2682 .mask
= mask_IO_APIC_irq
,
2683 .unmask
= unmask_IO_APIC_irq
,
2684 .ack
= ack_x2apic_edge
,
2685 .eoi
= ack_x2apic_level
,
2687 .set_affinity
= set_ir_ioapic_affinity_irq
,
2689 .retrigger
= ioapic_retrigger_irq
,
2693 static inline void init_IO_APIC_traps(void)
2696 struct irq_desc
*desc
;
2697 struct irq_cfg
*cfg
;
2700 * NOTE! The local APIC isn't very good at handling
2701 * multiple interrupts at the same interrupt level.
2702 * As the interrupt level is determined by taking the
2703 * vector number and shifting that right by 4, we
2704 * want to spread these out a bit so that they don't
2705 * all fall in the same interrupt level.
2707 * Also, we've got to be careful not to trash gate
2708 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2710 for_each_irq_desc(irq
, desc
) {
2711 cfg
= desc
->chip_data
;
2712 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2714 * Hmm.. We don't have an entry for this,
2715 * so default to an old-fashioned 8259
2716 * interrupt if we can..
2718 if (irq
< NR_IRQS_LEGACY
)
2719 make_8259A_irq(irq
);
2721 /* Strange. Oh, well.. */
2722 desc
->chip
= &no_irq_chip
;
2728 * The local APIC irq-chip implementation:
2731 static void mask_lapic_irq(unsigned int irq
)
2735 v
= apic_read(APIC_LVT0
);
2736 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2739 static void unmask_lapic_irq(unsigned int irq
)
2743 v
= apic_read(APIC_LVT0
);
2744 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2747 static void ack_lapic_irq(unsigned int irq
)
2752 static struct irq_chip lapic_chip __read_mostly
= {
2753 .name
= "local-APIC",
2754 .mask
= mask_lapic_irq
,
2755 .unmask
= unmask_lapic_irq
,
2756 .ack
= ack_lapic_irq
,
2759 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2761 desc
->status
&= ~IRQ_LEVEL
;
2762 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2766 static void __init
setup_nmi(void)
2769 * Dirty trick to enable the NMI watchdog ...
2770 * We put the 8259A master into AEOI mode and
2771 * unmask on all local APICs LVT0 as NMI.
2773 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2774 * is from Maciej W. Rozycki - so we do not have to EOI from
2775 * the NMI handler or the timer interrupt.
2777 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2779 enable_NMI_through_LVT0();
2781 apic_printk(APIC_VERBOSE
, " done.\n");
2785 * This looks a bit hackish but it's about the only one way of sending
2786 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2787 * not support the ExtINT mode, unfortunately. We need to send these
2788 * cycles as some i82489DX-based boards have glue logic that keeps the
2789 * 8259A interrupt line asserted until INTA. --macro
2791 static inline void __init
unlock_ExtINT_logic(void)
2794 struct IO_APIC_route_entry entry0
, entry1
;
2795 unsigned char save_control
, save_freq_select
;
2797 pin
= find_isa_irq_pin(8, mp_INT
);
2802 apic
= find_isa_irq_apic(8, mp_INT
);
2808 entry0
= ioapic_read_entry(apic
, pin
);
2809 clear_IO_APIC_pin(apic
, pin
);
2811 memset(&entry1
, 0, sizeof(entry1
));
2813 entry1
.dest_mode
= 0; /* physical delivery */
2814 entry1
.mask
= 0; /* unmask IRQ now */
2815 entry1
.dest
= hard_smp_processor_id();
2816 entry1
.delivery_mode
= dest_ExtINT
;
2817 entry1
.polarity
= entry0
.polarity
;
2821 ioapic_write_entry(apic
, pin
, entry1
);
2823 save_control
= CMOS_READ(RTC_CONTROL
);
2824 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2825 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2827 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2832 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2836 CMOS_WRITE(save_control
, RTC_CONTROL
);
2837 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2838 clear_IO_APIC_pin(apic
, pin
);
2840 ioapic_write_entry(apic
, pin
, entry0
);
2843 static int disable_timer_pin_1 __initdata
;
2844 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2845 static int __init
disable_timer_pin_setup(char *arg
)
2847 disable_timer_pin_1
= 1;
2850 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2852 int timer_through_8259 __initdata
;
2855 * This code may look a bit paranoid, but it's supposed to cooperate with
2856 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2857 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2858 * fanatically on his truly buggy board.
2860 * FIXME: really need to revamp this for all platforms.
2862 static inline void __init
check_timer(void)
2864 struct irq_desc
*desc
= irq_to_desc(0);
2865 struct irq_cfg
*cfg
= desc
->chip_data
;
2866 int cpu
= boot_cpu_id
;
2867 int apic1
, pin1
, apic2
, pin2
;
2868 unsigned long flags
;
2872 local_irq_save(flags
);
2874 ver
= apic_read(APIC_LVR
);
2875 ver
= GET_APIC_VERSION(ver
);
2878 * get/set the timer IRQ vector:
2880 disable_8259A_irq(0);
2881 assign_irq_vector(0, cfg
, TARGET_CPUS
);
2884 * As IRQ0 is to be enabled in the 8259A, the virtual
2885 * wire has to be disabled in the local APIC. Also
2886 * timer interrupts need to be acknowledged manually in
2887 * the 8259A for the i82489DX when using the NMI
2888 * watchdog as that APIC treats NMIs as level-triggered.
2889 * The AEOI mode will finish them in the 8259A
2892 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2894 #ifdef CONFIG_X86_32
2895 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2898 pin1
= find_isa_irq_pin(0, mp_INT
);
2899 apic1
= find_isa_irq_apic(0, mp_INT
);
2900 pin2
= ioapic_i8259
.pin
;
2901 apic2
= ioapic_i8259
.apic
;
2903 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2904 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2905 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2908 * Some BIOS writers are clueless and report the ExtINTA
2909 * I/O APIC input from the cascaded 8259A as the timer
2910 * interrupt input. So just in case, if only one pin
2911 * was found above, try it both directly and through the
2915 #ifdef CONFIG_INTR_REMAP
2916 if (intr_remapping_enabled
)
2917 panic("BIOS bug: timer not connected to IO-APIC");
2922 } else if (pin2
== -1) {
2929 * Ok, does IRQ0 through the IOAPIC work?
2932 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2933 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2935 unmask_IO_APIC_irq_desc(desc
);
2936 if (timer_irq_works()) {
2937 if (nmi_watchdog
== NMI_IO_APIC
) {
2939 enable_8259A_irq(0);
2941 if (disable_timer_pin_1
> 0)
2942 clear_IO_APIC_pin(0, pin1
);
2945 #ifdef CONFIG_INTR_REMAP
2946 if (intr_remapping_enabled
)
2947 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2949 clear_IO_APIC_pin(apic1
, pin1
);
2951 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2952 "8254 timer not connected to IO-APIC\n");
2954 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2955 "(IRQ0) through the 8259A ...\n");
2956 apic_printk(APIC_QUIET
, KERN_INFO
2957 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2959 * legacy devices should be connected to IO APIC #0
2961 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
2962 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2963 unmask_IO_APIC_irq_desc(desc
);
2964 enable_8259A_irq(0);
2965 if (timer_irq_works()) {
2966 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2967 timer_through_8259
= 1;
2968 if (nmi_watchdog
== NMI_IO_APIC
) {
2969 disable_8259A_irq(0);
2971 enable_8259A_irq(0);
2976 * Cleanup, just in case ...
2978 disable_8259A_irq(0);
2979 clear_IO_APIC_pin(apic2
, pin2
);
2980 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2983 if (nmi_watchdog
== NMI_IO_APIC
) {
2984 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2985 "through the IO-APIC - disabling NMI Watchdog!\n");
2986 nmi_watchdog
= NMI_NONE
;
2988 #ifdef CONFIG_X86_32
2992 apic_printk(APIC_QUIET
, KERN_INFO
2993 "...trying to set up timer as Virtual Wire IRQ...\n");
2995 lapic_register_intr(0, desc
);
2996 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2997 enable_8259A_irq(0);
2999 if (timer_irq_works()) {
3000 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3003 disable_8259A_irq(0);
3004 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3005 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3007 apic_printk(APIC_QUIET
, KERN_INFO
3008 "...trying to set up timer as ExtINT IRQ...\n");
3012 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3014 unlock_ExtINT_logic();
3016 if (timer_irq_works()) {
3017 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3020 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3021 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3022 "report. Then try booting with the 'noapic' option.\n");
3024 local_irq_restore(flags
);
3028 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3029 * to devices. However there may be an I/O APIC pin available for
3030 * this interrupt regardless. The pin may be left unconnected, but
3031 * typically it will be reused as an ExtINT cascade interrupt for
3032 * the master 8259A. In the MPS case such a pin will normally be
3033 * reported as an ExtINT interrupt in the MP table. With ACPI
3034 * there is no provision for ExtINT interrupts, and in the absence
3035 * of an override it would be treated as an ordinary ISA I/O APIC
3036 * interrupt, that is edge-triggered and unmasked by default. We
3037 * used to do this, but it caused problems on some systems because
3038 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3039 * the same ExtINT cascade interrupt to drive the local APIC of the
3040 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3041 * the I/O APIC in all cases now. No actual device should request
3042 * it anyway. --macro
3044 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3046 void __init
setup_IO_APIC(void)
3049 #ifdef CONFIG_X86_32
3053 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3057 io_apic_irqs
= ~PIC_IRQS
;
3059 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3061 * Set up IO-APIC IRQ routing.
3063 #ifdef CONFIG_X86_32
3065 setup_ioapic_ids_from_mpc();
3068 setup_IO_APIC_irqs();
3069 init_IO_APIC_traps();
3074 * Called after all the initialization is done. If we didnt find any
3075 * APIC bugs then we can allow the modify fast path
3078 static int __init
io_apic_bug_finalize(void)
3080 if (sis_apic_bug
== -1)
3085 late_initcall(io_apic_bug_finalize
);
3087 struct sysfs_ioapic_data
{
3088 struct sys_device dev
;
3089 struct IO_APIC_route_entry entry
[0];
3091 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3093 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3095 struct IO_APIC_route_entry
*entry
;
3096 struct sysfs_ioapic_data
*data
;
3099 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3100 entry
= data
->entry
;
3101 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3102 *entry
= ioapic_read_entry(dev
->id
, i
);
3107 static int ioapic_resume(struct sys_device
*dev
)
3109 struct IO_APIC_route_entry
*entry
;
3110 struct sysfs_ioapic_data
*data
;
3111 unsigned long flags
;
3112 union IO_APIC_reg_00 reg_00
;
3115 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3116 entry
= data
->entry
;
3118 spin_lock_irqsave(&ioapic_lock
, flags
);
3119 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3120 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
3121 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
3122 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3124 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3125 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3126 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3131 static struct sysdev_class ioapic_sysdev_class
= {
3133 .suspend
= ioapic_suspend
,
3134 .resume
= ioapic_resume
,
3137 static int __init
ioapic_init_sysfs(void)
3139 struct sys_device
* dev
;
3142 error
= sysdev_class_register(&ioapic_sysdev_class
);
3146 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3147 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3148 * sizeof(struct IO_APIC_route_entry
);
3149 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3150 if (!mp_ioapic_data
[i
]) {
3151 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3154 dev
= &mp_ioapic_data
[i
]->dev
;
3156 dev
->cls
= &ioapic_sysdev_class
;
3157 error
= sysdev_register(dev
);
3159 kfree(mp_ioapic_data
[i
]);
3160 mp_ioapic_data
[i
] = NULL
;
3161 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3169 device_initcall(ioapic_init_sysfs
);
3172 * Dynamic irq allocate and deallocation
3174 unsigned int create_irq_nr(unsigned int irq_want
)
3176 /* Allocate an unused irq */
3179 unsigned long flags
;
3180 struct irq_cfg
*cfg_new
= NULL
;
3181 int cpu
= boot_cpu_id
;
3182 struct irq_desc
*desc_new
= NULL
;
3185 spin_lock_irqsave(&vector_lock
, flags
);
3186 for (new = irq_want
; new < NR_IRQS
; new++) {
3187 if (platform_legacy_irq(new))
3190 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3192 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3195 cfg_new
= desc_new
->chip_data
;
3197 if (cfg_new
->vector
!= 0)
3199 if (__assign_irq_vector(new, cfg_new
, TARGET_CPUS
) == 0)
3203 spin_unlock_irqrestore(&vector_lock
, flags
);
3206 dynamic_irq_init(irq
);
3207 /* restore it, in case dynamic_irq_init clear it */
3209 desc_new
->chip_data
= cfg_new
;
3214 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3215 int create_irq(void)
3217 unsigned int irq_want
;
3220 irq_want
= nr_irqs_gsi
;
3221 irq
= create_irq_nr(irq_want
);
3229 void destroy_irq(unsigned int irq
)
3231 unsigned long flags
;
3232 struct irq_cfg
*cfg
;
3233 struct irq_desc
*desc
;
3235 /* store it, in case dynamic_irq_cleanup clear it */
3236 desc
= irq_to_desc(irq
);
3237 cfg
= desc
->chip_data
;
3238 dynamic_irq_cleanup(irq
);
3239 /* connect back irq_cfg */
3241 desc
->chip_data
= cfg
;
3243 #ifdef CONFIG_INTR_REMAP
3246 spin_lock_irqsave(&vector_lock
, flags
);
3247 __clear_irq_vector(irq
, cfg
);
3248 spin_unlock_irqrestore(&vector_lock
, flags
);
3252 * MSI message composition
3254 #ifdef CONFIG_PCI_MSI
3255 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3257 struct irq_cfg
*cfg
;
3262 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3266 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3268 #ifdef CONFIG_INTR_REMAP
3269 if (irq_remapped(irq
)) {
3274 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3275 BUG_ON(ir_index
== -1);
3277 memset (&irte
, 0, sizeof(irte
));
3280 irte
.dst_mode
= INT_DEST_MODE
;
3281 irte
.trigger_mode
= 0; /* edge */
3282 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3283 irte
.vector
= cfg
->vector
;
3284 irte
.dest_id
= IRTE_DEST(dest
);
3286 modify_irte(irq
, &irte
);
3288 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3289 msg
->data
= sub_handle
;
3290 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3292 MSI_ADDR_IR_INDEX1(ir_index
) |
3293 MSI_ADDR_IR_INDEX2(ir_index
);
3297 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3300 ((INT_DEST_MODE
== 0) ?
3301 MSI_ADDR_DEST_MODE_PHYSICAL
:
3302 MSI_ADDR_DEST_MODE_LOGICAL
) |
3303 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3304 MSI_ADDR_REDIRECTION_CPU
:
3305 MSI_ADDR_REDIRECTION_LOWPRI
) |
3306 MSI_ADDR_DEST_ID(dest
);
3309 MSI_DATA_TRIGGER_EDGE
|
3310 MSI_DATA_LEVEL_ASSERT
|
3311 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3312 MSI_DATA_DELIVERY_FIXED
:
3313 MSI_DATA_DELIVERY_LOWPRI
) |
3314 MSI_DATA_VECTOR(cfg
->vector
);
3320 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3322 struct irq_desc
*desc
= irq_to_desc(irq
);
3323 struct irq_cfg
*cfg
;
3327 dest
= set_desc_affinity(desc
, mask
);
3328 if (dest
== BAD_APICID
)
3331 cfg
= desc
->chip_data
;
3333 read_msi_msg_desc(desc
, &msg
);
3335 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3336 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3337 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3338 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3340 write_msi_msg_desc(desc
, &msg
);
3342 #ifdef CONFIG_INTR_REMAP
3344 * Migrate the MSI irq to another cpumask. This migration is
3345 * done in the process context using interrupt-remapping hardware.
3348 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3350 struct irq_desc
*desc
= irq_to_desc(irq
);
3351 struct irq_cfg
*cfg
= desc
->chip_data
;
3355 if (get_irte(irq
, &irte
))
3358 dest
= set_desc_affinity(desc
, mask
);
3359 if (dest
== BAD_APICID
)
3362 irte
.vector
= cfg
->vector
;
3363 irte
.dest_id
= IRTE_DEST(dest
);
3366 * atomically update the IRTE with the new destination and vector.
3368 modify_irte(irq
, &irte
);
3371 * After this point, all the interrupts will start arriving
3372 * at the new destination. So, time to cleanup the previous
3373 * vector allocation.
3375 if (cfg
->move_in_progress
)
3376 send_cleanup_vector(cfg
);
3380 #endif /* CONFIG_SMP */
3383 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3384 * which implement the MSI or MSI-X Capability Structure.
3386 static struct irq_chip msi_chip
= {
3388 .unmask
= unmask_msi_irq
,
3389 .mask
= mask_msi_irq
,
3390 .ack
= ack_apic_edge
,
3392 .set_affinity
= set_msi_irq_affinity
,
3394 .retrigger
= ioapic_retrigger_irq
,
3397 #ifdef CONFIG_INTR_REMAP
3398 static struct irq_chip msi_ir_chip
= {
3399 .name
= "IR-PCI-MSI",
3400 .unmask
= unmask_msi_irq
,
3401 .mask
= mask_msi_irq
,
3402 .ack
= ack_x2apic_edge
,
3404 .set_affinity
= ir_set_msi_irq_affinity
,
3406 .retrigger
= ioapic_retrigger_irq
,
3410 * Map the PCI dev to the corresponding remapping hardware unit
3411 * and allocate 'nvec' consecutive interrupt-remapping table entries
3414 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3416 struct intel_iommu
*iommu
;
3419 iommu
= map_dev_to_ir(dev
);
3422 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3426 index
= alloc_irte(iommu
, irq
, nvec
);
3429 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3437 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3442 ret
= msi_compose_msg(dev
, irq
, &msg
);
3446 set_irq_msi(irq
, msidesc
);
3447 write_msi_msg(irq
, &msg
);
3449 #ifdef CONFIG_INTR_REMAP
3450 if (irq_remapped(irq
)) {
3451 struct irq_desc
*desc
= irq_to_desc(irq
);
3453 * irq migration in process context
3455 desc
->status
|= IRQ_MOVE_PCNTXT
;
3456 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3459 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3461 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3466 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
)
3470 unsigned int irq_want
;
3472 irq_want
= nr_irqs_gsi
;
3473 irq
= create_irq_nr(irq_want
);
3477 #ifdef CONFIG_INTR_REMAP
3478 if (!intr_remapping_enabled
)
3481 ret
= msi_alloc_irte(dev
, irq
, 1);
3486 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3493 #ifdef CONFIG_INTR_REMAP
3500 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3503 int ret
, sub_handle
;
3504 struct msi_desc
*msidesc
;
3505 unsigned int irq_want
;
3507 #ifdef CONFIG_INTR_REMAP
3508 struct intel_iommu
*iommu
= 0;
3512 irq_want
= nr_irqs_gsi
;
3514 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3515 irq
= create_irq_nr(irq_want
);
3519 #ifdef CONFIG_INTR_REMAP
3520 if (!intr_remapping_enabled
)
3525 * allocate the consecutive block of IRTE's
3528 index
= msi_alloc_irte(dev
, irq
, nvec
);
3534 iommu
= map_dev_to_ir(dev
);
3540 * setup the mapping between the irq and the IRTE
3541 * base index, the sub_handle pointing to the
3542 * appropriate interrupt remap table entry.
3544 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3548 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3560 void arch_teardown_msi_irq(unsigned int irq
)
3567 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3569 struct irq_desc
*desc
= irq_to_desc(irq
);
3570 struct irq_cfg
*cfg
;
3574 dest
= set_desc_affinity(desc
, mask
);
3575 if (dest
== BAD_APICID
)
3578 cfg
= desc
->chip_data
;
3580 dmar_msi_read(irq
, &msg
);
3582 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3583 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3584 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3585 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3587 dmar_msi_write(irq
, &msg
);
3590 #endif /* CONFIG_SMP */
3592 struct irq_chip dmar_msi_type
= {
3594 .unmask
= dmar_msi_unmask
,
3595 .mask
= dmar_msi_mask
,
3596 .ack
= ack_apic_edge
,
3598 .set_affinity
= dmar_msi_set_affinity
,
3600 .retrigger
= ioapic_retrigger_irq
,
3603 int arch_setup_dmar_msi(unsigned int irq
)
3608 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3611 dmar_msi_write(irq
, &msg
);
3612 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3618 #ifdef CONFIG_HPET_TIMER
3621 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3623 struct irq_desc
*desc
= irq_to_desc(irq
);
3624 struct irq_cfg
*cfg
;
3628 dest
= set_desc_affinity(desc
, mask
);
3629 if (dest
== BAD_APICID
)
3632 cfg
= desc
->chip_data
;
3634 hpet_msi_read(irq
, &msg
);
3636 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3637 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3638 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3639 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3641 hpet_msi_write(irq
, &msg
);
3644 #endif /* CONFIG_SMP */
3646 struct irq_chip hpet_msi_type
= {
3648 .unmask
= hpet_msi_unmask
,
3649 .mask
= hpet_msi_mask
,
3650 .ack
= ack_apic_edge
,
3652 .set_affinity
= hpet_msi_set_affinity
,
3654 .retrigger
= ioapic_retrigger_irq
,
3657 int arch_setup_hpet_msi(unsigned int irq
)
3662 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3666 hpet_msi_write(irq
, &msg
);
3667 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3674 #endif /* CONFIG_PCI_MSI */
3676 * Hypertransport interrupt support
3678 #ifdef CONFIG_HT_IRQ
3682 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3684 struct ht_irq_msg msg
;
3685 fetch_ht_irq_msg(irq
, &msg
);
3687 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3688 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3690 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3691 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3693 write_ht_irq_msg(irq
, &msg
);
3696 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3698 struct irq_desc
*desc
= irq_to_desc(irq
);
3699 struct irq_cfg
*cfg
;
3702 dest
= set_desc_affinity(desc
, mask
);
3703 if (dest
== BAD_APICID
)
3706 cfg
= desc
->chip_data
;
3708 target_ht_irq(irq
, dest
, cfg
->vector
);
3713 static struct irq_chip ht_irq_chip
= {
3715 .mask
= mask_ht_irq
,
3716 .unmask
= unmask_ht_irq
,
3717 .ack
= ack_apic_edge
,
3719 .set_affinity
= set_ht_irq_affinity
,
3721 .retrigger
= ioapic_retrigger_irq
,
3724 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3726 struct irq_cfg
*cfg
;
3730 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3732 struct ht_irq_msg msg
;
3735 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3737 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3741 HT_IRQ_LOW_DEST_ID(dest
) |
3742 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3743 ((INT_DEST_MODE
== 0) ?
3744 HT_IRQ_LOW_DM_PHYSICAL
:
3745 HT_IRQ_LOW_DM_LOGICAL
) |
3746 HT_IRQ_LOW_RQEOI_EDGE
|
3747 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3748 HT_IRQ_LOW_MT_FIXED
:
3749 HT_IRQ_LOW_MT_ARBITRATED
) |
3750 HT_IRQ_LOW_IRQ_MASKED
;
3752 write_ht_irq_msg(irq
, &msg
);
3754 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3755 handle_edge_irq
, "edge");
3757 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3761 #endif /* CONFIG_HT_IRQ */
3763 #ifdef CONFIG_X86_64
3765 * Re-target the irq to the specified CPU and enable the specified MMR located
3766 * on the specified blade to allow the sending of MSIs to the specified CPU.
3768 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3769 unsigned long mmr_offset
)
3771 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3772 struct irq_cfg
*cfg
;
3774 unsigned long mmr_value
;
3775 struct uv_IO_APIC_route_entry
*entry
;
3776 unsigned long flags
;
3781 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3785 spin_lock_irqsave(&vector_lock
, flags
);
3786 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3788 spin_unlock_irqrestore(&vector_lock
, flags
);
3791 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3792 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3794 entry
->vector
= cfg
->vector
;
3795 entry
->delivery_mode
= INT_DELIVERY_MODE
;
3796 entry
->dest_mode
= INT_DEST_MODE
;
3797 entry
->polarity
= 0;
3800 entry
->dest
= cpu_mask_to_apicid(eligible_cpu
);
3802 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3803 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3809 * Disable the specified MMR located on the specified blade so that MSIs are
3810 * longer allowed to be sent.
3812 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3814 unsigned long mmr_value
;
3815 struct uv_IO_APIC_route_entry
*entry
;
3819 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3820 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3824 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3825 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3827 #endif /* CONFIG_X86_64 */
3829 int __init
io_apic_get_redir_entries (int ioapic
)
3831 union IO_APIC_reg_01 reg_01
;
3832 unsigned long flags
;
3834 spin_lock_irqsave(&ioapic_lock
, flags
);
3835 reg_01
.raw
= io_apic_read(ioapic
, 1);
3836 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3838 return reg_01
.bits
.entries
;
3841 void __init
probe_nr_irqs_gsi(void)
3846 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3847 nr
+= io_apic_get_redir_entries(idx
) + 1;
3849 if (nr
> nr_irqs_gsi
)
3853 /* --------------------------------------------------------------------------
3854 ACPI-based IOAPIC Configuration
3855 -------------------------------------------------------------------------- */
3859 #ifdef CONFIG_X86_32
3860 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3862 union IO_APIC_reg_00 reg_00
;
3863 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3865 unsigned long flags
;
3869 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3870 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3871 * supports up to 16 on one shared APIC bus.
3873 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3874 * advantage of new APIC bus architecture.
3877 if (physids_empty(apic_id_map
))
3878 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3880 spin_lock_irqsave(&ioapic_lock
, flags
);
3881 reg_00
.raw
= io_apic_read(ioapic
, 0);
3882 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3884 if (apic_id
>= get_physical_broadcast()) {
3885 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3886 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3887 apic_id
= reg_00
.bits
.ID
;
3891 * Every APIC in a system must have a unique ID or we get lots of nice
3892 * 'stuck on smp_invalidate_needed IPI wait' messages.
3894 if (check_apicid_used(apic_id_map
, apic_id
)) {
3896 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3897 if (!check_apicid_used(apic_id_map
, i
))
3901 if (i
== get_physical_broadcast())
3902 panic("Max apic_id exceeded!\n");
3904 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3905 "trying %d\n", ioapic
, apic_id
, i
);
3910 tmp
= apicid_to_cpu_present(apic_id
);
3911 physids_or(apic_id_map
, apic_id_map
, tmp
);
3913 if (reg_00
.bits
.ID
!= apic_id
) {
3914 reg_00
.bits
.ID
= apic_id
;
3916 spin_lock_irqsave(&ioapic_lock
, flags
);
3917 io_apic_write(ioapic
, 0, reg_00
.raw
);
3918 reg_00
.raw
= io_apic_read(ioapic
, 0);
3919 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3922 if (reg_00
.bits
.ID
!= apic_id
) {
3923 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3928 apic_printk(APIC_VERBOSE
, KERN_INFO
3929 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3934 int __init
io_apic_get_version(int ioapic
)
3936 union IO_APIC_reg_01 reg_01
;
3937 unsigned long flags
;
3939 spin_lock_irqsave(&ioapic_lock
, flags
);
3940 reg_01
.raw
= io_apic_read(ioapic
, 1);
3941 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3943 return reg_01
.bits
.version
;
3947 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3949 struct irq_desc
*desc
;
3950 struct irq_cfg
*cfg
;
3951 int cpu
= boot_cpu_id
;
3953 if (!IO_APIC_IRQ(irq
)) {
3954 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3959 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
3961 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3966 * IRQs < 16 are already in the irq_2_pin[] map
3968 if (irq
>= NR_IRQS_LEGACY
) {
3969 cfg
= desc
->chip_data
;
3970 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
3973 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3979 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3983 if (skip_ioapic_setup
)
3986 for (i
= 0; i
< mp_irq_entries
; i
++)
3987 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3988 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3990 if (i
>= mp_irq_entries
)
3993 *trigger
= irq_trigger(i
);
3994 *polarity
= irq_polarity(i
);
3998 #endif /* CONFIG_ACPI */
4001 * This function currently is only a helper for the i386 smp boot process where
4002 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4003 * so mask in all cases should simply be TARGET_CPUS
4006 void __init
setup_ioapic_dest(void)
4008 int pin
, ioapic
, irq
, irq_entry
;
4009 struct irq_desc
*desc
;
4010 struct irq_cfg
*cfg
;
4011 const struct cpumask
*mask
;
4013 if (skip_ioapic_setup
== 1)
4016 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
4017 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4018 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4019 if (irq_entry
== -1)
4021 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4023 /* setup_IO_APIC_irqs could fail to get vector for some device
4024 * when you have too many devices, because at that time only boot
4027 desc
= irq_to_desc(irq
);
4028 cfg
= desc
->chip_data
;
4030 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4031 irq_trigger(irq_entry
),
4032 irq_polarity(irq_entry
));
4038 * Honour affinities which have been set in early boot
4041 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4042 mask
= &desc
->affinity
;
4046 #ifdef CONFIG_INTR_REMAP
4047 if (intr_remapping_enabled
)
4048 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4051 set_ioapic_affinity_irq_desc(desc
, mask
);
4058 #define IOAPIC_RESOURCE_NAME_SIZE 11
4060 static struct resource
*ioapic_resources
;
4062 static struct resource
* __init
ioapic_setup_resources(void)
4065 struct resource
*res
;
4069 if (nr_ioapics
<= 0)
4072 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4075 mem
= alloc_bootmem(n
);
4079 mem
+= sizeof(struct resource
) * nr_ioapics
;
4081 for (i
= 0; i
< nr_ioapics
; i
++) {
4083 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4084 sprintf(mem
, "IOAPIC %u", i
);
4085 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4089 ioapic_resources
= res
;
4094 void __init
ioapic_init_mappings(void)
4096 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4097 struct resource
*ioapic_res
;
4100 ioapic_res
= ioapic_setup_resources();
4101 for (i
= 0; i
< nr_ioapics
; i
++) {
4102 if (smp_found_config
) {
4103 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
4104 #ifdef CONFIG_X86_32
4107 "WARNING: bogus zero IO-APIC "
4108 "address found in MPTABLE, "
4109 "disabling IO/APIC support!\n");
4110 smp_found_config
= 0;
4111 skip_ioapic_setup
= 1;
4112 goto fake_ioapic_page
;
4116 #ifdef CONFIG_X86_32
4119 ioapic_phys
= (unsigned long)
4120 alloc_bootmem_pages(PAGE_SIZE
);
4121 ioapic_phys
= __pa(ioapic_phys
);
4123 set_fixmap_nocache(idx
, ioapic_phys
);
4124 apic_printk(APIC_VERBOSE
,
4125 "mapped IOAPIC to %08lx (%08lx)\n",
4126 __fix_to_virt(idx
), ioapic_phys
);
4129 if (ioapic_res
!= NULL
) {
4130 ioapic_res
->start
= ioapic_phys
;
4131 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4137 static int __init
ioapic_insert_resources(void)
4140 struct resource
*r
= ioapic_resources
;
4144 "IO APIC resources could be not be allocated.\n");
4148 for (i
= 0; i
< nr_ioapics
; i
++) {
4149 insert_resource(&iomem_resource
, r
);
4156 /* Insert the IO APIC resources after PCI initialization has occured to handle
4157 * IO APICS that are mapped in on a BAR in PCI space. */
4158 late_initcall(ioapic_insert_resources
);