include/asm-arm/arch-s3c2410/regs-nand.h

   1 /* linux/include/asm-arm/arch-s3c2410/regs-nand.h
   2  *
   3  * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 NAND register definitions
  11  *
  12  *  Changelog:
  13  *    18-Aug-2004    BJD     Copied file from 2.4 and updated
  14  *    01-May-2005    BJD     Added definitions for s3c2440 controller
  15 */
  16
  17 #ifndef __ASM_ARM_REGS_NAND
  18 #define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
  19
  20
  21 #define S3C2410_NFREG(x) (x)
  22
  23 #define S3C2410_NFCONF  S3C2410_NFREG(0x00)
  24 #define S3C2410_NFCMD   S3C2410_NFREG(0x04)
  25 #define S3C2410_NFADDR  S3C2410_NFREG(0x08)
  26 #define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
  27 #define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
  28 #define S3C2410_NFECC   S3C2410_NFREG(0x14)
  29
  30 #define S3C2440_NFCONT   S3C2410_NFREG(0x04)
  31 #define S3C2440_NFCMD    S3C2410_NFREG(0x08)
  32 #define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
  33 #define S3C2440_NFDATA   S3C2410_NFREG(0x10)
  34 #define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
  35 #define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
  36 #define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
  37 #define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
  38 #define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
  39 #define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
  40 #define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
  41 #define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
  42 #define S3C2440_NFSECC   S3C24E10_NFREG(0x34)
  43 #define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
  44 #define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
  45
  46 #define S3C2412_NFSBLK          S3C2410_NFREG(0x20)
  47 #define S3C2412_NFEBLK          S3C2410_NFREG(0x24)
  48 #define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
  49 #define S3C2412_NFMECC_ERR0     S3C2410_NFREG(0x2C)
  50 #define S3C2412_NFMECC_ERR1     S3C2410_NFREG(0x30)
  51 #define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
  52 #define S3C2412_NFMECC1         S3C2410_NFREG(0x38)
  53 #define S3C2412_NFSECC          S3C2410_NFREG(0x3C)
  54
  55 #define S3C2410_NFCONF_EN          (1<<15)
  56 #define S3C2410_NFCONF_512BYTE     (1<<14)
  57 #define S3C2410_NFCONF_4STEP       (1<<13)
  58 #define S3C2410_NFCONF_INITECC     (1<<12)
  59 #define S3C2410_NFCONF_nFCE        (1<<11)
  60 #define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
  61 #define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
  62 #define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
  63
  64 #define S3C2410_NFSTAT_BUSY        (1<<0)
  65
  66 #define S3C2440_NFCONF_BUSWIDTH_8       (0<<0)
  67 #define S3C2440_NFCONF_BUSWIDTH_16      (1<<0)
  68 #define S3C2440_NFCONF_ADVFLASH         (1<<3)
  69 #define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
  70 #define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
  71 #define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
  72
  73 #define S3C2440_NFCONT_LOCKTIGHT        (1<<13)
  74 #define S3C2440_NFCONT_SOFTLOCK         (1<<12)
  75 #define S3C2440_NFCONT_ILLEGALACC_EN    (1<<10)
  76 #define S3C2440_NFCONT_RNBINT_EN        (1<<9)
  77 #define S3C2440_NFCONT_RN_FALLING       (1<<8)
  78 #define S3C2440_NFCONT_SPARE_ECCLOCK    (1<<6)
  79 #define S3C2440_NFCONT_MAIN_ECCLOCK     (1<<5)
  80 #define S3C2440_NFCONT_INITECC          (1<<4)
  81 #define S3C2440_NFCONT_nFCE             (1<<1)
  82 #define S3C2440_NFCONT_ENABLE           (1<<0)
  83
  84 #define S3C2440_NFSTAT_READY            (1<<0)
  85 #define S3C2440_NFSTAT_nCE              (1<<1)
  86 #define S3C2440_NFSTAT_RnB_CHANGE       (1<<2)
  87 #define S3C2440_NFSTAT_ILLEGAL_ACCESS   (1<<3)
  88
  89 #define S3C2412_NFCONF_NANDBOOT         (1<<31)
  90 #define S3C2412_NFCONF_ECCCLKCON        (1<<30)
  91 #define S3C2412_NFCONF_ECC_MLC          (1<<24)
  92 #define S3C2412_NFCONF_TACLS_MASK       (7<<12) /* 1 extra bit of Tacls */
  93
  94 #define S3C2412_NFCONT_ECC4_DIRWR       (1<<18)
  95 #define S3C2412_NFCONT_LOCKTIGHT        (1<<17)
  96 #define S3C2412_NFCONT_SOFTLOCK         (1<<16)
  97 #define S3C2412_NFCONT_ECC4_ENCINT      (1<<13)
  98 #define S3C2412_NFCONT_ECC4_DECINT      (1<<12)
  99 #define S3C2412_NFCONT_MAIN_ECC_LOCK    (1<<7)
 100 #define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
 101 #define S3C2412_NFCONT_nFCE1            (1<<2)
 102 #define S3C2412_NFCONT_nFCE0            (1<<1)
 103
 104 #define S3C2412_NFSTAT_ECC_ENCDONE      (1<<7)
 105 #define S3C2412_NFSTAT_ECC_DECDONE      (1<<6)
 106 #define S3C2412_NFSTAT_ILLEGAL_ACCESS   (1<<5)
 107 #define S3C2412_NFSTAT_RnB_CHANGE       (1<<4)
 108 #define S3C2412_NFSTAT_nFCE1            (1<<3)
 109 #define S3C2412_NFSTAT_nFCE0            (1<<2)
 110 #define S3C2412_NFSTAT_Res1             (1<<1)
 111 #define S3C2412_NFSTAT_READY            (1<<0)
 112
 113 #define S3C2412_NFECCERR_SERRDATA(x)    (((x) >> 21) & 0xf)
 114 #define S3C2412_NFECCERR_SERRBIT(x)     (((x) >> 18) & 0x7)
 115 #define S3C2412_NFECCERR_MERRDATA(x)    (((x) >> 7) & 0x3ff)
 116 #define S3C2412_NFECCERR_MERRBIT(x)     (((x) >> 4) & 0x7)
 117 #define S3C2412_NFECCERR_SPARE_ERR(x)   (((x) >> 2) & 0x3)
 118 #define S3C2412_NFECCERR_MAIN_ERR(x)    (((x) >> 2) & 0x3)
 119 #define S3C2412_NFECCERR_NONE           (0)
 120 #define S3C2412_NFECCERR_1BIT           (1)
 121 #define S3C2412_NFECCERR_MULTIBIT       (2)
 122 #define S3C2412_NFECCERR_ECCAREA        (3)
 123
 124
 125
 126 #endif /* __ASM_ARM_REGS_NAND */
 127