| blob | 095a6be622a71697d193133e911b8679260d1213 |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/mii.h>
46 #include <linux/ethtool.h>
47 #include <linux/if_vlan.h>
48 #include <linux/cpu.h>
49 #include <linux/smp.h>
50 #include <linux/pm_qos.h>
51 #include <linux/pm_runtime.h>
52 #include <linux/aer.h>
53 #include <linux/prefetch.h>
63 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
83 };
86 u32 ofs;
88 };
104 /* General Registers */
109 /* Interrupt Registers */
112 /* Rx Registers */
128 /* Tx Registers */
145 /* List Terminator */
147 };
149 /*
150 * e1000_regdump - register printout routine
151 */
153 {
175 }
179 }
183 {
195 }
196 }
197 }
199 /*
200 * e1000e_dump - Print registers, Tx-ring and Rx-ring
201 */
203 {
210 __le64 a;
211 __le64 b;
218 __le64 a;
219 __le64 b;
220 __le64 c;
221 __le64 d;
223 u32 staterr;
229 /* Print netdevice Info */
236 }
238 /* Print Registers */
244 }
246 /* Print Tx Ring Summary */
260 /* Print Tx Ring */
266 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
267 *
268 * Legacy Transmit Descriptor
269 * +--------------------------------------------------------------+
270 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
271 * +--------------------------------------------------------------+
272 * 8 | Special | CSS | Status | CMD | CSO | Length |
273 * +--------------------------------------------------------------+
274 * 63 48 47 36 35 32 31 24 23 16 15 0
275 *
276 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
277 * 63 48 47 40 39 32 31 16 15 8 7 0
278 * +----------------------------------------------------------------+
279 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
280 * +----------------------------------------------------------------+
281 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 *
285 * Extended Data Descriptor (DTYP=0x1)
286 * +----------------------------------------------------------------+
287 * 0 | Buffer Address [63:0] |
288 * +----------------------------------------------------------------+
289 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
290 * +----------------------------------------------------------------+
291 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
292 */
293 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
294 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
295 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
307 else
312 i,
324 }
326 /* Print Rx Ring Summary */
327 rx_ring_summary:
333 /* Print Rx Ring */
342 /* [Extended] Packet Split Receive Descriptor Format
343 *
344 * +-----------------------------------------------------+
345 * 0 | Buffer Address 0 [63:0] |
346 * +-----------------------------------------------------+
347 * 8 | Buffer Address 1 [63:0] |
348 * +-----------------------------------------------------+
349 * 16 | Buffer Address 2 [63:0] |
350 * +-----------------------------------------------------+
351 * 24 | Buffer Address 3 [63:0] |
352 * +-----------------------------------------------------+
353 */
354 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
355 /* [Extended] Receive Descriptor (Write-Back) Format
356 *
357 * 63 48 47 32 31 13 12 8 7 4 3 0
358 * +------------------------------------------------------+
359 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
360 * | Checksum | Ident | | Queue | | Type |
361 * +------------------------------------------------------+
362 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
363 * +------------------------------------------------------+
364 * 63 48 47 32 31 20 19 0
365 */
366 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
372 staterr =
379 else
383 /* Descriptor Done */
403 buffer_info);
404 }
405 }
409 /* Extended Receive Descriptor (Read) Format
410 *
411 * +-----------------------------------------------------+
412 * 0 | Buffer Address [63:0] |
413 * +-----------------------------------------------------+
414 * 8 | Reserved |
415 * +-----------------------------------------------------+
416 */
417 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
418 /* Extended Receive Descriptor (Write-Back) Format
419 *
420 * 63 48 47 32 31 24 23 4 3 0
421 * +------------------------------------------------------+
422 * | RSS Hash | | | |
423 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
424 * | Packet | IP | | | Type |
425 * | Checksum | Ident | | | |
426 * +------------------------------------------------------+
427 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
428 * +------------------------------------------------------+
429 * 63 48 47 32 31 20 19 0
430 */
445 else
449 /* Descriptor Done */
471 }
472 }
473 }
474 }
476 /**
477 * e1000_desc_unused - calculate if we have unused descriptors
478 **/
480 {
485 }
487 /**
488 * e1000_receive_skb - helper function to handle Rx indications
489 * @adapter: board private structure
490 * @status: descriptor status field as written by hardware
491 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
492 * @skb: pointer to sk_buff to be indicated to stack
493 **/
497 {
505 }
507 /**
508 * e1000_rx_checksum - Receive Checksum Offload
509 * @adapter: board private structure
510 * @status_err: receive descriptor status and error fields
511 * @csum: receive descriptor csum field
512 * @sk_buff: socket buffer with received data
513 **/
516 {
522 /* Rx checksum disabled */
526 /* Ignore Checksum bit is set */
530 /* TCP/UDP checksum error bit or IP checksum error bit is set */
532 /* let the stack verify checksum errors */
535 }
537 /* TCP/UDP Checksum has not been calculated */
541 /* It must be a TCP or UDP packet with a valid checksum */
544 }
547 {
559 }
560 }
563 {
575 }
576 }
578 /**
579 * e1000_alloc_rx_buffers - Replace used receive buffers
580 * @rx_ring: Rx descriptor ring
581 **/
584 {
602 }
606 /* Better luck next round */
609 }
612 map_skb:
615 DMA_FROM_DEVICE);
620 }
626 /*
627 * Force memory writes to complete before letting h/w
628 * know there are new descriptors to fetch. (Only
629 * applicable for weak-ordered memory model archs,
630 * such as IA-64).
631 */
635 else
637 }
638 i++;
642 }
645 }
647 /**
648 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
649 * @rx_ring: Rx descriptor ring
650 **/
653 {
672 /* all unused desc entries get hw null ptr */
676 }
682 }
686 DMA_FROM_DEVICE);
693 }
694 }
695 /*
696 * Refresh the desc even if buffer_addrs
697 * didn't change because each write-back
698 * erases this info.
699 */
702 }
706 gfp);
711 }
716 DMA_FROM_DEVICE);
720 /* cleanup skb */
724 }
729 /*
730 * Force memory writes to complete before letting h/w
731 * know there are new descriptors to fetch. (Only
732 * applicable for weak-ordered memory model archs,
733 * such as IA-64).
734 */
738 else
740 }
742 i++;
746 }
748 no_buffers:
750 }
752 /**
753 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
754 * @rx_ring: Rx descriptor ring
755 * @cleaned_count: number of buffers to allocate this pass
756 **/
760 {
778 }
782 /* Better luck next round */
785 }
788 check_page:
789 /* allocate a new page if necessary */
795 }
796 }
801 PAGE_SIZE,
802 DMA_FROM_DEVICE);
810 }
817 /* Force memory writes to complete before letting h/w
818 * know there are new descriptors to fetch. (Only
819 * applicable for weak-ordered memory model archs,
820 * such as IA-64). */
824 else
826 }
827 }
831 {
834 }
836 /**
837 * e1000_clean_rx_irq - Send received data up the network stack
838 * @rx_ring: Rx descriptor ring
839 *
840 * the return value indicates whether actual cleaning was done, there
841 * is no guarantee that everything was cleaned
842 **/
845 {
876 i++;
885 cleaned_count++;
889 DMA_FROM_DEVICE);
894 /*
895 * !EOP means multiple descriptors were used to store a single
896 * packet, if that's the case we need to toss it. In fact, we
897 * need to toss every packet with the EOP bit clear and the
898 * next frame that _does_ have the EOP bit set, as it is by
899 * definition only a frame fragment
900 */
905 /* All receives must fit into a single buffer */
907 /* recycle */
912 }
916 /* recycle */
919 }
921 /* adjust length to remove Ethernet CRC */
923 /* If configured to store CRC, don't subtract FCS,
924 * but keep the FCS bytes out of the total_rx_bytes
925 * counter
926 */
929 else
931 }
934 total_rx_packets++;
936 /*
937 * code added for copybreak, this should improve
938 * performance for small packets with large amounts
939 * of reassembly being done in the stack
940 */
948 NET_IP_ALIGN),
950 NET_IP_ALIGN));
951 /* save the skb in buffer_info as good */
954 }
955 /* else just continue with the old one */
956 }
957 /* end copybreak code */
960 /* Receive Checksum Offload */
968 next_desc:
971 /* return some buffers to hardware, one at a time is too slow */
974 GFP_ATOMIC);
976 }
978 /* use prefetched values */
983 }
993 }
997 {
1004 else
1008 }
1012 }
1014 }
1017 {
1020 print_hang_task);
1028 u16 pci_status;
1035 /*
1036 * May be block on write-back, flush and detect again
1037 * flush pending descriptor writebacks to memory
1038 */
1040 /* execute the writes immediately */
1042 /*
1043 * Due to rare timing issues, write to TIDV again to ensure
1044 * the write is successful
1045 */
1047 /* execute the writes immediately */
1051 }
1052 /* Real hang detected */
1062 /* detected Hardware unit hang */
1083 eop,
1084 jiffies,
1087 phy_status,
1088 phy_1000t_status,
1089 phy_ext_status,
1090 pci_status);
1092 /* Suggest workaround for known h/w issue */
1095 }
1097 /**
1098 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1099 * @tx_ring: Tx descriptor ring
1100 *
1101 * the return value indicates whether actual cleaning was done, there
1102 * is no guarantee that everything was cleaned
1103 **/
1105 {
1134 pkts_compl++;
1135 }
1136 }
1141 i++;
1144 }
1150 }
1156 #define TX_WAKE_THRESHOLD 32
1159 /* Make sure that anybody stopping the queue after this
1160 * sees the new next_to_clean.
1161 */
1168 }
1169 }
1172 /*
1173 * Detect a transmit hang in hardware, this serializes the
1174 * check with the clearing of time_stamp and movement of i
1175 */
1182 else
1184 }
1188 }
1190 /**
1191 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1192 * @rx_ring: Rx descriptor ring
1193 *
1194 * the return value indicates whether actual cleaning was done, there
1195 * is no guarantee that everything was cleaned
1196 **/
1199 {
1226 /* in the packet split case this is header only */
1229 i++;
1238 cleaned_count++;
1243 /* see !EOP comment in other Rx routine */
1253 }
1259 }
1267 }
1269 /* Good Receive */
1272 {
1273 /*
1274 * this looks ugly, but it seems compiler issues make
1275 * it more efficient than reusing j
1276 */
1279 /*
1280 * page alloc/put takes too long and effects small
1281 * packet throughput, so unsplit small packets and
1282 * save the alloc/put only valid in softirq (napi)
1283 * context to call kmap_*
1284 */
1291 /*
1292 * there is no documentation about how to call
1293 * kmap_atomic, so we can't hold the mapping
1294 * very long
1295 */
1298 PAGE_SIZE,
1299 DMA_FROM_DEVICE);
1305 PAGE_SIZE,
1306 DMA_FROM_DEVICE);
1308 /* remove the CRC */
1312 }
1317 }
1326 DMA_FROM_DEVICE);
1333 }
1335 /* strip the ethernet crc, problem is we're using pages now so
1336 * this whole operation can get a little cpu intensive
1337 */
1341 }
1343 copydone:
1345 total_rx_packets++;
1358 next_desc:
1362 /* return some buffers to hardware, one at a time is too slow */
1365 GFP_ATOMIC);
1367 }
1369 /* use prefetched values */
1374 }
1384 }
1386 /**
1387 * e1000_consume_page - helper function
1388 **/
1390 u16 length)
1391 {
1396 }
1398 /**
1399 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1400 * @adapter: board private structure
1401 *
1402 * the return value indicates whether actual cleaning was done, there
1403 * is no guarantee that everything was cleaned
1404 **/
1407 {
1444 cleaned_count++;
1446 DMA_FROM_DEVICE);
1451 /* errors is only valid for DD + EOP descriptors */
1455 /* recycle both page and skb */
1457 /* an error means any chain goes out the window too */
1462 }
1464 #define rxtop (rx_ring->rx_skb_top)
1466 /* this descriptor is only the beginning (or middle) */
1468 /* this is the beginning of a chain */
1473 /* this is the middle of a chain */
1477 /* re-use the skb, only consumed the page */
1479 }
1484 /* end of the chain */
1488 /* re-use the current skb, we only consumed the
1489 * page */
1495 /* no chain, got EOP, this buf is the packet
1496 * copybreak to save the put_page/alloc_page */
1502 length);
1504 /* re-use the page, so don't erase
1505 * buffer_info->page */
1510 length);
1512 length);
1513 }
1514 }
1515 }
1517 /* Receive Checksum Offload */
1522 /* probably a little skewed due to removing CRC */
1524 total_rx_packets++;
1526 /* eth type trans needs skb->data to point to something */
1531 }
1536 next_desc:
1539 /* return some buffers to hardware, one at a time is too slow */
1542 GFP_ATOMIC);
1544 }
1546 /* use prefetched values */
1551 }
1561 }
1563 /**
1564 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1565 * @rx_ring: Rx descriptor ring
1566 **/
1568 {
1575 /* Free all the Rx ring sk_buffs */
1582 DMA_FROM_DEVICE);
1585 PAGE_SIZE,
1586 DMA_FROM_DEVICE);
1590 DMA_FROM_DEVICE);
1592 }
1597 }
1602 }
1609 DMA_FROM_DEVICE);
1613 }
1614 }
1616 /* there also may be some cached data from a chained receive */
1620 }
1622 /* Zero out the descriptor ring */
1632 else
1634 }
1637 {
1645 }
1647 /**
1648 * e1000_intr_msi - Interrupt Handler
1649 * @irq: interrupt number
1650 * @data: pointer to a network interface device structure
1651 **/
1653 {
1659 /*
1660 * read ICR disables interrupts using IAM
1661 */
1665 /*
1666 * ICH8 workaround-- Call gig speed drop workaround on cable
1667 * disconnect (LSC) before accessing any PHY registers
1668 */
1673 /*
1674 * 80003ES2LAN workaround-- For packet buffer work-around on
1675 * link down event; disable receives here in the ISR and reset
1676 * adapter in watchdog
1677 */
1680 /* disable receives */
1684 }
1685 /* guard against interrupt when we're going down */
1688 }
1696 }
1699 }
1701 /**
1702 * e1000_intr - Interrupt Handler
1703 * @irq: interrupt number
1704 * @data: pointer to a network interface device structure
1705 **/
1707 {
1716 /*
1717 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1718 * not set, then the adapter didn't send an interrupt
1719 */
1723 /*
1724 * Interrupt Auto-Mask...upon reading ICR,
1725 * interrupts are masked. No need for the
1726 * IMC write
1727 */
1731 /*
1732 * ICH8 workaround-- Call gig speed drop workaround on cable
1733 * disconnect (LSC) before accessing any PHY registers
1734 */
1739 /*
1740 * 80003ES2LAN workaround--
1741 * For packet buffer work-around on link down event;
1742 * disable receives here in the ISR and
1743 * reset adapter in watchdog
1744 */
1747 /* disable receives */
1751 }
1752 /* guard against interrupt when we're going down */
1755 }
1763 }
1766 }
1769 {
1779 }
1788 /* guard against interrupt when we're going down */
1791 }
1793 no_link_interrupt:
1798 }
1802 {
1813 /* Ring was not completely cleaned, so fire another interrupt */
1817 }
1820 {
1825 /* Write the ITR value calculated at the end of the
1826 * previous interrupt.
1827 */
1832 }
1838 }
1840 }
1842 /**
1843 * e1000_configure_msix - Configure MSI-X hardware
1844 *
1845 * e1000_configure_msix sets up the hardware to properly
1846 * generate MSI-X interrupts.
1847 **/
1849 {
1858 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1863 }
1865 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1866 /* Configure Rx vector */
1872 else
1876 /* Configure Tx vector */
1878 vector++;
1882 else
1887 /* set vector for Other Causes, e.g. link changes */
1888 vector++;
1893 else
1896 /* Cause Tx interrupts on every write back */
1901 /* enable MSI-X PBA support */
1905 /* Auto-Mask Other interrupts upon ICR read */
1906 #define E1000_EIAC_MASK_82574 0x01F00000
1911 }
1914 {
1922 }
1923 }
1925 /**
1926 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1927 *
1928 * Attempt to configure interrupts using the best available
1929 * capabilities of the hardware and kernel.
1930 **/
1932 {
1942 GFP_KERNEL);
1952 }
1953 /* MSI-X failed, so fall through and try MSI */
1956 }
1958 /* Fall through */
1965 }
1966 /* Fall through */
1968 /* Don't do anything; this is the system default */
1970 }
1972 /* store the number of vectors being used */
1974 }
1976 /**
1977 * e1000_request_msix - Initialize MSI-X interrupts
1978 *
1979 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1980 * kernel.
1981 **/
1983 {
1991 else
1995 netdev);
2001 vector++;
2007 else
2011 netdev);
2017 vector++;
2027 }
2029 /**
2030 * e1000_request_irq - initialize interrupts
2031 *
2032 * Attempts to configure interrupts using the best available
2033 * capabilities of the hardware and kernel.
2034 **/
2036 {
2044 /* fall back to MSI */
2048 }
2055 /* fall back to legacy interrupt */
2058 }
2066 }
2069 {
2076 vector++;
2079 vector++;
2081 /* Other Causes interrupt vector */
2084 }
2087 }
2089 /**
2090 * e1000_irq_disable - Mask off interrupt generation on the NIC
2091 **/
2093 {
2107 }
2108 }
2110 /**
2111 * e1000_irq_enable - Enable default interrupt generation settings
2112 **/
2114 {
2122 }
2124 }
2126 /**
2127 * e1000e_get_hw_control - get control of the h/w from f/w
2128 * @adapter: address of board private structure
2129 *
2130 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2131 * For ASF and Pass Through versions of f/w this means that
2132 * the driver is loaded. For AMT version (only with 82573)
2133 * of the f/w this means that the network i/f is open.
2134 **/
2136 {
2138 u32 ctrl_ext;
2139 u32 swsm;
2141 /* Let firmware know the driver has taken over */
2148 }
2149 }
2151 /**
2152 * e1000e_release_hw_control - release control of the h/w to f/w
2153 * @adapter: address of board private structure
2154 *
2155 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2156 * For ASF and Pass Through versions of f/w this means that the
2157 * driver is no longer loaded. For AMT version (only with 82573) i
2158 * of the f/w this means that the network i/f is closed.
2159 *
2160 **/
2162 {
2164 u32 ctrl_ext;
2165 u32 swsm;
2167 /* Let firmware taken over control of h/w */
2174 }
2175 }
2177 /**
2178 * e1000_alloc_ring_dma - allocate memory for a ring structure
2179 **/
2182 {
2186 GFP_KERNEL);
2191 }
2193 /**
2194 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2195 * @tx_ring: Tx descriptor ring
2196 *
2197 * Return 0 on success, negative on failure
2198 **/
2200 {
2209 /* round up to nearest 4K */
2221 err:
2225 }
2227 /**
2228 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2229 * @rx_ring: Rx descriptor ring
2230 *
2231 * Returns 0 on success, negative on failure
2232 **/
2234 {
2248 GFP_KERNEL);
2251 }
2255 /* Round up to nearest 4K */
2269 err_pages:
2273 }
2274 err:
2278 }
2280 /**
2281 * e1000_clean_tx_ring - Free Tx Buffers
2282 * @tx_ring: Tx descriptor ring
2283 **/
2285 {
2294 }
2308 else
2310 }
2312 /**
2313 * e1000e_free_tx_resources - Free Tx Resources per Queue
2314 * @tx_ring: Tx descriptor ring
2315 *
2316 * Free all transmit software resources
2317 **/
2319 {
2331 }
2333 /**
2334 * e1000e_free_rx_resources - Free Rx Resources
2335 * @rx_ring: Rx descriptor ring
2336 *
2337 * Free all receive software resources
2338 **/
2340 {
2356 }
2358 /**
2359 * e1000_update_itr - update the dynamic ITR value based on statistics
2360 * @adapter: pointer to adapter
2361 * @itr_setting: current adapter->itr
2362 * @packets: the number of packets during this measurement interval
2363 * @bytes: the number of bytes during this measurement interval
2364 *
2365 * Stores a new ITR value based on packets and byte
2366 * counts during the last interrupt. The advantage of per interrupt
2367 * computation is faster updates and more accurate ITR for the current
2368 * traffic pattern. Constants in this function were computed
2369 * based on theoretical maximum wire speed and thresholds were set based
2370 * on testing data as well as attempting to minimize response time
2371 * while increasing bulk throughput. This functionality is controlled
2372 * by the InterruptThrottleRate module parameter.
2373 **/
2377 {
2385 /* handle TSO and jumbo frames */
2393 /* this if handles the TSO accounting */
2404 }
2412 }
2414 }
2417 }
2420 {
2422 u16 current_itr;
2425 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2430 }
2435 }
2441 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2449 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2456 /* counts and packets in update_itr are dependent on these numbers */
2468 }
2470 set_itr_now:
2472 /*
2473 * this attempts to bias the interrupt rate towards Bulk
2474 * by adding intermediate steps when interrupt rate is
2475 * increasing
2476 */
2479 new_itr;
2484 else
2487 else
2489 }
2490 }
2492 /**
2493 * e1000e_write_itr - write the ITR value to the appropriate registers
2494 * @adapter: address of board private structure
2495 * @itr: new ITR value to program
2496 *
2497 * e1000e_write_itr determines if the adapter is in MSI-X mode
2498 * and, if so, writes the EITR registers with the ITR value.
2499 * Otherwise, it writes the ITR value into the ITR register.
2500 **/
2502 {
2513 }
2514 }
2516 /**
2517 * e1000_alloc_queues - Allocate memory for all rings
2518 * @adapter: board private structure to initialize
2519 **/
2521 {
2537 err:
2542 }
2544 /**
2545 * e1000e_poll - NAPI Rx polling callback
2546 * @napi: struct associated with this polling callback
2547 * @weight: number of packets driver is allowed to process this poll
2548 **/
2550 {
2552 napi);
2568 /* If weight not fully consumed, exit the polling mode */
2576 else
2578 }
2579 }
2582 }
2585 {
2590 /* don't update vlan cookie if already programmed */
2592 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2596 /* add VID to filter table */
2602 }
2607 }
2610 {
2616 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2618 /* release control to f/w */
2621 }
2623 /* remove VID from filter table */
2629 }
2634 }
2636 /**
2637 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2638 * @adapter: board private structure to initialize
2639 **/
2641 {
2644 u32 rctl;
2647 /* disable VLAN receive filtering */
2655 }
2656 }
2657 }
2659 /**
2660 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2661 * @adapter: board private structure to initialize
2662 **/
2664 {
2666 u32 rctl;
2669 /* enable VLAN receive filtering */
2674 }
2675 }
2677 /**
2678 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2679 * @adapter: board private structure to initialize
2680 **/
2682 {
2684 u32 ctrl;
2686 /* disable VLAN tag insert/strip */
2690 }
2692 /**
2693 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2694 * @adapter: board private structure to initialize
2695 **/
2697 {
2699 u32 ctrl;
2701 /* enable VLAN tag insert/strip */
2705 }
2708 {
2714 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2717 }
2721 }
2724 {
2725 u16 vid;
2731 }
2734 {
2743 /*
2744 * enable receiving management packets to the host. this will probably
2745 * generate destination unreachable messages from the host OS, but
2746 * the packets will be handled on SMBUS
2747 */
2757 /*
2758 * Check if IPMI pass-through decision filter already exists;
2759 * if so, enable it.
2760 */
2764 /* Ignore filters with anything other than IPMI ports */
2768 /* Enable this decision filter in MANC2H */
2773 }
2778 /* Create new decision filter in an empty filter */
2782 E1000_MDEF_PORT_664));
2784 j++;
2786 }
2791 }
2795 }
2797 /**
2798 * e1000_configure_tx - Configure Transmit Unit after Reset
2799 * @adapter: board private structure
2800 *
2801 * Configure the Tx unit of the MAC after a reset.
2802 **/
2804 {
2807 u64 tdba;
2810 /* Setup the HW Tx Head and Tail descriptor pointers */
2821 /* Set the Tx Interrupt Delay register */
2823 /* Tx irq moderation */
2829 E1000_TXDCTL_WTHRESH);
2830 /*
2831 * set up some performance related parameters to encourage the
2832 * hardware to use the bus more efficiently in bursts, depends
2833 * on the tx_int_delay to be enabled,
2834 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2835 * hthresh = 1 ==> prefetch when one or more available
2836 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2837 * BEWARE: this seems to work but should be considered first if
2838 * there are Tx hangs or other Tx related bugs
2839 */
2842 }
2843 /* erratum work around: set txdctl the same for both queues */
2848 /*
2849 * set the speed mode bit, we'll clear it if we're not at
2850 * gigabit link later
2851 */
2852 #define SPEED_MODE_BIT (1 << 21)
2855 }
2857 /* errata: program both queues to unweighted RR */
2865 }
2867 /* Setup Transmit Descriptor Settings for eop descriptor */
2870 /* only set IDE if we are delaying interrupts using the timers */
2874 /* enable Report Status bit */
2878 }
2880 /**
2881 * e1000_setup_rctl - configure the receive control registers
2882 * @adapter: Board private structure
2883 **/
2884 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2885 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2887 {
2892 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2894 s32 ret_val;
2898 else
2903 }
2905 /* Program MC offset vector base */
2912 /* Do not Store bad packets */
2915 /* Enable Long Packet receive */
2918 else
2921 /* Some systems expect that the CRC is included in SMBUS traffic. The
2922 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2923 * host memory when this is enabled
2924 */
2928 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2930 u16 phy_data;
2943 }
2945 /* Setup buffer sizes */
2963 }
2965 /* Enable Extended Status in all Receive Descriptors */
2970 /*
2971 * 82571 and greater support packet-split where the protocol
2972 * header is placed in skb->data and the packet data is
2973 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2974 * In the case of a non-split, skb->data is linearly filled,
2975 * followed by the page buffers. Therefore, skb->data is
2976 * sized to hold the largest protocol header.
2977 *
2978 * allocations using alloc_page take too long for regular MTU
2979 * so only enable packet split for jumbo frames
2980 *
2981 * Using pages when the page size is greater than 16k wastes
2982 * a lot of memory, since we allocate 3 pages at all times
2983 * per packet.
2984 */
2988 else
2994 /* Enable Packet split descriptors */
2998 E1000_PSRCTL_BSIZE0_SHIFT;
3003 E1000_PSRCTL_BSIZE3_SHIFT;
3006 E1000_PSRCTL_BSIZE2_SHIFT;
3009 E1000_PSRCTL_BSIZE1_SHIFT;
3011 }
3014 }
3016 /* This is useful for sniffing bad packets. */
3018 /* UPE and MPE will be handled by normal PROMISC logic
3019 * in e1000e_set_rx_mode */
3027 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3028 * and that breaks VLANs.
3029 */
3030 }
3033 /* just started the receive unit, no need to restart */
3035 }
3037 /**
3038 * e1000_configure_rx - Configure Receive Unit after Reset
3039 * @adapter: board private structure
3040 *
3041 * Configure the Rx unit of the MAC after a reset.
3042 **/
3044 {
3047 u64 rdba;
3051 /* this is a 32 byte descriptor */
3064 }
3066 /* disable receives while setting up the descriptors */
3074 /*
3075 * set the writeback threshold (only takes effect if the RDTR
3076 * is set). set GRAN=1 and write back up to 0x4 worth, and
3077 * enable prefetching of 0x20 Rx descriptors
3078 * granularity = 01
3079 * wthresh = 04,
3080 * hthresh = 04,
3081 * pthresh = 0x20
3082 */
3086 /*
3087 * override the delay timers for enabling bursting, only if
3088 * the value was not set by the user via module options
3089 */
3094 }
3096 /* set the Receive Delay Timer Register */
3099 /* irq moderation */
3105 /* Auto-Mask interrupts upon ICR access */
3111 /*
3112 * Setup the HW Rx Head and Tail Descriptor Pointers and
3113 * the Base and Length of the Rx Descriptor Ring
3114 */
3124 /* Enable Receive Checksum Offload for TCP and UDP */
3128 else
3133 /*
3134 * With jumbo frames, excessive C-state transition
3135 * latencies result in dropped transactions.
3136 */
3143 PM_QOS_DEFAULT_VALUE);
3144 }
3145 }
3147 /* Enable Receives */
3149 }
3151 /**
3152 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3153 * @netdev: network interface device structure
3154 *
3155 * Writes multicast address list to the MTA hash table.
3156 * Returns: -ENOMEM on failure
3157 * 0 on no addresses written
3158 * X on writing X addresses to MTA
3159 */
3161 {
3169 /* nothing to program, so clear mc list */
3172 }
3178 /* update_mc_addr_list expects a packed array of only addresses. */
3187 }
3189 /**
3190 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3191 * @netdev: network interface device structure
3192 *
3193 * Writes unicast address list to the RAR table.
3194 * Returns: -ENOMEM on failure/insufficient address space
3195 * 0 on no addresses written
3196 * X on writing X addresses to the RAR table
3197 **/
3199 {
3205 /* save a rar entry for our hardware address */
3206 rar_entries--;
3208 /* save a rar entry for the LAA workaround */
3210 rar_entries--;
3212 /* return ENOMEM indicating insufficient memory for addresses */
3219 /*
3220 * write the addresses in reverse order to avoid write
3221 * combining
3222 */
3227 count++;
3228 }
3229 }
3231 /* zero out the remaining RAR entries not used above */
3235 }
3239 }
3241 /**
3242 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3243 * @netdev: network interface device structure
3244 *
3245 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3246 * address list or the network interface flags are updated. This routine is
3247 * responsible for configuring the hardware for proper unicast, multicast,
3248 * promiscuous mode, and all-multi behavior.
3249 **/
3251 {
3254 u32 rctl;
3256 /* Check for Promiscuous and All Multicast modes */
3259 /* clear the affected bits */
3264 /* Do not hardware filter VLANs in promisc mode */
3272 /*
3273 * Write addresses to the MTA, if the attempt fails
3274 * then we should just turn on promiscuous mode so
3275 * that we can at least receive multicast traffic
3276 */
3280 }
3282 /*
3283 * Write addresses to available RAR registers, if there is not
3284 * sufficient space to store all the addresses then enable
3285 * unicast promiscuous mode
3286 */
3290 }
3296 else
3298 }
3301 {
3308 };
3310 /* Fill out hash function seed */
3314 /* Direct all traffic to queue 0 */
3318 /*
3319 * Disable raw packet checksumming so that RSS hash is placed in
3320 * descriptor on writeback.
3321 */
3328 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3329 E1000_MRQC_RSS_FIELD_IPV6 |
3330 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3331 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3334 }
3336 /**
3337 * e1000_configure - configure the hardware for Rx and Tx
3338 * @adapter: private board structure
3339 **/
3341 {
3356 }
3358 /**
3359 * e1000e_power_up_phy - restore link in case the phy was powered down
3360 * @adapter: address of board private structure
3361 *
3362 * The phy may be powered down to save power and turn off link when the
3363 * driver is unloaded and wake on lan is not enabled (among others)
3364 * *** this routine MUST be followed by a call to e1000e_reset ***
3365 **/
3367 {
3372 }
3374 /**
3375 * e1000_power_down_phy - Power down the PHY
3376 *
3377 * Power down the PHY so no link is implied when interface is down.
3378 * The PHY cannot be powered down if management or WoL is active.
3379 */
3381 {
3382 /* WoL is enabled */
3388 }
3390 /**
3391 * e1000e_reset - bring the hardware into a known good state
3392 *
3393 * This function boots the hardware and enables some settings that
3394 * require a configuration cycle of the hardware - those cannot be
3395 * set/changed during runtime. After reset the device needs to be
3396 * properly configured for Rx, Tx etc.
3397 */
3399 {
3405 u16 hwm;
3407 /* reset Packet Buffer Allocation to default */
3411 /*
3412 * To maintain wire speed transmits, the Tx FIFO should be
3413 * large enough to accommodate two full transmit packets,
3414 * rounded up to the next 1KB and expressed in KB. Likewise,
3415 * the Rx FIFO should be large enough to accommodate at least
3416 * one full receive packet and is similarly rounded up and
3417 * expressed in KB.
3418 */
3420 /* upper 16 bits has Tx packet buffer allocation size in KB */
3422 /* lower 16 bits has Rx packet buffer allocation size in KB */
3424 /*
3425 * the Tx fifo also stores 16 bytes of information about the Tx
3426 * but don't include ethernet FCS because hardware appends it
3427 */
3433 /* software strips receive CRC, so leave room for it */
3438 /*
3439 * If current Tx allocation is less than the min Tx FIFO size,
3440 * and the min Tx FIFO size is less than the current Rx FIFO
3441 * allocation, take space away from current Rx allocation
3442 */
3447 /*
3448 * if short on Rx space, Rx wins and must trump Tx
3449 * adjustment
3450 */
3453 }
3456 }
3458 /*
3459 * flow control settings
3460 *
3461 * The high water mark must be low enough to fit one full frame
3462 * (or the size used for early receive) above it in the Rx FIFO.
3463 * Set it to the lower of:
3464 * - 90% of the Rx FIFO size, and
3465 * - the full Rx FIFO size minus one full frame
3466 */
3469 else
3483 }
3484 /* fall-through */
3493 /*
3494 * Workaround PCH LOM adapter hangs with certain network
3495 * loads. If hangs persist, try disabling Tx flow control.
3496 */
3503 }
3515 }
3517 }
3519 /*
3520 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3521 * fit in receive buffer.
3522 */
3530 }
3537 }
3538 }
3540 /* Allow time for pending master requests to run */
3543 /*
3544 * For parts with AMT enabled, let the firmware know
3545 * that the network interface is in control
3546 */
3557 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3566 }
3573 /*
3574 * speed up time to link by disabling smart power down, ignore
3575 * the return value of this function because there is nothing
3576 * different we would do if it failed
3577 */
3581 }
3582 }
3585 {
3588 /* hardware has been reset, we need to reload some things */
3599 /* fire a link change interrupt to start the watchdog */
3602 else
3606 }
3609 {
3615 /* flush pending descriptor writebacks to memory */
3619 /* execute the writes immediately */
3622 /*
3623 * due to rare timing issues, write to TIDV/RDTR again to ensure the
3624 * write is successful
3625 */
3629 /* execute the writes immediately */
3631 }
3636 {
3641 /*
3642 * signal that we're down so the interrupt handler does not
3643 * reschedule our watchdog timer
3644 */
3647 /* disable receives in the hardware */
3651 /* flush and sleep below */
3655 /* disable transmits in the hardware */
3660 /* flush both disables and wait for them to finish */
3685 /*
3686 * TODO: for power management, we could drop the link and
3687 * pci_disable_device here.
3688 */
3689 }
3692 {
3699 }
3701 /**
3702 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3703 * @adapter: board private structure to initialize
3704 *
3705 * e1000_sw_init initializes the Adapter private data structure.
3706 * Fields are initialized based on PCI device information and
3707 * OS network device settings (MTU size).
3708 **/
3710 {
3727 /* Explicitly disable IRQ since the NIC can be in any state. */
3732 }
3734 /**
3735 * e1000_intr_msi_test - Interrupt Handler
3736 * @irq: interrupt number
3737 * @data: pointer to a network interface device structure
3738 **/
3740 {
3749 /*
3750 * Force memory writes to complete before acknowledging the
3751 * interrupt is handled.
3752 */
3754 }
3757 }
3759 /**
3760 * e1000_test_msi_interrupt - Returns 0 for successful test
3761 * @adapter: board private struct
3762 *
3763 * code flow taken from tg3.c
3764 **/
3766 {
3771 /* poll_enable hasn't been called yet, so don't need disable */
3772 /* clear any pending events */
3775 /* free the real vector and request a test handler */
3779 /* Assume that the test fails, if it succeeds then the test
3780 * MSI irq handler will unset this flag */
3792 }
3794 /*
3795 * Force memory writes to complete before enabling and firing an
3796 * interrupt.
3797 */
3802 /* fire an unusual interrupt on the test handler */
3816 }
3821 msi_test_failed:
3824 }
3826 /**
3827 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3828 * @adapter: board private struct
3829 *
3830 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3831 **/
3833 {
3835 u16 pci_cmd;
3840 /* disable SERR in case the MSI write causes a master abort */
3848 /* re-enable SERR */
3853 }
3856 }
3858 /**
3859 * e1000_open - Called when a network interface is made active
3860 * @netdev: network interface device structure
3861 *
3862 * Returns 0 on success, negative value on failure
3863 *
3864 * The open entry point is called when a network interface is made
3865 * active by the system (IFF_UP). At this point all resources needed
3866 * for transmit and receive operations are allocated, the interrupt
3867 * handler is registered with the OS, the watchdog timer is started,
3868 * and the stack is notified that the interface is ready.
3869 **/
3871 {
3877 /* disallow open during test */
3885 /* allocate transmit descriptors */
3890 /* allocate receive descriptors */
3895 /*
3896 * If AMT is enabled, let the firmware know that the network
3897 * interface is now open and reset the part to a known state.
3898 */
3902 }
3908 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3911 /* DMA latency requirement to workaround jumbo issue */
3914 PM_QOS_CPU_DMA_LATENCY,
3915 PM_QOS_DEFAULT_VALUE);
3917 /*
3918 * before we allocate an interrupt, we must be ready to handle it.
3919 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3920 * as soon as we call pci_request_irq, so we have to setup our
3921 * clean_rx handler before we do so.
3922 */
3929 /*
3930 * Work around PCIe errata with MSI interrupts causing some chipsets to
3931 * ignore e1000e MSI messages, which means we need to test our MSI
3932 * interrupt now
3933 */
3939 }
3940 }
3942 /* From here on the code is the same as e1000e_up() */
3955 /* fire a link status change interrupt to start the watchdog */
3958 else
3963 err_req_irq:
3967 err_setup_rx:
3969 err_setup_tx:
3974 }
3976 /**
3977 * e1000_close - Disables a network interface
3978 * @netdev: network interface device structure
3979 *
3980 * Returns 0, this is not allowed to fail
3981 *
3982 * The close entry point is called when an interface is de-activated
3983 * by the OS. The hardware is still under the drivers control, but
3984 * needs to be disabled. A global MAC reset is issued to stop the
3985 * hardware, and all transmit and receive resources are freed.
3986 **/
3988 {
4005 }
4011 /*
4012 * kill manageability vlan ID if supported, but not if a vlan with
4013 * the same ID is registered on the host OS (let 8021q kill it)
4014 */
4016 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4019 /*
4020 * If AMT is enabled, let the firmware know that the network
4021 * interface is now closed
4022 */
4033 }
4034 /**
4035 * e1000_set_mac - Change the Ethernet Address of the NIC
4036 * @netdev: network interface device structure
4037 * @p: pointer to an address structure
4038 *
4039 * Returns 0 on success, negative on failure
4040 **/
4042 {
4056 /* activate the work around */
4059 /*
4060 * Hold a copy of the LAA in RAR[14] This is done so that
4061 * between the time RAR[0] gets clobbered and the time it
4062 * gets fixed (in e1000_watchdog), the actual LAA is in one
4063 * of the RARs and no incoming packets directed to this port
4064 * are dropped. Eventually the LAA will be in RAR[0] and
4065 * RAR[14]
4066 */
4069 }
4072 }
4074 /**
4075 * e1000e_update_phy_task - work thread to update phy
4076 * @work: pointer to our work struct
4077 *
4078 * this worker thread exists because we must acquire a
4079 * semaphore to read the phy, which we could msleep while
4080 * waiting for it, and we can't msleep in a timer.
4081 **/
4083 {
4091 }
4093 /*
4094 * Need to wait a few seconds after link up to get diagnostic information from
4095 * the phy
4096 */
4098 {
4105 }
4107 /**
4108 * e1000e_update_phy_stats - Update the PHY statistics counters
4109 * @adapter: board private structure
4110 *
4111 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4112 **/
4114 {
4116 s32 ret_val;
4117 u16 phy_data;
4123 /*
4124 * A page set is expensive so check if already on desired page.
4125 * If not, set to the page with the PHY status registers.
4126 */
4137 }
4139 /* Single Collision Count */
4145 /* Excessive Collision Count */
4151 /* Multiple Collision Count */
4157 /* Late Collision Count */
4163 /* Collision Count - also used for adaptive IFS */
4169 /* Defer Count */
4175 /* Transmit with no CRS */
4181 release:
4183 }
4185 /**
4186 * e1000e_update_stats - Update the board statistics counters
4187 * @adapter: board private structure
4188 **/
4190 {
4195 /*
4196 * Prevent stats update while adapter is being reset, or if the pci
4197 * connection is down.
4198 */
4214 /* Half-duplex statistics */
4230 }
4232 }
4247 /* used for adaptive IFS */
4258 /* Fill out the OS statistics structure */
4262 /* Rx Errors */
4264 /*
4265 * RLEC on some newer hardware can be incorrect so build
4266 * our own version based on RUC and ROC
4267 */
4278 /* Tx Errors */
4285 /* Tx Dropped needs to be maintained elsewhere */
4287 /* Management Stats */
4291 }
4293 /**
4294 * e1000_phy_read_status - Update the PHY register status snapshot
4295 * @adapter: board private structure
4296 **/
4298 {
4317 /*
4318 * Do not read PHY registers if link is not up
4319 * Set values to typical power-on defaults
4320 */
4324 BMSR_ERCAP);
4332 }
4333 }
4336 {
4340 /* Link status message must follow this format for user tools */
4348 }
4351 {
4356 /*
4357 * get_link_status is set on LSC (link status) interrupt or
4358 * Rx sequence error interrupt. get_link_status will stay
4359 * false until the check_for_link establishes link
4360 * for copper adapters ONLY
4361 */
4369 }
4382 }
4386 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4388 }
4391 }
4394 {
4395 /* make sure the receive unit is started */
4402 }
4403 }
4406 {
4409 /*
4410 * With 82574 controllers, PHY needs to be checked periodically
4411 * for hung state and reset, if two calls return true
4412 */
4415 else
4421 }
4422 }
4424 /**
4425 * e1000_watchdog - Timer Call-back
4426 * @data: pointer to adapter cast into an unsigned long
4427 **/
4429 {
4432 /* Do the rest outside of interrupt context */
4435 /* TODO: make this use queue_delayed_work() */
4436 }
4439 {
4454 /* Cancel scheduled suspend requests. */
4459 }
4469 /* Cancel scheduled suspend requests. */
4472 /* update snapshot of PHY registers on LSC */
4478 /*
4479 * On supported PHYs, check for duplex mismatch only
4480 * if link has autonegotiated at 10/100 half
4481 */
4488 u16 autoneg_exp;
4493 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4494 }
4496 /* adjust timeout factor according to speed/duplex */
4507 }
4509 /*
4510 * workaround: re-program speed mode bit after
4511 * link-up event
4512 */
4515 u32 tarc0;
4519 }
4521 /*
4522 * disable TSO for pcie and 10/100 speeds, to avoid
4523 * some hardware issues
4524 */
4538 /* oops */
4540 }
4541 }
4543 /*
4544 * enable transmits in the hardware, need to do this
4545 * after setting TARC(0)
4546 */
4551 /*
4552 * Perform any post-link-up configuration before
4553 * reporting link up.
4554 */
4563 }
4568 /* Link status message must follow this format */
4578 else
4580 LINK_TIMEOUT);
4581 }
4582 }
4584 link_up:
4603 /*
4604 * We've lost link, so the controller stops DMA,
4605 * but we've got queued Tx work that's never going
4606 * to get done, so reset controller to flush Tx.
4607 * (Do the reset outside of interrupt context).
4608 */
4610 /* return immediately since reset is imminent */
4612 }
4614 /* Simple mode for Interrupt Throttle Rate (ITR) */
4616 /*
4617 * Symmetric Tx/Rx gets a reduced ITR=2000;
4618 * Total asymmetrical Tx or Rx gets ITR=8000;
4619 * everyone else is between 2000-8000.
4620 */
4628 }
4630 /* Cause software interrupt to ensure Rx ring is cleaned */
4633 else
4636 /* flush pending descriptors to memory before detecting Tx hang */
4639 /* Force detection of hung controller every watchdog period */
4642 /*
4643 * With 82571 controllers, LAA may be overwritten due to controller
4644 * reset from the other port. Set the appropriate LAA in RAR[0]
4645 */
4652 /* Reset the timer */
4656 }
4658 #define E1000_TX_FLAGS_CSUM 0x00000001
4659 #define E1000_TX_FLAGS_VLAN 0x00000002
4660 #define E1000_TX_FLAGS_TSO 0x00000004
4661 #define E1000_TX_FLAGS_IPV4 0x00000008
4662 #define E1000_TX_FLAGS_NO_FCS 0x00000010
4663 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4664 #define E1000_TX_FLAGS_VLAN_SHIFT 16
4667 {
4683 }
4701 }
4727 i++;
4733 }
4736 {
4741 u8 css;
4743 __be16 protocol;
4750 else
4759 /* XXX not handling all IPV6 headers */
4768 }
4787 i++;
4793 }
4795 #define E1000_MAX_PER_TXD 8192
4796 #define E1000_MAX_TXD_PWR 12
4801 {
4827 count++;
4830 i++;
4833 }
4834 }
4844 i++;
4862 count++;
4863 }
4864 }
4867 /* multiply data chunks by size of headers */
4877 dma_error:
4881 count--;
4886 i--;
4889 }
4892 }
4895 {
4904 E1000_TXD_CMD_TSE;
4909 }
4914 }
4919 }
4934 i++;
4941 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4945 /*
4946 * Force memory writes to complete before letting h/w
4947 * know there are new descriptors to fetch. (Only
4948 * applicable for weak-ordered memory model archs,
4949 * such as IA-64).
4950 */
4957 else
4960 /*
4961 * we need this if more than one processor can write to our tail
4962 * at a time, it synchronizes IO on IA64/Altix systems
4963 */
4965 }
4967 #define MINIMUM_DHCP_PACKET_SIZE 282
4970 {
4977 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4979 }
4987 {
5001 }
5004 }
5007 {
5011 /*
5012 * Herbert's original patch had:
5013 * smp_mb__after_netif_stop_queue();
5014 * but since that doesn't exist yet, just open code it.
5015 */
5018 /*
5019 * We need to check again in a case another CPU has just
5020 * made room available.
5021 */
5025 /* A reprieve! */
5029 }
5032 {
5036 }
5038 #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
5041 {
5058 }
5063 }
5066 /*
5067 * The controller does a simple calculation to
5068 * make sure there is enough room in the FIFO before
5069 * initiating the DMA for each buffer. The calc is:
5070 * 4 = ceil(buffer len/mss). To make sure we don't
5071 * overrun the FIFO, adjust the max buffer len if mss
5072 * drops.
5073 */
5075 u8 hdr_len;
5079 /*
5080 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5081 * points to just header, pull a few bytes of payload from
5082 * frags into skb->data
5083 */
5085 /*
5086 * we do this workaround for ES2LAN, but it is un-necessary,
5087 * avoiding it could save a lot of cycles
5088 */
5097 }
5099 }
5100 }
5102 /* reserve a descriptor for the offload context */
5104 count++;
5105 count++;
5112 max_txd_pwr);
5117 /*
5118 * need: count + 2 desc gap to keep tail from touching
5119 * head, otherwise try next time
5120 */
5127 }
5135 }
5142 /*
5143 * Old method was to assume IPv4 packet by default if TSO was enabled.
5144 * 82571 hardware supports TSO capabilities for IPv6 as well...
5145 * no longer assume, we must.
5146 */
5153 /* if count is 0 then mapping error has occurred */
5160 /* Make sure there is space in the ring for the next send. */
5167 }
5170 }
5172 /**
5173 * e1000_tx_timeout - Respond to a Tx Hang
5174 * @netdev: network interface device structure
5175 **/
5177 {
5180 /* Do the reset outside of interrupt context */
5183 }
5186 {
5190 /* don't run the task if already down */
5198 }
5200 }
5202 /**
5203 * e1000_get_stats64 - Get System Network Statistics
5204 * @netdev: network interface device structure
5205 * @stats: rtnl_link_stats64 pointer
5206 *
5207 * Returns the address of the device statistics structure.
5208 **/
5211 {
5217 /* Fill out the OS statistics structure */
5225 /* Rx Errors */
5227 /*
5228 * RLEC on some newer hardware can be incorrect so build
5229 * our own version based on RUC and ROC
5230 */
5241 /* Tx Errors */
5248 /* Tx Dropped needs to be maintained elsewhere */
5252 }
5254 /**
5255 * e1000_change_mtu - Change the Maximum Transfer Unit
5256 * @netdev: network interface device structure
5257 * @new_mtu: new value for maximum frame size
5258 *
5259 * Returns 0 on success, negative on failure
5260 **/
5262 {
5266 /* Jumbo frame support */
5271 }
5273 /* Supported frame sizes */
5278 }
5280 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5286 }
5290 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5297 /*
5298 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5299 * means we reserve 2 more, this pushes us to allocate from the next
5300 * larger slab size.
5301 * i.e. RXBUFFER_2048 --> size-4096 slab
5302 * However with the new *_jumbo_rx* routines, jumbo receives will use
5303 * fragmented skbs
5304 */
5308 else
5311 /* adjust allocation if LPE protects us, and we aren't using SBP */
5319 else
5325 }
5329 {
5376 }
5381 }
5383 }
5386 {
5394 }
5395 }
5398 {
5404 /* copy MAC RARs to PHY RARs */
5411 }
5413 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5418 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5425 }
5427 /* configure PHY Rx Control register */
5447 /* enable PHY wakeup in MAC register */
5451 /* configure and enable PHY wakeup in PHY registers */
5455 /* activate PHY wakeup */
5460 release:
5464 }
5468 {
5473 /* Runtime suspend should only enable wakeup for link changes */
5488 }
5503 /* turn on all-multi mode if wake on multicast is enabled */
5508 }
5511 /* advertise wake from D3Cold */
5512 #define E1000_CTRL_ADVD3WUC 0x00100000
5513 /* phy power management enable */
5514 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5522 e1000_media_type_internal_serdes) {
5523 /* keep the laser running in D3 */
5527 }
5532 /* Allow time for pending master requests to run */
5536 /* enable wakeup by the PHY */
5541 /* enable wakeup by the MAC */
5544 }
5548 }
5552 /* make sure adapter isn't asleep if manageability is enabled */
5560 /*
5561 * Release control of h/w to f/w. If f/w is AMT enabled, this
5562 * would have already happened in close and is redundant.
5563 */
5569 }
5572 {
5576 }
5580 }
5584 {
5588 /*
5589 * The pci-e switch on some quad port adapters will report a
5590 * correctable error when the MAC transitions from D0 to D3. To
5591 * prevent this we need to mask off the correctable errors on the
5592 * downstream port of the pci-e switch.
5593 */
5597 u16 devctl;
5608 }
5609 }
5611 #ifdef CONFIG_PCIEASPM
5613 {
5615 }
5616 #else
5618 {
5620 u16 reg16;
5622 /*
5623 * Both device and parent should have the same ASPM setting.
5624 * Disable ASPM in downstream component first and then upstream.
5625 */
5638 }
5639 #endif
5641 {
5647 }
5649 #ifdef CONFIG_PM
5651 {
5653 }
5656 {
5661 u32 err;
5679 }
5686 /* report the system wakeup cause from S3/S4 */
5688 u16 phy_data;
5699 }
5711 }
5713 }
5724 /*
5725 * If the controller has AMT, do not set DRV_LOAD until the interface
5726 * is up. For all other cases, let the f/w know that the h/w is now
5727 * under the control of the driver.
5728 */
5733 }
5735 #ifdef CONFIG_PM_SLEEP
5737 {
5747 }
5750 {
5759 }
5762 #ifdef CONFIG_PM_RUNTIME
5764 {
5773 }
5776 }
5779 {
5791 }
5794 }
5797 {
5807 }
5812 {
5819 }
5821 #ifdef CONFIG_NET_POLL_CONTROLLER
5824 {
5837 vector++;
5843 vector++;
5848 }
5851 }
5853 /*
5854 * Polling 'interrupt' - used by things like netconsole to send skbs
5855 * without having to re-enable interrupts. It's not called while
5856 * the interrupt routine is executing.
5857 */
5859 {
5876 }
5877 }
5878 #endif
5880 /**
5881 * e1000_io_error_detected - called when PCI error is detected
5882 * @pdev: Pointer to PCI device
5883 * @state: The current pci connection state
5884 *
5885 * This function is called after a PCI bus error affecting
5886 * this device has been detected.
5887 */
5889 pci_channel_state_t state)
5890 {
5903 /* Request a slot slot reset. */
5905 }
5907 /**
5908 * e1000_io_slot_reset - called after the pci bus has been reset.
5909 * @pdev: Pointer to PCI device
5910 *
5911 * Restart the card from scratch, as if from a cold-boot. Implementation
5912 * resembles the first-half of the e1000_resume routine.
5913 */
5915 {
5921 pci_ers_result_t result;
5946 }
5951 }
5953 /**
5954 * e1000_io_resume - called when traffic can start flowing again.
5955 * @pdev: Pointer to PCI device
5956 *
5957 * This callback is called when the error recovery driver tells us that
5958 * its OK to resume normal operation. Implementation resembles the
5959 * second-half of the e1000_resume routine.
5960 */
5962 {
5973 }
5974 }
5978 /*
5979 * If the controller has AMT, do not set DRV_LOAD until the interface
5980 * is up. For all other cases, let the f/w know that the h/w is now
5981 * under the control of the driver.
5982 */
5986 }
5989 {
5992 u32 ret_val;
5995 /* print bus type/speed/width info */
5997 /* bus width */
6000 /* MAC address */
6005 E1000_PBANUM_LENGTH);
6010 }
6013 {
6024 /* Deep Smart Power Down (DSPD) */
6027 }
6028 }
6031 netdev_features_t features)
6032 {
6041 NETIF_F_RXALL)))
6048 /* We need to take it back to defaults, which might mean
6049 * stripping is still disabled at the adapter level.
6050 */
6053 else
6055 }
6056 }
6062 else
6066 }
6082 #ifdef CONFIG_NET_POLL_CONTROLLER
6084 #endif
6086 };
6088 /**
6089 * e1000_probe - Device Initialization Routine
6090 * @pdev: PCI device information struct
6091 * @ent: entry in e1000_pci_tbl
6092 *
6093 * Returns 0 on success, negative on failure
6094 *
6095 * e1000_probe initializes an adapter identified by a pci_dev structure.
6096 * The OS initialization, configuring of the adapter private structure,
6097 * and a hardware reset occur.
6098 **/
6101 {
6139 }
6140 }
6141 }
6145 e1000e_driver_name);
6149 /* AER (Advanced Error Reporting) hooks */
6153 /* PCI config space info */
6196 }
6198 /* construct the net_device struct */
6212 /* setup adapter struct */
6233 /* Copper options */
6238 }
6244 /* Set initial default active device features */
6246 NETIF_F_HW_VLAN_RX |
6247 NETIF_F_HW_VLAN_TX |
6248 NETIF_F_TSO |
6249 NETIF_F_TSO6 |
6250 NETIF_F_RXHASH |
6251 NETIF_F_RXCSUM |
6252 NETIF_F_HW_CSUM);
6254 /* Set user-changeable features (subset of all device features) */
6264 NETIF_F_TSO |
6265 NETIF_F_TSO6 |
6266 NETIF_F_HW_CSUM);
6273 }
6278 /*
6279 * before reading the NVM, reset the controller to
6280 * put the device in a known good starting state
6281 */
6284 /*
6285 * systems with ASPM and others may see the checksum fail on the first
6286 * attempt. Let's give it a few tries
6287 */
6295 }
6296 }
6300 /* copy the MAC address */
6313 }
6329 /* Initialize link parameters. User can change them with ethtool */
6336 /* ring size defaults */
6340 /*
6341 * Initial Wake on LAN setting - If APM wake is enabled in
6342 * the EEPROM, enable the ACPI Magic Packet filter
6343 */
6345 /* APME bit in EEPROM is mapped to WUC.APME */
6356 else
6359 }
6361 /* fetch WoL from EEPROM */
6365 /*
6366 * now that we have the eeprom settings, apply the special cases
6367 * where the eeprom may be wrong or the board simply won't support
6368 * wake on lan on a particular port
6369 */
6373 /* initialize the wol settings based on the eeprom settings */
6377 /* save off EEPROM version number */
6380 /* reset the hardware with the new settings */
6383 /*
6384 * If the controller has AMT, do not set DRV_LOAD until the interface
6385 * is up. For all other cases, let the f/w know that the h/w is now
6386 * under the control of the driver.
6387 */
6396 /* carrier off reporting is important to ethtool even BEFORE open */
6406 err_register:
6409 err_eeprom:
6412 err_hw_init:
6415 err_sw_init:
6419 err_flashmap:
6421 err_ioremap:
6423 err_alloc_etherdev:
6426 err_pci_reg:
6427 err_dma:
6430 }
6432 /**
6433 * e1000_remove - Device Removal Routine
6434 * @pdev: PCI device information struct
6435 *
6436 * e1000_remove is called by the PCI subsystem to alert the driver
6437 * that it should release a PCI device. The could be caused by a
6438 * Hot-Plug event, or because the driver is going to be removed from
6439 * memory.
6440 **/
6442 {
6447 /*
6448 * The timers may be rescheduled, so explicitly disable them
6449 * from being rescheduled.
6450 */
6465 /* Don't lie to e1000_close() down the road. */
6473 /*
6474 * Release control of h/w to f/w. If f/w is AMT enabled, this
6475 * would have already happened in close and is redundant.
6476 */
6491 /* AER disable */
6495 }
6497 /* PCI Error Recovery (ERS) */
6502 };
6529 board_80003es2lan },
6531 board_80003es2lan },
6533 board_80003es2lan },
6535 board_80003es2lan },
6576 };
6579 #ifdef CONFIG_PM
6584 };
6585 #endif
6587 /* PCI Device API Driver */
6593 #ifdef CONFIG_PM
6596 },
6597 #endif
6600 };
6602 /**
6603 * e1000_init_module - Driver Registration Routine
6604 *
6605 * e1000_init_module is the first routine called when the driver is
6606 * loaded. All it does is register with the PCI subsystem.
6607 **/
6609 {
6612 e1000e_driver_version);
6617 }
6620 /**
6621 * e1000_exit_module - Driver Exit Cleanup Routine
6622 *
6623 * e1000_exit_module is called just before the driver is removed
6624 * from memory.
6625 **/
6627 {
6629 }
6638 /* netdev.c */