arch/i386/kernel/acpi/cstate.c

   1 /*
   2  * arch/i386/kernel/acpi/cstate.c
   3  *
   4  * Copyright (C) 2005 Intel Corporation
   5  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
   6  *      - Added _PDC for SMP C-states on Intel CPUs
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/init.h>
  12 #include <linux/acpi.h>
  13
  14 #include <acpi/processor.h>
  15 #include <asm/acpi.h>
  16
  17 /*
  18  * Initialize bm_flags based on the CPU cache properties
  19  * On SMP it depends on cache configuration
  20  * - When cache is not shared among all CPUs, we flush cache
  21  *   before entering C3.
  22  * - When cache is shared among all CPUs, we use bm_check
  23  *   mechanism as in UP case
  24  *
  25  * This routine is called only after all the CPUs are online
  26  */
  27 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
  28                                         unsigned int cpu)
  29 {
  30         struct cpuinfo_x86 *c = cpu_data + cpu;
  31
  32         flags->bm_check = 0;
  33         if (num_online_cpus() == 1)
  34                 flags->bm_check = 1;
  35         else if (c->x86_vendor == X86_VENDOR_INTEL) {
  36                 /*
  37                  * Today all CPUs that support C3 share cache.
  38                  * TBD: This needs to look at cache shared map, once
  39                  * multi-core detection patch makes to the base.
  40                  */
  41                 flags->bm_check = 1;
  42         }
  43 }
  44
  45 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);