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AMD IOMMU: add device attach function for IOMMU API
[linux-2.6/cjktty.git] / arch / x86 / kernel / amd_iommu.c
blob2f7c0b3a448b4a482cab1e71382418faba42ba63
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #ifdef CONFIG_IOMMU_API
26 #include <linux/iommu.h>
27 #endif
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
33
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
35
36 #define EXIT_LOOP_COUNT 10000000
37
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
39
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
43
44 /*
45 * general struct to manage commands send to an IOMMU
46 */
47 struct iommu_cmd {
48 u32 data[4];
49 };
50
51 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
52 struct unity_map_entry *e);
53 static struct dma_ops_domain *find_protection_domain(u16 devid);
54
55
56 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
57 static int iommu_has_npcache(struct amd_iommu *iommu)
58 {
59 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
60 }
61
62 /****************************************************************************
63 *
64 * Interrupt handling functions
65 *
66 ****************************************************************************/
67
68 static void iommu_print_event(void *__evt)
69 {
70 u32 *event = __evt;
71 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
72 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
73 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
74 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
75 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
76
77 printk(KERN_ERR "AMD IOMMU: Event logged [");
78
79 switch (type) {
80 case EVENT_TYPE_ILL_DEV:
81 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
82 "address=0x%016llx flags=0x%04x]\n",
83 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
84 address, flags);
85 break;
86 case EVENT_TYPE_IO_FAULT:
87 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
88 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
89 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90 domid, address, flags);
91 break;
92 case EVENT_TYPE_DEV_TAB_ERR:
93 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
94 "address=0x%016llx flags=0x%04x]\n",
95 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
96 address, flags);
97 break;
98 case EVENT_TYPE_PAGE_TAB_ERR:
99 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
100 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
101 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
102 domid, address, flags);
103 break;
104 case EVENT_TYPE_ILL_CMD:
105 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
106 break;
107 case EVENT_TYPE_CMD_HARD_ERR:
108 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
109 "flags=0x%04x]\n", address, flags);
110 break;
111 case EVENT_TYPE_IOTLB_INV_TO:
112 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
113 "address=0x%016llx]\n",
114 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
115 address);
116 break;
117 case EVENT_TYPE_INV_DEV_REQ:
118 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
119 "address=0x%016llx flags=0x%04x]\n",
120 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
121 address, flags);
122 break;
123 default:
124 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
125 }
126 }
127
128 static void iommu_poll_events(struct amd_iommu *iommu)
129 {
130 u32 head, tail;
131 unsigned long flags;
132
133 spin_lock_irqsave(&iommu->lock, flags);
134
135 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
136 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
137
138 while (head != tail) {
139 iommu_print_event(iommu->evt_buf + head);
140 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
141 }
142
143 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
144
145 spin_unlock_irqrestore(&iommu->lock, flags);
146 }
147
148 irqreturn_t amd_iommu_int_handler(int irq, void *data)
149 {
150 struct amd_iommu *iommu;
151
152 list_for_each_entry(iommu, &amd_iommu_list, list)
153 iommu_poll_events(iommu);
154
155 return IRQ_HANDLED;
156 }
157
158 /****************************************************************************
159 *
160 * IOMMU command queuing functions
161 *
162 ****************************************************************************/
163
164 /*
165 * Writes the command to the IOMMUs command buffer and informs the
166 * hardware about the new command. Must be called with iommu->lock held.
167 */
168 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
169 {
170 u32 tail, head;
171 u8 *target;
172
173 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
174 target = iommu->cmd_buf + tail;
175 memcpy_toio(target, cmd, sizeof(*cmd));
176 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
177 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
178 if (tail == head)
179 return -ENOMEM;
180 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
181
182 return 0;
183 }
184
185 /*
186 * General queuing function for commands. Takes iommu->lock and calls
187 * __iommu_queue_command().
188 */
189 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
190 {
191 unsigned long flags;
192 int ret;
193
194 spin_lock_irqsave(&iommu->lock, flags);
195 ret = __iommu_queue_command(iommu, cmd);
196 if (!ret)
197 iommu->need_sync = 1;
198 spin_unlock_irqrestore(&iommu->lock, flags);
199
200 return ret;
201 }
202
203 /*
204 * This function waits until an IOMMU has completed a completion
205 * wait command
206 */
207 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
208 {
209 int ready = 0;
210 unsigned status = 0;
211 unsigned long i = 0;
212
213 while (!ready && (i < EXIT_LOOP_COUNT)) {
214 ++i;
215 /* wait for the bit to become one */
216 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
217 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
218 }
219
220 /* set bit back to zero */
221 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
222 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
223
224 if (unlikely(i == EXIT_LOOP_COUNT))
225 panic("AMD IOMMU: Completion wait loop failed\n");
226 }
227
228 /*
229 * This function queues a completion wait command into the command
230 * buffer of an IOMMU
231 */
232 static int __iommu_completion_wait(struct amd_iommu *iommu)
233 {
234 struct iommu_cmd cmd;
235
236 memset(&cmd, 0, sizeof(cmd));
237 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
238 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
239
240 return __iommu_queue_command(iommu, &cmd);
241 }
242
243 /*
244 * This function is called whenever we need to ensure that the IOMMU has
245 * completed execution of all commands we sent. It sends a
246 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
247 * us about that by writing a value to a physical address we pass with
248 * the command.
249 */
250 static int iommu_completion_wait(struct amd_iommu *iommu)
251 {
252 int ret = 0;
253 unsigned long flags;
254
255 spin_lock_irqsave(&iommu->lock, flags);
256
257 if (!iommu->need_sync)
258 goto out;
259
260 ret = __iommu_completion_wait(iommu);
261
262 iommu->need_sync = 0;
263
264 if (ret)
265 goto out;
266
267 __iommu_wait_for_completion(iommu);
268
269 out:
270 spin_unlock_irqrestore(&iommu->lock, flags);
271
272 return 0;
273 }
274
275 /*
276 * Command send function for invalidating a device table entry
277 */
278 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
279 {
280 struct iommu_cmd cmd;
281 int ret;
282
283 BUG_ON(iommu == NULL);
284
285 memset(&cmd, 0, sizeof(cmd));
286 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
287 cmd.data[0] = devid;
288
289 ret = iommu_queue_command(iommu, &cmd);
290
291 return ret;
292 }
293
294 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
295 u16 domid, int pde, int s)
296 {
297 memset(cmd, 0, sizeof(*cmd));
298 address &= PAGE_MASK;
299 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
300 cmd->data[1] |= domid;
301 cmd->data[2] = lower_32_bits(address);
302 cmd->data[3] = upper_32_bits(address);
303 if (s) /* size bit - we flush more than one 4kb page */
304 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
305 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
306 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
307 }
308
309 /*
310 * Generic command send function for invalidaing TLB entries
311 */
312 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
313 u64 address, u16 domid, int pde, int s)
314 {
315 struct iommu_cmd cmd;
316 int ret;
317
318 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
319
320 ret = iommu_queue_command(iommu, &cmd);
321
322 return ret;
323 }
324
325 /*
326 * TLB invalidation function which is called from the mapping functions.
327 * It invalidates a single PTE if the range to flush is within a single
328 * page. Otherwise it flushes the whole TLB of the IOMMU.
329 */
330 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
331 u64 address, size_t size)
332 {
333 int s = 0;
334 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
335
336 address &= PAGE_MASK;
337
338 if (pages > 1) {
339 /*
340 * If we have to flush more than one page, flush all
341 * TLB entries for this domain
342 */
343 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
344 s = 1;
345 }
346
347 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
348
349 return 0;
350 }
351
352 /* Flush the whole IO/TLB for a given protection domain */
353 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
354 {
355 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
356
357 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
358 }
359
360 #ifdef CONFIG_IOMMU_API
361 /*
362 * This function is used to flush the IO/TLB for a given protection domain
363 * on every IOMMU in the system
364 */
365 static void iommu_flush_domain(u16 domid)
366 {
367 unsigned long flags;
368 struct amd_iommu *iommu;
369 struct iommu_cmd cmd;
370
371 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
372 domid, 1, 1);
373
374 list_for_each_entry(iommu, &amd_iommu_list, list) {
375 spin_lock_irqsave(&iommu->lock, flags);
376 __iommu_queue_command(iommu, &cmd);
377 __iommu_completion_wait(iommu);
378 __iommu_wait_for_completion(iommu);
379 spin_unlock_irqrestore(&iommu->lock, flags);
380 }
381 }
382 #endif
383
384 /****************************************************************************
385 *
386 * The functions below are used the create the page table mappings for
387 * unity mapped regions.
388 *
389 ****************************************************************************/
390
391 /*
392 * Generic mapping functions. It maps a physical address into a DMA
393 * address space. It allocates the page table pages if necessary.
394 * In the future it can be extended to a generic mapping function
395 * supporting all features of AMD IOMMU page tables like level skipping
396 * and full 64 bit address spaces.
397 */
398 static int iommu_map_page(struct protection_domain *dom,
399 unsigned long bus_addr,
400 unsigned long phys_addr,
401 int prot)
402 {
403 u64 __pte, *pte, *page;
404
405 bus_addr = PAGE_ALIGN(bus_addr);
406 phys_addr = PAGE_ALIGN(phys_addr);
407
408 /* only support 512GB address spaces for now */
409 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
410 return -EINVAL;
411
412 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
413
414 if (!IOMMU_PTE_PRESENT(*pte)) {
415 page = (u64 *)get_zeroed_page(GFP_KERNEL);
416 if (!page)
417 return -ENOMEM;
418 *pte = IOMMU_L2_PDE(virt_to_phys(page));
419 }
420
421 pte = IOMMU_PTE_PAGE(*pte);
422 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
423
424 if (!IOMMU_PTE_PRESENT(*pte)) {
425 page = (u64 *)get_zeroed_page(GFP_KERNEL);
426 if (!page)
427 return -ENOMEM;
428 *pte = IOMMU_L1_PDE(virt_to_phys(page));
429 }
430
431 pte = IOMMU_PTE_PAGE(*pte);
432 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
433
434 if (IOMMU_PTE_PRESENT(*pte))
435 return -EBUSY;
436
437 __pte = phys_addr | IOMMU_PTE_P;
438 if (prot & IOMMU_PROT_IR)
439 __pte |= IOMMU_PTE_IR;
440 if (prot & IOMMU_PROT_IW)
441 __pte |= IOMMU_PTE_IW;
442
443 *pte = __pte;
444
445 return 0;
446 }
447
448 /*
449 * This function checks if a specific unity mapping entry is needed for
450 * this specific IOMMU.
451 */
452 static int iommu_for_unity_map(struct amd_iommu *iommu,
453 struct unity_map_entry *entry)
454 {
455 u16 bdf, i;
456
457 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
458 bdf = amd_iommu_alias_table[i];
459 if (amd_iommu_rlookup_table[bdf] == iommu)
460 return 1;
461 }
462
463 return 0;
464 }
465
466 /*
467 * Init the unity mappings for a specific IOMMU in the system
468 *
469 * Basically iterates over all unity mapping entries and applies them to
470 * the default domain DMA of that IOMMU if necessary.
471 */
472 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
473 {
474 struct unity_map_entry *entry;
475 int ret;
476
477 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
478 if (!iommu_for_unity_map(iommu, entry))
479 continue;
480 ret = dma_ops_unity_map(iommu->default_dom, entry);
481 if (ret)
482 return ret;
483 }
484
485 return 0;
486 }
487
488 /*
489 * This function actually applies the mapping to the page table of the
490 * dma_ops domain.
491 */
492 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
493 struct unity_map_entry *e)
494 {
495 u64 addr;
496 int ret;
497
498 for (addr = e->address_start; addr < e->address_end;
499 addr += PAGE_SIZE) {
500 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
501 if (ret)
502 return ret;
503 /*
504 * if unity mapping is in aperture range mark the page
505 * as allocated in the aperture
506 */
507 if (addr < dma_dom->aperture_size)
508 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
509 }
510
511 return 0;
512 }
513
514 /*
515 * Inits the unity mappings required for a specific device
516 */
517 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
518 u16 devid)
519 {
520 struct unity_map_entry *e;
521 int ret;
522
523 list_for_each_entry(e, &amd_iommu_unity_map, list) {
524 if (!(devid >= e->devid_start && devid <= e->devid_end))
525 continue;
526 ret = dma_ops_unity_map(dma_dom, e);
527 if (ret)
528 return ret;
529 }
530
531 return 0;
532 }
533
534 /****************************************************************************
535 *
536 * The next functions belong to the address allocator for the dma_ops
537 * interface functions. They work like the allocators in the other IOMMU
538 * drivers. Its basically a bitmap which marks the allocated pages in
539 * the aperture. Maybe it could be enhanced in the future to a more
540 * efficient allocator.
541 *
542 ****************************************************************************/
543
544 /*
545 * The address allocator core function.
546 *
547 * called with domain->lock held
548 */
549 static unsigned long dma_ops_alloc_addresses(struct device *dev,
550 struct dma_ops_domain *dom,
551 unsigned int pages,
552 unsigned long align_mask,
553 u64 dma_mask)
554 {
555 unsigned long limit;
556 unsigned long address;
557 unsigned long boundary_size;
558
559 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
560 PAGE_SIZE) >> PAGE_SHIFT;
561 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
562 dma_mask >> PAGE_SHIFT);
563
564 if (dom->next_bit >= limit) {
565 dom->next_bit = 0;
566 dom->need_flush = true;
567 }
568
569 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
570 0 , boundary_size, align_mask);
571 if (address == -1) {
572 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
573 0, boundary_size, align_mask);
574 dom->need_flush = true;
575 }
576
577 if (likely(address != -1)) {
578 dom->next_bit = address + pages;
579 address <<= PAGE_SHIFT;
580 } else
581 address = bad_dma_address;
582
583 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
584
585 return address;
586 }
587
588 /*
589 * The address free function.
590 *
591 * called with domain->lock held
592 */
593 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
594 unsigned long address,
595 unsigned int pages)
596 {
597 address >>= PAGE_SHIFT;
598 iommu_area_free(dom->bitmap, address, pages);
599
600 if (address >= dom->next_bit)
601 dom->need_flush = true;
602 }
603
604 /****************************************************************************
605 *
606 * The next functions belong to the domain allocation. A domain is
607 * allocated for every IOMMU as the default domain. If device isolation
608 * is enabled, every device get its own domain. The most important thing
609 * about domains is the page table mapping the DMA address space they
610 * contain.
611 *
612 ****************************************************************************/
613
614 static u16 domain_id_alloc(void)
615 {
616 unsigned long flags;
617 int id;
618
619 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
620 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
621 BUG_ON(id == 0);
622 if (id > 0 && id < MAX_DOMAIN_ID)
623 __set_bit(id, amd_iommu_pd_alloc_bitmap);
624 else
625 id = 0;
626 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
627
628 return id;
629 }
630
631 #ifdef CONFIG_IOMMU_API
632 static void domain_id_free(int id)
633 {
634 unsigned long flags;
635
636 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
637 if (id > 0 && id < MAX_DOMAIN_ID)
638 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
639 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
640 }
641 #endif
642
643 /*
644 * Used to reserve address ranges in the aperture (e.g. for exclusion
645 * ranges.
646 */
647 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
648 unsigned long start_page,
649 unsigned int pages)
650 {
651 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
652
653 if (start_page + pages > last_page)
654 pages = last_page - start_page;
655
656 iommu_area_reserve(dom->bitmap, start_page, pages);
657 }
658
659 static void free_pagetable(struct protection_domain *domain)
660 {
661 int i, j;
662 u64 *p1, *p2, *p3;
663
664 p1 = domain->pt_root;
665
666 if (!p1)
667 return;
668
669 for (i = 0; i < 512; ++i) {
670 if (!IOMMU_PTE_PRESENT(p1[i]))
671 continue;
672
673 p2 = IOMMU_PTE_PAGE(p1[i]);
674 for (j = 0; j < 512; ++j) {
675 if (!IOMMU_PTE_PRESENT(p2[j]))
676 continue;
677 p3 = IOMMU_PTE_PAGE(p2[j]);
678 free_page((unsigned long)p3);
679 }
680
681 free_page((unsigned long)p2);
682 }
683
684 free_page((unsigned long)p1);
685
686 domain->pt_root = NULL;
687 }
688
689 /*
690 * Free a domain, only used if something went wrong in the
691 * allocation path and we need to free an already allocated page table
692 */
693 static void dma_ops_domain_free(struct dma_ops_domain *dom)
694 {
695 if (!dom)
696 return;
697
698 free_pagetable(&dom->domain);
699
700 kfree(dom->pte_pages);
701
702 kfree(dom->bitmap);
703
704 kfree(dom);
705 }
706
707 /*
708 * Allocates a new protection domain usable for the dma_ops functions.
709 * It also intializes the page table and the address allocator data
710 * structures required for the dma_ops interface
711 */
712 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
713 unsigned order)
714 {
715 struct dma_ops_domain *dma_dom;
716 unsigned i, num_pte_pages;
717 u64 *l2_pde;
718 u64 address;
719
720 /*
721 * Currently the DMA aperture must be between 32 MB and 1GB in size
722 */
723 if ((order < 25) || (order > 30))
724 return NULL;
725
726 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
727 if (!dma_dom)
728 return NULL;
729
730 spin_lock_init(&dma_dom->domain.lock);
731
732 dma_dom->domain.id = domain_id_alloc();
733 if (dma_dom->domain.id == 0)
734 goto free_dma_dom;
735 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
736 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
737 dma_dom->domain.flags = PD_DMA_OPS_MASK;
738 dma_dom->domain.priv = dma_dom;
739 if (!dma_dom->domain.pt_root)
740 goto free_dma_dom;
741 dma_dom->aperture_size = (1ULL << order);
742 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
743 GFP_KERNEL);
744 if (!dma_dom->bitmap)
745 goto free_dma_dom;
746 /*
747 * mark the first page as allocated so we never return 0 as
748 * a valid dma-address. So we can use 0 as error value
749 */
750 dma_dom->bitmap[0] = 1;
751 dma_dom->next_bit = 0;
752
753 dma_dom->need_flush = false;
754 dma_dom->target_dev = 0xffff;
755
756 /* Intialize the exclusion range if necessary */
757 if (iommu->exclusion_start &&
758 iommu->exclusion_start < dma_dom->aperture_size) {
759 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
760 int pages = iommu_num_pages(iommu->exclusion_start,
761 iommu->exclusion_length,
762 PAGE_SIZE);
763 dma_ops_reserve_addresses(dma_dom, startpage, pages);
764 }
765
766 /*
767 * At the last step, build the page tables so we don't need to
768 * allocate page table pages in the dma_ops mapping/unmapping
769 * path.
770 */
771 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
772 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
773 GFP_KERNEL);
774 if (!dma_dom->pte_pages)
775 goto free_dma_dom;
776
777 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
778 if (l2_pde == NULL)
779 goto free_dma_dom;
780
781 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
782
783 for (i = 0; i < num_pte_pages; ++i) {
784 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
785 if (!dma_dom->pte_pages[i])
786 goto free_dma_dom;
787 address = virt_to_phys(dma_dom->pte_pages[i]);
788 l2_pde[i] = IOMMU_L1_PDE(address);
789 }
790
791 return dma_dom;
792
793 free_dma_dom:
794 dma_ops_domain_free(dma_dom);
795
796 return NULL;
797 }
798
799 /*
800 * little helper function to check whether a given protection domain is a
801 * dma_ops domain
802 */
803 static bool dma_ops_domain(struct protection_domain *domain)
804 {
805 return domain->flags & PD_DMA_OPS_MASK;
806 }
807
808 /*
809 * Find out the protection domain structure for a given PCI device. This
810 * will give us the pointer to the page table root for example.
811 */
812 static struct protection_domain *domain_for_device(u16 devid)
813 {
814 struct protection_domain *dom;
815 unsigned long flags;
816
817 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
818 dom = amd_iommu_pd_table[devid];
819 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
820
821 return dom;
822 }
823
824 /*
825 * If a device is not yet associated with a domain, this function does
826 * assigns it visible for the hardware
827 */
828 static void attach_device(struct amd_iommu *iommu,
829 struct protection_domain *domain,
830 u16 devid)
831 {
832 unsigned long flags;
833 u64 pte_root = virt_to_phys(domain->pt_root);
834
835 domain->dev_cnt += 1;
836
837 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
838 << DEV_ENTRY_MODE_SHIFT;
839 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
840
841 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
842 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
843 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
844 amd_iommu_dev_table[devid].data[2] = domain->id;
845
846 amd_iommu_pd_table[devid] = domain;
847 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
848
849 iommu_queue_inv_dev_entry(iommu, devid);
850 }
851
852 /*
853 * Removes a device from a protection domain (unlocked)
854 */
855 static void __detach_device(struct protection_domain *domain, u16 devid)
856 {
857
858 /* lock domain */
859 spin_lock(&domain->lock);
860
861 /* remove domain from the lookup table */
862 amd_iommu_pd_table[devid] = NULL;
863
864 /* remove entry from the device table seen by the hardware */
865 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
866 amd_iommu_dev_table[devid].data[1] = 0;
867 amd_iommu_dev_table[devid].data[2] = 0;
868
869 /* decrease reference counter */
870 domain->dev_cnt -= 1;
871
872 /* ready */
873 spin_unlock(&domain->lock);
874 }
875
876 /*
877 * Removes a device from a protection domain (with devtable_lock held)
878 */
879 static void detach_device(struct protection_domain *domain, u16 devid)
880 {
881 unsigned long flags;
882
883 /* lock device table */
884 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
885 __detach_device(domain, devid);
886 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
887 }
888
889 static int device_change_notifier(struct notifier_block *nb,
890 unsigned long action, void *data)
891 {
892 struct device *dev = data;
893 struct pci_dev *pdev = to_pci_dev(dev);
894 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
895 struct protection_domain *domain;
896 struct dma_ops_domain *dma_domain;
897 struct amd_iommu *iommu;
898
899 if (devid > amd_iommu_last_bdf)
900 goto out;
901
902 devid = amd_iommu_alias_table[devid];
903
904 iommu = amd_iommu_rlookup_table[devid];
905 if (iommu == NULL)
906 goto out;
907
908 domain = domain_for_device(devid);
909
910 if (domain && !dma_ops_domain(domain))
911 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
912 "to a non-dma-ops domain\n", dev_name(dev));
913
914 switch (action) {
915 case BUS_NOTIFY_BOUND_DRIVER:
916 if (domain)
917 goto out;
918 dma_domain = find_protection_domain(devid);
919 if (!dma_domain)
920 dma_domain = iommu->default_dom;
921 attach_device(iommu, &dma_domain->domain, devid);
922 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
923 "device %s\n", dma_domain->domain.id, dev_name(dev));
924 break;
925 case BUS_NOTIFY_UNBIND_DRIVER:
926 if (!domain)
927 goto out;
928 detach_device(domain, devid);
929 break;
930 default:
931 goto out;
932 }
933
934 iommu_queue_inv_dev_entry(iommu, devid);
935 iommu_completion_wait(iommu);
936
937 out:
938 return 0;
939 }
940
941 struct notifier_block device_nb = {
942 .notifier_call = device_change_notifier,
943 };
944
945 /*****************************************************************************
946 *
947 * The next functions belong to the dma_ops mapping/unmapping code.
948 *
949 *****************************************************************************/
950
951 /*
952 * This function checks if the driver got a valid device from the caller to
953 * avoid dereferencing invalid pointers.
954 */
955 static bool check_device(struct device *dev)
956 {
957 if (!dev || !dev->dma_mask)
958 return false;
959
960 return true;
961 }
962
963 /*
964 * In this function the list of preallocated protection domains is traversed to
965 * find the domain for a specific device
966 */
967 static struct dma_ops_domain *find_protection_domain(u16 devid)
968 {
969 struct dma_ops_domain *entry, *ret = NULL;
970 unsigned long flags;
971
972 if (list_empty(&iommu_pd_list))
973 return NULL;
974
975 spin_lock_irqsave(&iommu_pd_list_lock, flags);
976
977 list_for_each_entry(entry, &iommu_pd_list, list) {
978 if (entry->target_dev == devid) {
979 ret = entry;
980 break;
981 }
982 }
983
984 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
985
986 return ret;
987 }
988
989 /*
990 * In the dma_ops path we only have the struct device. This function
991 * finds the corresponding IOMMU, the protection domain and the
992 * requestor id for a given device.
993 * If the device is not yet associated with a domain this is also done
994 * in this function.
995 */
996 static int get_device_resources(struct device *dev,
997 struct amd_iommu **iommu,
998 struct protection_domain **domain,
999 u16 *bdf)
1000 {
1001 struct dma_ops_domain *dma_dom;
1002 struct pci_dev *pcidev;
1003 u16 _bdf;
1004
1005 *iommu = NULL;
1006 *domain = NULL;
1007 *bdf = 0xffff;
1008
1009 if (dev->bus != &pci_bus_type)
1010 return 0;
1011
1012 pcidev = to_pci_dev(dev);
1013 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1014
1015 /* device not translated by any IOMMU in the system? */
1016 if (_bdf > amd_iommu_last_bdf)
1017 return 0;
1018
1019 *bdf = amd_iommu_alias_table[_bdf];
1020
1021 *iommu = amd_iommu_rlookup_table[*bdf];
1022 if (*iommu == NULL)
1023 return 0;
1024 *domain = domain_for_device(*bdf);
1025 if (*domain == NULL) {
1026 dma_dom = find_protection_domain(*bdf);
1027 if (!dma_dom)
1028 dma_dom = (*iommu)->default_dom;
1029 *domain = &dma_dom->domain;
1030 attach_device(*iommu, *domain, *bdf);
1031 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1032 "device ", (*domain)->id);
1033 print_devid(_bdf, 1);
1034 }
1035
1036 if (domain_for_device(_bdf) == NULL)
1037 attach_device(*iommu, *domain, _bdf);
1038
1039 return 1;
1040 }
1041
1042 /*
1043 * This is the generic map function. It maps one 4kb page at paddr to
1044 * the given address in the DMA address space for the domain.
1045 */
1046 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1047 struct dma_ops_domain *dom,
1048 unsigned long address,
1049 phys_addr_t paddr,
1050 int direction)
1051 {
1052 u64 *pte, __pte;
1053
1054 WARN_ON(address > dom->aperture_size);
1055
1056 paddr &= PAGE_MASK;
1057
1058 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1059 pte += IOMMU_PTE_L0_INDEX(address);
1060
1061 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1062
1063 if (direction == DMA_TO_DEVICE)
1064 __pte |= IOMMU_PTE_IR;
1065 else if (direction == DMA_FROM_DEVICE)
1066 __pte |= IOMMU_PTE_IW;
1067 else if (direction == DMA_BIDIRECTIONAL)
1068 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1069
1070 WARN_ON(*pte);
1071
1072 *pte = __pte;
1073
1074 return (dma_addr_t)address;
1075 }
1076
1077 /*
1078 * The generic unmapping function for on page in the DMA address space.
1079 */
1080 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1081 struct dma_ops_domain *dom,
1082 unsigned long address)
1083 {
1084 u64 *pte;
1085
1086 if (address >= dom->aperture_size)
1087 return;
1088
1089 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1090
1091 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1092 pte += IOMMU_PTE_L0_INDEX(address);
1093
1094 WARN_ON(!*pte);
1095
1096 *pte = 0ULL;
1097 }
1098
1099 /*
1100 * This function contains common code for mapping of a physically
1101 * contiguous memory region into DMA address space. It is used by all
1102 * mapping functions provided with this IOMMU driver.
1103 * Must be called with the domain lock held.
1104 */
1105 static dma_addr_t __map_single(struct device *dev,
1106 struct amd_iommu *iommu,
1107 struct dma_ops_domain *dma_dom,
1108 phys_addr_t paddr,
1109 size_t size,
1110 int dir,
1111 bool align,
1112 u64 dma_mask)
1113 {
1114 dma_addr_t offset = paddr & ~PAGE_MASK;
1115 dma_addr_t address, start;
1116 unsigned int pages;
1117 unsigned long align_mask = 0;
1118 int i;
1119
1120 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1121 paddr &= PAGE_MASK;
1122
1123 if (align)
1124 align_mask = (1UL << get_order(size)) - 1;
1125
1126 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1127 dma_mask);
1128 if (unlikely(address == bad_dma_address))
1129 goto out;
1130
1131 start = address;
1132 for (i = 0; i < pages; ++i) {
1133 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1134 paddr += PAGE_SIZE;
1135 start += PAGE_SIZE;
1136 }
1137 address += offset;
1138
1139 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1140 iommu_flush_tlb(iommu, dma_dom->domain.id);
1141 dma_dom->need_flush = false;
1142 } else if (unlikely(iommu_has_npcache(iommu)))
1143 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1144
1145 out:
1146 return address;
1147 }
1148
1149 /*
1150 * Does the reverse of the __map_single function. Must be called with
1151 * the domain lock held too
1152 */
1153 static void __unmap_single(struct amd_iommu *iommu,
1154 struct dma_ops_domain *dma_dom,
1155 dma_addr_t dma_addr,
1156 size_t size,
1157 int dir)
1158 {
1159 dma_addr_t i, start;
1160 unsigned int pages;
1161
1162 if ((dma_addr == bad_dma_address) ||
1163 (dma_addr + size > dma_dom->aperture_size))
1164 return;
1165
1166 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1167 dma_addr &= PAGE_MASK;
1168 start = dma_addr;
1169
1170 for (i = 0; i < pages; ++i) {
1171 dma_ops_domain_unmap(iommu, dma_dom, start);
1172 start += PAGE_SIZE;
1173 }
1174
1175 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1176
1177 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1178 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1179 dma_dom->need_flush = false;
1180 }
1181 }
1182
1183 /*
1184 * The exported map_single function for dma_ops.
1185 */
1186 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1187 size_t size, int dir)
1188 {
1189 unsigned long flags;
1190 struct amd_iommu *iommu;
1191 struct protection_domain *domain;
1192 u16 devid;
1193 dma_addr_t addr;
1194 u64 dma_mask;
1195
1196 if (!check_device(dev))
1197 return bad_dma_address;
1198
1199 dma_mask = *dev->dma_mask;
1200
1201 get_device_resources(dev, &iommu, &domain, &devid);
1202
1203 if (iommu == NULL || domain == NULL)
1204 /* device not handled by any AMD IOMMU */
1205 return (dma_addr_t)paddr;
1206
1207 if (!dma_ops_domain(domain))
1208 return bad_dma_address;
1209
1210 spin_lock_irqsave(&domain->lock, flags);
1211 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1212 dma_mask);
1213 if (addr == bad_dma_address)
1214 goto out;
1215
1216 iommu_completion_wait(iommu);
1217
1218 out:
1219 spin_unlock_irqrestore(&domain->lock, flags);
1220
1221 return addr;
1222 }
1223
1224 /*
1225 * The exported unmap_single function for dma_ops.
1226 */
1227 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1228 size_t size, int dir)
1229 {
1230 unsigned long flags;
1231 struct amd_iommu *iommu;
1232 struct protection_domain *domain;
1233 u16 devid;
1234
1235 if (!check_device(dev) ||
1236 !get_device_resources(dev, &iommu, &domain, &devid))
1237 /* device not handled by any AMD IOMMU */
1238 return;
1239
1240 if (!dma_ops_domain(domain))
1241 return;
1242
1243 spin_lock_irqsave(&domain->lock, flags);
1244
1245 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1246
1247 iommu_completion_wait(iommu);
1248
1249 spin_unlock_irqrestore(&domain->lock, flags);
1250 }
1251
1252 /*
1253 * This is a special map_sg function which is used if we should map a
1254 * device which is not handled by an AMD IOMMU in the system.
1255 */
1256 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1257 int nelems, int dir)
1258 {
1259 struct scatterlist *s;
1260 int i;
1261
1262 for_each_sg(sglist, s, nelems, i) {
1263 s->dma_address = (dma_addr_t)sg_phys(s);
1264 s->dma_length = s->length;
1265 }
1266
1267 return nelems;
1268 }
1269
1270 /*
1271 * The exported map_sg function for dma_ops (handles scatter-gather
1272 * lists).
1273 */
1274 static int map_sg(struct device *dev, struct scatterlist *sglist,
1275 int nelems, int dir)
1276 {
1277 unsigned long flags;
1278 struct amd_iommu *iommu;
1279 struct protection_domain *domain;
1280 u16 devid;
1281 int i;
1282 struct scatterlist *s;
1283 phys_addr_t paddr;
1284 int mapped_elems = 0;
1285 u64 dma_mask;
1286
1287 if (!check_device(dev))
1288 return 0;
1289
1290 dma_mask = *dev->dma_mask;
1291
1292 get_device_resources(dev, &iommu, &domain, &devid);
1293
1294 if (!iommu || !domain)
1295 return map_sg_no_iommu(dev, sglist, nelems, dir);
1296
1297 if (!dma_ops_domain(domain))
1298 return 0;
1299
1300 spin_lock_irqsave(&domain->lock, flags);
1301
1302 for_each_sg(sglist, s, nelems, i) {
1303 paddr = sg_phys(s);
1304
1305 s->dma_address = __map_single(dev, iommu, domain->priv,
1306 paddr, s->length, dir, false,
1307 dma_mask);
1308
1309 if (s->dma_address) {
1310 s->dma_length = s->length;
1311 mapped_elems++;
1312 } else
1313 goto unmap;
1314 }
1315
1316 iommu_completion_wait(iommu);
1317
1318 out:
1319 spin_unlock_irqrestore(&domain->lock, flags);
1320
1321 return mapped_elems;
1322 unmap:
1323 for_each_sg(sglist, s, mapped_elems, i) {
1324 if (s->dma_address)
1325 __unmap_single(iommu, domain->priv, s->dma_address,
1326 s->dma_length, dir);
1327 s->dma_address = s->dma_length = 0;
1328 }
1329
1330 mapped_elems = 0;
1331
1332 goto out;
1333 }
1334
1335 /*
1336 * The exported map_sg function for dma_ops (handles scatter-gather
1337 * lists).
1338 */
1339 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1340 int nelems, int dir)
1341 {
1342 unsigned long flags;
1343 struct amd_iommu *iommu;
1344 struct protection_domain *domain;
1345 struct scatterlist *s;
1346 u16 devid;
1347 int i;
1348
1349 if (!check_device(dev) ||
1350 !get_device_resources(dev, &iommu, &domain, &devid))
1351 return;
1352
1353 if (!dma_ops_domain(domain))
1354 return;
1355
1356 spin_lock_irqsave(&domain->lock, flags);
1357
1358 for_each_sg(sglist, s, nelems, i) {
1359 __unmap_single(iommu, domain->priv, s->dma_address,
1360 s->dma_length, dir);
1361 s->dma_address = s->dma_length = 0;
1362 }
1363
1364 iommu_completion_wait(iommu);
1365
1366 spin_unlock_irqrestore(&domain->lock, flags);
1367 }
1368
1369 /*
1370 * The exported alloc_coherent function for dma_ops.
1371 */
1372 static void *alloc_coherent(struct device *dev, size_t size,
1373 dma_addr_t *dma_addr, gfp_t flag)
1374 {
1375 unsigned long flags;
1376 void *virt_addr;
1377 struct amd_iommu *iommu;
1378 struct protection_domain *domain;
1379 u16 devid;
1380 phys_addr_t paddr;
1381 u64 dma_mask = dev->coherent_dma_mask;
1382
1383 if (!check_device(dev))
1384 return NULL;
1385
1386 if (!get_device_resources(dev, &iommu, &domain, &devid))
1387 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1388
1389 flag |= __GFP_ZERO;
1390 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1391 if (!virt_addr)
1392 return 0;
1393
1394 paddr = virt_to_phys(virt_addr);
1395
1396 if (!iommu || !domain) {
1397 *dma_addr = (dma_addr_t)paddr;
1398 return virt_addr;
1399 }
1400
1401 if (!dma_ops_domain(domain))
1402 goto out_free;
1403
1404 if (!dma_mask)
1405 dma_mask = *dev->dma_mask;
1406
1407 spin_lock_irqsave(&domain->lock, flags);
1408
1409 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1410 size, DMA_BIDIRECTIONAL, true, dma_mask);
1411
1412 if (*dma_addr == bad_dma_address)
1413 goto out_free;
1414
1415 iommu_completion_wait(iommu);
1416
1417 spin_unlock_irqrestore(&domain->lock, flags);
1418
1419 return virt_addr;
1420
1421 out_free:
1422
1423 free_pages((unsigned long)virt_addr, get_order(size));
1424
1425 return NULL;
1426 }
1427
1428 /*
1429 * The exported free_coherent function for dma_ops.
1430 */
1431 static void free_coherent(struct device *dev, size_t size,
1432 void *virt_addr, dma_addr_t dma_addr)
1433 {
1434 unsigned long flags;
1435 struct amd_iommu *iommu;
1436 struct protection_domain *domain;
1437 u16 devid;
1438
1439 if (!check_device(dev))
1440 return;
1441
1442 get_device_resources(dev, &iommu, &domain, &devid);
1443
1444 if (!iommu || !domain)
1445 goto free_mem;
1446
1447 if (!dma_ops_domain(domain))
1448 goto free_mem;
1449
1450 spin_lock_irqsave(&domain->lock, flags);
1451
1452 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1453
1454 iommu_completion_wait(iommu);
1455
1456 spin_unlock_irqrestore(&domain->lock, flags);
1457
1458 free_mem:
1459 free_pages((unsigned long)virt_addr, get_order(size));
1460 }
1461
1462 /*
1463 * This function is called by the DMA layer to find out if we can handle a
1464 * particular device. It is part of the dma_ops.
1465 */
1466 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1467 {
1468 u16 bdf;
1469 struct pci_dev *pcidev;
1470
1471 /* No device or no PCI device */
1472 if (!dev || dev->bus != &pci_bus_type)
1473 return 0;
1474
1475 pcidev = to_pci_dev(dev);
1476
1477 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1478
1479 /* Out of our scope? */
1480 if (bdf > amd_iommu_last_bdf)
1481 return 0;
1482
1483 return 1;
1484 }
1485
1486 /*
1487 * The function for pre-allocating protection domains.
1488 *
1489 * If the driver core informs the DMA layer if a driver grabs a device
1490 * we don't need to preallocate the protection domains anymore.
1491 * For now we have to.
1492 */
1493 void prealloc_protection_domains(void)
1494 {
1495 struct pci_dev *dev = NULL;
1496 struct dma_ops_domain *dma_dom;
1497 struct amd_iommu *iommu;
1498 int order = amd_iommu_aperture_order;
1499 u16 devid;
1500
1501 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1502 devid = (dev->bus->number << 8) | dev->devfn;
1503 if (devid > amd_iommu_last_bdf)
1504 continue;
1505 devid = amd_iommu_alias_table[devid];
1506 if (domain_for_device(devid))
1507 continue;
1508 iommu = amd_iommu_rlookup_table[devid];
1509 if (!iommu)
1510 continue;
1511 dma_dom = dma_ops_domain_alloc(iommu, order);
1512 if (!dma_dom)
1513 continue;
1514 init_unity_mappings_for_device(dma_dom, devid);
1515 dma_dom->target_dev = devid;
1516
1517 list_add_tail(&dma_dom->list, &iommu_pd_list);
1518 }
1519 }
1520
1521 static struct dma_mapping_ops amd_iommu_dma_ops = {
1522 .alloc_coherent = alloc_coherent,
1523 .free_coherent = free_coherent,
1524 .map_single = map_single,
1525 .unmap_single = unmap_single,
1526 .map_sg = map_sg,
1527 .unmap_sg = unmap_sg,
1528 .dma_supported = amd_iommu_dma_supported,
1529 };
1530
1531 /*
1532 * The function which clues the AMD IOMMU driver into dma_ops.
1533 */
1534 int __init amd_iommu_init_dma_ops(void)
1535 {
1536 struct amd_iommu *iommu;
1537 int order = amd_iommu_aperture_order;
1538 int ret;
1539
1540 /*
1541 * first allocate a default protection domain for every IOMMU we
1542 * found in the system. Devices not assigned to any other
1543 * protection domain will be assigned to the default one.
1544 */
1545 list_for_each_entry(iommu, &amd_iommu_list, list) {
1546 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1547 if (iommu->default_dom == NULL)
1548 return -ENOMEM;
1549 ret = iommu_init_unity_mappings(iommu);
1550 if (ret)
1551 goto free_domains;
1552 }
1553
1554 /*
1555 * If device isolation is enabled, pre-allocate the protection
1556 * domains for each device.
1557 */
1558 if (amd_iommu_isolate)
1559 prealloc_protection_domains();
1560
1561 iommu_detected = 1;
1562 force_iommu = 1;
1563 bad_dma_address = 0;
1564 #ifdef CONFIG_GART_IOMMU
1565 gart_iommu_aperture_disabled = 1;
1566 gart_iommu_aperture = 0;
1567 #endif
1568
1569 /* Make the driver finally visible to the drivers */
1570 dma_ops = &amd_iommu_dma_ops;
1571
1572 bus_register_notifier(&pci_bus_type, &device_nb);
1573
1574 return 0;
1575
1576 free_domains:
1577
1578 list_for_each_entry(iommu, &amd_iommu_list, list) {
1579 if (iommu->default_dom)
1580 dma_ops_domain_free(iommu->default_dom);
1581 }
1582
1583 return ret;
1584 }
1585
1586 /*****************************************************************************
1587 *
1588 * The following functions belong to the exported interface of AMD IOMMU
1589 *
1590 * This interface allows access to lower level functions of the IOMMU
1591 * like protection domain handling and assignement of devices to domains
1592 * which is not possible with the dma_ops interface.
1593 *
1594 *****************************************************************************/
1595
1596 #ifdef CONFIG_IOMMU_API
1597
1598 static void cleanup_domain(struct protection_domain *domain)
1599 {
1600 unsigned long flags;
1601 u16 devid;
1602
1603 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1604
1605 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1606 if (amd_iommu_pd_table[devid] == domain)
1607 __detach_device(domain, devid);
1608
1609 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1610 }
1611
1612 static int amd_iommu_domain_init(struct iommu_domain *dom)
1613 {
1614 struct protection_domain *domain;
1615
1616 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1617 if (!domain)
1618 return -ENOMEM;
1619
1620 spin_lock_init(&domain->lock);
1621 domain->mode = PAGE_MODE_3_LEVEL;
1622 domain->id = domain_id_alloc();
1623 if (!domain->id)
1624 goto out_free;
1625 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1626 if (!domain->pt_root)
1627 goto out_free;
1628
1629 dom->priv = domain;
1630
1631 return 0;
1632
1633 out_free:
1634 kfree(domain);
1635
1636 return -ENOMEM;
1637 }
1638
1639 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1640 {
1641 struct protection_domain *domain = dom->priv;
1642
1643 if (!domain)
1644 return;
1645
1646 if (domain->dev_cnt > 0)
1647 cleanup_domain(domain);
1648
1649 BUG_ON(domain->dev_cnt != 0);
1650
1651 free_pagetable(domain);
1652
1653 domain_id_free(domain->id);
1654
1655 kfree(domain);
1656
1657 dom->priv = NULL;
1658 }
1659
1660 static void amd_iommu_detach_device(struct iommu_domain *dom,
1661 struct device *dev)
1662 {
1663 struct protection_domain *domain = dom->priv;
1664 struct amd_iommu *iommu;
1665 struct pci_dev *pdev;
1666 u16 devid;
1667
1668 if (dev->bus != &pci_bus_type)
1669 return;
1670
1671 pdev = to_pci_dev(dev);
1672
1673 devid = calc_devid(pdev->bus->number, pdev->devfn);
1674
1675 if (devid > 0)
1676 detach_device(domain, devid);
1677
1678 iommu = amd_iommu_rlookup_table[devid];
1679 if (!iommu)
1680 return;
1681
1682 iommu_queue_inv_dev_entry(iommu, devid);
1683 iommu_completion_wait(iommu);
1684 }
1685
1686 static int amd_iommu_attach_device(struct iommu_domain *dom,
1687 struct device *dev)
1688 {
1689 struct protection_domain *domain = dom->priv;
1690 struct protection_domain *old_domain;
1691 struct amd_iommu *iommu;
1692 struct pci_dev *pdev;
1693 u16 devid;
1694
1695 if (dev->bus != &pci_bus_type)
1696 return -EINVAL;
1697
1698 pdev = to_pci_dev(dev);
1699
1700 devid = calc_devid(pdev->bus->number, pdev->devfn);
1701
1702 if (devid >= amd_iommu_last_bdf ||
1703 devid != amd_iommu_alias_table[devid])
1704 return -EINVAL;
1705
1706 iommu = amd_iommu_rlookup_table[devid];
1707 if (!iommu)
1708 return -EINVAL;
1709
1710 old_domain = domain_for_device(devid);
1711 if (old_domain)
1712 return -EBUSY;
1713
1714 attach_device(iommu, domain, devid);
1715
1716 iommu_completion_wait(iommu);
1717
1718 return 0;
1719 }
1720
1721 #endif
CJK support for tty framebuffer vt