drivers/staging/et131x/et1310_address_map.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_address_map.h - Contains the register mapping for the ET1310
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright © 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #ifndef _ET1310_ADDRESS_MAP_H_
  59 #define _ET1310_ADDRESS_MAP_H_
  60
  61
  62 /* START OF GLOBAL REGISTER ADDRESS MAP */
  63
  64 /*
  65  * 10bit registers
  66  *
  67  * Tx queue start address reg in global address map at address 0x0000
  68  * tx queue end address reg in global address map at address 0x0004
  69  * rx queue start address reg in global address map at address 0x0008
  70  * rx queue end address reg in global address map at address 0x000C
  71  */
  72
  73 /*
  74  * structure for power management control status reg in global address map
  75  * located at address 0x0010
  76  *      jagcore_rx_rdy  bit 9
  77  *      jagcore_tx_rdy  bit 8
  78  *      phy_lped_en     bit 7
  79  *      phy_sw_coma     bit 6
  80  *      rxclk_gate      bit 5
  81  *      txclk_gate      bit 4
  82  *      sysclk_gate     bit 3
  83  *      jagcore_rx_en   bit 2
  84  *      jagcore_tx_en   bit 1
  85  *      gigephy_en      bit 0
  86  */
  87
  88 #define ET_PM_PHY_SW_COMA               0x40
  89 #define ET_PMCSR_INIT                   0x38
  90
  91 /*
  92  * Interrupt status reg at address 0x0018
  93  */
  94
  95 #define ET_INTR_TXDMA_ISR       0x00000008
  96 #define ET_INTR_TXDMA_ERR       0x00000010
  97 #define ET_INTR_RXDMA_XFR_DONE  0x00000020
  98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
  99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
 100 #define ET_INTR_RXDMA_STAT_LOW  0x00000100
 101 #define ET_INTR_RXDMA_ERR       0x00000200
 102 #define ET_INTR_WATCHDOG        0x00004000
 103 #define ET_INTR_WOL             0x00008000
 104 #define ET_INTR_PHY             0x00010000
 105 #define ET_INTR_TXMAC           0x00020000
 106 #define ET_INTR_RXMAC           0x00040000
 107 #define ET_INTR_MAC_STAT        0x00080000
 108 #define ET_INTR_SLV_TIMEOUT     0x00100000
 109
 110 /*
 111  * Interrupt mask register at address 0x001C
 112  * Interrupt alias clear mask reg at address 0x0020
 113  * Interrupt status alias reg at address 0x0024
 114  *
 115  * Same masks as above
 116  */
 117
 118 /*
 119  * Software reset reg at address 0x0028
 120  * 0:   txdma_sw_reset
 121  * 1:   rxdma_sw_reset
 122  * 2:   txmac_sw_reset
 123  * 3:   rxmac_sw_reset
 124  * 4:   mac_sw_reset
 125  * 5:   mac_stat_sw_reset
 126  * 6:   mmc_sw_reset
 127  *31:   selfclr_disable
 128  */
 129
 130 /*
 131  * SLV Timer reg at address 0x002C (low 24 bits)
 132  */
 133
 134 /*
 135  * MSI Configuration reg at address 0x0030
 136  */
 137
 138 #define ET_MSI_VECTOR   0x0000001F
 139 #define ET_MSI_TC       0x00070000
 140
 141 /*
 142  * Loopback reg located at address 0x0034
 143  */
 144
 145 #define ET_LOOP_MAC     0x00000001
 146 #define ET_LOOP_DMA     0x00000002
 147
 148 /*
 149  * GLOBAL Module of JAGCore Address Mapping
 150  * Located at address 0x0000
 151  */
 152 struct global_regs {                    /* Location: */
 153         u32 txq_start_addr;                     /*  0x0000 */
 154         u32 txq_end_addr;                       /*  0x0004 */
 155         u32 rxq_start_addr;                     /*  0x0008 */
 156         u32 rxq_end_addr;                       /*  0x000C */
 157         u32 pm_csr;                             /*  0x0010 */
 158         u32 unused;                             /*  0x0014 */
 159         u32 int_status;                         /*  0x0018 */
 160         u32 int_mask;                           /*  0x001C */
 161         u32 int_alias_clr_en;                   /*  0x0020 */
 162         u32 int_status_alias;                   /*  0x0024 */
 163         u32 sw_reset;                           /*  0x0028 */
 164         u32 slv_timer;                          /*  0x002C */
 165         u32 msi_config;                         /*  0x0030 */
 166         u32 loopback;                   /*  0x0034 */
 167         u32 watchdog_timer;                     /*  0x0038 */
 168 };
 169
 170
 171 /* START OF TXDMA REGISTER ADDRESS MAP */
 172
 173 /*
 174  * txdma control status reg at address 0x1000
 175  */
 176
 177 #define ET_TXDMA_CSR_HALT       0x00000001
 178 #define ET_TXDMA_DROP_TLP       0x00000002
 179 #define ET_TXDMA_CACHE_THRS     0x000000F0
 180 #define ET_TXDMA_CACHE_SHIFT    4
 181 #define ET_TXDMA_SNGL_EPKT      0x00000100
 182 #define ET_TXDMA_CLASS          0x00001E00
 183
 184 /*
 185  * structure for txdma packet ring base address hi reg in txdma address map
 186  * located at address 0x1004
 187  * Defined earlier (u32)
 188  */
 189
 190 /*
 191  * structure for txdma packet ring base address low reg in txdma address map
 192  * located at address 0x1008
 193  * Defined earlier (u32)
 194  */
 195
 196 /*
 197  * structure for txdma packet ring number of descriptor reg in txdma address
 198  * map.  Located at address 0x100C
 199  *
 200  * 31-10: unused
 201  * 9-0: pr ndes
 202  */
 203
 204 #define ET_DMA12_MASK           0x0FFF  /* 12 bit mask for DMA12W types */
 205 #define ET_DMA12_WRAP           0x1000
 206 #define ET_DMA10_MASK           0x03FF  /* 10 bit mask for DMA10W types */
 207 #define ET_DMA10_WRAP           0x0400
 208 #define ET_DMA4_MASK            0x000F  /* 4 bit mask for DMA4W types */
 209 #define ET_DMA4_WRAP            0x0010
 210
 211 #define INDEX12(x)      ((x) & ET_DMA12_MASK)
 212 #define INDEX10(x)      ((x) & ET_DMA10_MASK)
 213 #define INDEX4(x)       ((x) & ET_DMA4_MASK)
 214
 215 extern inline void add_10bit(u32 *v, int n)
 216 {
 217         *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
 218 }
 219
 220 extern inline void add_12bit(u32 *v, int n)
 221 {
 222         *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
 223 }
 224
 225 /*
 226  * 10bit DMA with wrap
 227  * txdma tx queue write address reg in txdma address map at 0x1010
 228  * txdma tx queue write address external reg in txdma address map at 0x1014
 229  * txdma tx queue read address reg in txdma address map at 0x1018
 230  *
 231  * u32
 232  * txdma status writeback address hi reg in txdma address map at0x101C
 233  * txdma status writeback address lo reg in txdma address map at 0x1020
 234  *
 235  * 10bit DMA with wrap
 236  * txdma service request reg in txdma address map at 0x1024
 237  * structure for txdma service complete reg in txdma address map at 0x1028
 238  *
 239  * 4bit DMA with wrap
 240  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
 241  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
 242  *
 243  * txdma error reg in txdma address map at address 0x1034
 244  * 0: PyldResend
 245  * 1: PyldRewind
 246  * 4: DescrResend
 247  * 5: DescrRewind
 248  * 8: WrbkResend
 249  * 9: WrbkRewind
 250  */
 251
 252 /*
 253  * Tx DMA Module of JAGCore Address Mapping
 254  * Located at address 0x1000
 255  */
 256 struct txdma_regs {                     /* Location: */
 257         u32 csr;                        /*  0x1000 */
 258         u32 pr_base_hi;                 /*  0x1004 */
 259         u32 pr_base_lo;                 /*  0x1008 */
 260         u32 pr_num_des;                 /*  0x100C */
 261         u32 txq_wr_addr;                /*  0x1010 */
 262         u32 txq_wr_addr_ext;            /*  0x1014 */
 263         u32 txq_rd_addr;                /*  0x1018 */
 264         u32 dma_wb_base_hi;             /*  0x101C */
 265         u32 dma_wb_base_lo;             /*  0x1020 */
 266         u32 service_request;            /*  0x1024 */
 267         u32 service_complete;           /*  0x1028 */
 268         u32 cache_rd_index;             /*  0x102C */
 269         u32 cache_wr_index;             /*  0x1030 */
 270         u32 TxDmaError;                 /*  0x1034 */
 271         u32 DescAbortCount;             /*  0x1038 */
 272         u32 PayloadAbortCnt;            /*  0x103c */
 273         u32 WriteBackAbortCnt;          /*  0x1040 */
 274         u32 DescTimeoutCnt;             /*  0x1044 */
 275         u32 PayloadTimeoutCnt;          /*  0x1048 */
 276         u32 WriteBackTimeoutCnt;        /*  0x104c */
 277         u32 DescErrorCount;             /*  0x1050 */
 278         u32 PayloadErrorCnt;            /*  0x1054 */
 279         u32 WriteBackErrorCnt;          /*  0x1058 */
 280         u32 DroppedTLPCount;            /*  0x105c */
 281         u32 NewServiceComplete;         /*  0x1060 */
 282         u32 EthernetPacketCount;        /*  0x1064 */
 283 };
 284
 285 /* END OF TXDMA REGISTER ADDRESS MAP */
 286
 287
 288 /* START OF RXDMA REGISTER ADDRESS MAP */
 289
 290 /*
 291  * structure for control status reg in rxdma address map
 292  * Located at address 0x2000
 293  *
 294  * CSR
 295  * 0: halt
 296  * 1-3: tc
 297  * 4: fbr_big_endian
 298  * 5: psr_big_endian
 299  * 6: pkt_big_endian
 300  * 7: dma_big_endian
 301  * 8-9: fbr0_size
 302  * 10: fbr0_enable
 303  * 11-12: fbr1_size
 304  * 13: fbr1_enable
 305  * 14: unused
 306  * 15: pkt_drop_disable
 307  * 16: pkt_done_flush
 308  * 17: halt_status
 309  * 18-31: unused
 310  */
 311
 312
 313 /*
 314  * structure for dma writeback lo reg in rxdma address map
 315  * located at address 0x2004
 316  * Defined earlier (u32)
 317  */
 318
 319 /*
 320  * structure for dma writeback hi reg in rxdma address map
 321  * located at address 0x2008
 322  * Defined earlier (u32)
 323  */
 324
 325 /*
 326  * structure for number of packets done reg in rxdma address map
 327  * located at address 0x200C
 328  *
 329  * 31-8: unused
 330  * 7-0: num done
 331  */
 332
 333 /*
 334  * structure for max packet time reg in rxdma address map
 335  * located at address 0x2010
 336  *
 337  * 31-18: unused
 338  * 17-0: time done
 339  */
 340
 341 /*
 342  * structure for rx queue read address reg in rxdma address map
 343  * located at address 0x2014
 344  * Defined earlier (u32)
 345  */
 346
 347 /*
 348  * structure for rx queue read address external reg in rxdma address map
 349  * located at address 0x2018
 350  * Defined earlier (u32)
 351  */
 352
 353 /*
 354  * structure for rx queue write address reg in rxdma address map
 355  * located at address 0x201C
 356  * Defined earlier (u32)
 357  */
 358
 359 /*
 360  * structure for packet status ring base address lo reg in rxdma address map
 361  * located at address 0x2020
 362  * Defined earlier (u32)
 363  */
 364
 365 /*
 366  * structure for packet status ring base address hi reg in rxdma address map
 367  * located at address 0x2024
 368  * Defined earlier (u32)
 369  */
 370
 371 /*
 372  * structure for packet status ring number of descriptors reg in rxdma address
 373  * map.  Located at address 0x2028
 374  *
 375  * 31-12: unused
 376  * 11-0: psr ndes
 377  */
 378
 379 /*
 380  * structure for packet status ring available offset reg in rxdma address map
 381  * located at address 0x202C
 382  *
 383  * 31-13: unused
 384  * 12: psr avail wrap
 385  * 11-0: psr avail
 386  */
 387
 388 /*
 389  * structure for packet status ring full offset reg in rxdma address map
 390  * located at address 0x2030
 391  *
 392  * 31-13: unused
 393  * 12: psr full wrap
 394  * 11-0: psr full
 395  */
 396
 397 /*
 398  * structure for packet status ring access index reg in rxdma address map
 399  * located at address 0x2034
 400  *
 401  * 31-5: unused
 402  * 4-0: psr_ai
 403  */
 404
 405 /*
 406  * structure for packet status ring minimum descriptors reg in rxdma address
 407  * map.  Located at address 0x2038
 408  *
 409  * 31-12: unused
 410  * 11-0: psr_min
 411  */
 412
 413 /*
 414  * structure for free buffer ring base lo address reg in rxdma address map
 415  * located at address 0x203C
 416  * Defined earlier (u32)
 417  */
 418
 419 /*
 420  * structure for free buffer ring base hi address reg in rxdma address map
 421  * located at address 0x2040
 422  * Defined earlier (u32)
 423  */
 424
 425 /*
 426  * structure for free buffer ring number of descriptors reg in rxdma address
 427  * map.  Located at address 0x2044
 428  *
 429  * 31-10: unused
 430  * 9-0: fbr ndesc
 431  */
 432
 433 /*
 434  * structure for free buffer ring 0 available offset reg in rxdma address map
 435  * located at address 0x2048
 436  * Defined earlier (u32)
 437  */
 438
 439 /*
 440  * structure for free buffer ring 0 full offset reg in rxdma address map
 441  * located at address 0x204C
 442  * Defined earlier (u32)
 443  */
 444
 445 /*
 446  * structure for free buffer cache 0 full offset reg in rxdma address map
 447  * located at address 0x2050
 448  *
 449  * 31-5: unused
 450  * 4-0: fbc rdi
 451  */
 452
 453 /*
 454  * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
 455  * located at address 0x2054
 456  *
 457  * 31-10: unused
 458  * 9-0: fbr min
 459  */
 460
 461 /*
 462  * structure for free buffer ring 1 base address lo reg in rxdma address map
 463  * located at address 0x2058 - 0x205C
 464  * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
 465  */
 466
 467 /*
 468  * structure for free buffer ring 1 number of descriptors reg in rxdma address
 469  * map.  Located at address 0x2060
 470  * Defined earlier (RXDMA_FBR_NUM_DES_t)
 471  */
 472
 473 /*
 474  * structure for free buffer ring 1 available offset reg in rxdma address map
 475  * located at address 0x2064
 476  * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
 477  */
 478
 479 /*
 480  * structure for free buffer ring 1 full offset reg in rxdma address map
 481  * located at address 0x2068
 482  * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
 483  */
 484
 485 /*
 486  * structure for free buffer cache 1 read index reg in rxdma address map
 487  * located at address 0x206C
 488  * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
 489  */
 490
 491 /*
 492  * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
 493  * located at address 0x2070
 494  * Defined Earlier (RXDMA_FBR_MIN_DES_t)
 495  */
 496
 497 /*
 498  * Rx DMA Module of JAGCore Address Mapping
 499  * Located at address 0x2000
 500  */
 501 struct rxdma_regs {                                     /* Location: */
 502         u32 csr;                                        /*  0x2000 */
 503         u32 dma_wb_base_lo;                             /*  0x2004 */
 504         u32 dma_wb_base_hi;                             /*  0x2008 */
 505         u32 num_pkt_done;                               /*  0x200C */
 506         u32 max_pkt_time;                               /*  0x2010 */
 507         u32 rxq_rd_addr;                                /*  0x2014 */
 508         u32 rxq_rd_addr_ext;                            /*  0x2018 */
 509         u32 rxq_wr_addr;                                /*  0x201C */
 510         u32 psr_base_lo;                                /*  0x2020 */
 511         u32 psr_base_hi;                                /*  0x2024 */
 512         u32 psr_num_des;                                /*  0x2028 */
 513         u32 psr_avail_offset;                           /*  0x202C */
 514         u32 psr_full_offset;                            /*  0x2030 */
 515         u32 psr_access_index;                           /*  0x2034 */
 516         u32 psr_min_des;                                /*  0x2038 */
 517         u32 fbr0_base_lo;                               /*  0x203C */
 518         u32 fbr0_base_hi;                               /*  0x2040 */
 519         u32 fbr0_num_des;                               /*  0x2044 */
 520         u32 fbr0_avail_offset;                          /*  0x2048 */
 521         u32 fbr0_full_offset;                           /*  0x204C */
 522         u32 fbr0_rd_index;                              /*  0x2050 */
 523         u32 fbr0_min_des;                               /*  0x2054 */
 524         u32 fbr1_base_lo;                               /*  0x2058 */
 525         u32 fbr1_base_hi;                               /*  0x205C */
 526         u32 fbr1_num_des;                               /*  0x2060 */
 527         u32 fbr1_avail_offset;                          /*  0x2064 */
 528         u32 fbr1_full_offset;                           /*  0x2068 */
 529         u32 fbr1_rd_index;                              /*  0x206C */
 530         u32 fbr1_min_des;                               /*  0x2070 */
 531 };
 532
 533 /* END OF RXDMA REGISTER ADDRESS MAP */
 534
 535
 536 /* START OF TXMAC REGISTER ADDRESS MAP */
 537
 538 /*
 539  * structure for control reg in txmac address map
 540  * located at address 0x3000
 541  *
 542  * bits
 543  * 31-8: unused
 544  * 7: cklseg_disable
 545  * 6: ckbcnt_disable
 546  * 5: cksegnum
 547  * 4: async_disable
 548  * 3: fc_disable
 549  * 2: mcif_disable
 550  * 1: mif_disable
 551  * 0: txmac_en
 552  */
 553
 554 /*
 555  * structure for shadow pointer reg in txmac address map
 556  * located at address 0x3004
 557  * 31-27: reserved
 558  * 26-16: txq rd ptr
 559  * 15-11: reserved
 560  * 10-0: txq wr ptr
 561  */
 562
 563 /*
 564  * structure for error count reg in txmac address map
 565  * located at address 0x3008
 566  *
 567  * 31-12: unused
 568  * 11-8: reserved
 569  * 7-4: txq_underrun
 570  * 3-0: fifo_underrun
 571  */
 572
 573 /*
 574  * structure for max fill reg in txmac address map
 575  * located at address 0x300C
 576  * 31-12: unused
 577  * 11-0: max fill
 578  */
 579
 580 /*
 581  * structure for cf parameter reg in txmac address map
 582  * located at address 0x3010
 583  * 31-16: cfep
 584  * 15-0: cfpt
 585  */
 586
 587 /*
 588  * structure for tx test reg in txmac address map
 589  * located at address 0x3014
 590  * 31-17: unused
 591  * 16: reserved1
 592  * 15: txtest_en
 593  * 14-11: unused
 594  * 10-0: txq test pointer
 595  */
 596
 597 /*
 598  * structure for error reg in txmac address map
 599  * located at address 0x3018
 600  *
 601  * 31-9: unused
 602  * 8: fifo_underrun
 603  * 7-6: unused
 604  * 5: ctrl2_err
 605  * 4: txq_underrun
 606  * 3: bcnt_err
 607  * 2: lseg_err
 608  * 1: segnum_err
 609  * 0: seg0_err
 610  */
 611
 612 /*
 613  * structure for error interrupt reg in txmac address map
 614  * located at address 0x301C
 615  */
 616 typedef union _TXMAC_ERR_INT_t {
 617         u32 value;
 618         struct {
 619 #ifdef _BIT_FIELDS_HTOL
 620                 u32 unused2:23;         /* bits 9-31 */
 621                 u32 fifo_underrun:1;    /* bit 8 */
 622                 u32 unused1:2;          /* bits 6-7 */
 623                 u32 ctrl2_err:1;        /* bit 5 */
 624                 u32 txq_underrun:1;     /* bit 4 */
 625                 u32 bcnt_err:1;         /* bit 3 */
 626                 u32 lseg_err:1;         /* bit 2 */
 627                 u32 segnum_err:1;       /* bit 1 */
 628                 u32 seg0_err:1;         /* bit 0 */
 629 #else
 630                 u32 seg0_err:1;         /* bit 0 */
 631                 u32 segnum_err:1;       /* bit 1 */
 632                 u32 lseg_err:1;         /* bit 2 */
 633                 u32 bcnt_err:1;         /* bit 3 */
 634                 u32 txq_underrun:1;     /* bit 4 */
 635                 u32 ctrl2_err:1;        /* bit 5 */
 636                 u32 unused1:2;          /* bits 6-7 */
 637                 u32 fifo_underrun:1;    /* bit 8 */
 638                 u32 unused2:23;         /* bits 9-31 */
 639 #endif
 640         } bits;
 641 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
 642
 643 /*
 644  * structure for error interrupt reg in txmac address map
 645  * located at address 0x3020
 646  *
 647  * 31-2: unused
 648  * 1: bp_req
 649  * 0: bp_xonxoff
 650  */
 651
 652 /*
 653  * Tx MAC Module of JAGCore Address Mapping
 654  */
 655 typedef struct _TXMAC_t {               /* Location: */
 656         u32 ctl;                        /*  0x3000 */
 657         u32 shadow_ptr;                 /*  0x3004 */
 658         u32 err_cnt;                    /*  0x3008 */
 659         u32 max_fill;                   /*  0x300C */
 660         u32 cf_param;                   /*  0x3010 */
 661         u32 tx_test;                    /*  0x3014 */
 662         u32 err;                        /*  0x3018 */
 663         TXMAC_ERR_INT_t err_int;        /*  0x301C */
 664         u32 bp_ctrl;                    /*  0x3020 */
 665 } TXMAC_t, *PTXMAC_t;
 666
 667 /* END OF TXMAC REGISTER ADDRESS MAP */
 668
 669 /* START OF RXMAC REGISTER ADDRESS MAP */
 670
 671 /*
 672  * structure for rxmac control reg in rxmac address map
 673  * located at address 0x4000
 674  */
 675 typedef union _RXMAC_CTRL_t {
 676         u32 value;
 677         struct {
 678 #ifdef _BIT_FIELDS_HTOL
 679                 u32 reserved:25;                /* bits 7-31 */
 680                 u32 rxmac_int_disable:1;        /* bit 6 */
 681                 u32 async_disable:1;            /* bit 5 */
 682                 u32 mif_disable:1;              /* bit 4 */
 683                 u32 wol_disable:1;              /* bit 3 */
 684                 u32 pkt_filter_disable:1;       /* bit 2 */
 685                 u32 mcif_disable:1;             /* bit 1 */
 686                 u32 rxmac_en:1;                 /* bit 0 */
 687 #else
 688                 u32 rxmac_en:1;                 /* bit 0 */
 689                 u32 mcif_disable:1;             /* bit 1 */
 690                 u32 pkt_filter_disable:1;       /* bit 2 */
 691                 u32 wol_disable:1;              /* bit 3 */
 692                 u32 mif_disable:1;              /* bit 4 */
 693                 u32 async_disable:1;            /* bit 5 */
 694                 u32 rxmac_int_disable:1;        /* bit 6 */
 695                 u32 reserved:25;                /* bits 7-31 */
 696 #endif
 697         } bits;
 698 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
 699
 700 /*
 701  * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
 702  * located at address 0x4004
 703  */
 704 typedef union _RXMAC_WOL_CTL_CRC0_t {
 705         u32 value;
 706         struct {
 707 #ifdef _BIT_FIELDS_HTOL
 708                 u32 crc0:16;            /* bits 16-31 */
 709                 u32 reserve:4;          /* bits 12-15 */
 710                 u32 ignore_pp:1;        /* bit 11 */
 711                 u32 ignore_mp:1;        /* bit 10 */
 712                 u32 clr_intr:1;         /* bit 9 */
 713                 u32 ignore_link_chg:1;  /* bit 8 */
 714                 u32 ignore_uni:1;       /* bit 7 */
 715                 u32 ignore_multi:1;     /* bit 6 */
 716                 u32 ignore_broad:1;     /* bit 5 */
 717                 u32 valid_crc4:1;       /* bit 4 */
 718                 u32 valid_crc3:1;       /* bit 3 */
 719                 u32 valid_crc2:1;       /* bit 2 */
 720                 u32 valid_crc1:1;       /* bit 1 */
 721                 u32 valid_crc0:1;       /* bit 0 */
 722 #else
 723                 u32 valid_crc0:1;       /* bit 0 */
 724                 u32 valid_crc1:1;       /* bit 1 */
 725                 u32 valid_crc2:1;       /* bit 2 */
 726                 u32 valid_crc3:1;       /* bit 3 */
 727                 u32 valid_crc4:1;       /* bit 4 */
 728                 u32 ignore_broad:1;     /* bit 5 */
 729                 u32 ignore_multi:1;     /* bit 6 */
 730                 u32 ignore_uni:1;       /* bit 7 */
 731                 u32 ignore_link_chg:1;  /* bit 8 */
 732                 u32 clr_intr:1;         /* bit 9 */
 733                 u32 ignore_mp:1;        /* bit 10 */
 734                 u32 ignore_pp:1;        /* bit 11 */
 735                 u32 reserve:4;          /* bits 12-15 */
 736                 u32 crc0:16;            /* bits 16-31 */
 737 #endif
 738         } bits;
 739 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
 740
 741 /*
 742  * structure for CRC 1 and CRC 2 reg in rxmac address map
 743  * located at address 0x4008
 744  */
 745 typedef union _RXMAC_WOL_CRC12_t {
 746         u32 value;
 747         struct {
 748 #ifdef _BIT_FIELDS_HTOL
 749                 u32 crc2:16;    /* bits 16-31 */
 750                 u32 crc1:16;    /* bits 0-15 */
 751 #else
 752                 u32 crc1:16;    /* bits 0-15 */
 753                 u32 crc2:16;    /* bits 16-31 */
 754 #endif
 755         } bits;
 756 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
 757
 758 /*
 759  * structure for CRC 3 and CRC 4 reg in rxmac address map
 760  * located at address 0x400C
 761  */
 762 typedef union _RXMAC_WOL_CRC34_t {
 763         u32 value;
 764         struct {
 765 #ifdef _BIT_FIELDS_HTOL
 766                 u32 crc4:16;    /* bits 16-31 */
 767                 u32 crc3:16;    /* bits 0-15 */
 768 #else
 769                 u32 crc3:16;    /* bits 0-15 */
 770                 u32 crc4:16;    /* bits 16-31 */
 771 #endif
 772         } bits;
 773 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
 774
 775 /*
 776  * structure for Wake On Lan Source Address Lo reg in rxmac address map
 777  * located at address 0x4010
 778  */
 779 typedef union _RXMAC_WOL_SA_LO_t {
 780         u32 value;
 781         struct {
 782 #ifdef _BIT_FIELDS_HTOL
 783                 u32 sa3:8;      /* bits 24-31 */
 784                 u32 sa4:8;      /* bits 16-23 */
 785                 u32 sa5:8;      /* bits 8-15 */
 786                 u32 sa6:8;      /* bits 0-7 */
 787 #else
 788                 u32 sa6:8;      /* bits 0-7 */
 789                 u32 sa5:8;      /* bits 8-15 */
 790                 u32 sa4:8;      /* bits 16-23 */
 791                 u32 sa3:8;      /* bits 24-31 */
 792 #endif
 793         } bits;
 794 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
 795
 796 /*
 797  * structure for Wake On Lan Source Address Hi reg in rxmac address map
 798  * located at address 0x4014
 799  */
 800 typedef union _RXMAC_WOL_SA_HI_t {
 801         u32 value;
 802         struct {
 803 #ifdef _BIT_FIELDS_HTOL
 804                 u32 reserved:16;        /* bits 16-31 */
 805                 u32 sa1:8;              /* bits 8-15 */
 806                 u32 sa2:8;              /* bits 0-7 */
 807 #else
 808                 u32 sa2:8;              /* bits 0-7 */
 809                 u32 sa1:8;              /* bits 8-15 */
 810                 u32 reserved:16;        /* bits 16-31 */
 811 #endif
 812         } bits;
 813 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
 814
 815 /*
 816  * structure for Wake On Lan mask reg in rxmac address map
 817  * located at address 0x4018 - 0x4064
 818  * Defined earlier (u32)
 819  */
 820
 821 /*
 822  * structure for Unicast Paket Filter Address 1 reg in rxmac address map
 823  * located at address 0x4068
 824  */
 825 typedef union _RXMAC_UNI_PF_ADDR1_t {
 826         u32 value;
 827         struct {
 828 #ifdef _BIT_FIELDS_HTOL
 829                 u32 addr1_3:8;  /* bits 24-31 */
 830                 u32 addr1_4:8;  /* bits 16-23 */
 831                 u32 addr1_5:8;  /* bits 8-15 */
 832                 u32 addr1_6:8;  /* bits 0-7 */
 833 #else
 834                 u32 addr1_6:8;  /* bits 0-7 */
 835                 u32 addr1_5:8;  /* bits 8-15 */
 836                 u32 addr1_4:8;  /* bits 16-23 */
 837                 u32 addr1_3:8;  /* bits 24-31 */
 838 #endif
 839         } bits;
 840 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
 841
 842 /*
 843  * structure for Unicast Paket Filter Address 2 reg in rxmac address map
 844  * located at address 0x406C
 845  */
 846 typedef union _RXMAC_UNI_PF_ADDR2_t {
 847         u32 value;
 848         struct {
 849 #ifdef _BIT_FIELDS_HTOL
 850                 u32 addr2_3:8;  /* bits 24-31 */
 851                 u32 addr2_4:8;  /* bits 16-23 */
 852                 u32 addr2_5:8;  /* bits 8-15 */
 853                 u32 addr2_6:8;  /* bits 0-7 */
 854 #else
 855                 u32 addr2_6:8;  /* bits 0-7 */
 856                 u32 addr2_5:8;  /* bits 8-15 */
 857                 u32 addr2_4:8;  /* bits 16-23 */
 858                 u32 addr2_3:8;  /* bits 24-31 */
 859 #endif
 860         } bits;
 861 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
 862
 863 /*
 864  * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
 865  * located at address 0x4070
 866  */
 867 typedef union _RXMAC_UNI_PF_ADDR3_t {
 868         u32 value;
 869         struct {
 870 #ifdef _BIT_FIELDS_HTOL
 871                 u32 addr2_1:8;  /* bits 24-31 */
 872                 u32 addr2_2:8;  /* bits 16-23 */
 873                 u32 addr1_1:8;  /* bits 8-15 */
 874                 u32 addr1_2:8;  /* bits 0-7 */
 875 #else
 876                 u32 addr1_2:8;  /* bits 0-7 */
 877                 u32 addr1_1:8;  /* bits 8-15 */
 878                 u32 addr2_2:8;  /* bits 16-23 */
 879                 u32 addr2_1:8;  /* bits 24-31 */
 880 #endif
 881         } bits;
 882 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
 883
 884 /*
 885  * structure for Multicast Hash reg in rxmac address map
 886  * located at address 0x4074 - 0x4080
 887  * Defined earlier (u32)
 888  */
 889
 890 /*
 891  * structure for Packet Filter Control reg in rxmac address map
 892  * located at address 0x4084
 893  */
 894 typedef union _RXMAC_PF_CTRL_t {
 895         u32 value;
 896         struct {
 897 #ifdef _BIT_FIELDS_HTOL
 898                 u32 unused2:9;          /* bits 23-31 */
 899                 u32 min_pkt_size:7;     /* bits 16-22 */
 900                 u32 unused1:12;         /* bits 4-15 */
 901                 u32 filter_frag_en:1;   /* bit 3 */
 902                 u32 filter_uni_en:1;    /* bit 2 */
 903                 u32 filter_multi_en:1;  /* bit 1 */
 904                 u32 filter_broad_en:1;  /* bit 0 */
 905 #else
 906                 u32 filter_broad_en:1;  /* bit 0 */
 907                 u32 filter_multi_en:1;  /* bit 1 */
 908                 u32 filter_uni_en:1;    /* bit 2 */
 909                 u32 filter_frag_en:1;   /* bit 3 */
 910                 u32 unused1:12;         /* bits 4-15 */
 911                 u32 min_pkt_size:7;     /* bits 16-22 */
 912                 u32 unused2:9;          /* bits 23-31 */
 913 #endif
 914         } bits;
 915 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
 916
 917 /*
 918  * structure for Memory Controller Interface Control Max Segment reg in rxmac
 919  * address map.  Located at address 0x4088
 920  */
 921 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
 922         u32 value;
 923         struct {
 924 #ifdef _BIT_FIELDS_HTOL
 925                 u32 reserved:22;        /* bits 10-31 */
 926                 u32 max_size:8; /* bits 2-9 */
 927                 u32 fc_en:1;    /* bit 1 */
 928                 u32 seg_en:1;   /* bit 0 */
 929 #else
 930                 u32 seg_en:1;   /* bit 0 */
 931                 u32 fc_en:1;    /* bit 1 */
 932                 u32 max_size:8; /* bits 2-9 */
 933                 u32 reserved:22;        /* bits 10-31 */
 934 #endif
 935         } bits;
 936 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
 937
 938 /*
 939  * structure for Memory Controller Interface Water Mark reg in rxmac address
 940  * map.  Located at address 0x408C
 941  */
 942 typedef union _RXMAC_MCIF_WATER_MARK_t {
 943         u32 value;
 944         struct {
 945 #ifdef _BIT_FIELDS_HTOL
 946                 u32 reserved2:6;        /* bits 26-31 */
 947                 u32 mark_hi:10; /* bits 16-25 */
 948                 u32 reserved1:6;        /* bits 10-15 */
 949                 u32 mark_lo:10; /* bits 0-9 */
 950 #else
 951                 u32 mark_lo:10; /* bits 0-9 */
 952                 u32 reserved1:6;        /* bits 10-15 */
 953                 u32 mark_hi:10; /* bits 16-25 */
 954                 u32 reserved2:6;        /* bits 26-31 */
 955 #endif
 956         } bits;
 957 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
 958
 959 /*
 960  * structure for Rx Queue Dialog reg in rxmac address map.
 961  * located at address 0x4090
 962  */
 963 typedef union _RXMAC_RXQ_DIAG_t {
 964         u32 value;
 965         struct {
 966 #ifdef _BIT_FIELDS_HTOL
 967                 u32 reserved2:6;        /* bits 26-31 */
 968                 u32 rd_ptr:10;  /* bits 16-25 */
 969                 u32 reserved1:6;        /* bits 10-15 */
 970                 u32 wr_ptr:10;  /* bits 0-9 */
 971 #else
 972                 u32 wr_ptr:10;  /* bits 0-9 */
 973                 u32 reserved1:6;        /* bits 10-15 */
 974                 u32 rd_ptr:10;  /* bits 16-25 */
 975                 u32 reserved2:6;        /* bits 26-31 */
 976 #endif
 977         } bits;
 978 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
 979
 980 /*
 981  * structure for space availiable reg in rxmac address map.
 982  * located at address 0x4094
 983  */
 984 typedef union _RXMAC_SPACE_AVAIL_t {
 985         u32 value;
 986         struct {
 987 #ifdef _BIT_FIELDS_HTOL
 988                 u32 reserved2:15;               /* bits 17-31 */
 989                 u32 space_avail_en:1;   /* bit 16 */
 990                 u32 reserved1:6;                /* bits 10-15 */
 991                 u32 space_avail:10;     /* bits 0-9 */
 992 #else
 993                 u32 space_avail:10;     /* bits 0-9 */
 994                 u32 reserved1:6;                /* bits 10-15 */
 995                 u32 space_avail_en:1;   /* bit 16 */
 996                 u32 reserved2:15;               /* bits 17-31 */
 997 #endif
 998         } bits;
 999 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1000
1001 /*
1002  * structure for management interface reg in rxmac address map.
1003  * located at address 0x4098
1004  */
1005 typedef union _RXMAC_MIF_CTL_t {
1006         u32 value;
1007         struct {
1008 #ifdef _BIT_FIELDS_HTOL
1009                 u32 reserve:14;         /* bits 18-31 */
1010                 u32 drop_pkt_en:1;              /* bit 17 */
1011                 u32 drop_pkt_mask:17;   /* bits 0-16 */
1012 #else
1013                 u32 drop_pkt_mask:17;   /* bits 0-16 */
1014                 u32 drop_pkt_en:1;              /* bit 17 */
1015                 u32 reserve:14;         /* bits 18-31 */
1016 #endif
1017         } bits;
1018 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1019
1020 /*
1021  * structure for Error reg in rxmac address map.
1022  * located at address 0x409C
1023  */
1024 typedef union _RXMAC_ERROR_REG_t {
1025         u32 value;
1026         struct {
1027 #ifdef _BIT_FIELDS_HTOL
1028                 u32 reserve:28; /* bits 4-31 */
1029                 u32 mif:1;              /* bit 3 */
1030                 u32 async:1;    /* bit 2 */
1031                 u32 pkt_filter:1;       /* bit 1 */
1032                 u32 mcif:1;     /* bit 0 */
1033 #else
1034                 u32 mcif:1;     /* bit 0 */
1035                 u32 pkt_filter:1;       /* bit 1 */
1036                 u32 async:1;    /* bit 2 */
1037                 u32 mif:1;              /* bit 3 */
1038                 u32 reserve:28; /* bits 4-31 */
1039 #endif
1040         } bits;
1041 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1042
1043 /*
1044  * Rx MAC Module of JAGCore Address Mapping
1045  */
1046 typedef struct _RXMAC_t {                               /* Location: */
1047         RXMAC_CTRL_t ctrl;                              /*  0x4000 */
1048         RXMAC_WOL_CTL_CRC0_t crc0;                      /*  0x4004 */
1049         RXMAC_WOL_CRC12_t crc12;                        /*  0x4008 */
1050         RXMAC_WOL_CRC34_t crc34;                        /*  0x400C */
1051         RXMAC_WOL_SA_LO_t sa_lo;                        /*  0x4010 */
1052         RXMAC_WOL_SA_HI_t sa_hi;                        /*  0x4014 */
1053         u32 mask0_word0;                                /*  0x4018 */
1054         u32 mask0_word1;                                /*  0x401C */
1055         u32 mask0_word2;                                /*  0x4020 */
1056         u32 mask0_word3;                                /*  0x4024 */
1057         u32 mask1_word0;                                /*  0x4028 */
1058         u32 mask1_word1;                                /*  0x402C */
1059         u32 mask1_word2;                                /*  0x4030 */
1060         u32 mask1_word3;                                /*  0x4034 */
1061         u32 mask2_word0;                                /*  0x4038 */
1062         u32 mask2_word1;                                /*  0x403C */
1063         u32 mask2_word2;                                /*  0x4040 */
1064         u32 mask2_word3;                                /*  0x4044 */
1065         u32 mask3_word0;                                /*  0x4048 */
1066         u32 mask3_word1;                                /*  0x404C */
1067         u32 mask3_word2;                                /*  0x4050 */
1068         u32 mask3_word3;                                /*  0x4054 */
1069         u32 mask4_word0;                                /*  0x4058 */
1070         u32 mask4_word1;                                /*  0x405C */
1071         u32 mask4_word2;                                /*  0x4060 */
1072         u32 mask4_word3;                                /*  0x4064 */
1073         RXMAC_UNI_PF_ADDR1_t uni_pf_addr1;              /*  0x4068 */
1074         RXMAC_UNI_PF_ADDR2_t uni_pf_addr2;              /*  0x406C */
1075         RXMAC_UNI_PF_ADDR3_t uni_pf_addr3;              /*  0x4070 */
1076         u32 multi_hash1;                                /*  0x4074 */
1077         u32 multi_hash2;                                /*  0x4078 */
1078         u32 multi_hash3;                                /*  0x407C */
1079         u32 multi_hash4;                                /*  0x4080 */
1080         RXMAC_PF_CTRL_t pf_ctrl;                        /*  0x4084 */
1081         RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;    /*  0x4088 */
1082         RXMAC_MCIF_WATER_MARK_t mcif_water_mark;        /*  0x408C */
1083         RXMAC_RXQ_DIAG_t rxq_diag;                      /*  0x4090 */
1084         RXMAC_SPACE_AVAIL_t space_avail;                /*  0x4094 */
1085
1086         RXMAC_MIF_CTL_t mif_ctrl;                       /*  0x4098 */
1087         RXMAC_ERROR_REG_t err_reg;                      /*  0x409C */
1088 } RXMAC_t, *PRXMAC_t;
1089
1090 /* END OF TXMAC REGISTER ADDRESS MAP */
1091
1092
1093 /* START OF MAC REGISTER ADDRESS MAP */
1094
1095 /*
1096  * structure for configuration #1 reg in mac address map.
1097  * located at address 0x5000
1098  *
1099  * 31: soft reset
1100  * 30: sim reset
1101  * 29-20: reserved
1102  * 19: reset rx mc
1103  * 18: reset tx mc
1104  * 17: reset rx func
1105  * 16: reset tx fnc
1106  * 15-9: reserved
1107  * 8: loopback
1108  * 7-6: reserved
1109  * 5: rx flow
1110  * 4: tx flow
1111  * 3: syncd rx en
1112  * 2: rx enable
1113  * 1: syncd tx en
1114  * 0: tx enable
1115  */
1116
1117 #define CFG1_LOOPBACK   0x00000100
1118 #define CFG1_RX_FLOW    0x00000020
1119 #define CFG1_TX_FLOW    0x00000010
1120 #define CFG1_RX_ENABLE  0x00000004
1121 #define CFG1_TX_ENABLE  0x00000001
1122 #define CFG1_WAIT       0x0000000A      /* RX & TX syncd */
1123
1124 /*
1125  * structure for configuration #2 reg in mac address map.
1126  * located at address 0x5004
1127  * 31-16: reserved
1128  * 15-12: preamble
1129  * 11-10: reserved
1130  * 9-8: if mode
1131  * 7-6: reserved
1132  * 5: huge frame
1133  * 4: length check
1134  * 3: undefined
1135  * 2: pad crc
1136  * 1: crc enable
1137  * 0: full duplex
1138  */
1139
1140
1141 /*
1142  * structure for Interpacket gap reg in mac address map.
1143  * located at address 0x5008
1144  *
1145  * 31: reserved
1146  * 30-24: non B2B ipg 1
1147  * 23: undefined
1148  * 22-16: non B2B ipg 2
1149  * 15-8: Min ifg enforce
1150  * 7-0: B2B ipg
1151  *
1152  * structure for half duplex reg in mac address map.
1153  * located at address 0x500C
1154  * 31-24: reserved
1155  * 23-20: Alt BEB trunc
1156  * 19: Alt BEB enable
1157  * 18: BP no backoff
1158  * 17: no backoff
1159  * 16: excess defer
1160  * 15-12: re-xmit max
1161  * 11-10: reserved
1162  * 9-0: collision window
1163  */
1164
1165 /*
1166  * structure for Maximum Frame Length reg in mac address map.
1167  * located at address 0x5010: bits 0-15 hold the length.
1168  */
1169
1170 /*
1171  * structure for Reserve 1 reg in mac address map.
1172  * located at address 0x5014 - 0x5018
1173  * Defined earlier (u32)
1174  */
1175
1176 /*
1177  * structure for Test reg in mac address map.
1178  * located at address 0x501C
1179  * test: bits 0-2, rest unused
1180  */
1181
1182 /*
1183  * structure for MII Management Configuration reg in mac address map.
1184  * located at address 0x5020
1185  *
1186  * 31: reset MII mgmt
1187  * 30-6: unused
1188  * 5: scan auto increment
1189  * 4: preamble supress
1190  * 3: undefined
1191  * 2-0: mgmt clock reset
1192  */
1193
1194 /*
1195  * structure for MII Management Command reg in mac address map.
1196  * located at address 0x5024
1197  * bit 1: scan cycle
1198  * bit 0: read cycle
1199  */
1200
1201 /*
1202  * structure for MII Management Address reg in mac address map.
1203  * located at address 0x5028
1204  * 31-13: reserved
1205  * 12-8: phy addr
1206  * 7-5: reserved
1207  * 4-0: register
1208  */
1209
1210 #define MII_ADDR(phy,reg)       ((phy) << 8 | (reg))
1211
1212 /*
1213  * structure for MII Management Control reg in mac address map.
1214  * located at address 0x502C
1215  * 31-16: reserved
1216  * 15-0: phy control
1217  */
1218
1219 /*
1220  * structure for MII Management Status reg in mac address map.
1221  * located at address 0x5030
1222  * 31-16: reserved
1223  * 15-0: phy control
1224  */
1225
1226 /*
1227  * structure for MII Management Indicators reg in mac address map.
1228  * located at address 0x5034
1229  * 31-3: reserved
1230  * 2: not valid
1231  * 1: scanning
1232  * 0: busy
1233  */
1234
1235 #define MGMT_BUSY       0x00000001      /* busy */
1236 #define MGMT_WAIT       0x00000005      /* busy | not valid */
1237
1238 /*
1239  * structure for Interface Control reg in mac address map.
1240  * located at address 0x5038
1241  *
1242  * 31: reset if module
1243  * 30-28: reserved
1244  * 27: tbi mode
1245  * 26: ghd mode
1246  * 25: lhd mode
1247  * 24: phy mode
1248  * 23: reset per mii
1249  * 22-17: reserved
1250  * 16: speed
1251  * 15: reset pe100x
1252  * 14-11: reserved
1253  * 10: force quiet
1254  * 9: no cipher
1255  * 8: disable link fail
1256  * 7: reset gpsi
1257  * 6-1: reserved
1258  * 0: enable jabber protection
1259  */
1260
1261 /*
1262  * structure for Interface Status reg in mac address map.
1263  * located at address 0x503C
1264  */
1265 typedef union _MAC_IF_STAT_t {
1266         u32 value;
1267         struct {
1268 #ifdef _BIT_FIELDS_HTOL
1269                 u32 reserved:22;                /* bits 10-31 */
1270                 u32 excess_defer:1;     /* bit 9 */
1271                 u32 clash:1;            /* bit 8 */
1272                 u32 phy_jabber:1;               /* bit 7 */
1273                 u32 phy_link_ok:1;              /* bit 6 */
1274                 u32 phy_full_duplex:1;  /* bit 5 */
1275                 u32 phy_speed:1;                /* bit 4 */
1276                 u32 pe100x_link_fail:1; /* bit 3 */
1277                 u32 pe10t_loss_carrie:1;        /* bit 2 */
1278                 u32 pe10t_sqe_error:1;  /* bit 1 */
1279                 u32 pe10t_jabber:1;     /* bit 0 */
1280 #else
1281                 u32 pe10t_jabber:1;     /* bit 0 */
1282                 u32 pe10t_sqe_error:1;  /* bit 1 */
1283                 u32 pe10t_loss_carrie:1;        /* bit 2 */
1284                 u32 pe100x_link_fail:1; /* bit 3 */
1285                 u32 phy_speed:1;                /* bit 4 */
1286                 u32 phy_full_duplex:1;  /* bit 5 */
1287                 u32 phy_link_ok:1;              /* bit 6 */
1288                 u32 phy_jabber:1;               /* bit 7 */
1289                 u32 clash:1;            /* bit 8 */
1290                 u32 excess_defer:1;     /* bit 9 */
1291                 u32 reserved:22;                /* bits 10-31 */
1292 #endif
1293         } bits;
1294 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1295
1296 /*
1297  * structure for Mac Station Address, Part 1 reg in mac address map.
1298  * located at address 0x5040
1299  */
1300 typedef union _MAC_STATION_ADDR1_t {
1301         u32 value;
1302         struct {
1303 #ifdef _BIT_FIELDS_HTOL
1304                 u32 Octet6:8;   /* bits 24-31 */
1305                 u32 Octet5:8;   /* bits 16-23 */
1306                 u32 Octet4:8;   /* bits 8-15 */
1307                 u32 Octet3:8;   /* bits 0-7 */
1308 #else
1309                 u32 Octet3:8;   /* bits 0-7 */
1310                 u32 Octet4:8;   /* bits 8-15 */
1311                 u32 Octet5:8;   /* bits 16-23 */
1312                 u32 Octet6:8;   /* bits 24-31 */
1313 #endif
1314         } bits;
1315 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1316
1317 /*
1318  * structure for Mac Station Address, Part 2 reg in mac address map.
1319  * located at address 0x5044
1320  */
1321 typedef union _MAC_STATION_ADDR2_t {
1322         u32 value;
1323         struct {
1324 #ifdef _BIT_FIELDS_HTOL
1325                 u32 Octet2:8;   /* bits 24-31 */
1326                 u32 Octet1:8;   /* bits 16-23 */
1327                 u32 reserved:16;        /* bits 0-15 */
1328 #else
1329                 u32 reserved:16;        /* bit 0-15 */
1330                 u32 Octet1:8;   /* bits 16-23 */
1331                 u32 Octet2:8;   /* bits 24-31 */
1332 #endif
1333         } bits;
1334 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1335
1336 /*
1337  * MAC Module of JAGCore Address Mapping
1338  */
1339 typedef struct _MAC_t {                                 /* Location: */
1340         u32 cfg1;                                       /*  0x5000 */
1341         u32 cfg2;                                       /*  0x5004 */
1342         u32 ipg;                                        /*  0x5008 */
1343         u32 hfdp;                                       /*  0x500C */
1344         u32 max_fm_len;                                 /*  0x5010 */
1345         u32 rsv1;                                       /*  0x5014 */
1346         u32 rsv2;                                       /*  0x5018 */
1347         u32 mac_test;                                   /*  0x501C */
1348         u32 mii_mgmt_cfg;                               /*  0x5020 */
1349         u32 mii_mgmt_cmd;                               /*  0x5024 */
1350         u32 mii_mgmt_addr;                              /*  0x5028 */
1351         u32 mii_mgmt_ctrl;                              /*  0x502C */
1352         u32 mii_mgmt_stat;                              /*  0x5030 */
1353         u32 mii_mgmt_indicator;                         /*  0x5034 */
1354         u32 if_ctrl;                                    /*  0x5038 */
1355         MAC_IF_STAT_t if_stat;                          /*  0x503C */
1356         MAC_STATION_ADDR1_t station_addr_1;             /*  0x5040 */
1357         MAC_STATION_ADDR2_t station_addr_2;             /*  0x5044 */
1358 } MAC_t, *PMAC_t;
1359
1360 /* END OF MAC REGISTER ADDRESS MAP */
1361
1362 /* START OF MAC STAT REGISTER ADDRESS MAP */
1363
1364 /*
1365  * structure for Carry Register One and it's Mask Register reg located in mac
1366  * stat address map address 0x6130 and 0x6138.
1367  *
1368  * 31: tr64
1369  * 30: tr127
1370  * 29: tr255
1371  * 28: tr511
1372  * 27: tr1k
1373  * 26: trmax
1374  * 25: trmgv
1375  * 24-17: unused
1376  * 16: rbyt
1377  * 15: rpkt
1378  * 14: rfcs
1379  * 13: rmca
1380  * 12: rbca
1381  * 11: rxcf
1382  * 10: rxpf
1383  * 9: rxuo
1384  * 8: raln
1385  * 7: rflr
1386  * 6: rcde
1387  * 5: rcse
1388  * 4: rund
1389  * 3: rovr
1390  * 2: rfrg
1391  * 1: rjbr
1392  * 0: rdrp
1393  */
1394
1395 /*
1396  * structure for Carry Register Two Mask Register reg in mac stat address map.
1397  * located at address 0x613C
1398  *
1399  * 31-20: unused
1400  * 19: tjbr
1401  * 18: tfcs
1402  * 17: txcf
1403  * 16: tovr
1404  * 15: tund
1405  * 14: trfg
1406  * 13: tbyt
1407  * 12: tpkt
1408  * 11: tmca
1409  * 10: tbca
1410  * 9: txpf
1411  * 8: tdfr
1412  * 7: tedf
1413  * 6: tscl
1414  * 5: tmcl
1415  * 4: tlcl
1416  * 3: txcl
1417  * 2: tncl
1418  * 1: tpfh
1419  * 0: tdrp
1420  */
1421
1422 /*
1423  * MAC STATS Module of JAGCore Address Mapping
1424  */
1425 struct macstat_regs
1426 {                                       /* Location: */
1427         u32 pad[32];                    /*  0x6000 - 607C */
1428
1429         /* Tx/Rx 0-64 Byte Frame Counter */
1430         u32 TR64;                       /*  0x6080 */
1431
1432         /* Tx/Rx 65-127 Byte Frame Counter */
1433         u32 TR127;                      /*  0x6084 */
1434
1435         /* Tx/Rx 128-255 Byte Frame Counter */
1436         u32 TR255;                      /*  0x6088 */
1437
1438         /* Tx/Rx 256-511 Byte Frame Counter */
1439         u32 TR511;                      /*  0x608C */
1440
1441         /* Tx/Rx 512-1023 Byte Frame Counter */
1442         u32 TR1K;                       /*  0x6090 */
1443
1444         /* Tx/Rx 1024-1518 Byte Frame Counter */
1445         u32 TRMax;                      /*  0x6094 */
1446
1447         /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1448         u32 TRMgv;                      /*  0x6098 */
1449
1450         /* Rx Byte Counter */
1451         u32 RByt;                       /*  0x609C */
1452
1453         /* Rx Packet Counter */
1454         u32 RPkt;                       /*  0x60A0 */
1455
1456         /* Rx FCS Error Counter */
1457         u32 RFcs;                       /*  0x60A4 */
1458
1459         /* Rx Multicast Packet Counter */
1460         u32 RMca;                       /*  0x60A8 */
1461
1462         /* Rx Broadcast Packet Counter */
1463         u32 RBca;                       /*  0x60AC */
1464
1465         /* Rx Control Frame Packet Counter */
1466         u32 RxCf;                       /*  0x60B0 */
1467
1468         /* Rx Pause Frame Packet Counter */
1469         u32 RxPf;                       /*  0x60B4 */
1470
1471         /* Rx Unknown OP Code Counter */
1472         u32 RxUo;                       /*  0x60B8 */
1473
1474         /* Rx Alignment Error Counter */
1475         u32 RAln;                       /*  0x60BC */
1476
1477         /* Rx Frame Length Error Counter */
1478         u32 RFlr;                       /*  0x60C0 */
1479
1480         /* Rx Code Error Counter */
1481         u32 RCde;                       /*  0x60C4 */
1482
1483         /* Rx Carrier Sense Error Counter */
1484         u32 RCse;                       /*  0x60C8 */
1485
1486         /* Rx Undersize Packet Counter */
1487         u32 RUnd;                       /*  0x60CC */
1488
1489         /* Rx Oversize Packet Counter */
1490         u32 ROvr;                       /*  0x60D0 */
1491
1492         /* Rx Fragment Counter */
1493         u32 RFrg;                       /*  0x60D4 */
1494
1495         /* Rx Jabber Counter */
1496         u32 RJbr;                       /*  0x60D8 */
1497
1498         /* Rx Drop */
1499         u32 RDrp;                       /*  0x60DC */
1500
1501         /* Tx Byte Counter */
1502         u32 TByt;                       /*  0x60E0 */
1503
1504         /* Tx Packet Counter */
1505         u32 TPkt;                       /*  0x60E4 */
1506
1507         /* Tx Multicast Packet Counter */
1508         u32 TMca;                       /*  0x60E8 */
1509
1510         /* Tx Broadcast Packet Counter */
1511         u32 TBca;                       /*  0x60EC */
1512
1513         /* Tx Pause Control Frame Counter */
1514         u32 TxPf;                       /*  0x60F0 */
1515
1516         /* Tx Deferral Packet Counter */
1517         u32 TDfr;                       /*  0x60F4 */
1518
1519         /* Tx Excessive Deferral Packet Counter */
1520         u32 TEdf;                       /*  0x60F8 */
1521
1522         /* Tx Single Collision Packet Counter */
1523         u32 TScl;                       /*  0x60FC */
1524
1525         /* Tx Multiple Collision Packet Counter */
1526         u32 TMcl;                       /*  0x6100 */
1527
1528         /* Tx Late Collision Packet Counter */
1529         u32 TLcl;                       /*  0x6104 */
1530
1531         /* Tx Excessive Collision Packet Counter */
1532         u32 TXcl;                       /*  0x6108 */
1533
1534         /* Tx Total Collision Packet Counter */
1535         u32 TNcl;                       /*  0x610C */
1536
1537         /* Tx Pause Frame Honored Counter */
1538         u32 TPfh;                       /*  0x6110 */
1539
1540         /* Tx Drop Frame Counter */
1541         u32 TDrp;                       /*  0x6114 */
1542
1543         /* Tx Jabber Frame Counter */
1544         u32 TJbr;                       /*  0x6118 */
1545
1546         /* Tx FCS Error Counter */
1547         u32 TFcs;                       /*  0x611C */
1548
1549         /* Tx Control Frame Counter */
1550         u32 TxCf;                       /*  0x6120 */
1551
1552         /* Tx Oversize Frame Counter */
1553         u32 TOvr;                       /*  0x6124 */
1554
1555         /* Tx Undersize Frame Counter */
1556         u32 TUnd;                       /*  0x6128 */
1557
1558         /* Tx Fragments Frame Counter */
1559         u32 TFrg;                       /*  0x612C */
1560
1561         /* Carry Register One Register */
1562         u32 Carry1;                     /*  0x6130 */
1563
1564         /* Carry Register Two Register */
1565         u32 Carry2;                     /*  0x6134 */
1566
1567         /* Carry Register One Mask Register */
1568         u32 Carry1M;                    /*  0x6138 */
1569
1570         /* Carry Register Two Mask Register */
1571         u32 Carry2M;                    /*  0x613C */
1572 };
1573
1574 /* END OF MAC STAT REGISTER ADDRESS MAP */
1575
1576
1577 /* START OF MMC REGISTER ADDRESS MAP */
1578
1579 /*
1580  * Main Memory Controller Control reg in mmc address map.
1581  * located at address 0x7000
1582  */
1583
1584 #define ET_MMC_ENABLE           1
1585 #define ET_MMC_ARB_DISABLE      2
1586 #define ET_MMC_RXMAC_DISABLE    4
1587 #define ET_MMC_TXMAC_DISABLE    8
1588 #define ET_MMC_TXDMA_DISABLE    16
1589 #define ET_MMC_RXDMA_DISABLE    32
1590 #define ET_MMC_FORCE_CE         64
1591
1592 /*
1593  * Main Memory Controller Host Memory Access Address reg in mmc
1594  * address map.  Located at address 0x7004. Top 16 bits hold the address bits
1595  */
1596
1597 #define ET_SRAM_REQ_ACCESS      1
1598 #define ET_SRAM_WR_ACCESS       2
1599 #define ET_SRAM_IS_CTRL         4
1600
1601 /*
1602  * structure for Main Memory Controller Host Memory Access Data reg in mmc
1603  * address map.  Located at address 0x7008 - 0x7014
1604  * Defined earlier (u32)
1605  */
1606
1607 /*
1608  * Memory Control Module of JAGCore Address Mapping
1609  */
1610 struct mmc_regs {               /* Location: */
1611         u32 mmc_ctrl;           /*  0x7000 */
1612         u32 sram_access;        /*  0x7004 */
1613         u32 sram_word1;         /*  0x7008 */
1614         u32 sram_word2;         /*  0x700C */
1615         u32 sram_word3;         /*  0x7010 */
1616         u32 sram_word4;         /*  0x7014 */
1617 };
1618
1619 /* END OF MMC REGISTER ADDRESS MAP */
1620
1621
1622 /*
1623  * JAGCore Address Mapping
1624  */
1625 typedef struct _ADDRESS_MAP_t {
1626         struct global_regs global;
1627         /* unused section of global address map */
1628         u8 unused_global[4096 - sizeof(struct global_regs)];
1629         struct txdma_regs txdma;
1630         /* unused section of txdma address map */
1631         u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1632         struct rxdma_regs rxdma;
1633         /* unused section of rxdma address map */
1634         u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1635         TXMAC_t txmac;
1636         /* unused section of txmac address map */
1637         u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1638         RXMAC_t rxmac;
1639         /* unused section of rxmac address map */
1640         u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1641         MAC_t mac;
1642         /* unused section of mac address map */
1643         u8 unused_mac[4096 - sizeof(MAC_t)];
1644         struct macstat_regs macstat;
1645         /* unused section of mac stat address map */
1646         u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1647         struct mmc_regs mmc;
1648         /* unused section of mmc address map */
1649         u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1650         /* unused section of address map */
1651         u8 unused_[1015808];
1652
1653         u8 unused_exp_rom[4096];        /* MGS-size TBD */
1654         u8 unused__[524288];    /* unused section of address map */
1655 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1656
1657 #endif /* _ET1310_ADDRESS_MAP_H_ */