2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Erin.Lo <erin.lo@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "skeleton64.dtsi"
20 compatible = "mediatek,mt2701";
21 interrupt-parent = <&sysirq>;
29 compatible = "arm,cortex-a7";
34 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7";
44 compatible = "arm,cortex-a7";
49 system_clk: dummy13m {
50 compatible = "fixed-clock";
51 clock-frequency = <13000000>;
56 compatible = "fixed-clock";
57 clock-frequency = <32000>;
62 compatible = "fixed-clock";
63 clock-frequency = <26000000>;
68 compatible = "arm,armv7-timer";
69 interrupt-parent = <&gic>;
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
76 watchdog: watchdog@10007000 {
77 compatible = "mediatek,mt2701-wdt",
78 "mediatek,mt6589-wdt";
79 reg = <0 0x10007000 0 0x100>;
82 timer: timer@10008000 {
83 compatible = "mediatek,mt2701-timer",
84 "mediatek,mt6577-timer";
85 reg = <0 0x10008000 0 0x80>;
86 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
87 clocks = <&system_clk>, <&rtc_clk>;
88 clock-names = "system-clk", "rtc-clk";
91 sysirq: interrupt-controller@10200100 {
92 compatible = "mediatek,mt2701-sysirq",
93 "mediatek,mt6577-sysirq";
95 #interrupt-cells = <3>;
96 interrupt-parent = <&gic>;
97 reg = <0 0x10200100 0 0x1c>;
100 gic: interrupt-controller@10211000 {
101 compatible = "arm,cortex-a7-gic";
102 interrupt-controller;
103 #interrupt-cells = <3>;
104 interrupt-parent = <&gic>;
105 reg = <0 0x10211000 0 0x1000>,
106 <0 0x10212000 0 0x1000>,
107 <0 0x10214000 0 0x2000>,
108 <0 0x10216000 0 0x2000>;
111 uart0: serial@11002000 {
112 compatible = "mediatek,mt2701-uart",
113 "mediatek,mt6577-uart";
114 reg = <0 0x11002000 0 0x400>;
115 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
116 clocks = <&uart_clk>;
120 uart1: serial@11003000 {
121 compatible = "mediatek,mt2701-uart",
122 "mediatek,mt6577-uart";
123 reg = <0 0x11003000 0 0x400>;
124 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
125 clocks = <&uart_clk>;
129 uart2: serial@11004000 {
130 compatible = "mediatek,mt2701-uart",
131 "mediatek,mt6577-uart";
132 reg = <0 0x11004000 0 0x400>;
133 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
134 clocks = <&uart_clk>;
138 uart3: serial@11005000 {
139 compatible = "mediatek,mt2701-uart",
140 "mediatek,mt6577-uart";
141 reg = <0 0x11005000 0 0x400>;
142 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
143 clocks = <&uart_clk>;