drivers/clocksource/time-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370/XP SoC timer handling.
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Timer 0 is used as free-running clocksource, while timer 1 is
  15  * used as clock_event_device.
  16  *
  17  * ---
  18  * Clocksource driver for Armada 370 and Armada XP SoC.
  19  * This driver implements one compatible string for each SoC, given
  20  * each has its own characteristics:
  21  *
  22  *   * Armada 370 has no 25 MHz fixed timer.
  23  *
  24  *   * Armada XP cannot work properly without such 25 MHz fixed timer as
  25  *     doing otherwise leads to using a clocksource whose frequency varies
  26  *     when doing cpufreq frequency changes.
  27  *
  28  * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
  29  */
  30
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/kernel.h>
  34 #include <linux/clk.h>
  35 #include <linux/cpu.h>
  36 #include <linux/timer.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/of.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/of_address.h>
  42 #include <linux/irq.h>
  43 #include <linux/module.h>
  44 #include <linux/sched_clock.h>
  45 #include <linux/percpu.h>
  46
  47 /*
  48  * Timer block registers.
  49  */
  50 #define TIMER_CTRL_OFF          0x0000
  51 #define  TIMER0_EN               BIT(0)
  52 #define  TIMER0_RELOAD_EN        BIT(1)
  53 #define  TIMER0_25MHZ            BIT(11)
  54 #define  TIMER0_DIV(div)         ((div) << 19)
  55 #define  TIMER1_EN               BIT(2)
  56 #define  TIMER1_RELOAD_EN        BIT(3)
  57 #define  TIMER1_25MHZ            BIT(12)
  58 #define  TIMER1_DIV(div)         ((div) << 22)
  59 #define TIMER_EVENTS_STATUS     0x0004
  60 #define  TIMER0_CLR_MASK         (~0x1)
  61 #define  TIMER1_CLR_MASK         (~0x100)
  62 #define TIMER0_RELOAD_OFF       0x0010
  63 #define TIMER0_VAL_OFF          0x0014
  64 #define TIMER1_RELOAD_OFF       0x0018
  65 #define TIMER1_VAL_OFF          0x001c
  66
  67 #define LCL_TIMER_EVENTS_STATUS 0x0028
  68 /* Global timers are connected to the coherency fabric clock, and the
  69    below divider reduces their incrementing frequency. */
  70 #define TIMER_DIVIDER_SHIFT     5
  71 #define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
  72
  73 /*
  74  * SoC-specific data.
  75  */
  76 static void __iomem *timer_base, *local_base;
  77 static unsigned int timer_clk;
  78 static bool timer25Mhz = true;
  79 static u32 enable_mask;
  80
  81 /*
  82  * Number of timer ticks per jiffy.
  83  */
  84 static u32 ticks_per_jiffy;
  85
  86 static struct clock_event_device __percpu *armada_370_xp_evt;
  87
  88 static void local_timer_ctrl_clrset(u32 clr, u32 set)
  89 {
  90         writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
  91                 local_base + TIMER_CTRL_OFF);
  92 }
  93
  94 static u64 notrace armada_370_xp_read_sched_clock(void)
  95 {
  96         return ~readl(timer_base + TIMER0_VAL_OFF);
  97 }
  98
  99 /*
 100  * Clockevent handling.
 101  */
 102 static int
 103 armada_370_xp_clkevt_next_event(unsigned long delta,
 104                                 struct clock_event_device *dev)
 105 {
 106         /*
 107          * Clear clockevent timer interrupt.
 108          */
 109         writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 110
 111         /*
 112          * Setup new clockevent timer value.
 113          */
 114         writel(delta, local_base + TIMER0_VAL_OFF);
 115
 116         /*
 117          * Enable the timer.
 118          */
 119         local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
 120         return 0;
 121 }
 122
 123 static void
 124 armada_370_xp_clkevt_mode(enum clock_event_mode mode,
 125                           struct clock_event_device *dev)
 126 {
 127         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 128
 129                 /*
 130                  * Setup timer to fire at 1/HZ intervals.
 131                  */
 132                 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
 133                 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
 134
 135                 /*
 136                  * Enable timer.
 137                  */
 138                 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 139         } else {
 140                 /*
 141                  * Disable timer.
 142                  */
 143                 local_timer_ctrl_clrset(TIMER0_EN, 0);
 144
 145                 /*
 146                  * ACK pending timer interrupt.
 147                  */
 148                 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 149         }
 150 }
 151
 152 static int armada_370_xp_clkevt_irq;
 153
 154 static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
 155 {
 156         /*
 157          * ACK timer interrupt and call event handler.
 158          */
 159         struct clock_event_device *evt = dev_id;
 160
 161         writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 162         evt->event_handler(evt);
 163
 164         return IRQ_HANDLED;
 165 }
 166
 167 /*
 168  * Setup the local clock events for a CPU.
 169  */
 170 static int armada_370_xp_timer_setup(struct clock_event_device *evt)
 171 {
 172         u32 clr = 0, set = 0;
 173         int cpu = smp_processor_id();
 174
 175         if (timer25Mhz)
 176                 set = TIMER0_25MHZ;
 177         else
 178                 clr = TIMER0_25MHZ;
 179         local_timer_ctrl_clrset(clr, set);
 180
 181         evt->name               = "armada_370_xp_per_cpu_tick",
 182         evt->features           = CLOCK_EVT_FEAT_ONESHOT |
 183                                   CLOCK_EVT_FEAT_PERIODIC;
 184         evt->shift              = 32,
 185         evt->rating             = 300,
 186         evt->set_next_event     = armada_370_xp_clkevt_next_event,
 187         evt->set_mode           = armada_370_xp_clkevt_mode,
 188         evt->irq                = armada_370_xp_clkevt_irq;
 189         evt->cpumask            = cpumask_of(cpu);
 190
 191         clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
 192         enable_percpu_irq(evt->irq, 0);
 193
 194         return 0;
 195 }
 196
 197 static void armada_370_xp_timer_stop(struct clock_event_device *evt)
 198 {
 199         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 200         disable_percpu_irq(evt->irq);
 201 }
 202
 203 static int armada_370_xp_timer_cpu_notify(struct notifier_block *self,
 204                                            unsigned long action, void *hcpu)
 205 {
 206         /*
 207          * Grab cpu pointer in each case to avoid spurious
 208          * preemptible warnings
 209          */
 210         switch (action & ~CPU_TASKS_FROZEN) {
 211         case CPU_STARTING:
 212                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 213                 break;
 214         case CPU_DYING:
 215                 armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
 216                 break;
 217         }
 218
 219         return NOTIFY_OK;
 220 }
 221
 222 static struct notifier_block armada_370_xp_timer_cpu_nb = {
 223         .notifier_call = armada_370_xp_timer_cpu_notify,
 224 };
 225
 226 static void __init armada_370_xp_timer_common_init(struct device_node *np)
 227 {
 228         u32 clr = 0, set = 0;
 229         int res;
 230
 231         timer_base = of_iomap(np, 0);
 232         WARN_ON(!timer_base);
 233         local_base = of_iomap(np, 1);
 234
 235         if (timer25Mhz) {
 236                 set = TIMER0_25MHZ;
 237                 enable_mask = TIMER0_EN;
 238         } else {
 239                 clr = TIMER0_25MHZ;
 240                 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
 241         }
 242         atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
 243         local_timer_ctrl_clrset(clr, set);
 244
 245         /*
 246          * We use timer 0 as clocksource, and private(local) timer 0
 247          * for clockevents
 248          */
 249         armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
 250
 251         ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
 252
 253         /*
 254          * Setup free-running clocksource timer (interrupts
 255          * disabled).
 256          */
 257         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 258         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 259
 260         atomic_io_modify(timer_base + TIMER_CTRL_OFF,
 261                 TIMER0_RELOAD_EN | enable_mask,
 262                 TIMER0_RELOAD_EN | enable_mask);
 263
 264         /*
 265          * Set scale and timer for sched_clock.
 266          */
 267         sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
 268
 269         clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
 270                               "armada_370_xp_clocksource",
 271                               timer_clk, 300, 32, clocksource_mmio_readl_down);
 272
 273         register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
 274
 275         armada_370_xp_evt = alloc_percpu(struct clock_event_device);
 276
 277
 278         /*
 279          * Setup clockevent timer (interrupt-driven).
 280          */
 281         res = request_percpu_irq(armada_370_xp_clkevt_irq,
 282                                 armada_370_xp_timer_interrupt,
 283                                 "armada_370_xp_per_cpu_tick",
 284                                 armada_370_xp_evt);
 285         /* Immediately configure the timer on the boot CPU */
 286         if (!res)
 287                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 288 }
 289
 290 static void __init armada_xp_timer_init(struct device_node *np)
 291 {
 292         struct clk *clk = of_clk_get_by_name(np, "fixed");
 293
 294         /* The 25Mhz fixed clock is mandatory, and must always be available */
 295         BUG_ON(IS_ERR(clk));
 296         timer_clk = clk_get_rate(clk);
 297
 298         armada_370_xp_timer_common_init(np);
 299 }
 300 CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
 301                        armada_xp_timer_init);
 302
 303 static void __init armada_370_timer_init(struct device_node *np)
 304 {
 305         struct clk *clk = of_clk_get(np, 0);
 306
 307         BUG_ON(IS_ERR(clk));
 308         timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
 309         timer25Mhz = false;
 310
 311         armada_370_xp_timer_common_init(np);
 312 }
 313 CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
 314                        armada_370_timer_init);