2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_LOCK (0x1 << 31)
26 #define IMX7_ENET_PLL_POWER (0x1 << 5)
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source
31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL
33 * @powerdown: pll powerdown offset bit
34 * @div_mask: mask of divider bits
35 * @div_shift: shift of divider bits
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
38 * is actually a multiplier, and always sits at bit 0.
47 unsigned long ref_clock
;
50 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
52 static int clk_pllv3_wait_lock(struct clk_pllv3
*pll
)
54 unsigned long timeout
= jiffies
+ msecs_to_jiffies(10);
55 u32 val
= readl_relaxed(pll
->base
) & pll
->powerdown
;
57 /* No need to wait for lock when pll is not powered up */
58 if ((pll
->powerup_set
&& !val
) || (!pll
->powerup_set
&& val
))
61 /* Wait for PLL to lock */
63 if (readl_relaxed(pll
->base
) & BM_PLL_LOCK
)
65 if (time_after(jiffies
, timeout
))
67 usleep_range(50, 500);
70 return readl_relaxed(pll
->base
) & BM_PLL_LOCK
? 0 : -ETIMEDOUT
;
73 static int clk_pllv3_prepare(struct clk_hw
*hw
)
75 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
78 val
= readl_relaxed(pll
->base
);
83 writel_relaxed(val
, pll
->base
);
85 return clk_pllv3_wait_lock(pll
);
88 static void clk_pllv3_unprepare(struct clk_hw
*hw
)
90 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
93 val
= readl_relaxed(pll
->base
);
98 writel_relaxed(val
, pll
->base
);
101 static int clk_pllv3_is_prepared(struct clk_hw
*hw
)
103 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
105 if (readl_relaxed(pll
->base
) & BM_PLL_LOCK
)
111 static unsigned long clk_pllv3_recalc_rate(struct clk_hw
*hw
,
112 unsigned long parent_rate
)
114 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
115 u32 div
= (readl_relaxed(pll
->base
) >> pll
->div_shift
) & pll
->div_mask
;
117 return (div
== 1) ? parent_rate
* 22 : parent_rate
* 20;
120 static long clk_pllv3_round_rate(struct clk_hw
*hw
, unsigned long rate
,
121 unsigned long *prate
)
123 unsigned long parent_rate
= *prate
;
125 return (rate
>= parent_rate
* 22) ? parent_rate
* 22 :
129 static int clk_pllv3_set_rate(struct clk_hw
*hw
, unsigned long rate
,
130 unsigned long parent_rate
)
132 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
135 if (rate
== parent_rate
* 22)
137 else if (rate
== parent_rate
* 20)
142 val
= readl_relaxed(pll
->base
);
143 val
&= ~(pll
->div_mask
<< pll
->div_shift
);
144 val
|= (div
<< pll
->div_shift
);
145 writel_relaxed(val
, pll
->base
);
147 return clk_pllv3_wait_lock(pll
);
150 static const struct clk_ops clk_pllv3_ops
= {
151 .prepare
= clk_pllv3_prepare
,
152 .unprepare
= clk_pllv3_unprepare
,
153 .is_prepared
= clk_pllv3_is_prepared
,
154 .recalc_rate
= clk_pllv3_recalc_rate
,
155 .round_rate
= clk_pllv3_round_rate
,
156 .set_rate
= clk_pllv3_set_rate
,
159 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw
*hw
,
160 unsigned long parent_rate
)
162 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
163 u32 div
= readl_relaxed(pll
->base
) & pll
->div_mask
;
165 return parent_rate
* div
/ 2;
168 static long clk_pllv3_sys_round_rate(struct clk_hw
*hw
, unsigned long rate
,
169 unsigned long *prate
)
171 unsigned long parent_rate
= *prate
;
172 unsigned long min_rate
= parent_rate
* 54 / 2;
173 unsigned long max_rate
= parent_rate
* 108 / 2;
178 else if (rate
< min_rate
)
180 div
= rate
* 2 / parent_rate
;
182 return parent_rate
* div
/ 2;
185 static int clk_pllv3_sys_set_rate(struct clk_hw
*hw
, unsigned long rate
,
186 unsigned long parent_rate
)
188 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
189 unsigned long min_rate
= parent_rate
* 54 / 2;
190 unsigned long max_rate
= parent_rate
* 108 / 2;
193 if (rate
< min_rate
|| rate
> max_rate
)
196 div
= rate
* 2 / parent_rate
;
197 val
= readl_relaxed(pll
->base
);
198 val
&= ~pll
->div_mask
;
200 writel_relaxed(val
, pll
->base
);
202 return clk_pllv3_wait_lock(pll
);
205 static const struct clk_ops clk_pllv3_sys_ops
= {
206 .prepare
= clk_pllv3_prepare
,
207 .unprepare
= clk_pllv3_unprepare
,
208 .is_prepared
= clk_pllv3_is_prepared
,
209 .recalc_rate
= clk_pllv3_sys_recalc_rate
,
210 .round_rate
= clk_pllv3_sys_round_rate
,
211 .set_rate
= clk_pllv3_sys_set_rate
,
214 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw
*hw
,
215 unsigned long parent_rate
)
217 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
218 u32 mfn
= readl_relaxed(pll
->base
+ PLL_NUM_OFFSET
);
219 u32 mfd
= readl_relaxed(pll
->base
+ PLL_DENOM_OFFSET
);
220 u32 div
= readl_relaxed(pll
->base
) & pll
->div_mask
;
222 return (parent_rate
* div
) + ((parent_rate
/ mfd
) * mfn
);
225 static long clk_pllv3_av_round_rate(struct clk_hw
*hw
, unsigned long rate
,
226 unsigned long *prate
)
228 unsigned long parent_rate
= *prate
;
229 unsigned long min_rate
= parent_rate
* 27;
230 unsigned long max_rate
= parent_rate
* 54;
232 u32 mfn
, mfd
= 1000000;
237 else if (rate
< min_rate
)
240 div
= rate
/ parent_rate
;
241 temp64
= (u64
) (rate
- div
* parent_rate
);
243 do_div(temp64
, parent_rate
);
246 return parent_rate
* div
+ parent_rate
/ mfd
* mfn
;
249 static int clk_pllv3_av_set_rate(struct clk_hw
*hw
, unsigned long rate
,
250 unsigned long parent_rate
)
252 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
253 unsigned long min_rate
= parent_rate
* 27;
254 unsigned long max_rate
= parent_rate
* 54;
256 u32 mfn
, mfd
= 1000000;
259 if (rate
< min_rate
|| rate
> max_rate
)
262 div
= rate
/ parent_rate
;
263 temp64
= (u64
) (rate
- div
* parent_rate
);
265 do_div(temp64
, parent_rate
);
268 val
= readl_relaxed(pll
->base
);
269 val
&= ~pll
->div_mask
;
271 writel_relaxed(val
, pll
->base
);
272 writel_relaxed(mfn
, pll
->base
+ PLL_NUM_OFFSET
);
273 writel_relaxed(mfd
, pll
->base
+ PLL_DENOM_OFFSET
);
275 return clk_pllv3_wait_lock(pll
);
278 static const struct clk_ops clk_pllv3_av_ops
= {
279 .prepare
= clk_pllv3_prepare
,
280 .unprepare
= clk_pllv3_unprepare
,
281 .is_prepared
= clk_pllv3_is_prepared
,
282 .recalc_rate
= clk_pllv3_av_recalc_rate
,
283 .round_rate
= clk_pllv3_av_round_rate
,
284 .set_rate
= clk_pllv3_av_set_rate
,
287 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw
*hw
,
288 unsigned long parent_rate
)
290 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
292 return pll
->ref_clock
;
295 static const struct clk_ops clk_pllv3_enet_ops
= {
296 .prepare
= clk_pllv3_prepare
,
297 .unprepare
= clk_pllv3_unprepare
,
298 .is_prepared
= clk_pllv3_is_prepared
,
299 .recalc_rate
= clk_pllv3_enet_recalc_rate
,
302 struct clk
*imx_clk_pllv3(enum imx_pllv3_type type
, const char *name
,
303 const char *parent_name
, void __iomem
*base
,
306 struct clk_pllv3
*pll
;
307 const struct clk_ops
*ops
;
309 struct clk_init_data init
;
311 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
313 return ERR_PTR(-ENOMEM
);
315 pll
->powerdown
= BM_PLL_POWER
;
319 ops
= &clk_pllv3_sys_ops
;
321 case IMX_PLLV3_USB_VF610
:
324 ops
= &clk_pllv3_ops
;
325 pll
->powerup_set
= true;
328 ops
= &clk_pllv3_av_ops
;
330 case IMX_PLLV3_ENET_IMX7
:
331 pll
->powerdown
= IMX7_ENET_PLL_POWER
;
332 pll
->ref_clock
= 1000000000;
333 ops
= &clk_pllv3_enet_ops
;
336 pll
->ref_clock
= 500000000;
337 ops
= &clk_pllv3_enet_ops
;
340 ops
= &clk_pllv3_ops
;
343 pll
->div_mask
= div_mask
;
348 init
.parent_names
= &parent_name
;
349 init
.num_parents
= 1;
351 pll
->hw
.init
= &init
;
353 clk
= clk_register(NULL
, &pll
->hw
);