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iwlwifi: mvm: don't request SMPS on non-STA iface
[linux-2.6/btrfs-unstable.git] / drivers / ata / ata_piix.c
blob2f48123d74c4c85d84180e3e7a39c712a1b7a175
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
129
130 PIIX_AHCI_DEVICE = 6,
131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 };
135
136 enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb,
153 ich8_2port_sata_snb,
154 };
155
156 struct piix_map_db {
157 const u32 mask;
158 const u16 port_enable;
159 const int map[][4];
160 };
161
162 struct piix_host_priv {
163 const int *map;
164 u32 saved_iocfg;
165 void __iomem *sidpr;
166 };
167
168 static unsigned int in_module_init = 1;
169
170 static const struct pci_device_id piix_pci_tbl[] = {
171 /* Intel PIIX3 for the 430HX etc */
172 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
173 /* VMware ICH4 */
174 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
175 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
176 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
177 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel PIIX4 */
179 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel PIIX4 */
181 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX */
183 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel ICH (i810, i815, i840) UDMA 66*/
185 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
186 /* Intel ICH0 : UDMA 33*/
187 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
188 /* Intel ICH2M */
189 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
191 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH3M */
193 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3 (E7500/1) UDMA 100 */
195 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH4-L */
197 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214
215 /* SATA ports */
216
217 /* 82801EB (ICH5) */
218 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
219 /* 82801EB (ICH5) */
220 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
221 /* 6300ESB (ICH5 variant with broken PCS present bits) */
222 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
223 /* 6300ESB pretending RAID */
224 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
225 /* 82801FB/FW (ICH6/ICH6W) */
226 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
227 /* 82801FR/FRW (ICH6R/ICH6RW) */
228 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
229 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
230 * Attach iff the controller is in IDE mode. */
231 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
232 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
239 /* SATA Controller 1 IDE (ICH8) */
240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
241 /* SATA Controller 2 IDE (ICH8) */
242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
243 /* Mobile SATA Controller IDE (ICH8M), Apple */
244 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
245 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
246 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
247 /* Mobile SATA Controller IDE (ICH8M) */
248 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
249 /* SATA Controller IDE (ICH9) */
250 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
251 /* SATA Controller IDE (ICH9) */
252 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
253 /* SATA Controller IDE (ICH9) */
254 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
257 /* SATA Controller IDE (ICH9M) */
258 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
259 /* SATA Controller IDE (ICH9M) */
260 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
261 /* SATA Controller IDE (Tolapai) */
262 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
263 /* SATA Controller IDE (ICH10) */
264 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
265 /* SATA Controller IDE (ICH10) */
266 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
267 /* SATA Controller IDE (ICH10) */
268 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
269 /* SATA Controller IDE (ICH10) */
270 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
271 /* SATA Controller IDE (PCH) */
272 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
273 /* SATA Controller IDE (PCH) */
274 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
275 /* SATA Controller IDE (PCH) */
276 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
277 /* SATA Controller IDE (PCH) */
278 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
279 /* SATA Controller IDE (PCH) */
280 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
281 /* SATA Controller IDE (PCH) */
282 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
283 /* SATA Controller IDE (CPT) */
284 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
285 /* SATA Controller IDE (CPT) */
286 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
287 /* SATA Controller IDE (CPT) */
288 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
289 /* SATA Controller IDE (CPT) */
290 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
291 /* SATA Controller IDE (PBG) */
292 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
293 /* SATA Controller IDE (PBG) */
294 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
295 /* SATA Controller IDE (Panther Point) */
296 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
297 /* SATA Controller IDE (Panther Point) */
298 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
299 /* SATA Controller IDE (Panther Point) */
300 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
301 /* SATA Controller IDE (Panther Point) */
302 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303 /* SATA Controller IDE (Lynx Point) */
304 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
305 /* SATA Controller IDE (Lynx Point) */
306 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
307 /* SATA Controller IDE (Lynx Point) */
308 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
309 /* SATA Controller IDE (Lynx Point) */
310 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
311 /* SATA Controller IDE (Lynx Point-LP) */
312 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
313 /* SATA Controller IDE (Lynx Point-LP) */
314 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
315 /* SATA Controller IDE (Lynx Point-LP) */
316 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
317 /* SATA Controller IDE (Lynx Point-LP) */
318 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
319 /* SATA Controller IDE (DH89xxCC) */
320 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
321 /* SATA Controller IDE (Avoton) */
322 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
323 /* SATA Controller IDE (Avoton) */
324 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
325 /* SATA Controller IDE (Avoton) */
326 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
327 /* SATA Controller IDE (Avoton) */
328 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
329 /* SATA Controller IDE (Wellsburg) */
330 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
331 /* SATA Controller IDE (Wellsburg) */
332 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
333 /* SATA Controller IDE (Wellsburg) */
334 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
335 /* SATA Controller IDE (Wellsburg) */
336 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
337
338 { } /* terminate list */
339 };
340
341 static const struct piix_map_db ich5_map_db = {
342 .mask = 0x7,
343 .port_enable = 0x3,
344 .map = {
345 /* PM PS SM SS MAP */
346 { P0, NA, P1, NA }, /* 000b */
347 { P1, NA, P0, NA }, /* 001b */
348 { RV, RV, RV, RV },
349 { RV, RV, RV, RV },
350 { P0, P1, IDE, IDE }, /* 100b */
351 { P1, P0, IDE, IDE }, /* 101b */
352 { IDE, IDE, P0, P1 }, /* 110b */
353 { IDE, IDE, P1, P0 }, /* 111b */
354 },
355 };
356
357 static const struct piix_map_db ich6_map_db = {
358 .mask = 0x3,
359 .port_enable = 0xf,
360 .map = {
361 /* PM PS SM SS MAP */
362 { P0, P2, P1, P3 }, /* 00b */
363 { IDE, IDE, P1, P3 }, /* 01b */
364 { P0, P2, IDE, IDE }, /* 10b */
365 { RV, RV, RV, RV },
366 },
367 };
368
369 static const struct piix_map_db ich6m_map_db = {
370 .mask = 0x3,
371 .port_enable = 0x5,
372
373 /* Map 01b isn't specified in the doc but some notebooks use
374 * it anyway. MAP 01b have been spotted on both ICH6M and
375 * ICH7M.
376 */
377 .map = {
378 /* PM PS SM SS MAP */
379 { P0, P2, NA, NA }, /* 00b */
380 { IDE, IDE, P1, P3 }, /* 01b */
381 { P0, P2, IDE, IDE }, /* 10b */
382 { RV, RV, RV, RV },
383 },
384 };
385
386 static const struct piix_map_db ich8_map_db = {
387 .mask = 0x3,
388 .port_enable = 0xf,
389 .map = {
390 /* PM PS SM SS MAP */
391 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
392 { RV, RV, RV, RV },
393 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
394 { RV, RV, RV, RV },
395 },
396 };
397
398 static const struct piix_map_db ich8_2port_map_db = {
399 .mask = 0x3,
400 .port_enable = 0x3,
401 .map = {
402 /* PM PS SM SS MAP */
403 { P0, NA, P1, NA }, /* 00b */
404 { RV, RV, RV, RV }, /* 01b */
405 { RV, RV, RV, RV }, /* 10b */
406 { RV, RV, RV, RV },
407 },
408 };
409
410 static const struct piix_map_db ich8m_apple_map_db = {
411 .mask = 0x3,
412 .port_enable = 0x1,
413 .map = {
414 /* PM PS SM SS MAP */
415 { P0, NA, NA, NA }, /* 00b */
416 { RV, RV, RV, RV },
417 { P0, P2, IDE, IDE }, /* 10b */
418 { RV, RV, RV, RV },
419 },
420 };
421
422 static const struct piix_map_db tolapai_map_db = {
423 .mask = 0x3,
424 .port_enable = 0x3,
425 .map = {
426 /* PM PS SM SS MAP */
427 { P0, NA, P1, NA }, /* 00b */
428 { RV, RV, RV, RV }, /* 01b */
429 { RV, RV, RV, RV }, /* 10b */
430 { RV, RV, RV, RV },
431 },
432 };
433
434 static const struct piix_map_db *piix_map_db_table[] = {
435 [ich5_sata] = &ich5_map_db,
436 [ich6_sata] = &ich6_map_db,
437 [ich6m_sata] = &ich6m_map_db,
438 [ich8_sata] = &ich8_map_db,
439 [ich8_2port_sata] = &ich8_2port_map_db,
440 [ich8m_apple_sata] = &ich8m_apple_map_db,
441 [tolapai_sata] = &tolapai_map_db,
442 [ich8_sata_snb] = &ich8_map_db,
443 [ich8_2port_sata_snb] = &ich8_2port_map_db,
444 };
445
446 static struct pci_bits piix_enable_bits[] = {
447 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
448 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
449 };
450
451 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
452 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
453 MODULE_LICENSE("GPL");
454 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
455 MODULE_VERSION(DRV_VERSION);
456
457 struct ich_laptop {
458 u16 device;
459 u16 subvendor;
460 u16 subdevice;
461 };
462
463 /*
464 * List of laptops that use short cables rather than 80 wire
465 */
466
467 static const struct ich_laptop ich_laptop[] = {
468 /* devid, subvendor, subdev */
469 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
470 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
471 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
472 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
473 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
474 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
475 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
476 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
477 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
478 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
479 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
480 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
481 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
482 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
483 /* end marker */
484 { 0, }
485 };
486
487 static int piix_port_start(struct ata_port *ap)
488 {
489 if (!(ap->flags & PIIX_FLAG_PIO16))
490 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
491
492 return ata_bmdma_port_start(ap);
493 }
494
495 /**
496 * ich_pata_cable_detect - Probe host controller cable detect info
497 * @ap: Port for which cable detect info is desired
498 *
499 * Read 80c cable indicator from ATA PCI device's PCI config
500 * register. This register is normally set by firmware (BIOS).
501 *
502 * LOCKING:
503 * None (inherited from caller).
504 */
505
506 static int ich_pata_cable_detect(struct ata_port *ap)
507 {
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
509 struct piix_host_priv *hpriv = ap->host->private_data;
510 const struct ich_laptop *lap = &ich_laptop[0];
511 u8 mask;
512
513 /* Check for specials - Acer Aspire 5602WLMi */
514 while (lap->device) {
515 if (lap->device == pdev->device &&
516 lap->subvendor == pdev->subsystem_vendor &&
517 lap->subdevice == pdev->subsystem_device)
518 return ATA_CBL_PATA40_SHORT;
519
520 lap++;
521 }
522
523 /* check BIOS cable detect results */
524 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
525 if ((hpriv->saved_iocfg & mask) == 0)
526 return ATA_CBL_PATA40;
527 return ATA_CBL_PATA80;
528 }
529
530 /**
531 * piix_pata_prereset - prereset for PATA host controller
532 * @link: Target link
533 * @deadline: deadline jiffies for the operation
534 *
535 * LOCKING:
536 * None (inherited from caller).
537 */
538 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
539 {
540 struct ata_port *ap = link->ap;
541 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
542
543 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
544 return -ENOENT;
545 return ata_sff_prereset(link, deadline);
546 }
547
548 static DEFINE_SPINLOCK(piix_lock);
549
550 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
551 u8 pio)
552 {
553 struct pci_dev *dev = to_pci_dev(ap->host->dev);
554 unsigned long flags;
555 unsigned int is_slave = (adev->devno != 0);
556 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
557 unsigned int slave_port = 0x44;
558 u16 master_data;
559 u8 slave_data;
560 u8 udma_enable;
561 int control = 0;
562
563 /*
564 * See Intel Document 298600-004 for the timing programing rules
565 * for ICH controllers.
566 */
567
568 static const /* ISP RTC */
569 u8 timings[][2] = { { 0, 0 },
570 { 0, 0 },
571 { 1, 0 },
572 { 2, 1 },
573 { 2, 3 }, };
574
575 if (pio >= 2)
576 control |= 1; /* TIME1 enable */
577 if (ata_pio_need_iordy(adev))
578 control |= 2; /* IE enable */
579 /* Intel specifies that the PPE functionality is for disk only */
580 if (adev->class == ATA_DEV_ATA)
581 control |= 4; /* PPE enable */
582 /*
583 * If the drive MWDMA is faster than it can do PIO then
584 * we must force PIO into PIO0
585 */
586 if (adev->pio_mode < XFER_PIO_0 + pio)
587 /* Enable DMA timing only */
588 control |= 8; /* PIO cycles in PIO0 */
589
590 spin_lock_irqsave(&piix_lock, flags);
591
592 /* PIO configuration clears DTE unconditionally. It will be
593 * programmed in set_dmamode which is guaranteed to be called
594 * after set_piomode if any DMA mode is available.
595 */
596 pci_read_config_word(dev, master_port, &master_data);
597 if (is_slave) {
598 /* clear TIME1|IE1|PPE1|DTE1 */
599 master_data &= 0xff0f;
600 /* enable PPE1, IE1 and TIME1 as needed */
601 master_data |= (control << 4);
602 pci_read_config_byte(dev, slave_port, &slave_data);
603 slave_data &= (ap->port_no ? 0x0f : 0xf0);
604 /* Load the timing nibble for this slave */
605 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
606 << (ap->port_no ? 4 : 0);
607 } else {
608 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
609 master_data &= 0xccf0;
610 /* Enable PPE, IE and TIME as appropriate */
611 master_data |= control;
612 /* load ISP and RCT */
613 master_data |=
614 (timings[pio][0] << 12) |
615 (timings[pio][1] << 8);
616 }
617
618 /* Enable SITRE (separate slave timing register) */
619 master_data |= 0x4000;
620 pci_write_config_word(dev, master_port, master_data);
621 if (is_slave)
622 pci_write_config_byte(dev, slave_port, slave_data);
623
624 /* Ensure the UDMA bit is off - it will be turned back on if
625 UDMA is selected */
626
627 if (ap->udma_mask) {
628 pci_read_config_byte(dev, 0x48, &udma_enable);
629 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
630 pci_write_config_byte(dev, 0x48, udma_enable);
631 }
632
633 spin_unlock_irqrestore(&piix_lock, flags);
634 }
635
636 /**
637 * piix_set_piomode - Initialize host controller PATA PIO timings
638 * @ap: Port whose timings we are configuring
639 * @adev: Drive in question
640 *
641 * Set PIO mode for device, in host controller PCI config space.
642 *
643 * LOCKING:
644 * None (inherited from caller).
645 */
646
647 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
648 {
649 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
650 }
651
652 /**
653 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
654 * @ap: Port whose timings we are configuring
655 * @adev: Drive in question
656 * @isich: set if the chip is an ICH device
657 *
658 * Set UDMA mode for device, in host controller PCI config space.
659 *
660 * LOCKING:
661 * None (inherited from caller).
662 */
663
664 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
665 {
666 struct pci_dev *dev = to_pci_dev(ap->host->dev);
667 unsigned long flags;
668 u8 speed = adev->dma_mode;
669 int devid = adev->devno + 2 * ap->port_no;
670 u8 udma_enable = 0;
671
672 if (speed >= XFER_UDMA_0) {
673 unsigned int udma = speed - XFER_UDMA_0;
674 u16 udma_timing;
675 u16 ideconf;
676 int u_clock, u_speed;
677
678 spin_lock_irqsave(&piix_lock, flags);
679
680 pci_read_config_byte(dev, 0x48, &udma_enable);
681
682 /*
683 * UDMA is handled by a combination of clock switching and
684 * selection of dividers
685 *
686 * Handy rule: Odd modes are UDMATIMx 01, even are 02
687 * except UDMA0 which is 00
688 */
689 u_speed = min(2 - (udma & 1), udma);
690 if (udma == 5)
691 u_clock = 0x1000; /* 100Mhz */
692 else if (udma > 2)
693 u_clock = 1; /* 66Mhz */
694 else
695 u_clock = 0; /* 33Mhz */
696
697 udma_enable |= (1 << devid);
698
699 /* Load the CT/RP selection */
700 pci_read_config_word(dev, 0x4A, &udma_timing);
701 udma_timing &= ~(3 << (4 * devid));
702 udma_timing |= u_speed << (4 * devid);
703 pci_write_config_word(dev, 0x4A, udma_timing);
704
705 if (isich) {
706 /* Select a 33/66/100Mhz clock */
707 pci_read_config_word(dev, 0x54, &ideconf);
708 ideconf &= ~(0x1001 << devid);
709 ideconf |= u_clock << devid;
710 /* For ICH or later we should set bit 10 for better
711 performance (WR_PingPong_En) */
712 pci_write_config_word(dev, 0x54, ideconf);
713 }
714
715 pci_write_config_byte(dev, 0x48, udma_enable);
716
717 spin_unlock_irqrestore(&piix_lock, flags);
718 } else {
719 /* MWDMA is driven by the PIO timings. */
720 unsigned int mwdma = speed - XFER_MW_DMA_0;
721 const unsigned int needed_pio[3] = {
722 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
723 };
724 int pio = needed_pio[mwdma] - XFER_PIO_0;
725
726 /* XFER_PIO_0 is never used currently */
727 piix_set_timings(ap, adev, pio);
728 }
729 }
730
731 /**
732 * piix_set_dmamode - Initialize host controller PATA DMA timings
733 * @ap: Port whose timings we are configuring
734 * @adev: um
735 *
736 * Set MW/UDMA mode for device, in host controller PCI config space.
737 *
738 * LOCKING:
739 * None (inherited from caller).
740 */
741
742 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
743 {
744 do_pata_set_dmamode(ap, adev, 0);
745 }
746
747 /**
748 * ich_set_dmamode - Initialize host controller PATA DMA timings
749 * @ap: Port whose timings we are configuring
750 * @adev: um
751 *
752 * Set MW/UDMA mode for device, in host controller PCI config space.
753 *
754 * LOCKING:
755 * None (inherited from caller).
756 */
757
758 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
759 {
760 do_pata_set_dmamode(ap, adev, 1);
761 }
762
763 /*
764 * Serial ATA Index/Data Pair Superset Registers access
765 *
766 * Beginning from ICH8, there's a sane way to access SCRs using index
767 * and data register pair located at BAR5 which means that we have
768 * separate SCRs for master and slave. This is handled using libata
769 * slave_link facility.
770 */
771 static const int piix_sidx_map[] = {
772 [SCR_STATUS] = 0,
773 [SCR_ERROR] = 2,
774 [SCR_CONTROL] = 1,
775 };
776
777 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
778 {
779 struct ata_port *ap = link->ap;
780 struct piix_host_priv *hpriv = ap->host->private_data;
781
782 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
783 hpriv->sidpr + PIIX_SIDPR_IDX);
784 }
785
786 static int piix_sidpr_scr_read(struct ata_link *link,
787 unsigned int reg, u32 *val)
788 {
789 struct piix_host_priv *hpriv = link->ap->host->private_data;
790
791 if (reg >= ARRAY_SIZE(piix_sidx_map))
792 return -EINVAL;
793
794 piix_sidpr_sel(link, reg);
795 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
796 return 0;
797 }
798
799 static int piix_sidpr_scr_write(struct ata_link *link,
800 unsigned int reg, u32 val)
801 {
802 struct piix_host_priv *hpriv = link->ap->host->private_data;
803
804 if (reg >= ARRAY_SIZE(piix_sidx_map))
805 return -EINVAL;
806
807 piix_sidpr_sel(link, reg);
808 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
809 return 0;
810 }
811
812 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
813 unsigned hints)
814 {
815 return sata_link_scr_lpm(link, policy, false);
816 }
817
818 static bool piix_irq_check(struct ata_port *ap)
819 {
820 if (unlikely(!ap->ioaddr.bmdma_addr))
821 return false;
822
823 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
824 }
825
826 #ifdef CONFIG_PM
827 static int piix_broken_suspend(void)
828 {
829 static const struct dmi_system_id sysids[] = {
830 {
831 .ident = "TECRA M3",
832 .matches = {
833 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
834 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
835 },
836 },
837 {
838 .ident = "TECRA M3",
839 .matches = {
840 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
841 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
842 },
843 },
844 {
845 .ident = "TECRA M4",
846 .matches = {
847 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
848 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
849 },
850 },
851 {
852 .ident = "TECRA M4",
853 .matches = {
854 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
855 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
856 },
857 },
858 {
859 .ident = "TECRA M5",
860 .matches = {
861 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
862 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
863 },
864 },
865 {
866 .ident = "TECRA M6",
867 .matches = {
868 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
869 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
870 },
871 },
872 {
873 .ident = "TECRA M7",
874 .matches = {
875 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
876 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
877 },
878 },
879 {
880 .ident = "TECRA A8",
881 .matches = {
882 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
883 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
884 },
885 },
886 {
887 .ident = "Satellite R20",
888 .matches = {
889 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
890 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
891 },
892 },
893 {
894 .ident = "Satellite R25",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
897 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
898 },
899 },
900 {
901 .ident = "Satellite U200",
902 .matches = {
903 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
904 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
905 },
906 },
907 {
908 .ident = "Satellite U200",
909 .matches = {
910 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
911 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
912 },
913 },
914 {
915 .ident = "Satellite Pro U200",
916 .matches = {
917 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
918 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
919 },
920 },
921 {
922 .ident = "Satellite U205",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
925 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
926 },
927 },
928 {
929 .ident = "SATELLITE U205",
930 .matches = {
931 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
932 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
933 },
934 },
935 {
936 .ident = "Satellite Pro A120",
937 .matches = {
938 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
939 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
940 },
941 },
942 {
943 .ident = "Portege M500",
944 .matches = {
945 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
946 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
947 },
948 },
949 {
950 .ident = "VGN-BX297XP",
951 .matches = {
952 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
953 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
954 },
955 },
956
957 { } /* terminate list */
958 };
959 static const char *oemstrs[] = {
960 "Tecra M3,",
961 };
962 int i;
963
964 if (dmi_check_system(sysids))
965 return 1;
966
967 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
968 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
969 return 1;
970
971 /* TECRA M4 sometimes forgets its identify and reports bogus
972 * DMI information. As the bogus information is a bit
973 * generic, match as many entries as possible. This manual
974 * matching is necessary because dmi_system_id.matches is
975 * limited to four entries.
976 */
977 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
978 dmi_match(DMI_PRODUCT_NAME, "000000") &&
979 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
980 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
981 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
982 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
983 dmi_match(DMI_BOARD_VERSION, "Version A0"))
984 return 1;
985
986 return 0;
987 }
988
989 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
990 {
991 struct ata_host *host = dev_get_drvdata(&pdev->dev);
992 unsigned long flags;
993 int rc = 0;
994
995 rc = ata_host_suspend(host, mesg);
996 if (rc)
997 return rc;
998
999 /* Some braindamaged ACPI suspend implementations expect the
1000 * controller to be awake on entry; otherwise, it burns cpu
1001 * cycles and power trying to do something to the sleeping
1002 * beauty.
1003 */
1004 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1005 pci_save_state(pdev);
1006
1007 /* mark its power state as "unknown", since we don't
1008 * know if e.g. the BIOS will change its device state
1009 * when we suspend.
1010 */
1011 if (pdev->current_state == PCI_D0)
1012 pdev->current_state = PCI_UNKNOWN;
1013
1014 /* tell resume that it's waking up from broken suspend */
1015 spin_lock_irqsave(&host->lock, flags);
1016 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1017 spin_unlock_irqrestore(&host->lock, flags);
1018 } else
1019 ata_pci_device_do_suspend(pdev, mesg);
1020
1021 return 0;
1022 }
1023
1024 static int piix_pci_device_resume(struct pci_dev *pdev)
1025 {
1026 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1027 unsigned long flags;
1028 int rc;
1029
1030 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1031 spin_lock_irqsave(&host->lock, flags);
1032 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1033 spin_unlock_irqrestore(&host->lock, flags);
1034
1035 pci_set_power_state(pdev, PCI_D0);
1036 pci_restore_state(pdev);
1037
1038 /* PCI device wasn't disabled during suspend. Use
1039 * pci_reenable_device() to avoid affecting the enable
1040 * count.
1041 */
1042 rc = pci_reenable_device(pdev);
1043 if (rc)
1044 dev_err(&pdev->dev,
1045 "failed to enable device after resume (%d)\n",
1046 rc);
1047 } else
1048 rc = ata_pci_device_do_resume(pdev);
1049
1050 if (rc == 0)
1051 ata_host_resume(host);
1052
1053 return rc;
1054 }
1055 #endif
1056
1057 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1058 {
1059 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1060 }
1061
1062 static struct scsi_host_template piix_sht = {
1063 ATA_BMDMA_SHT(DRV_NAME),
1064 };
1065
1066 static struct ata_port_operations piix_sata_ops = {
1067 .inherits = &ata_bmdma32_port_ops,
1068 .sff_irq_check = piix_irq_check,
1069 .port_start = piix_port_start,
1070 };
1071
1072 static struct ata_port_operations piix_pata_ops = {
1073 .inherits = &piix_sata_ops,
1074 .cable_detect = ata_cable_40wire,
1075 .set_piomode = piix_set_piomode,
1076 .set_dmamode = piix_set_dmamode,
1077 .prereset = piix_pata_prereset,
1078 };
1079
1080 static struct ata_port_operations piix_vmw_ops = {
1081 .inherits = &piix_pata_ops,
1082 .bmdma_status = piix_vmw_bmdma_status,
1083 };
1084
1085 static struct ata_port_operations ich_pata_ops = {
1086 .inherits = &piix_pata_ops,
1087 .cable_detect = ich_pata_cable_detect,
1088 .set_dmamode = ich_set_dmamode,
1089 };
1090
1091 static struct device_attribute *piix_sidpr_shost_attrs[] = {
1092 &dev_attr_link_power_management_policy,
1093 NULL
1094 };
1095
1096 static struct scsi_host_template piix_sidpr_sht = {
1097 ATA_BMDMA_SHT(DRV_NAME),
1098 .shost_attrs = piix_sidpr_shost_attrs,
1099 };
1100
1101 static struct ata_port_operations piix_sidpr_sata_ops = {
1102 .inherits = &piix_sata_ops,
1103 .hardreset = sata_std_hardreset,
1104 .scr_read = piix_sidpr_scr_read,
1105 .scr_write = piix_sidpr_scr_write,
1106 .set_lpm = piix_sidpr_set_lpm,
1107 };
1108
1109 static struct ata_port_info piix_port_info[] = {
1110 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
1111 {
1112 .flags = PIIX_PATA_FLAGS,
1113 .pio_mask = ATA_PIO4,
1114 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1115 .port_ops = &piix_pata_ops,
1116 },
1117
1118 [piix_pata_33] = /* PIIX4 at 33MHz */
1119 {
1120 .flags = PIIX_PATA_FLAGS,
1121 .pio_mask = ATA_PIO4,
1122 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1123 .udma_mask = ATA_UDMA2,
1124 .port_ops = &piix_pata_ops,
1125 },
1126
1127 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1128 {
1129 .flags = PIIX_PATA_FLAGS,
1130 .pio_mask = ATA_PIO4,
1131 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
1132 .udma_mask = ATA_UDMA2,
1133 .port_ops = &ich_pata_ops,
1134 },
1135
1136 [ich_pata_66] = /* ICH controllers up to 66MHz */
1137 {
1138 .flags = PIIX_PATA_FLAGS,
1139 .pio_mask = ATA_PIO4,
1140 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1141 .udma_mask = ATA_UDMA4,
1142 .port_ops = &ich_pata_ops,
1143 },
1144
1145 [ich_pata_100] =
1146 {
1147 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1148 .pio_mask = ATA_PIO4,
1149 .mwdma_mask = ATA_MWDMA12_ONLY,
1150 .udma_mask = ATA_UDMA5,
1151 .port_ops = &ich_pata_ops,
1152 },
1153
1154 [ich_pata_100_nomwdma1] =
1155 {
1156 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1157 .pio_mask = ATA_PIO4,
1158 .mwdma_mask = ATA_MWDMA2_ONLY,
1159 .udma_mask = ATA_UDMA5,
1160 .port_ops = &ich_pata_ops,
1161 },
1162
1163 [ich5_sata] =
1164 {
1165 .flags = PIIX_SATA_FLAGS,
1166 .pio_mask = ATA_PIO4,
1167 .mwdma_mask = ATA_MWDMA2,
1168 .udma_mask = ATA_UDMA6,
1169 .port_ops = &piix_sata_ops,
1170 },
1171
1172 [ich6_sata] =
1173 {
1174 .flags = PIIX_SATA_FLAGS,
1175 .pio_mask = ATA_PIO4,
1176 .mwdma_mask = ATA_MWDMA2,
1177 .udma_mask = ATA_UDMA6,
1178 .port_ops = &piix_sata_ops,
1179 },
1180
1181 [ich6m_sata] =
1182 {
1183 .flags = PIIX_SATA_FLAGS,
1184 .pio_mask = ATA_PIO4,
1185 .mwdma_mask = ATA_MWDMA2,
1186 .udma_mask = ATA_UDMA6,
1187 .port_ops = &piix_sata_ops,
1188 },
1189
1190 [ich8_sata] =
1191 {
1192 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1193 .pio_mask = ATA_PIO4,
1194 .mwdma_mask = ATA_MWDMA2,
1195 .udma_mask = ATA_UDMA6,
1196 .port_ops = &piix_sata_ops,
1197 },
1198
1199 [ich8_2port_sata] =
1200 {
1201 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1202 .pio_mask = ATA_PIO4,
1203 .mwdma_mask = ATA_MWDMA2,
1204 .udma_mask = ATA_UDMA6,
1205 .port_ops = &piix_sata_ops,
1206 },
1207
1208 [tolapai_sata] =
1209 {
1210 .flags = PIIX_SATA_FLAGS,
1211 .pio_mask = ATA_PIO4,
1212 .mwdma_mask = ATA_MWDMA2,
1213 .udma_mask = ATA_UDMA6,
1214 .port_ops = &piix_sata_ops,
1215 },
1216
1217 [ich8m_apple_sata] =
1218 {
1219 .flags = PIIX_SATA_FLAGS,
1220 .pio_mask = ATA_PIO4,
1221 .mwdma_mask = ATA_MWDMA2,
1222 .udma_mask = ATA_UDMA6,
1223 .port_ops = &piix_sata_ops,
1224 },
1225
1226 [piix_pata_vmw] =
1227 {
1228 .flags = PIIX_PATA_FLAGS,
1229 .pio_mask = ATA_PIO4,
1230 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1231 .udma_mask = ATA_UDMA2,
1232 .port_ops = &piix_vmw_ops,
1233 },
1234
1235 /*
1236 * some Sandybridge chipsets have broken 32 mode up to now,
1237 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1238 */
1239 [ich8_sata_snb] =
1240 {
1241 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1242 .pio_mask = ATA_PIO4,
1243 .mwdma_mask = ATA_MWDMA2,
1244 .udma_mask = ATA_UDMA6,
1245 .port_ops = &piix_sata_ops,
1246 },
1247
1248 [ich8_2port_sata_snb] =
1249 {
1250 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1251 | PIIX_FLAG_PIO16,
1252 .pio_mask = ATA_PIO4,
1253 .mwdma_mask = ATA_MWDMA2,
1254 .udma_mask = ATA_UDMA6,
1255 .port_ops = &piix_sata_ops,
1256 },
1257 };
1258
1259 #define AHCI_PCI_BAR 5
1260 #define AHCI_GLOBAL_CTL 0x04
1261 #define AHCI_ENABLE (1 << 31)
1262 static int piix_disable_ahci(struct pci_dev *pdev)
1263 {
1264 void __iomem *mmio;
1265 u32 tmp;
1266 int rc = 0;
1267
1268 /* BUG: pci_enable_device has not yet been called. This
1269 * works because this device is usually set up by BIOS.
1270 */
1271
1272 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1273 !pci_resource_len(pdev, AHCI_PCI_BAR))
1274 return 0;
1275
1276 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1277 if (!mmio)
1278 return -ENOMEM;
1279
1280 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1281 if (tmp & AHCI_ENABLE) {
1282 tmp &= ~AHCI_ENABLE;
1283 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1284
1285 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1286 if (tmp & AHCI_ENABLE)
1287 rc = -EIO;
1288 }
1289
1290 pci_iounmap(pdev, mmio);
1291 return rc;
1292 }
1293
1294 /**
1295 * piix_check_450nx_errata - Check for problem 450NX setup
1296 * @ata_dev: the PCI device to check
1297 *
1298 * Check for the present of 450NX errata #19 and errata #25. If
1299 * they are found return an error code so we can turn off DMA
1300 */
1301
1302 static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1303 {
1304 struct pci_dev *pdev = NULL;
1305 u16 cfg;
1306 int no_piix_dma = 0;
1307
1308 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1309 /* Look for 450NX PXB. Check for problem configurations
1310 A PCI quirk checks bit 6 already */
1311 pci_read_config_word(pdev, 0x41, &cfg);
1312 /* Only on the original revision: IDE DMA can hang */
1313 if (pdev->revision == 0x00)
1314 no_piix_dma = 1;
1315 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1316 else if (cfg & (1<<14) && pdev->revision < 5)
1317 no_piix_dma = 2;
1318 }
1319 if (no_piix_dma)
1320 dev_warn(&ata_dev->dev,
1321 "450NX errata present, disabling IDE DMA%s\n",
1322 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1323 : "");
1324
1325 return no_piix_dma;
1326 }
1327
1328 static void piix_init_pcs(struct ata_host *host,
1329 const struct piix_map_db *map_db)
1330 {
1331 struct pci_dev *pdev = to_pci_dev(host->dev);
1332 u16 pcs, new_pcs;
1333
1334 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1335
1336 new_pcs = pcs | map_db->port_enable;
1337
1338 if (new_pcs != pcs) {
1339 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1340 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1341 msleep(150);
1342 }
1343 }
1344
1345 static const int *piix_init_sata_map(struct pci_dev *pdev,
1346 struct ata_port_info *pinfo,
1347 const struct piix_map_db *map_db)
1348 {
1349 const int *map;
1350 int i, invalid_map = 0;
1351 u8 map_value;
1352
1353 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1354
1355 map = map_db->map[map_value & map_db->mask];
1356
1357 dev_info(&pdev->dev, "MAP [");
1358 for (i = 0; i < 4; i++) {
1359 switch (map[i]) {
1360 case RV:
1361 invalid_map = 1;
1362 pr_cont(" XX");
1363 break;
1364
1365 case NA:
1366 pr_cont(" --");
1367 break;
1368
1369 case IDE:
1370 WARN_ON((i & 1) || map[i + 1] != IDE);
1371 pinfo[i / 2] = piix_port_info[ich_pata_100];
1372 i++;
1373 pr_cont(" IDE IDE");
1374 break;
1375
1376 default:
1377 pr_cont(" P%d", map[i]);
1378 if (i & 1)
1379 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1380 break;
1381 }
1382 }
1383 pr_cont(" ]\n");
1384
1385 if (invalid_map)
1386 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1387
1388 return map;
1389 }
1390
1391 static bool piix_no_sidpr(struct ata_host *host)
1392 {
1393 struct pci_dev *pdev = to_pci_dev(host->dev);
1394
1395 /*
1396 * Samsung DB-P70 only has three ATA ports exposed and
1397 * curiously the unconnected first port reports link online
1398 * while not responding to SRST protocol causing excessive
1399 * detection delay.
1400 *
1401 * Unfortunately, the system doesn't carry enough DMI
1402 * information to identify the machine but does have subsystem
1403 * vendor and device set. As it's unclear whether the
1404 * subsystem vendor/device is used only for this specific
1405 * board, the port can't be disabled solely with the
1406 * information; however, turning off SIDPR access works around
1407 * the problem. Turn it off.
1408 *
1409 * This problem is reported in bnc#441240.
1410 *
1411 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1412 */
1413 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1414 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1415 pdev->subsystem_device == 0xb049) {
1416 dev_warn(host->dev,
1417 "Samsung DB-P70 detected, disabling SIDPR\n");
1418 return true;
1419 }
1420
1421 return false;
1422 }
1423
1424 static int piix_init_sidpr(struct ata_host *host)
1425 {
1426 struct pci_dev *pdev = to_pci_dev(host->dev);
1427 struct piix_host_priv *hpriv = host->private_data;
1428 struct ata_link *link0 = &host->ports[0]->link;
1429 u32 scontrol;
1430 int i, rc;
1431
1432 /* check for availability */
1433 for (i = 0; i < 4; i++)
1434 if (hpriv->map[i] == IDE)
1435 return 0;
1436
1437 /* is it blacklisted? */
1438 if (piix_no_sidpr(host))
1439 return 0;
1440
1441 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1442 return 0;
1443
1444 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1445 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1446 return 0;
1447
1448 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1449 return 0;
1450
1451 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1452
1453 /* SCR access via SIDPR doesn't work on some configurations.
1454 * Give it a test drive by inhibiting power save modes which
1455 * we'll do anyway.
1456 */
1457 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1458
1459 /* if IPM is already 3, SCR access is probably working. Don't
1460 * un-inhibit power save modes as BIOS might have inhibited
1461 * them for a reason.
1462 */
1463 if ((scontrol & 0xf00) != 0x300) {
1464 scontrol |= 0x300;
1465 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1466 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1467
1468 if ((scontrol & 0xf00) != 0x300) {
1469 dev_info(host->dev,
1470 "SCR access via SIDPR is available but doesn't work\n");
1471 return 0;
1472 }
1473 }
1474
1475 /* okay, SCRs available, set ops and ask libata for slave_link */
1476 for (i = 0; i < 2; i++) {
1477 struct ata_port *ap = host->ports[i];
1478
1479 ap->ops = &piix_sidpr_sata_ops;
1480
1481 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1482 rc = ata_slave_link_init(ap);
1483 if (rc)
1484 return rc;
1485 }
1486 }
1487
1488 return 0;
1489 }
1490
1491 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1492 {
1493 static const struct dmi_system_id sysids[] = {
1494 {
1495 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1496 * isn't used to boot the system which
1497 * disables the channel.
1498 */
1499 .ident = "M570U",
1500 .matches = {
1501 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1502 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1503 },
1504 },
1505
1506 { } /* terminate list */
1507 };
1508 struct pci_dev *pdev = to_pci_dev(host->dev);
1509 struct piix_host_priv *hpriv = host->private_data;
1510
1511 if (!dmi_check_system(sysids))
1512 return;
1513
1514 /* The datasheet says that bit 18 is NOOP but certain systems
1515 * seem to use it to disable a channel. Clear the bit on the
1516 * affected systems.
1517 */
1518 if (hpriv->saved_iocfg & (1 << 18)) {
1519 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1520 pci_write_config_dword(pdev, PIIX_IOCFG,
1521 hpriv->saved_iocfg & ~(1 << 18));
1522 }
1523 }
1524
1525 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1526 {
1527 static const struct dmi_system_id broken_systems[] = {
1528 {
1529 .ident = "HP Compaq 2510p",
1530 .matches = {
1531 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1532 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1533 },
1534 /* PCI slot number of the controller */
1535 .driver_data = (void *)0x1FUL,
1536 },
1537 {
1538 .ident = "HP Compaq nc6000",
1539 .matches = {
1540 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1541 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1542 },
1543 /* PCI slot number of the controller */
1544 .driver_data = (void *)0x1FUL,
1545 },
1546
1547 { } /* terminate list */
1548 };
1549 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1550
1551 if (dmi) {
1552 unsigned long slot = (unsigned long)dmi->driver_data;
1553 /* apply the quirk only to on-board controllers */
1554 return slot == PCI_SLOT(pdev->devfn);
1555 }
1556
1557 return false;
1558 }
1559
1560 static int prefer_ms_hyperv = 1;
1561 module_param(prefer_ms_hyperv, int, 0);
1562 MODULE_PARM_DESC(prefer_ms_hyperv,
1563 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1564 "0 - Use ATA drivers, "
1565 "1 (Default) - Use the paravirtualization drivers.");
1566
1567 static void piix_ignore_devices_quirk(struct ata_host *host)
1568 {
1569 #if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1570 static const struct dmi_system_id ignore_hyperv[] = {
1571 {
1572 /* On Hyper-V hypervisors the disks are exposed on
1573 * both the emulated SATA controller and on the
1574 * paravirtualised drivers. The CD/DVD devices
1575 * are only exposed on the emulated controller.
1576 * Request we ignore ATA devices on this host.
1577 */
1578 .ident = "Hyper-V Virtual Machine",
1579 .matches = {
1580 DMI_MATCH(DMI_SYS_VENDOR,
1581 "Microsoft Corporation"),
1582 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1583 },
1584 },
1585 { } /* terminate list */
1586 };
1587 static const struct dmi_system_id allow_virtual_pc[] = {
1588 {
1589 /* In MS Virtual PC guests the DMI ident is nearly
1590 * identical to a Hyper-V guest. One difference is the
1591 * product version which is used here to identify
1592 * a Virtual PC guest. This entry allows ata_piix to
1593 * drive the emulated hardware.
1594 */
1595 .ident = "MS Virtual PC 2007",
1596 .matches = {
1597 DMI_MATCH(DMI_SYS_VENDOR,
1598 "Microsoft Corporation"),
1599 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1600 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1601 },
1602 },
1603 { } /* terminate list */
1604 };
1605 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1606 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1607
1608 if (ignore && !allow && prefer_ms_hyperv) {
1609 host->flags |= ATA_HOST_IGNORE_ATA;
1610 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1611 ignore->ident);
1612 }
1613 #endif
1614 }
1615
1616 /**
1617 * piix_init_one - Register PIIX ATA PCI device with kernel services
1618 * @pdev: PCI device to register
1619 * @ent: Entry in piix_pci_tbl matching with @pdev
1620 *
1621 * Called from kernel PCI layer. We probe for combined mode (sigh),
1622 * and then hand over control to libata, for it to do the rest.
1623 *
1624 * LOCKING:
1625 * Inherited from PCI layer (may sleep).
1626 *
1627 * RETURNS:
1628 * Zero on success, or -ERRNO value.
1629 */
1630
1631 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1632 {
1633 struct device *dev = &pdev->dev;
1634 struct ata_port_info port_info[2];
1635 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1636 struct scsi_host_template *sht = &piix_sht;
1637 unsigned long port_flags;
1638 struct ata_host *host;
1639 struct piix_host_priv *hpriv;
1640 int rc;
1641
1642 ata_print_version_once(&pdev->dev, DRV_VERSION);
1643
1644 /* no hotplugging support for later devices (FIXME) */
1645 if (!in_module_init && ent->driver_data >= ich5_sata)
1646 return -ENODEV;
1647
1648 if (piix_broken_system_poweroff(pdev)) {
1649 piix_port_info[ent->driver_data].flags |=
1650 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1651 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1652 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1653 "on poweroff and hibernation\n");
1654 }
1655
1656 port_info[0] = piix_port_info[ent->driver_data];
1657 port_info[1] = piix_port_info[ent->driver_data];
1658
1659 port_flags = port_info[0].flags;
1660
1661 /* enable device and prepare host */
1662 rc = pcim_enable_device(pdev);
1663 if (rc)
1664 return rc;
1665
1666 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1667 if (!hpriv)
1668 return -ENOMEM;
1669
1670 /* Save IOCFG, this will be used for cable detection, quirk
1671 * detection and restoration on detach. This is necessary
1672 * because some ACPI implementations mess up cable related
1673 * bits on _STM. Reported on kernel bz#11879.
1674 */
1675 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1676
1677 /* ICH6R may be driven by either ata_piix or ahci driver
1678 * regardless of BIOS configuration. Make sure AHCI mode is
1679 * off.
1680 */
1681 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1682 rc = piix_disable_ahci(pdev);
1683 if (rc)
1684 return rc;
1685 }
1686
1687 /* SATA map init can change port_info, do it before prepping host */
1688 if (port_flags & ATA_FLAG_SATA)
1689 hpriv->map = piix_init_sata_map(pdev, port_info,
1690 piix_map_db_table[ent->driver_data]);
1691
1692 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1693 if (rc)
1694 return rc;
1695 host->private_data = hpriv;
1696
1697 /* initialize controller */
1698 if (port_flags & ATA_FLAG_SATA) {
1699 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1700 rc = piix_init_sidpr(host);
1701 if (rc)
1702 return rc;
1703 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1704 sht = &piix_sidpr_sht;
1705 }
1706
1707 /* apply IOCFG bit18 quirk */
1708 piix_iocfg_bit18_quirk(host);
1709
1710 /* On ICH5, some BIOSen disable the interrupt using the
1711 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1712 * On ICH6, this bit has the same effect, but only when
1713 * MSI is disabled (and it is disabled, as we don't use
1714 * message-signalled interrupts currently).
1715 */
1716 if (port_flags & PIIX_FLAG_CHECKINTR)
1717 pci_intx(pdev, 1);
1718
1719 if (piix_check_450nx_errata(pdev)) {
1720 /* This writes into the master table but it does not
1721 really matter for this errata as we will apply it to
1722 all the PIIX devices on the board */
1723 host->ports[0]->mwdma_mask = 0;
1724 host->ports[0]->udma_mask = 0;
1725 host->ports[1]->mwdma_mask = 0;
1726 host->ports[1]->udma_mask = 0;
1727 }
1728 host->flags |= ATA_HOST_PARALLEL_SCAN;
1729
1730 /* Allow hosts to specify device types to ignore when scanning. */
1731 piix_ignore_devices_quirk(host);
1732
1733 pci_set_master(pdev);
1734 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1735 }
1736
1737 static void piix_remove_one(struct pci_dev *pdev)
1738 {
1739 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1740 struct piix_host_priv *hpriv = host->private_data;
1741
1742 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1743
1744 ata_pci_remove_one(pdev);
1745 }
1746
1747 static struct pci_driver piix_pci_driver = {
1748 .name = DRV_NAME,
1749 .id_table = piix_pci_tbl,
1750 .probe = piix_init_one,
1751 .remove = piix_remove_one,
1752 #ifdef CONFIG_PM
1753 .suspend = piix_pci_device_suspend,
1754 .resume = piix_pci_device_resume,
1755 #endif
1756 };
1757
1758 static int __init piix_init(void)
1759 {
1760 int rc;
1761
1762 DPRINTK("pci_register_driver\n");
1763 rc = pci_register_driver(&piix_pci_driver);
1764 if (rc)
1765 return rc;
1766
1767 in_module_init = 0;
1768
1769 DPRINTK("done\n");
1770 return 0;
1771 }
1772
1773 static void __exit piix_exit(void)
1774 {
1775 pci_unregister_driver(&piix_pci_driver);
1776 }
1777
1778 module_init(piix_init);
1779 module_exit(piix_exit);
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