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be2net: support ethtool get-dump option
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
blob241819b36ca72ac6c133875f88d17f4359c0c5d4
1 /*
2 * Copyright (C) 2005 - 2015 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 /*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26 struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30 };
31
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35 struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45 };
46
47 #define CQE_FLAGS_VALID_MASK BIT(31)
48 #define CQE_FLAGS_ASYNC_MASK BIT(30)
49 #define CQE_FLAGS_COMPLETED_MASK BIT(28)
50 #define CQE_FLAGS_CONSUMED_MASK BIT(27)
51
52 /* Completion Status */
53 enum mcc_base_status {
54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
60 MCC_STATUS_NOT_SUPPORTED = 66,
61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68
62 };
63
64 /* Additional status */
65 enum mcc_addl_status {
66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
69 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab,
70 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56,
71 MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57
72 };
73
74 #define CQE_BASE_STATUS_MASK 0xFFFF
75 #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */
76 #define CQE_ADDL_STATUS_MASK 0xFF
77 #define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */
78
79 #define base_status(status) \
80 ((enum mcc_base_status) \
81 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0))
82 #define addl_status(status) \
83 ((enum mcc_addl_status) \
84 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \
85 CQE_ADDL_STATUS_MASK : 0))
86
87 struct be_mcc_compl {
88 u32 status; /* dword 0 */
89 u32 tag0; /* dword 1 */
90 u32 tag1; /* dword 2 */
91 u32 flags; /* dword 3 */
92 };
93
94 /* When the async bit of mcc_compl flags is set, flags
95 * is interpreted as follows:
96 */
97 #define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
98 #define ASYNC_EVENT_CODE_MASK 0xFF
99 #define ASYNC_EVENT_TYPE_SHIFT 16
100 #define ASYNC_EVENT_TYPE_MASK 0xFF
101 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
102 #define ASYNC_EVENT_CODE_GRP_5 0x5
103 #define ASYNC_EVENT_QOS_SPEED 0x1
104 #define ASYNC_EVENT_COS_PRIORITY 0x2
105 #define ASYNC_EVENT_PVID_STATE 0x3
106 #define ASYNC_EVENT_CODE_QNQ 0x6
107 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
108 #define ASYNC_EVENT_CODE_SLIPORT 0x11
109 #define ASYNC_EVENT_PORT_MISCONFIG 0x9
110 #define ASYNC_EVENT_FW_CONTROL 0x5
111
112 enum {
113 LINK_DOWN = 0x0,
114 LINK_UP = 0x1
115 };
116 #define LINK_STATUS_MASK 0x1
117 #define LOGICAL_LINK_STATUS_MASK 0x2
118
119 /* When the event code of compl->flags is link-state, the mcc_compl
120 * must be interpreted as follows
121 */
122 struct be_async_event_link_state {
123 u8 physical_port;
124 u8 port_link_status;
125 u8 port_duplex;
126 u8 port_speed;
127 u8 port_fault;
128 u8 rsvd0[7];
129 u32 flags;
130 } __packed;
131
132 /* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED
133 * the mcc_compl must be interpreted as follows
134 */
135 struct be_async_event_grp5_qos_link_speed {
136 u8 physical_port;
137 u8 rsvd[5];
138 u16 qos_link_speed;
139 u32 event_tag;
140 u32 flags;
141 } __packed;
142
143 /* When the event code of compl->flags is GRP5 and event type is
144 * CoS-Priority, the mcc_compl must be interpreted as follows
145 */
146 struct be_async_event_grp5_cos_priority {
147 u8 physical_port;
148 u8 available_priority_bmap;
149 u8 reco_default_priority;
150 u8 valid;
151 u8 rsvd0;
152 u8 event_tag;
153 u32 flags;
154 } __packed;
155
156 /* When the event code of compl->flags is GRP5 and event type is
157 * PVID state, the mcc_compl must be interpreted as follows
158 */
159 struct be_async_event_grp5_pvid_state {
160 u8 enabled;
161 u8 rsvd0;
162 u16 tag;
163 u32 event_tag;
164 u32 rsvd1;
165 u32 flags;
166 } __packed;
167
168 /* async event indicating outer VLAN tag in QnQ */
169 struct be_async_event_qnq {
170 u8 valid; /* Indicates if outer VLAN is valid */
171 u8 rsvd0;
172 u16 vlan_tag;
173 u32 event_tag;
174 u8 rsvd1[4];
175 u32 flags;
176 } __packed;
177
178 #define INCOMPATIBLE_SFP 0x3
179 /* async event indicating misconfigured port */
180 struct be_async_event_misconfig_port {
181 u32 event_data_word1;
182 u32 event_data_word2;
183 u32 rsvd0;
184 u32 flags;
185 } __packed;
186
187 #define BMC_FILT_BROADCAST_ARP BIT(0)
188 #define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1)
189 #define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2)
190 #define BMC_FILT_BROADCAST_NET_BIOS BIT(3)
191 #define BMC_FILT_BROADCAST BIT(7)
192 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8)
193 #define BMC_FILT_MULTICAST_IPV6_RA BIT(9)
194 #define BMC_FILT_MULTICAST_IPV6_RAS BIT(10)
195 #define BMC_FILT_MULTICAST BIT(15)
196 struct be_async_fw_control {
197 u32 event_data_word1;
198 u32 event_data_word2;
199 u32 evt_tag;
200 u32 event_data_word4;
201 } __packed;
202
203 struct be_mcc_mailbox {
204 struct be_mcc_wrb wrb;
205 struct be_mcc_compl compl;
206 };
207
208 #define CMD_SUBSYSTEM_COMMON 0x1
209 #define CMD_SUBSYSTEM_ETH 0x3
210 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
211
212 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
213 #define OPCODE_COMMON_NTWK_MAC_SET 2
214 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
215 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
216 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
217 #define OPCODE_COMMON_READ_FLASHROM 6
218 #define OPCODE_COMMON_WRITE_FLASHROM 7
219 #define OPCODE_COMMON_CQ_CREATE 12
220 #define OPCODE_COMMON_EQ_CREATE 13
221 #define OPCODE_COMMON_MCC_CREATE 21
222 #define OPCODE_COMMON_SET_QOS 28
223 #define OPCODE_COMMON_MCC_CREATE_EXT 90
224 #define OPCODE_COMMON_SEEPROM_READ 30
225 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
226 #define OPCODE_COMMON_NTWK_RX_FILTER 34
227 #define OPCODE_COMMON_GET_FW_VERSION 35
228 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
229 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
230 #define OPCODE_COMMON_SET_FRAME_SIZE 39
231 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
232 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
233 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
234 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
235 #define OPCODE_COMMON_MCC_DESTROY 53
236 #define OPCODE_COMMON_CQ_DESTROY 54
237 #define OPCODE_COMMON_EQ_DESTROY 55
238 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
239 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
240 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
241 #define OPCODE_COMMON_FUNCTION_RESET 61
242 #define OPCODE_COMMON_MANAGE_FAT 68
243 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
244 #define OPCODE_COMMON_GET_BEACON_STATE 70
245 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
246 #define OPCODE_COMMON_GET_PORT_NAME 77
247 #define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80
248 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
249 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100
250 #define OPCODE_COMMON_GET_PHY_DETAILS 102
251 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
252 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
253 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
254 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
255 #define OPCODE_COMMON_GET_MAC_LIST 147
256 #define OPCODE_COMMON_SET_MAC_LIST 148
257 #define OPCODE_COMMON_GET_HSW_CONFIG 152
258 #define OPCODE_COMMON_GET_FUNC_CONFIG 160
259 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164
260 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165
261 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167
262 #define OPCODE_COMMON_SET_HSW_CONFIG 153
263 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170
264 #define OPCODE_COMMON_READ_OBJECT 171
265 #define OPCODE_COMMON_WRITE_OBJECT 172
266 #define OPCODE_COMMON_DELETE_OBJECT 174
267 #define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193
268 #define OPCODE_COMMON_GET_IFACE_LIST 194
269 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196
270
271 #define OPCODE_ETH_RSS_CONFIG 1
272 #define OPCODE_ETH_ACPI_CONFIG 2
273 #define OPCODE_ETH_PROMISCUOUS 3
274 #define OPCODE_ETH_GET_STATISTICS 4
275 #define OPCODE_ETH_TX_CREATE 7
276 #define OPCODE_ETH_RX_CREATE 8
277 #define OPCODE_ETH_TX_DESTROY 9
278 #define OPCODE_ETH_RX_DESTROY 10
279 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
280 #define OPCODE_ETH_GET_PPORT_STATS 18
281
282 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
283 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
284 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
285
286 struct be_cmd_req_hdr {
287 u8 opcode; /* dword 0 */
288 u8 subsystem; /* dword 0 */
289 u8 port_number; /* dword 0 */
290 u8 domain; /* dword 0 */
291 u32 timeout; /* dword 1 */
292 u32 request_length; /* dword 2 */
293 u8 version; /* dword 3 */
294 u8 rsvd[3]; /* dword 3 */
295 };
296
297 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
298 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
299 struct be_cmd_resp_hdr {
300 u8 opcode; /* dword 0 */
301 u8 subsystem; /* dword 0 */
302 u8 rsvd[2]; /* dword 0 */
303 u8 base_status; /* dword 1 */
304 u8 addl_status; /* dword 1 */
305 u8 rsvd1[2]; /* dword 1 */
306 u32 response_length; /* dword 2 */
307 u32 actual_resp_len; /* dword 3 */
308 };
309
310 struct phys_addr {
311 u32 lo;
312 u32 hi;
313 };
314
315 /**************************
316 * BE Command definitions *
317 **************************/
318
319 /* Pseudo amap definition in which each bit of the actual structure is defined
320 * as a byte: used to calculate offset/shift/mask of each field */
321 struct amap_eq_context {
322 u8 cidx[13]; /* dword 0*/
323 u8 rsvd0[3]; /* dword 0*/
324 u8 epidx[13]; /* dword 0*/
325 u8 valid; /* dword 0*/
326 u8 rsvd1; /* dword 0*/
327 u8 size; /* dword 0*/
328 u8 pidx[13]; /* dword 1*/
329 u8 rsvd2[3]; /* dword 1*/
330 u8 pd[10]; /* dword 1*/
331 u8 count[3]; /* dword 1*/
332 u8 solevent; /* dword 1*/
333 u8 stalled; /* dword 1*/
334 u8 armed; /* dword 1*/
335 u8 rsvd3[4]; /* dword 2*/
336 u8 func[8]; /* dword 2*/
337 u8 rsvd4; /* dword 2*/
338 u8 delaymult[10]; /* dword 2*/
339 u8 rsvd5[2]; /* dword 2*/
340 u8 phase[2]; /* dword 2*/
341 u8 nodelay; /* dword 2*/
342 u8 rsvd6[4]; /* dword 2*/
343 u8 rsvd7[32]; /* dword 3*/
344 } __packed;
345
346 struct be_cmd_req_eq_create {
347 struct be_cmd_req_hdr hdr;
348 u16 num_pages; /* sword */
349 u16 rsvd0; /* sword */
350 u8 context[sizeof(struct amap_eq_context) / 8];
351 struct phys_addr pages[8];
352 } __packed;
353
354 struct be_cmd_resp_eq_create {
355 struct be_cmd_resp_hdr resp_hdr;
356 u16 eq_id; /* sword */
357 u16 msix_idx; /* available only in v2 */
358 } __packed;
359
360 /******************** Mac query ***************************/
361 enum {
362 MAC_ADDRESS_TYPE_STORAGE = 0x0,
363 MAC_ADDRESS_TYPE_NETWORK = 0x1,
364 MAC_ADDRESS_TYPE_PD = 0x2,
365 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
366 };
367
368 struct mac_addr {
369 u16 size_of_struct;
370 u8 addr[ETH_ALEN];
371 } __packed;
372
373 struct be_cmd_req_mac_query {
374 struct be_cmd_req_hdr hdr;
375 u8 type;
376 u8 permanent;
377 u16 if_id;
378 u32 pmac_id;
379 } __packed;
380
381 struct be_cmd_resp_mac_query {
382 struct be_cmd_resp_hdr hdr;
383 struct mac_addr mac;
384 };
385
386 /******************** PMac Add ***************************/
387 struct be_cmd_req_pmac_add {
388 struct be_cmd_req_hdr hdr;
389 u32 if_id;
390 u8 mac_address[ETH_ALEN];
391 u8 rsvd0[2];
392 } __packed;
393
394 struct be_cmd_resp_pmac_add {
395 struct be_cmd_resp_hdr hdr;
396 u32 pmac_id;
397 };
398
399 /******************** PMac Del ***************************/
400 struct be_cmd_req_pmac_del {
401 struct be_cmd_req_hdr hdr;
402 u32 if_id;
403 u32 pmac_id;
404 };
405
406 /******************** Create CQ ***************************/
407 /* Pseudo amap definition in which each bit of the actual structure is defined
408 * as a byte: used to calculate offset/shift/mask of each field */
409 struct amap_cq_context_be {
410 u8 cidx[11]; /* dword 0*/
411 u8 rsvd0; /* dword 0*/
412 u8 coalescwm[2]; /* dword 0*/
413 u8 nodelay; /* dword 0*/
414 u8 epidx[11]; /* dword 0*/
415 u8 rsvd1; /* dword 0*/
416 u8 count[2]; /* dword 0*/
417 u8 valid; /* dword 0*/
418 u8 solevent; /* dword 0*/
419 u8 eventable; /* dword 0*/
420 u8 pidx[11]; /* dword 1*/
421 u8 rsvd2; /* dword 1*/
422 u8 pd[10]; /* dword 1*/
423 u8 eqid[8]; /* dword 1*/
424 u8 stalled; /* dword 1*/
425 u8 armed; /* dword 1*/
426 u8 rsvd3[4]; /* dword 2*/
427 u8 func[8]; /* dword 2*/
428 u8 rsvd4[20]; /* dword 2*/
429 u8 rsvd5[32]; /* dword 3*/
430 } __packed;
431
432 struct amap_cq_context_v2 {
433 u8 rsvd0[12]; /* dword 0*/
434 u8 coalescwm[2]; /* dword 0*/
435 u8 nodelay; /* dword 0*/
436 u8 rsvd1[12]; /* dword 0*/
437 u8 count[2]; /* dword 0*/
438 u8 valid; /* dword 0*/
439 u8 rsvd2; /* dword 0*/
440 u8 eventable; /* dword 0*/
441 u8 eqid[16]; /* dword 1*/
442 u8 rsvd3[15]; /* dword 1*/
443 u8 armed; /* dword 1*/
444 u8 rsvd4[32]; /* dword 2*/
445 u8 rsvd5[32]; /* dword 3*/
446 } __packed;
447
448 struct be_cmd_req_cq_create {
449 struct be_cmd_req_hdr hdr;
450 u16 num_pages;
451 u8 page_size;
452 u8 rsvd0;
453 u8 context[sizeof(struct amap_cq_context_be) / 8];
454 struct phys_addr pages[8];
455 } __packed;
456
457
458 struct be_cmd_resp_cq_create {
459 struct be_cmd_resp_hdr hdr;
460 u16 cq_id;
461 u16 rsvd0;
462 } __packed;
463
464 struct be_cmd_req_get_fat {
465 struct be_cmd_req_hdr hdr;
466 u32 fat_operation;
467 u32 read_log_offset;
468 u32 read_log_length;
469 u32 data_buffer_size;
470 u32 data_buffer[1];
471 } __packed;
472
473 struct be_cmd_resp_get_fat {
474 struct be_cmd_resp_hdr hdr;
475 u32 log_size;
476 u32 read_log_length;
477 u32 rsvd[2];
478 u32 data_buffer[1];
479 } __packed;
480
481
482 /******************** Create MCCQ ***************************/
483 /* Pseudo amap definition in which each bit of the actual structure is defined
484 * as a byte: used to calculate offset/shift/mask of each field */
485 struct amap_mcc_context_be {
486 u8 con_index[14];
487 u8 rsvd0[2];
488 u8 ring_size[4];
489 u8 fetch_wrb;
490 u8 fetch_r2t;
491 u8 cq_id[10];
492 u8 prod_index[14];
493 u8 fid[8];
494 u8 pdid[9];
495 u8 valid;
496 u8 rsvd1[32];
497 u8 rsvd2[32];
498 } __packed;
499
500 struct amap_mcc_context_v1 {
501 u8 async_cq_id[16];
502 u8 ring_size[4];
503 u8 rsvd0[12];
504 u8 rsvd1[31];
505 u8 valid;
506 u8 async_cq_valid[1];
507 u8 rsvd2[31];
508 u8 rsvd3[32];
509 } __packed;
510
511 struct be_cmd_req_mcc_create {
512 struct be_cmd_req_hdr hdr;
513 u16 num_pages;
514 u16 cq_id;
515 u8 context[sizeof(struct amap_mcc_context_be) / 8];
516 struct phys_addr pages[8];
517 } __packed;
518
519 struct be_cmd_req_mcc_ext_create {
520 struct be_cmd_req_hdr hdr;
521 u16 num_pages;
522 u16 cq_id;
523 u32 async_event_bitmap[1];
524 u8 context[sizeof(struct amap_mcc_context_v1) / 8];
525 struct phys_addr pages[8];
526 } __packed;
527
528 struct be_cmd_resp_mcc_create {
529 struct be_cmd_resp_hdr hdr;
530 u16 id;
531 u16 rsvd0;
532 } __packed;
533
534 /******************** Create TxQ ***************************/
535 #define BE_ETH_TX_RING_TYPE_STANDARD 2
536 #define BE_ULP1_NUM 1
537
538 struct be_cmd_req_eth_tx_create {
539 struct be_cmd_req_hdr hdr;
540 u8 num_pages;
541 u8 ulp_num;
542 u16 type;
543 u16 if_id;
544 u8 queue_size;
545 u8 rsvd0;
546 u32 rsvd1;
547 u16 cq_id;
548 u16 rsvd2;
549 u32 rsvd3[13];
550 struct phys_addr pages[8];
551 } __packed;
552
553 struct be_cmd_resp_eth_tx_create {
554 struct be_cmd_resp_hdr hdr;
555 u16 cid;
556 u16 rid;
557 u32 db_offset;
558 u32 rsvd0[4];
559 } __packed;
560
561 /******************** Create RxQ ***************************/
562 struct be_cmd_req_eth_rx_create {
563 struct be_cmd_req_hdr hdr;
564 u16 cq_id;
565 u8 frag_size;
566 u8 num_pages;
567 struct phys_addr pages[2];
568 u32 interface_id;
569 u16 max_frame_size;
570 u16 rsvd0;
571 u32 rss_queue;
572 } __packed;
573
574 struct be_cmd_resp_eth_rx_create {
575 struct be_cmd_resp_hdr hdr;
576 u16 id;
577 u8 rss_id;
578 u8 rsvd0;
579 } __packed;
580
581 /******************** Q Destroy ***************************/
582 /* Type of Queue to be destroyed */
583 enum {
584 QTYPE_EQ = 1,
585 QTYPE_CQ,
586 QTYPE_TXQ,
587 QTYPE_RXQ,
588 QTYPE_MCCQ
589 };
590
591 struct be_cmd_req_q_destroy {
592 struct be_cmd_req_hdr hdr;
593 u16 id;
594 u16 bypass_flush; /* valid only for rx q destroy */
595 } __packed;
596
597 /************ I/f Create (it's actually I/f Config Create)**********/
598
599 /* Capability flags for the i/f */
600 enum be_if_flags {
601 BE_IF_FLAGS_RSS = 0x4,
602 BE_IF_FLAGS_PROMISCUOUS = 0x8,
603 BE_IF_FLAGS_BROADCAST = 0x10,
604 BE_IF_FLAGS_UNTAGGED = 0x20,
605 BE_IF_FLAGS_ULP = 0x40,
606 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
607 BE_IF_FLAGS_VLAN = 0x100,
608 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
609 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
610 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
611 BE_IF_FLAGS_MULTICAST = 0x1000,
612 BE_IF_FLAGS_DEFQ_RSS = 0x1000000
613 };
614
615 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
616 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
617 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
618 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
619 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS)
620
621 #define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \
622 BE_IF_FLAGS_VLAN_PROMISCUOUS |\
623 BE_IF_FLAGS_MCAST_PROMISCUOUS)
624
625 #define BE_IF_EN_FLAGS (BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PASS_L3L4_ERRORS |\
626 BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_UNTAGGED)
627
628 #define BE_IF_ALL_FILT_FLAGS (BE_IF_EN_FLAGS | BE_IF_FLAGS_ALL_PROMISCUOUS)
629
630 /* An RX interface is an object with one or more MAC addresses and
631 * filtering capabilities. */
632 struct be_cmd_req_if_create {
633 struct be_cmd_req_hdr hdr;
634 u32 version; /* ignore currently */
635 u32 capability_flags;
636 u32 enable_flags;
637 u8 mac_addr[ETH_ALEN];
638 u8 rsvd0;
639 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
640 u32 vlan_tag; /* not used currently */
641 } __packed;
642
643 struct be_cmd_resp_if_create {
644 struct be_cmd_resp_hdr hdr;
645 u32 interface_id;
646 u32 pmac_id;
647 };
648
649 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
650 struct be_cmd_req_if_destroy {
651 struct be_cmd_req_hdr hdr;
652 u32 interface_id;
653 };
654
655 /*************** HW Stats Get **********************************/
656 struct be_port_rxf_stats_v0 {
657 u32 rx_bytes_lsd; /* dword 0*/
658 u32 rx_bytes_msd; /* dword 1*/
659 u32 rx_total_frames; /* dword 2*/
660 u32 rx_unicast_frames; /* dword 3*/
661 u32 rx_multicast_frames; /* dword 4*/
662 u32 rx_broadcast_frames; /* dword 5*/
663 u32 rx_crc_errors; /* dword 6*/
664 u32 rx_alignment_symbol_errors; /* dword 7*/
665 u32 rx_pause_frames; /* dword 8*/
666 u32 rx_control_frames; /* dword 9*/
667 u32 rx_in_range_errors; /* dword 10*/
668 u32 rx_out_range_errors; /* dword 11*/
669 u32 rx_frame_too_long; /* dword 12*/
670 u32 rx_address_filtered; /* dword 13*/
671 u32 rx_vlan_filtered; /* dword 14*/
672 u32 rx_dropped_too_small; /* dword 15*/
673 u32 rx_dropped_too_short; /* dword 16*/
674 u32 rx_dropped_header_too_small; /* dword 17*/
675 u32 rx_dropped_tcp_length; /* dword 18*/
676 u32 rx_dropped_runt; /* dword 19*/
677 u32 rx_64_byte_packets; /* dword 20*/
678 u32 rx_65_127_byte_packets; /* dword 21*/
679 u32 rx_128_256_byte_packets; /* dword 22*/
680 u32 rx_256_511_byte_packets; /* dword 23*/
681 u32 rx_512_1023_byte_packets; /* dword 24*/
682 u32 rx_1024_1518_byte_packets; /* dword 25*/
683 u32 rx_1519_2047_byte_packets; /* dword 26*/
684 u32 rx_2048_4095_byte_packets; /* dword 27*/
685 u32 rx_4096_8191_byte_packets; /* dword 28*/
686 u32 rx_8192_9216_byte_packets; /* dword 29*/
687 u32 rx_ip_checksum_errs; /* dword 30*/
688 u32 rx_tcp_checksum_errs; /* dword 31*/
689 u32 rx_udp_checksum_errs; /* dword 32*/
690 u32 rx_non_rss_packets; /* dword 33*/
691 u32 rx_ipv4_packets; /* dword 34*/
692 u32 rx_ipv6_packets; /* dword 35*/
693 u32 rx_ipv4_bytes_lsd; /* dword 36*/
694 u32 rx_ipv4_bytes_msd; /* dword 37*/
695 u32 rx_ipv6_bytes_lsd; /* dword 38*/
696 u32 rx_ipv6_bytes_msd; /* dword 39*/
697 u32 rx_chute1_packets; /* dword 40*/
698 u32 rx_chute2_packets; /* dword 41*/
699 u32 rx_chute3_packets; /* dword 42*/
700 u32 rx_management_packets; /* dword 43*/
701 u32 rx_switched_unicast_packets; /* dword 44*/
702 u32 rx_switched_multicast_packets; /* dword 45*/
703 u32 rx_switched_broadcast_packets; /* dword 46*/
704 u32 tx_bytes_lsd; /* dword 47*/
705 u32 tx_bytes_msd; /* dword 48*/
706 u32 tx_unicastframes; /* dword 49*/
707 u32 tx_multicastframes; /* dword 50*/
708 u32 tx_broadcastframes; /* dword 51*/
709 u32 tx_pauseframes; /* dword 52*/
710 u32 tx_controlframes; /* dword 53*/
711 u32 tx_64_byte_packets; /* dword 54*/
712 u32 tx_65_127_byte_packets; /* dword 55*/
713 u32 tx_128_256_byte_packets; /* dword 56*/
714 u32 tx_256_511_byte_packets; /* dword 57*/
715 u32 tx_512_1023_byte_packets; /* dword 58*/
716 u32 tx_1024_1518_byte_packets; /* dword 59*/
717 u32 tx_1519_2047_byte_packets; /* dword 60*/
718 u32 tx_2048_4095_byte_packets; /* dword 61*/
719 u32 tx_4096_8191_byte_packets; /* dword 62*/
720 u32 tx_8192_9216_byte_packets; /* dword 63*/
721 u32 rx_fifo_overflow; /* dword 64*/
722 u32 rx_input_fifo_overflow; /* dword 65*/
723 };
724
725 struct be_rxf_stats_v0 {
726 struct be_port_rxf_stats_v0 port[2];
727 u32 rx_drops_no_pbuf; /* dword 132*/
728 u32 rx_drops_no_txpb; /* dword 133*/
729 u32 rx_drops_no_erx_descr; /* dword 134*/
730 u32 rx_drops_no_tpre_descr; /* dword 135*/
731 u32 management_rx_port_packets; /* dword 136*/
732 u32 management_rx_port_bytes; /* dword 137*/
733 u32 management_rx_port_pause_frames; /* dword 138*/
734 u32 management_rx_port_errors; /* dword 139*/
735 u32 management_tx_port_packets; /* dword 140*/
736 u32 management_tx_port_bytes; /* dword 141*/
737 u32 management_tx_port_pause; /* dword 142*/
738 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
739 u32 rx_drops_too_many_frags; /* dword 144*/
740 u32 rx_drops_invalid_ring; /* dword 145*/
741 u32 forwarded_packets; /* dword 146*/
742 u32 rx_drops_mtu; /* dword 147*/
743 u32 rsvd0[7];
744 u32 port0_jabber_events;
745 u32 port1_jabber_events;
746 u32 rsvd1[6];
747 };
748
749 struct be_erx_stats_v0 {
750 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
751 u32 rsvd[4];
752 };
753
754 struct be_pmem_stats {
755 u32 eth_red_drops;
756 u32 rsvd[5];
757 };
758
759 struct be_hw_stats_v0 {
760 struct be_rxf_stats_v0 rxf;
761 u32 rsvd[48];
762 struct be_erx_stats_v0 erx;
763 struct be_pmem_stats pmem;
764 };
765
766 struct be_cmd_req_get_stats_v0 {
767 struct be_cmd_req_hdr hdr;
768 u8 rsvd[sizeof(struct be_hw_stats_v0)];
769 };
770
771 struct be_cmd_resp_get_stats_v0 {
772 struct be_cmd_resp_hdr hdr;
773 struct be_hw_stats_v0 hw_stats;
774 };
775
776 struct lancer_pport_stats {
777 u32 tx_packets_lo;
778 u32 tx_packets_hi;
779 u32 tx_unicast_packets_lo;
780 u32 tx_unicast_packets_hi;
781 u32 tx_multicast_packets_lo;
782 u32 tx_multicast_packets_hi;
783 u32 tx_broadcast_packets_lo;
784 u32 tx_broadcast_packets_hi;
785 u32 tx_bytes_lo;
786 u32 tx_bytes_hi;
787 u32 tx_unicast_bytes_lo;
788 u32 tx_unicast_bytes_hi;
789 u32 tx_multicast_bytes_lo;
790 u32 tx_multicast_bytes_hi;
791 u32 tx_broadcast_bytes_lo;
792 u32 tx_broadcast_bytes_hi;
793 u32 tx_discards_lo;
794 u32 tx_discards_hi;
795 u32 tx_errors_lo;
796 u32 tx_errors_hi;
797 u32 tx_pause_frames_lo;
798 u32 tx_pause_frames_hi;
799 u32 tx_pause_on_frames_lo;
800 u32 tx_pause_on_frames_hi;
801 u32 tx_pause_off_frames_lo;
802 u32 tx_pause_off_frames_hi;
803 u32 tx_internal_mac_errors_lo;
804 u32 tx_internal_mac_errors_hi;
805 u32 tx_control_frames_lo;
806 u32 tx_control_frames_hi;
807 u32 tx_packets_64_bytes_lo;
808 u32 tx_packets_64_bytes_hi;
809 u32 tx_packets_65_to_127_bytes_lo;
810 u32 tx_packets_65_to_127_bytes_hi;
811 u32 tx_packets_128_to_255_bytes_lo;
812 u32 tx_packets_128_to_255_bytes_hi;
813 u32 tx_packets_256_to_511_bytes_lo;
814 u32 tx_packets_256_to_511_bytes_hi;
815 u32 tx_packets_512_to_1023_bytes_lo;
816 u32 tx_packets_512_to_1023_bytes_hi;
817 u32 tx_packets_1024_to_1518_bytes_lo;
818 u32 tx_packets_1024_to_1518_bytes_hi;
819 u32 tx_packets_1519_to_2047_bytes_lo;
820 u32 tx_packets_1519_to_2047_bytes_hi;
821 u32 tx_packets_2048_to_4095_bytes_lo;
822 u32 tx_packets_2048_to_4095_bytes_hi;
823 u32 tx_packets_4096_to_8191_bytes_lo;
824 u32 tx_packets_4096_to_8191_bytes_hi;
825 u32 tx_packets_8192_to_9216_bytes_lo;
826 u32 tx_packets_8192_to_9216_bytes_hi;
827 u32 tx_lso_packets_lo;
828 u32 tx_lso_packets_hi;
829 u32 rx_packets_lo;
830 u32 rx_packets_hi;
831 u32 rx_unicast_packets_lo;
832 u32 rx_unicast_packets_hi;
833 u32 rx_multicast_packets_lo;
834 u32 rx_multicast_packets_hi;
835 u32 rx_broadcast_packets_lo;
836 u32 rx_broadcast_packets_hi;
837 u32 rx_bytes_lo;
838 u32 rx_bytes_hi;
839 u32 rx_unicast_bytes_lo;
840 u32 rx_unicast_bytes_hi;
841 u32 rx_multicast_bytes_lo;
842 u32 rx_multicast_bytes_hi;
843 u32 rx_broadcast_bytes_lo;
844 u32 rx_broadcast_bytes_hi;
845 u32 rx_unknown_protos;
846 u32 rsvd_69; /* Word 69 is reserved */
847 u32 rx_discards_lo;
848 u32 rx_discards_hi;
849 u32 rx_errors_lo;
850 u32 rx_errors_hi;
851 u32 rx_crc_errors_lo;
852 u32 rx_crc_errors_hi;
853 u32 rx_alignment_errors_lo;
854 u32 rx_alignment_errors_hi;
855 u32 rx_symbol_errors_lo;
856 u32 rx_symbol_errors_hi;
857 u32 rx_pause_frames_lo;
858 u32 rx_pause_frames_hi;
859 u32 rx_pause_on_frames_lo;
860 u32 rx_pause_on_frames_hi;
861 u32 rx_pause_off_frames_lo;
862 u32 rx_pause_off_frames_hi;
863 u32 rx_frames_too_long_lo;
864 u32 rx_frames_too_long_hi;
865 u32 rx_internal_mac_errors_lo;
866 u32 rx_internal_mac_errors_hi;
867 u32 rx_undersize_packets;
868 u32 rx_oversize_packets;
869 u32 rx_fragment_packets;
870 u32 rx_jabbers;
871 u32 rx_control_frames_lo;
872 u32 rx_control_frames_hi;
873 u32 rx_control_frames_unknown_opcode_lo;
874 u32 rx_control_frames_unknown_opcode_hi;
875 u32 rx_in_range_errors;
876 u32 rx_out_of_range_errors;
877 u32 rx_address_filtered;
878 u32 rx_vlan_filtered;
879 u32 rx_dropped_too_small;
880 u32 rx_dropped_too_short;
881 u32 rx_dropped_header_too_small;
882 u32 rx_dropped_invalid_tcp_length;
883 u32 rx_dropped_runt;
884 u32 rx_ip_checksum_errors;
885 u32 rx_tcp_checksum_errors;
886 u32 rx_udp_checksum_errors;
887 u32 rx_non_rss_packets;
888 u32 rsvd_111;
889 u32 rx_ipv4_packets_lo;
890 u32 rx_ipv4_packets_hi;
891 u32 rx_ipv6_packets_lo;
892 u32 rx_ipv6_packets_hi;
893 u32 rx_ipv4_bytes_lo;
894 u32 rx_ipv4_bytes_hi;
895 u32 rx_ipv6_bytes_lo;
896 u32 rx_ipv6_bytes_hi;
897 u32 rx_nic_packets_lo;
898 u32 rx_nic_packets_hi;
899 u32 rx_tcp_packets_lo;
900 u32 rx_tcp_packets_hi;
901 u32 rx_iscsi_packets_lo;
902 u32 rx_iscsi_packets_hi;
903 u32 rx_management_packets_lo;
904 u32 rx_management_packets_hi;
905 u32 rx_switched_unicast_packets_lo;
906 u32 rx_switched_unicast_packets_hi;
907 u32 rx_switched_multicast_packets_lo;
908 u32 rx_switched_multicast_packets_hi;
909 u32 rx_switched_broadcast_packets_lo;
910 u32 rx_switched_broadcast_packets_hi;
911 u32 num_forwards_lo;
912 u32 num_forwards_hi;
913 u32 rx_fifo_overflow;
914 u32 rx_input_fifo_overflow;
915 u32 rx_drops_too_many_frags_lo;
916 u32 rx_drops_too_many_frags_hi;
917 u32 rx_drops_invalid_queue;
918 u32 rsvd_141;
919 u32 rx_drops_mtu_lo;
920 u32 rx_drops_mtu_hi;
921 u32 rx_packets_64_bytes_lo;
922 u32 rx_packets_64_bytes_hi;
923 u32 rx_packets_65_to_127_bytes_lo;
924 u32 rx_packets_65_to_127_bytes_hi;
925 u32 rx_packets_128_to_255_bytes_lo;
926 u32 rx_packets_128_to_255_bytes_hi;
927 u32 rx_packets_256_to_511_bytes_lo;
928 u32 rx_packets_256_to_511_bytes_hi;
929 u32 rx_packets_512_to_1023_bytes_lo;
930 u32 rx_packets_512_to_1023_bytes_hi;
931 u32 rx_packets_1024_to_1518_bytes_lo;
932 u32 rx_packets_1024_to_1518_bytes_hi;
933 u32 rx_packets_1519_to_2047_bytes_lo;
934 u32 rx_packets_1519_to_2047_bytes_hi;
935 u32 rx_packets_2048_to_4095_bytes_lo;
936 u32 rx_packets_2048_to_4095_bytes_hi;
937 u32 rx_packets_4096_to_8191_bytes_lo;
938 u32 rx_packets_4096_to_8191_bytes_hi;
939 u32 rx_packets_8192_to_9216_bytes_lo;
940 u32 rx_packets_8192_to_9216_bytes_hi;
941 };
942
943 struct pport_stats_params {
944 u16 pport_num;
945 u8 rsvd;
946 u8 reset_stats;
947 };
948
949 struct lancer_cmd_req_pport_stats {
950 struct be_cmd_req_hdr hdr;
951 union {
952 struct pport_stats_params params;
953 u8 rsvd[sizeof(struct lancer_pport_stats)];
954 } cmd_params;
955 };
956
957 struct lancer_cmd_resp_pport_stats {
958 struct be_cmd_resp_hdr hdr;
959 struct lancer_pport_stats pport_stats;
960 };
961
962 static inline struct lancer_pport_stats*
963 pport_stats_from_cmd(struct be_adapter *adapter)
964 {
965 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
966 return &cmd->pport_stats;
967 }
968
969 struct be_cmd_req_get_cntl_addnl_attribs {
970 struct be_cmd_req_hdr hdr;
971 u8 rsvd[8];
972 };
973
974 struct be_cmd_resp_get_cntl_addnl_attribs {
975 struct be_cmd_resp_hdr hdr;
976 u16 ipl_file_number;
977 u8 ipl_file_version;
978 u8 rsvd0;
979 u8 on_die_temperature; /* in degrees centigrade*/
980 u8 rsvd1[3];
981 };
982
983 struct be_cmd_req_vlan_config {
984 struct be_cmd_req_hdr hdr;
985 u8 interface_id;
986 u8 promiscuous;
987 u8 untagged;
988 u8 num_vlan;
989 u16 normal_vlan[64];
990 } __packed;
991
992 /******************* RX FILTER ******************************/
993 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
994 struct macaddr {
995 u8 byte[ETH_ALEN];
996 };
997
998 struct be_cmd_req_rx_filter {
999 struct be_cmd_req_hdr hdr;
1000 u32 global_flags_mask;
1001 u32 global_flags;
1002 u32 if_flags_mask;
1003 u32 if_flags;
1004 u32 if_id;
1005 u32 mcast_num;
1006 struct macaddr mcast_mac[BE_MAX_MC];
1007 };
1008
1009 /******************** Link Status Query *******************/
1010 struct be_cmd_req_link_status {
1011 struct be_cmd_req_hdr hdr;
1012 u32 rsvd;
1013 };
1014
1015 enum {
1016 PHY_LINK_DUPLEX_NONE = 0x0,
1017 PHY_LINK_DUPLEX_HALF = 0x1,
1018 PHY_LINK_DUPLEX_FULL = 0x2
1019 };
1020
1021 enum {
1022 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
1023 PHY_LINK_SPEED_10MBPS = 0x1,
1024 PHY_LINK_SPEED_100MBPS = 0x2,
1025 PHY_LINK_SPEED_1GBPS = 0x3,
1026 PHY_LINK_SPEED_10GBPS = 0x4,
1027 PHY_LINK_SPEED_20GBPS = 0x5,
1028 PHY_LINK_SPEED_25GBPS = 0x6,
1029 PHY_LINK_SPEED_40GBPS = 0x7
1030 };
1031
1032 struct be_cmd_resp_link_status {
1033 struct be_cmd_resp_hdr hdr;
1034 u8 physical_port;
1035 u8 mac_duplex;
1036 u8 mac_speed;
1037 u8 mac_fault;
1038 u8 mgmt_mac_duplex;
1039 u8 mgmt_mac_speed;
1040 u16 link_speed;
1041 u8 logical_link_status;
1042 u8 rsvd1[3];
1043 } __packed;
1044
1045 /******************** Port Identification ***************************/
1046 /* Identifies the type of port attached to NIC */
1047 struct be_cmd_req_port_type {
1048 struct be_cmd_req_hdr hdr;
1049 __le32 page_num;
1050 __le32 port;
1051 };
1052
1053 enum {
1054 TR_PAGE_A0 = 0xa0,
1055 TR_PAGE_A2 = 0xa2
1056 };
1057
1058 /* From SFF-8436 QSFP+ spec */
1059 #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83
1060 #define QSFP_PLUS_CR4_CABLE 0x8
1061 #define QSFP_PLUS_SR4_CABLE 0x4
1062 #define QSFP_PLUS_LR4_CABLE 0x2
1063
1064 /* From SFF-8472 spec */
1065 #define SFP_PLUS_SFF_8472_COMP 0x5E
1066 #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8
1067 #define SFP_PLUS_COPPER_CABLE 0x4
1068 #define SFP_VENDOR_NAME_OFFSET 0x14
1069 #define SFP_VENDOR_PN_OFFSET 0x28
1070
1071 #define PAGE_DATA_LEN 256
1072 struct be_cmd_resp_port_type {
1073 struct be_cmd_resp_hdr hdr;
1074 u32 page_num;
1075 u32 port;
1076 u8 page_data[PAGE_DATA_LEN];
1077 };
1078
1079 /******************** Get FW Version *******************/
1080 struct be_cmd_req_get_fw_version {
1081 struct be_cmd_req_hdr hdr;
1082 u8 rsvd0[FW_VER_LEN];
1083 u8 rsvd1[FW_VER_LEN];
1084 } __packed;
1085
1086 struct be_cmd_resp_get_fw_version {
1087 struct be_cmd_resp_hdr hdr;
1088 u8 firmware_version_string[FW_VER_LEN];
1089 u8 fw_on_flash_version_string[FW_VER_LEN];
1090 } __packed;
1091
1092 /******************** Set Flow Contrl *******************/
1093 struct be_cmd_req_set_flow_control {
1094 struct be_cmd_req_hdr hdr;
1095 u16 tx_flow_control;
1096 u16 rx_flow_control;
1097 } __packed;
1098
1099 /******************** Get Flow Contrl *******************/
1100 struct be_cmd_req_get_flow_control {
1101 struct be_cmd_req_hdr hdr;
1102 u32 rsvd;
1103 };
1104
1105 struct be_cmd_resp_get_flow_control {
1106 struct be_cmd_resp_hdr hdr;
1107 u16 tx_flow_control;
1108 u16 rx_flow_control;
1109 } __packed;
1110
1111 /******************** Modify EQ Delay *******************/
1112 struct be_set_eqd {
1113 u32 eq_id;
1114 u32 phase;
1115 u32 delay_multiplier;
1116 };
1117
1118 struct be_cmd_req_modify_eq_delay {
1119 struct be_cmd_req_hdr hdr;
1120 u32 num_eq;
1121 struct be_set_eqd set_eqd[MAX_EVT_QS];
1122 } __packed;
1123
1124 /******************** Get FW Config *******************/
1125 /* The HW can come up in either of the following multi-channel modes
1126 * based on the skew/IPL.
1127 */
1128 #define RDMA_ENABLED 0x4
1129 #define QNQ_MODE 0x400
1130 #define VNIC_MODE 0x20000
1131 #define UMC_ENABLED 0x1000000
1132 struct be_cmd_req_query_fw_cfg {
1133 struct be_cmd_req_hdr hdr;
1134 u32 rsvd[31];
1135 };
1136
1137 struct be_cmd_resp_query_fw_cfg {
1138 struct be_cmd_resp_hdr hdr;
1139 u32 be_config_number;
1140 u32 asic_revision;
1141 u32 phys_port;
1142 u32 function_mode;
1143 u32 rsvd[26];
1144 u32 function_caps;
1145 };
1146
1147 /******************** RSS Config ****************************************/
1148 /* RSS type Input parameters used to compute RX hash
1149 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1150 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1151 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1152 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1153 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1154 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1155 *
1156 * When multiple RSS types are enabled, HW picks the best hash policy
1157 * based on the type of the received packet.
1158 */
1159 #define RSS_ENABLE_NONE 0x0
1160 #define RSS_ENABLE_IPV4 0x1
1161 #define RSS_ENABLE_TCP_IPV4 0x2
1162 #define RSS_ENABLE_IPV6 0x4
1163 #define RSS_ENABLE_TCP_IPV6 0x8
1164 #define RSS_ENABLE_UDP_IPV4 0x10
1165 #define RSS_ENABLE_UDP_IPV6 0x20
1166
1167 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1168 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1169
1170 struct be_cmd_req_rss_config {
1171 struct be_cmd_req_hdr hdr;
1172 u32 if_id;
1173 u16 enable_rss;
1174 u16 cpu_table_size_log2;
1175 u32 hash[10];
1176 u8 cpu_table[128];
1177 u8 flush;
1178 u8 rsvd0[3];
1179 };
1180
1181 /******************** Port Beacon ***************************/
1182
1183 #define BEACON_STATE_ENABLED 0x1
1184 #define BEACON_STATE_DISABLED 0x0
1185
1186 struct be_cmd_req_enable_disable_beacon {
1187 struct be_cmd_req_hdr hdr;
1188 u8 port_num;
1189 u8 beacon_state;
1190 u8 beacon_duration;
1191 u8 status_duration;
1192 } __packed;
1193
1194 struct be_cmd_req_get_beacon_state {
1195 struct be_cmd_req_hdr hdr;
1196 u8 port_num;
1197 u8 rsvd0;
1198 u16 rsvd1;
1199 } __packed;
1200
1201 struct be_cmd_resp_get_beacon_state {
1202 struct be_cmd_resp_hdr resp_hdr;
1203 u8 beacon_state;
1204 u8 rsvd0[3];
1205 } __packed;
1206
1207 /* Flashrom related descriptors */
1208 #define MAX_FLASH_COMP 32
1209
1210 /* Optypes of each component in the UFI */
1211 enum {
1212 OPTYPE_ISCSI_ACTIVE = 0,
1213 OPTYPE_REDBOOT = 1,
1214 OPTYPE_BIOS = 2,
1215 OPTYPE_PXE_BIOS = 3,
1216 OPTYPE_OFFSET_SPECIFIED = 7,
1217 OPTYPE_FCOE_BIOS = 8,
1218 OPTYPE_ISCSI_BACKUP = 9,
1219 OPTYPE_FCOE_FW_ACTIVE = 10,
1220 OPTYPE_FCOE_FW_BACKUP = 11,
1221 OPTYPE_NCSI_FW = 13,
1222 OPTYPE_REDBOOT_DIR = 18,
1223 OPTYPE_REDBOOT_CONFIG = 19,
1224 OPTYPE_SH_PHY_FW = 21,
1225 OPTYPE_FLASHISM_JUMPVECTOR = 22,
1226 OPTYPE_UFI_DIR = 23,
1227 OPTYPE_PHY_FW = 99
1228 };
1229
1230 /* Maximum sizes of components in BE2 FW UFI */
1231 enum {
1232 BE2_BIOS_COMP_MAX_SIZE = 0x40000,
1233 BE2_REDBOOT_COMP_MAX_SIZE = 0x40000,
1234 BE2_COMP_MAX_SIZE = 0x140000
1235 };
1236
1237 /* Maximum sizes of components in BE3 FW UFI */
1238 enum {
1239 BE3_NCSI_COMP_MAX_SIZE = 0x40000,
1240 BE3_PHY_FW_COMP_MAX_SIZE = 0x40000,
1241 BE3_BIOS_COMP_MAX_SIZE = 0x80000,
1242 BE3_REDBOOT_COMP_MAX_SIZE = 0x100000,
1243 BE3_COMP_MAX_SIZE = 0x200000
1244 };
1245
1246 /* Offsets for components in BE2 FW UFI */
1247 enum {
1248 BE2_REDBOOT_START = 0x8000,
1249 BE2_FCOE_BIOS_START = 0x80000,
1250 BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000,
1251 BE2_ISCSI_BACKUP_IMAGE_START = 0x240000,
1252 BE2_FCOE_PRIMARY_IMAGE_START = 0x380000,
1253 BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000,
1254 BE2_ISCSI_BIOS_START = 0x700000,
1255 BE2_PXE_BIOS_START = 0x780000
1256 };
1257
1258 /* Offsets for components in BE3 FW UFI */
1259 enum {
1260 BE3_REDBOOT_START = 0x40000,
1261 BE3_PHY_FW_START = 0x140000,
1262 BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000,
1263 BE3_ISCSI_BACKUP_IMAGE_START = 0x400000,
1264 BE3_FCOE_PRIMARY_IMAGE_START = 0x600000,
1265 BE3_FCOE_BACKUP_IMAGE_START = 0x800000,
1266 BE3_ISCSI_BIOS_START = 0xc00000,
1267 BE3_PXE_BIOS_START = 0xc80000,
1268 BE3_FCOE_BIOS_START = 0xd00000,
1269 BE3_NCSI_START = 0xf40000
1270 };
1271
1272 /* Component entry types */
1273 enum {
1274 IMAGE_NCSI = 0x10,
1275 IMAGE_OPTION_ROM_PXE = 0x20,
1276 IMAGE_OPTION_ROM_FCOE = 0x21,
1277 IMAGE_OPTION_ROM_ISCSI = 0x22,
1278 IMAGE_FLASHISM_JUMPVECTOR = 0x30,
1279 IMAGE_FIRMWARE_ISCSI = 0xa0,
1280 IMAGE_FIRMWARE_FCOE = 0xa2,
1281 IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0,
1282 IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2,
1283 IMAGE_FIRMWARE_PHY = 0xc0,
1284 IMAGE_REDBOOT_DIR = 0xd0,
1285 IMAGE_REDBOOT_CONFIG = 0xd1,
1286 IMAGE_UFI_DIR = 0xd2,
1287 IMAGE_BOOT_CODE = 0xe2
1288 };
1289
1290 struct controller_id {
1291 u32 vendor;
1292 u32 device;
1293 u32 subvendor;
1294 u32 subdevice;
1295 };
1296
1297 struct flash_comp {
1298 unsigned long offset;
1299 int optype;
1300 int size;
1301 int img_type;
1302 };
1303
1304 struct image_hdr {
1305 u32 imageid;
1306 u32 imageoffset;
1307 u32 imagelength;
1308 u32 image_checksum;
1309 u8 image_version[32];
1310 };
1311
1312 struct flash_file_hdr_g2 {
1313 u8 sign[32];
1314 u32 cksum;
1315 u32 antidote;
1316 struct controller_id cont_id;
1317 u32 file_len;
1318 u32 chunk_num;
1319 u32 total_chunks;
1320 u32 num_imgs;
1321 u8 build[24];
1322 };
1323
1324 /* First letter of the build version of the image */
1325 #define BLD_STR_UFI_TYPE_BE2 '2'
1326 #define BLD_STR_UFI_TYPE_BE3 '3'
1327 #define BLD_STR_UFI_TYPE_SH '4'
1328
1329 struct flash_file_hdr_g3 {
1330 u8 sign[52];
1331 u8 ufi_version[4];
1332 u32 file_len;
1333 u32 cksum;
1334 u32 antidote;
1335 u32 num_imgs;
1336 u8 build[24];
1337 u8 asic_type_rev;
1338 u8 rsvd[31];
1339 };
1340
1341 struct flash_section_hdr {
1342 u32 format_rev;
1343 u32 cksum;
1344 u32 antidote;
1345 u32 num_images;
1346 u8 id_string[128];
1347 u32 rsvd[4];
1348 } __packed;
1349
1350 struct flash_section_hdr_g2 {
1351 u32 format_rev;
1352 u32 cksum;
1353 u32 antidote;
1354 u32 build_num;
1355 u8 id_string[128];
1356 u32 rsvd[8];
1357 } __packed;
1358
1359 struct flash_section_entry {
1360 u32 type;
1361 u32 offset;
1362 u32 pad_size;
1363 u32 image_size;
1364 u32 cksum;
1365 u32 entry_point;
1366 u16 optype;
1367 u16 rsvd0;
1368 u32 rsvd1;
1369 u8 ver_data[32];
1370 } __packed;
1371
1372 struct flash_section_info {
1373 u8 cookie[32];
1374 struct flash_section_hdr fsec_hdr;
1375 struct flash_section_entry fsec_entry[32];
1376 } __packed;
1377
1378 struct flash_section_info_g2 {
1379 u8 cookie[32];
1380 struct flash_section_hdr_g2 fsec_hdr;
1381 struct flash_section_entry fsec_entry[32];
1382 } __packed;
1383
1384 /****************** Firmware Flash ******************/
1385 #define FLASHROM_OPER_FLASH 1
1386 #define FLASHROM_OPER_SAVE 2
1387 #define FLASHROM_OPER_REPORT 4
1388 #define FLASHROM_OPER_PHY_FLASH 9
1389 #define FLASHROM_OPER_PHY_SAVE 10
1390
1391 struct flashrom_params {
1392 u32 op_code;
1393 u32 op_type;
1394 u32 data_buf_size;
1395 u32 offset;
1396 };
1397
1398 struct be_cmd_write_flashrom {
1399 struct be_cmd_req_hdr hdr;
1400 struct flashrom_params params;
1401 u8 data_buf[32768];
1402 u8 rsvd[4];
1403 } __packed;
1404
1405 /* cmd to read flash crc */
1406 struct be_cmd_read_flash_crc {
1407 struct be_cmd_req_hdr hdr;
1408 struct flashrom_params params;
1409 u8 crc[4];
1410 u8 rsvd[4];
1411 } __packed;
1412
1413 /**************** Lancer Firmware Flash ************/
1414 #define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024)
1415 #define LANCER_FW_DOWNLOAD_LOCATION "/prg"
1416
1417 struct amap_lancer_write_obj_context {
1418 u8 write_length[24];
1419 u8 reserved1[7];
1420 u8 eof;
1421 } __packed;
1422
1423 struct lancer_cmd_req_write_object {
1424 struct be_cmd_req_hdr hdr;
1425 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1426 u32 write_offset;
1427 u8 object_name[104];
1428 u32 descriptor_count;
1429 u32 buf_len;
1430 u32 addr_low;
1431 u32 addr_high;
1432 };
1433
1434 #define LANCER_NO_RESET_NEEDED 0x00
1435 #define LANCER_FW_RESET_NEEDED 0x02
1436 struct lancer_cmd_resp_write_object {
1437 u8 opcode;
1438 u8 subsystem;
1439 u8 rsvd1[2];
1440 u8 status;
1441 u8 additional_status;
1442 u8 rsvd2[2];
1443 u32 resp_len;
1444 u32 actual_resp_len;
1445 u32 actual_write_len;
1446 u8 change_status;
1447 u8 rsvd3[3];
1448 };
1449
1450 /************************ Lancer Read FW info **************/
1451 #define LANCER_READ_FILE_CHUNK (32*1024)
1452 #define LANCER_READ_FILE_EOF_MASK 0x80000000
1453
1454 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
1455 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1456 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
1457
1458 struct lancer_cmd_req_read_object {
1459 struct be_cmd_req_hdr hdr;
1460 u32 desired_read_len;
1461 u32 read_offset;
1462 u8 object_name[104];
1463 u32 descriptor_count;
1464 u32 buf_len;
1465 u32 addr_low;
1466 u32 addr_high;
1467 };
1468
1469 struct lancer_cmd_resp_read_object {
1470 u8 opcode;
1471 u8 subsystem;
1472 u8 rsvd1[2];
1473 u8 status;
1474 u8 additional_status;
1475 u8 rsvd2[2];
1476 u32 resp_len;
1477 u32 actual_resp_len;
1478 u32 actual_read_len;
1479 u32 eof;
1480 };
1481
1482 struct lancer_cmd_req_delete_object {
1483 struct be_cmd_req_hdr hdr;
1484 u32 rsvd1;
1485 u32 rsvd2;
1486 u8 object_name[104];
1487 };
1488
1489 /************************ WOL *******************************/
1490 struct be_cmd_req_acpi_wol_magic_config{
1491 struct be_cmd_req_hdr hdr;
1492 u32 rsvd0[145];
1493 u8 magic_mac[6];
1494 u8 rsvd2[2];
1495 } __packed;
1496
1497 struct be_cmd_req_acpi_wol_magic_config_v1 {
1498 struct be_cmd_req_hdr hdr;
1499 u8 rsvd0[2];
1500 u8 query_options;
1501 u8 rsvd1[5];
1502 u32 rsvd2[288];
1503 u8 magic_mac[6];
1504 u8 rsvd3[22];
1505 } __packed;
1506
1507 struct be_cmd_resp_acpi_wol_magic_config_v1 {
1508 struct be_cmd_resp_hdr hdr;
1509 u8 rsvd0[2];
1510 u8 wol_settings;
1511 u8 rsvd1[5];
1512 u32 rsvd2[295];
1513 } __packed;
1514
1515 #define BE_GET_WOL_CAP 2
1516
1517 #define BE_WOL_CAP 0x1
1518 #define BE_PME_D0_CAP 0x8
1519 #define BE_PME_D1_CAP 0x10
1520 #define BE_PME_D2_CAP 0x20
1521 #define BE_PME_D3HOT_CAP 0x40
1522 #define BE_PME_D3COLD_CAP 0x80
1523
1524 /********************** LoopBack test *********************/
1525 #define SET_LB_MODE_TIMEOUT 12000
1526
1527 struct be_cmd_req_loopback_test {
1528 struct be_cmd_req_hdr hdr;
1529 u32 loopback_type;
1530 u32 num_pkts;
1531 u64 pattern;
1532 u32 src_port;
1533 u32 dest_port;
1534 u32 pkt_size;
1535 };
1536
1537 struct be_cmd_resp_loopback_test {
1538 struct be_cmd_resp_hdr resp_hdr;
1539 u32 status;
1540 u32 num_txfer;
1541 u32 num_rx;
1542 u32 miscomp_off;
1543 u32 ticks_compl;
1544 };
1545
1546 struct be_cmd_req_set_lmode {
1547 struct be_cmd_req_hdr hdr;
1548 u8 src_port;
1549 u8 dest_port;
1550 u8 loopback_type;
1551 u8 loopback_state;
1552 };
1553
1554 /********************** DDR DMA test *********************/
1555 struct be_cmd_req_ddrdma_test {
1556 struct be_cmd_req_hdr hdr;
1557 u64 pattern;
1558 u32 byte_count;
1559 u32 rsvd0;
1560 u8 snd_buff[4096];
1561 u8 rsvd1[4096];
1562 };
1563
1564 struct be_cmd_resp_ddrdma_test {
1565 struct be_cmd_resp_hdr hdr;
1566 u64 pattern;
1567 u32 byte_cnt;
1568 u32 snd_err;
1569 u8 rsvd0[4096];
1570 u8 rcv_buff[4096];
1571 };
1572
1573 /*********************** SEEPROM Read ***********************/
1574
1575 #define BE_READ_SEEPROM_LEN 1024
1576 struct be_cmd_req_seeprom_read {
1577 struct be_cmd_req_hdr hdr;
1578 u8 rsvd0[BE_READ_SEEPROM_LEN];
1579 };
1580
1581 struct be_cmd_resp_seeprom_read {
1582 struct be_cmd_req_hdr hdr;
1583 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1584 };
1585
1586 enum {
1587 PHY_TYPE_CX4_10GB = 0,
1588 PHY_TYPE_XFP_10GB,
1589 PHY_TYPE_SFP_1GB,
1590 PHY_TYPE_SFP_PLUS_10GB,
1591 PHY_TYPE_KR_10GB,
1592 PHY_TYPE_KX4_10GB,
1593 PHY_TYPE_BASET_10GB,
1594 PHY_TYPE_BASET_1GB,
1595 PHY_TYPE_BASEX_1GB,
1596 PHY_TYPE_SGMII,
1597 PHY_TYPE_QSFP,
1598 PHY_TYPE_KR4_40GB,
1599 PHY_TYPE_KR2_20GB,
1600 PHY_TYPE_TN_8022,
1601 PHY_TYPE_DISABLED = 255
1602 };
1603
1604 #define BE_SUPPORTED_SPEED_NONE 0
1605 #define BE_SUPPORTED_SPEED_10MBPS 1
1606 #define BE_SUPPORTED_SPEED_100MBPS 2
1607 #define BE_SUPPORTED_SPEED_1GBPS 4
1608 #define BE_SUPPORTED_SPEED_10GBPS 8
1609 #define BE_SUPPORTED_SPEED_20GBPS 0x10
1610 #define BE_SUPPORTED_SPEED_40GBPS 0x20
1611
1612 #define BE_AN_EN 0x2
1613 #define BE_PAUSE_SYM_EN 0x80
1614
1615 /* MAC speed valid values */
1616 #define SPEED_DEFAULT 0x0
1617 #define SPEED_FORCED_10GB 0x1
1618 #define SPEED_FORCED_1GB 0x2
1619 #define SPEED_AUTONEG_10GB 0x3
1620 #define SPEED_AUTONEG_1GB 0x4
1621 #define SPEED_AUTONEG_100MB 0x5
1622 #define SPEED_AUTONEG_10GB_1GB 0x6
1623 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1624 #define SPEED_AUTONEG_1GB_100MB 0x8
1625 #define SPEED_AUTONEG_10MB 0x9
1626 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1627 #define SPEED_AUTONEG_100MB_10MB 0xb
1628 #define SPEED_FORCED_100MB 0xc
1629 #define SPEED_FORCED_10MB 0xd
1630
1631 struct be_cmd_req_get_phy_info {
1632 struct be_cmd_req_hdr hdr;
1633 u8 rsvd0[24];
1634 };
1635
1636 struct be_phy_info {
1637 u16 phy_type;
1638 u16 interface_type;
1639 u32 misc_params;
1640 u16 ext_phy_details;
1641 u16 rsvd;
1642 u16 auto_speeds_supported;
1643 u16 fixed_speeds_supported;
1644 u32 future_use[2];
1645 };
1646
1647 struct be_cmd_resp_get_phy_info {
1648 struct be_cmd_req_hdr hdr;
1649 struct be_phy_info phy_info;
1650 };
1651
1652 /*********************** Set QOS ***********************/
1653
1654 #define BE_QOS_BITS_NIC 1
1655
1656 struct be_cmd_req_set_qos {
1657 struct be_cmd_req_hdr hdr;
1658 u32 valid_bits;
1659 u32 max_bps_nic;
1660 u32 rsvd[7];
1661 };
1662
1663 /*********************** Controller Attributes ***********************/
1664 struct mgmt_hba_attribs {
1665 u32 rsvd0[24];
1666 u8 controller_model_number[32];
1667 u32 rsvd1[16];
1668 u32 controller_serial_number[8];
1669 u32 rsvd2[55];
1670 u8 rsvd3[3];
1671 u8 phy_port;
1672 u32 rsvd4[13];
1673 } __packed;
1674
1675 struct mgmt_controller_attrib {
1676 struct mgmt_hba_attribs hba_attribs;
1677 u32 rsvd0[10];
1678 } __packed;
1679
1680 struct be_cmd_req_cntl_attribs {
1681 struct be_cmd_req_hdr hdr;
1682 };
1683
1684 struct be_cmd_resp_cntl_attribs {
1685 struct be_cmd_resp_hdr hdr;
1686 struct mgmt_controller_attrib attribs;
1687 };
1688
1689 /*********************** Set driver function ***********************/
1690 #define CAPABILITY_SW_TIMESTAMPS 2
1691 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1692
1693 struct be_cmd_req_set_func_cap {
1694 struct be_cmd_req_hdr hdr;
1695 u32 valid_cap_flags;
1696 u32 cap_flags;
1697 u8 rsvd[212];
1698 };
1699
1700 struct be_cmd_resp_set_func_cap {
1701 struct be_cmd_resp_hdr hdr;
1702 u32 valid_cap_flags;
1703 u32 cap_flags;
1704 u8 rsvd[212];
1705 };
1706
1707 /*********************** Function Privileges ***********************/
1708 enum {
1709 BE_PRIV_DEFAULT = 0x1,
1710 BE_PRIV_LNKQUERY = 0x2,
1711 BE_PRIV_LNKSTATS = 0x4,
1712 BE_PRIV_LNKMGMT = 0x8,
1713 BE_PRIV_LNKDIAG = 0x10,
1714 BE_PRIV_UTILQUERY = 0x20,
1715 BE_PRIV_FILTMGMT = 0x40,
1716 BE_PRIV_IFACEMGMT = 0x80,
1717 BE_PRIV_VHADM = 0x100,
1718 BE_PRIV_DEVCFG = 0x200,
1719 BE_PRIV_DEVSEC = 0x400
1720 };
1721 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1722 BE_PRIV_DEVSEC)
1723 #define MIN_PRIVILEGES BE_PRIV_DEFAULT
1724
1725 struct be_cmd_priv_map {
1726 u8 opcode;
1727 u8 subsystem;
1728 u32 priv_mask;
1729 };
1730
1731 struct be_cmd_req_get_fn_privileges {
1732 struct be_cmd_req_hdr hdr;
1733 u32 rsvd;
1734 };
1735
1736 struct be_cmd_resp_get_fn_privileges {
1737 struct be_cmd_resp_hdr hdr;
1738 u32 privilege_mask;
1739 };
1740
1741 struct be_cmd_req_set_fn_privileges {
1742 struct be_cmd_req_hdr hdr;
1743 u32 privileges; /* Used by BE3, SH-R */
1744 u32 privileges_lancer; /* Used by Lancer */
1745 };
1746
1747 /******************** GET/SET_MACLIST **************************/
1748 #define BE_MAX_MAC 64
1749 struct be_cmd_req_get_mac_list {
1750 struct be_cmd_req_hdr hdr;
1751 u8 mac_type;
1752 u8 perm_override;
1753 u16 iface_id;
1754 u32 mac_id;
1755 u32 rsvd[3];
1756 } __packed;
1757
1758 struct get_list_macaddr {
1759 u16 mac_addr_size;
1760 union {
1761 u8 macaddr[6];
1762 struct {
1763 u8 rsvd[2];
1764 u32 mac_id;
1765 } __packed s_mac_id;
1766 } __packed mac_addr_id;
1767 } __packed;
1768
1769 struct be_cmd_resp_get_mac_list {
1770 struct be_cmd_resp_hdr hdr;
1771 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1772 struct get_list_macaddr macid_macaddr; /* soft mac */
1773 u8 true_mac_count;
1774 u8 pseudo_mac_count;
1775 u8 mac_list_size;
1776 u8 rsvd;
1777 /* perm override mac */
1778 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1779 } __packed;
1780
1781 struct be_cmd_req_set_mac_list {
1782 struct be_cmd_req_hdr hdr;
1783 u8 mac_count;
1784 u8 rsvd1;
1785 u16 rsvd2;
1786 struct macaddr mac[BE_MAX_MAC];
1787 } __packed;
1788
1789 /*********************** HSW Config ***********************/
1790 #define PORT_FWD_TYPE_VEPA 0x3
1791 #define PORT_FWD_TYPE_VEB 0x2
1792 #define PORT_FWD_TYPE_PASSTHRU 0x1
1793
1794 #define ENABLE_MAC_SPOOFCHK 0x2
1795 #define DISABLE_MAC_SPOOFCHK 0x3
1796
1797 struct amap_set_hsw_context {
1798 u8 interface_id[16];
1799 u8 rsvd0[8];
1800 u8 mac_spoofchk[2];
1801 u8 rsvd1[4];
1802 u8 pvid_valid;
1803 u8 pport;
1804 u8 rsvd2[6];
1805 u8 port_fwd_type[3];
1806 u8 rsvd3[5];
1807 u8 vlan_spoofchk[2];
1808 u8 pvid[16];
1809 u8 rsvd4[32];
1810 u8 rsvd5[32];
1811 u8 rsvd6[32];
1812 } __packed;
1813
1814 struct be_cmd_req_set_hsw_config {
1815 struct be_cmd_req_hdr hdr;
1816 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1817 } __packed;
1818
1819 struct amap_get_hsw_req_context {
1820 u8 interface_id[16];
1821 u8 rsvd0[14];
1822 u8 pvid_valid;
1823 u8 pport;
1824 } __packed;
1825
1826 struct amap_get_hsw_resp_context {
1827 u8 rsvd0[6];
1828 u8 port_fwd_type[3];
1829 u8 rsvd1[5];
1830 u8 spoofchk;
1831 u8 rsvd2;
1832 u8 pvid[16];
1833 u8 rsvd3[32];
1834 u8 rsvd4[32];
1835 u8 rsvd5[32];
1836 } __packed;
1837
1838 struct be_cmd_req_get_hsw_config {
1839 struct be_cmd_req_hdr hdr;
1840 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1841 } __packed;
1842
1843 struct be_cmd_resp_get_hsw_config {
1844 struct be_cmd_resp_hdr hdr;
1845 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1846 u32 rsvd;
1847 };
1848
1849 /******************* get port names ***************/
1850 struct be_cmd_req_get_port_name {
1851 struct be_cmd_req_hdr hdr;
1852 u32 rsvd0;
1853 };
1854
1855 struct be_cmd_resp_get_port_name {
1856 struct be_cmd_req_hdr hdr;
1857 u8 port_name[4];
1858 };
1859
1860 /*************** HW Stats Get v1 **********************************/
1861 #define BE_TXP_SW_SZ 48
1862 struct be_port_rxf_stats_v1 {
1863 u32 rsvd0[12];
1864 u32 rx_crc_errors;
1865 u32 rx_alignment_symbol_errors;
1866 u32 rx_pause_frames;
1867 u32 rx_priority_pause_frames;
1868 u32 rx_control_frames;
1869 u32 rx_in_range_errors;
1870 u32 rx_out_range_errors;
1871 u32 rx_frame_too_long;
1872 u32 rx_address_filtered;
1873 u32 rx_dropped_too_small;
1874 u32 rx_dropped_too_short;
1875 u32 rx_dropped_header_too_small;
1876 u32 rx_dropped_tcp_length;
1877 u32 rx_dropped_runt;
1878 u32 rsvd1[10];
1879 u32 rx_ip_checksum_errs;
1880 u32 rx_tcp_checksum_errs;
1881 u32 rx_udp_checksum_errs;
1882 u32 rsvd2[7];
1883 u32 rx_switched_unicast_packets;
1884 u32 rx_switched_multicast_packets;
1885 u32 rx_switched_broadcast_packets;
1886 u32 rsvd3[3];
1887 u32 tx_pauseframes;
1888 u32 tx_priority_pauseframes;
1889 u32 tx_controlframes;
1890 u32 rsvd4[10];
1891 u32 rxpp_fifo_overflow_drop;
1892 u32 rx_input_fifo_overflow_drop;
1893 u32 pmem_fifo_overflow_drop;
1894 u32 jabber_events;
1895 u32 rsvd5[3];
1896 };
1897
1898
1899 struct be_rxf_stats_v1 {
1900 struct be_port_rxf_stats_v1 port[4];
1901 u32 rsvd0[2];
1902 u32 rx_drops_no_pbuf;
1903 u32 rx_drops_no_txpb;
1904 u32 rx_drops_no_erx_descr;
1905 u32 rx_drops_no_tpre_descr;
1906 u32 rsvd1[6];
1907 u32 rx_drops_too_many_frags;
1908 u32 rx_drops_invalid_ring;
1909 u32 forwarded_packets;
1910 u32 rx_drops_mtu;
1911 u32 rsvd2[14];
1912 };
1913
1914 struct be_erx_stats_v1 {
1915 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1916 u32 rsvd[4];
1917 };
1918
1919 struct be_port_rxf_stats_v2 {
1920 u32 rsvd0[10];
1921 u32 roce_bytes_received_lsd;
1922 u32 roce_bytes_received_msd;
1923 u32 rsvd1[5];
1924 u32 roce_frames_received;
1925 u32 rx_crc_errors;
1926 u32 rx_alignment_symbol_errors;
1927 u32 rx_pause_frames;
1928 u32 rx_priority_pause_frames;
1929 u32 rx_control_frames;
1930 u32 rx_in_range_errors;
1931 u32 rx_out_range_errors;
1932 u32 rx_frame_too_long;
1933 u32 rx_address_filtered;
1934 u32 rx_dropped_too_small;
1935 u32 rx_dropped_too_short;
1936 u32 rx_dropped_header_too_small;
1937 u32 rx_dropped_tcp_length;
1938 u32 rx_dropped_runt;
1939 u32 rsvd2[10];
1940 u32 rx_ip_checksum_errs;
1941 u32 rx_tcp_checksum_errs;
1942 u32 rx_udp_checksum_errs;
1943 u32 rsvd3[7];
1944 u32 rx_switched_unicast_packets;
1945 u32 rx_switched_multicast_packets;
1946 u32 rx_switched_broadcast_packets;
1947 u32 rsvd4[3];
1948 u32 tx_pauseframes;
1949 u32 tx_priority_pauseframes;
1950 u32 tx_controlframes;
1951 u32 rsvd5[10];
1952 u32 rxpp_fifo_overflow_drop;
1953 u32 rx_input_fifo_overflow_drop;
1954 u32 pmem_fifo_overflow_drop;
1955 u32 jabber_events;
1956 u32 rsvd6[3];
1957 u32 rx_drops_payload_size;
1958 u32 rx_drops_clipped_header;
1959 u32 rx_drops_crc;
1960 u32 roce_drops_payload_len;
1961 u32 roce_drops_crc;
1962 u32 rsvd7[19];
1963 };
1964
1965 struct be_rxf_stats_v2 {
1966 struct be_port_rxf_stats_v2 port[4];
1967 u32 rsvd0[2];
1968 u32 rx_drops_no_pbuf;
1969 u32 rx_drops_no_txpb;
1970 u32 rx_drops_no_erx_descr;
1971 u32 rx_drops_no_tpre_descr;
1972 u32 rsvd1[6];
1973 u32 rx_drops_too_many_frags;
1974 u32 rx_drops_invalid_ring;
1975 u32 forwarded_packets;
1976 u32 rx_drops_mtu;
1977 u32 rsvd2[35];
1978 };
1979
1980 struct be_hw_stats_v1 {
1981 struct be_rxf_stats_v1 rxf;
1982 u32 rsvd0[BE_TXP_SW_SZ];
1983 struct be_erx_stats_v1 erx;
1984 struct be_pmem_stats pmem;
1985 u32 rsvd1[18];
1986 };
1987
1988 struct be_cmd_req_get_stats_v1 {
1989 struct be_cmd_req_hdr hdr;
1990 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1991 };
1992
1993 struct be_cmd_resp_get_stats_v1 {
1994 struct be_cmd_resp_hdr hdr;
1995 struct be_hw_stats_v1 hw_stats;
1996 };
1997
1998 struct be_erx_stats_v2 {
1999 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
2000 u32 rsvd[3];
2001 };
2002
2003 struct be_hw_stats_v2 {
2004 struct be_rxf_stats_v2 rxf;
2005 u32 rsvd0[BE_TXP_SW_SZ];
2006 struct be_erx_stats_v2 erx;
2007 struct be_pmem_stats pmem;
2008 u32 rsvd1[18];
2009 };
2010
2011 struct be_cmd_req_get_stats_v2 {
2012 struct be_cmd_req_hdr hdr;
2013 u8 rsvd[sizeof(struct be_hw_stats_v2)];
2014 };
2015
2016 struct be_cmd_resp_get_stats_v2 {
2017 struct be_cmd_resp_hdr hdr;
2018 struct be_hw_stats_v2 hw_stats;
2019 };
2020
2021 /************** get fat capabilites *******************/
2022 #define MAX_MODULES 27
2023 #define MAX_MODES 4
2024 #define MODE_UART 0
2025 #define FW_LOG_LEVEL_DEFAULT 48
2026 #define FW_LOG_LEVEL_FATAL 64
2027
2028 struct ext_fat_mode {
2029 u8 mode;
2030 u8 rsvd0;
2031 u16 port_mask;
2032 u32 dbg_lvl;
2033 u64 fun_mask;
2034 } __packed;
2035
2036 struct ext_fat_modules {
2037 u8 modules_str[32];
2038 u32 modules_id;
2039 u32 num_modes;
2040 struct ext_fat_mode trace_lvl[MAX_MODES];
2041 } __packed;
2042
2043 struct be_fat_conf_params {
2044 u32 max_log_entries;
2045 u32 log_entry_size;
2046 u8 log_type;
2047 u8 max_log_funs;
2048 u8 max_log_ports;
2049 u8 rsvd0;
2050 u32 supp_modes;
2051 u32 num_modules;
2052 struct ext_fat_modules module[MAX_MODULES];
2053 } __packed;
2054
2055 struct be_cmd_req_get_ext_fat_caps {
2056 struct be_cmd_req_hdr hdr;
2057 u32 parameter_type;
2058 };
2059
2060 struct be_cmd_resp_get_ext_fat_caps {
2061 struct be_cmd_resp_hdr hdr;
2062 struct be_fat_conf_params get_params;
2063 };
2064
2065 struct be_cmd_req_set_ext_fat_caps {
2066 struct be_cmd_req_hdr hdr;
2067 struct be_fat_conf_params set_params;
2068 };
2069
2070 #define RESOURCE_DESC_SIZE_V0 72
2071 #define RESOURCE_DESC_SIZE_V1 88
2072 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40
2073 #define NIC_RESOURCE_DESC_TYPE_V0 0x41
2074 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50
2075 #define NIC_RESOURCE_DESC_TYPE_V1 0x51
2076 #define PORT_RESOURCE_DESC_TYPE_V1 0x55
2077 #define MAX_RESOURCE_DESC 264
2078
2079 #define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */
2080 #define VFT_SHIFT 3 /* VF template */
2081 #define IMM_SHIFT 6 /* Immediate */
2082 #define NOSV_SHIFT 7 /* No save */
2083
2084 struct be_res_desc_hdr {
2085 u8 desc_type;
2086 u8 desc_len;
2087 } __packed;
2088
2089 struct be_port_res_desc {
2090 struct be_res_desc_hdr hdr;
2091 u8 rsvd0;
2092 u8 flags;
2093 u8 link_num;
2094 u8 mc_type;
2095 u16 rsvd1;
2096
2097 #define NV_TYPE_MASK 0x3 /* bits 0-1 */
2098 #define NV_TYPE_DISABLED 1
2099 #define NV_TYPE_VXLAN 3
2100 #define SOCVID_SHIFT 2 /* Strip outer vlan */
2101 #define RCVID_SHIFT 4 /* Report vlan */
2102 #define PF_NUM_IGNORE 255
2103 u8 nv_flags;
2104 u8 rsvd2;
2105 __le16 nv_port; /* vxlan/gre port */
2106 u32 rsvd3[19];
2107 } __packed;
2108
2109 struct be_pcie_res_desc {
2110 struct be_res_desc_hdr hdr;
2111 u8 rsvd0;
2112 u8 flags;
2113 u16 rsvd1;
2114 u8 pf_num;
2115 u8 rsvd2;
2116 u32 rsvd3;
2117 u8 sriov_state;
2118 u8 pf_state;
2119 u8 pf_type;
2120 u8 rsvd4;
2121 u16 num_vfs;
2122 u16 rsvd5;
2123 u32 rsvd6[17];
2124 } __packed;
2125
2126 struct be_nic_res_desc {
2127 struct be_res_desc_hdr hdr;
2128 u8 rsvd1;
2129
2130 #define QUN_SHIFT 4 /* QoS is in absolute units */
2131 u8 flags;
2132 u8 vf_num;
2133 u8 rsvd2;
2134 u8 pf_num;
2135 u8 rsvd3;
2136 u16 unicast_mac_count;
2137 u8 rsvd4[6];
2138 u16 mcc_count;
2139 u16 vlan_count;
2140 u16 mcast_mac_count;
2141 u16 txq_count;
2142 u16 rq_count;
2143 u16 rssq_count;
2144 u16 lro_count;
2145 u16 cq_count;
2146 u16 toe_conn_count;
2147 u16 eq_count;
2148 u16 vlan_id;
2149 u16 iface_count;
2150 u32 cap_flags;
2151 u8 link_param;
2152 u8 rsvd6;
2153 u16 channel_id_param;
2154 u32 bw_min;
2155 u32 bw_max;
2156 u8 acpi_params;
2157 u8 wol_param;
2158 u16 rsvd7;
2159 u16 tunnel_iface_count;
2160 u16 direct_tenant_iface_count;
2161 u32 rsvd8[6];
2162 } __packed;
2163
2164 /************ Multi-Channel type ***********/
2165 enum mc_type {
2166 MC_NONE = 0x01,
2167 UMC = 0x02,
2168 FLEX10 = 0x03,
2169 vNIC1 = 0x04,
2170 nPAR = 0x05,
2171 UFP = 0x06,
2172 vNIC2 = 0x07
2173 };
2174
2175 /* Is BE in a multi-channel mode */
2176 static inline bool be_is_mc(struct be_adapter *adapter)
2177 {
2178 return adapter->mc_type > MC_NONE;
2179 }
2180
2181 struct be_cmd_req_get_func_config {
2182 struct be_cmd_req_hdr hdr;
2183 };
2184
2185 struct be_cmd_resp_get_func_config {
2186 struct be_cmd_resp_hdr hdr;
2187 u32 desc_count;
2188 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
2189 };
2190
2191 enum {
2192 RESOURCE_LIMITS,
2193 RESOURCE_MODIFIABLE
2194 };
2195
2196 struct be_cmd_req_get_profile_config {
2197 struct be_cmd_req_hdr hdr;
2198 u8 rsvd;
2199 #define ACTIVE_PROFILE_TYPE 0x2
2200 #define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3)
2201 u8 type;
2202 u16 rsvd1;
2203 };
2204
2205 struct be_cmd_resp_get_profile_config {
2206 struct be_cmd_resp_hdr hdr;
2207 __le16 desc_count;
2208 u16 rsvd;
2209 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
2210 };
2211
2212 #define FIELD_MODIFIABLE 0xFFFF
2213 struct be_cmd_req_set_profile_config {
2214 struct be_cmd_req_hdr hdr;
2215 u32 rsvd;
2216 u32 desc_count;
2217 u8 desc[2 * RESOURCE_DESC_SIZE_V1];
2218 } __packed;
2219
2220 struct be_cmd_req_get_active_profile {
2221 struct be_cmd_req_hdr hdr;
2222 u32 rsvd;
2223 } __packed;
2224
2225 struct be_cmd_resp_get_active_profile {
2226 struct be_cmd_resp_hdr hdr;
2227 u16 active_profile_id;
2228 u16 next_profile_id;
2229 } __packed;
2230
2231 struct be_cmd_enable_disable_vf {
2232 struct be_cmd_req_hdr hdr;
2233 u8 enable;
2234 u8 rsvd[3];
2235 };
2236
2237 struct be_cmd_req_intr_set {
2238 struct be_cmd_req_hdr hdr;
2239 u8 intr_enabled;
2240 u8 rsvd[3];
2241 };
2242
2243 static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
2244 {
2245 return flags & adapter->cmd_privileges ? true : false;
2246 }
2247
2248 /************** Get IFACE LIST *******************/
2249 struct be_if_desc {
2250 u32 if_id;
2251 u32 cap_flags;
2252 u32 en_flags;
2253 };
2254
2255 struct be_cmd_req_get_iface_list {
2256 struct be_cmd_req_hdr hdr;
2257 };
2258
2259 struct be_cmd_resp_get_iface_list {
2260 struct be_cmd_req_hdr hdr;
2261 u32 if_cnt;
2262 struct be_if_desc if_desc;
2263 };
2264
2265 /*************** Set logical link ********************/
2266 #define PLINK_ENABLE BIT(0)
2267 #define PLINK_TRACK BIT(8)
2268 struct be_cmd_req_set_ll_link {
2269 struct be_cmd_req_hdr hdr;
2270 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */
2271 };
2272
2273 /************** Manage IFACE Filters *******************/
2274 #define OP_CONVERT_NORMAL_TO_TUNNEL 0
2275 #define OP_CONVERT_TUNNEL_TO_NORMAL 1
2276
2277 struct be_cmd_req_manage_iface_filters {
2278 struct be_cmd_req_hdr hdr;
2279 u8 op;
2280 u8 rsvd0;
2281 u8 flags;
2282 u8 rsvd1;
2283 u32 tunnel_iface_id;
2284 u32 target_iface_id;
2285 u8 mac[6];
2286 u16 vlan_tag;
2287 u32 tenant_id;
2288 u32 filter_id;
2289 u32 cap_flags;
2290 u32 cap_control_flags;
2291 } __packed;
2292
2293 int be_pci_fnum_get(struct be_adapter *adapter);
2294 int be_fw_wait_ready(struct be_adapter *adapter);
2295 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
2296 bool permanent, u32 if_handle, u32 pmac_id);
2297 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
2298 u32 *pmac_id, u32 domain);
2299 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
2300 u32 domain);
2301 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
2302 u32 *if_handle, u32 domain);
2303 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
2304 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
2305 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
2306 struct be_queue_info *eq, bool no_delay,
2307 int num_cqe_dma_coalesce);
2308 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
2309 struct be_queue_info *cq);
2310 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
2311 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
2312 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
2313 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
2314 int type);
2315 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
2316 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
2317 u8 *link_status, u32 dom);
2318 int be_cmd_reset(struct be_adapter *adapter);
2319 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2320 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2321 struct be_dma_mem *nonemb_cmd);
2322 int be_cmd_get_fw_ver(struct be_adapter *adapter);
2323 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
2324 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
2325 u32 num, u32 domain);
2326 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2327 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2328 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
2329 int be_cmd_query_fw_cfg(struct be_adapter *adapter);
2330 int be_cmd_reset_function(struct be_adapter *adapter);
2331 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2332 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey);
2333 int be_process_mcc(struct be_adapter *adapter);
2334 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2335 u8 status, u8 state);
2336 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2337 u32 *state);
2338 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2339 u8 page_num, u8 *data);
2340 int be_cmd_query_cable_type(struct be_adapter *adapter);
2341 int be_cmd_query_sfp_info(struct be_adapter *adapter);
2342 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2343 u32 data_size, u32 data_offset, const char *obj_name,
2344 u32 *data_read, u32 *eof, u8 *addn_status);
2345 int lancer_fw_download(struct be_adapter *adapter, const struct firmware *fw);
2346 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw);
2347 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2348 struct be_dma_mem *nonemb_cmd);
2349 int be_cmd_fw_init(struct be_adapter *adapter);
2350 int be_cmd_fw_clean(struct be_adapter *adapter);
2351 void be_async_mcc_enable(struct be_adapter *adapter);
2352 void be_async_mcc_disable(struct be_adapter *adapter);
2353 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2354 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2355 u64 pattern);
2356 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2357 struct be_dma_mem *cmd);
2358 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2359 struct be_dma_mem *nonemb_cmd);
2360 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2361 u8 loopback_type, u8 enable);
2362 int be_cmd_get_phy_info(struct be_adapter *adapter);
2363 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate,
2364 u16 link_speed, u8 domain);
2365 void be_detect_error(struct be_adapter *adapter);
2366 int be_cmd_get_die_temperature(struct be_adapter *adapter);
2367 int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2368 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size);
2369 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf);
2370 int be_cmd_req_native_mode(struct be_adapter *adapter);
2371 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2372 u32 domain);
2373 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2374 u32 vf_num);
2375 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2376 bool *pmac_id_active, u32 *pmac_id,
2377 u32 if_handle, u8 domain);
2378 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2379 u32 if_handle, bool active, u32 domain);
2380 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2381 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2382 u32 domain);
2383 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2384 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
2385 u16 intf_id, u16 hsw_mode, u8 spoofchk);
2386 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
2387 u16 intf_id, u8 *mode, bool *spoofchk);
2388 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
2389 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2390 int be_cmd_get_fw_log_level(struct be_adapter *adapter);
2391 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2392 struct be_dma_mem *cmd);
2393 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2394 struct be_dma_mem *cmd,
2395 struct be_fat_conf_params *cfgs);
2396 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2397 int lancer_initiate_dump(struct be_adapter *adapter);
2398 int lancer_delete_dump(struct be_adapter *adapter);
2399 bool dump_present(struct be_adapter *adapter);
2400 int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
2401 int be_cmd_query_port_name(struct be_adapter *adapter);
2402 int be_cmd_get_func_config(struct be_adapter *adapter,
2403 struct be_resources *res);
2404 int be_cmd_get_profile_config(struct be_adapter *adapter,
2405 struct be_resources *res, u8 query, u8 domain);
2406 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
2407 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2408 int vf_num);
2409 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2410 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
2411 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
2412 int link_state, u8 domain);
2413 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port);
2414 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op);
2415 int be_cmd_set_sriov_config(struct be_adapter *adapter,
2416 struct be_resources res, u16 num_vfs,
2417 u16 num_vf_qs);
(deprecated) Btrfs devel tree