drivers/video/via/viamode.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  26 {VIASR, SR15, 0x02, 0x02},
  27 {VIASR, SR16, 0xBF, 0x08},
  28 {VIASR, SR17, 0xFF, 0x1F},
  29 {VIASR, SR18, 0xFF, 0x4E},
  30 {VIASR, SR1A, 0xFB, 0x08},
  31 {VIASR, SR1E, 0x0F, 0x01},
  32 {VIASR, SR2A, 0xFF, 0x00},
  33 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
  34 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
  35 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
  36 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
  37 {VIACR, CR32, 0xFF, 0x00},
  38 {VIACR, CR33, 0xFF, 0x00},
  39 {VIACR, CR35, 0xFF, 0x00},
  40 {VIACR, CR36, 0x08, 0x00},
  41 {VIACR, CR69, 0xFF, 0x00},
  42 {VIACR, CR6A, 0xFF, 0x40},
  43 {VIACR, CR6B, 0xFF, 0x00},
  44 {VIACR, CR6C, 0xFF, 0x00},
  45 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1             */
  46 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2             */
  47 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3             */
  48 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4             */
  49 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5             */
  50 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6             */
  51 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7             */
  52 {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8             */
  53 {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9             */
  54 {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10            */
  55 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11            */
  56 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12            */
  57 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13            */
  58 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14            */
  59 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
  60 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
  61 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
  62 {VIACR, CR8B, 0xFF, 0x69},      /* LCD Power Sequence Control 0        */
  63 {VIACR, CR8C, 0xFF, 0x57},      /* LCD Power Sequence Control 1        */
  64 {VIACR, CR8D, 0xFF, 0x00},      /* LCD Power Sequence Control 2        */
  65 {VIACR, CR8E, 0xFF, 0x7B},      /* LCD Power Sequence Control 3        */
  66 {VIACR, CR8F, 0xFF, 0x03},      /* LCD Power Sequence Control 4        */
  67 {VIACR, CR90, 0xFF, 0x30},      /* LCD Power Sequence Control 5        */
  68 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off             */
  69 {VIACR, CR96, 0xFF, 0x00},
  70 {VIACR, CR97, 0xFF, 0x00},
  71 {VIACR, CR99, 0xFF, 0x00},
  72 {VIACR, CR9B, 0xFF, 0x00}
  73 };
  74
  75 /* Video Mode Table for VT3314 chipset*/
  76 /* Common Setting for Video Mode */
  77 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  78 {VIASR, SR15, 0x02, 0x02},
  79 {VIASR, SR16, 0xBF, 0x08},
  80 {VIASR, SR17, 0xFF, 0x1F},
  81 {VIASR, SR18, 0xFF, 0x4E},
  82 {VIASR, SR1A, 0xFB, 0x82},
  83 {VIASR, SR1B, 0xFF, 0xF0},
  84 {VIASR, SR1F, 0xFF, 0x00},
  85 {VIASR, SR1E, 0xFF, 0x01},
  86 {VIASR, SR22, 0xFF, 0x1F},
  87 {VIASR, SR2A, 0x0F, 0x00},
  88 {VIASR, SR2E, 0xFF, 0xFF},
  89 {VIASR, SR3F, 0xFF, 0xFF},
  90 {VIASR, SR40, 0xF7, 0x00},
  91 {VIASR, CR30, 0xFF, 0x04},
  92 {VIACR, CR32, 0xFF, 0x00},
  93 {VIACR, CR33, 0x7F, 0x00},
  94 {VIACR, CR35, 0xFF, 0x00},
  95 {VIACR, CR36, 0xFF, 0x31},
  96 {VIACR, CR41, 0xFF, 0x80},
  97 {VIACR, CR42, 0xFF, 0x00},
  98 {VIACR, CR55, 0x80, 0x00},
  99 {VIACR, CR5D, 0x80, 0x00},      /*Horizontal Retrace Start bit[11] should be 0*/
 100 {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2 */
 101 {VIACR, CR69, 0xFF, 0x00},
 102 {VIACR, CR6A, 0xFD, 0x40},
 103 {VIACR, CR6B, 0xFF, 0x00},
 104 {VIACR, CR6C, 0xFF, 0x00},
 105 {VIACR, CR77, 0xFF, 0x00},      /* LCD scaling Factor */
 106 {VIACR, CR78, 0xFF, 0x00},      /* LCD scaling Factor */
 107 {VIACR, CR79, 0xFF, 0x00},      /* LCD scaling Factor */
 108 {VIACR, CR9F, 0x03, 0x00},      /* LCD scaling Factor */
 109 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
 110 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
 111 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
 112 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
 113 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
 114 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
 115 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
 116 {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
 117 {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
 118 {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
 119 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
 120 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
 121 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
 122 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 123 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type */
 124 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0 */
 125 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1 */
 126 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0 */
 127 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1 */
 128 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2 */
 129 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3 */
 130 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4 */
 131 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5 */
 132 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off */
 133 {VIACR, CR96, 0xFF, 0x00},
 134 {VIACR, CR97, 0xFF, 0x00},
 135 {VIACR, CR99, 0xFF, 0x00},
 136 {VIACR, CR9B, 0xFF, 0x00},
 137 {VIACR, CR9D, 0xFF, 0x80},
 138 {VIACR, CR9E, 0xFF, 0x80}
 139 };
 140
 141 struct io_reg KM400_ModeXregs[] = {
 142         {VIASR, SR10, 0xFF, 0x01},      /* Unlock Register                 */
 143         {VIASR, SR16, 0xFF, 0x08},      /* Display FIFO threshold Control  */
 144         {VIASR, SR17, 0xFF, 0x1F},      /* Display FIFO Control            */
 145         {VIASR, SR18, 0xFF, 0x4E},      /* GFX PREQ threshold              */
 146         {VIASR, SR1A, 0xFF, 0x0a},      /* GFX PREQ threshold              */
 147         {VIASR, SR1F, 0xFF, 0x00},      /* Memory Control 0                */
 148         {VIASR, SR1B, 0xFF, 0xF0},      /* Power Management Control 0      */
 149         {VIASR, SR1E, 0xFF, 0x01},      /* Power Management Control        */
 150         {VIASR, SR20, 0xFF, 0x00},      /* Sequencer Arbiter Control 0     */
 151         {VIASR, SR21, 0xFF, 0x00},      /* Sequencer Arbiter Control 1     */
 152         {VIASR, SR22, 0xFF, 0x1F},      /* Display Arbiter Control 1       */
 153         {VIASR, SR2A, 0xFF, 0x00},      /* Power Management Control 5      */
 154         {VIASR, SR2D, 0xFF, 0xFF},      /* Power Management Control 1      */
 155         {VIASR, SR2E, 0xFF, 0xFF},      /* Power Management Control 2      */
 156         {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                    */
 157         {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                      */
 158         {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High            */
 159         {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low            */
 160         {VIACR, CR33, 0xFF, 0x00},
 161         {VIACR, CR55, 0x80, 0x00},
 162         {VIACR, CR5D, 0x80, 0x00},
 163         {VIACR, CR36, 0xFF, 0x01},      /* Power Mangement 3                  */
 164         {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2              */
 165         {VIACR, CR6A, 0x20, 0x20},      /* Extended FIFO On                   */
 166         {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1            */
 167         {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2            */
 168         {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3            */
 169         {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4            */
 170         {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5            */
 171         {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6            */
 172         {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7            */
 173         {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8            */
 174         {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9            */
 175         {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10           */
 176         {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11           */
 177         {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12           */
 178         {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13           */
 179         {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14           */
 180         {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                     */
 181         {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0               */
 182         {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1               */
 183         {VIACR, CR8B, 0xFF, 0x2D},      /* LCD Power Sequence Control 0       */
 184         {VIACR, CR8C, 0xFF, 0x2D},      /* LCD Power Sequence Control 1       */
 185         {VIACR, CR8D, 0xFF, 0xC8},      /* LCD Power Sequence Control 2       */
 186         {VIACR, CR8E, 0xFF, 0x36},      /* LCD Power Sequence Control 3       */
 187         {VIACR, CR8F, 0xFF, 0x00},      /* LCD Power Sequence Control 4       */
 188         {VIACR, CR90, 0xFF, 0x10},      /* LCD Power Sequence Control 5       */
 189         {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off            */
 190         {VIACR, CR96, 0xFF, 0x03},      /* DVP0        ; DVP0 Clock Skew */
 191         {VIACR, CR97, 0xFF, 0x03},      /* DFP high    ; DFPH Clock Skew */
 192         {VIACR, CR99, 0xFF, 0x03},      /* DFP low           ; DFPL Clock Skew*/
 193         {VIACR, CR9B, 0xFF, 0x07}       /* DVI on DVP1       ; DVP1 Clock Skew*/
 194 };
 195
 196 /* For VT3324: Common Setting for Video Mode */
 197 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 198 {VIASR, SR15, 0x02, 0x02},
 199 {VIASR, SR16, 0xBF, 0x08},
 200 {VIASR, SR17, 0xFF, 0x1F},
 201 {VIASR, SR18, 0xFF, 0x4E},
 202 {VIASR, SR1A, 0xFB, 0x08},
 203 {VIASR, SR1B, 0xFF, 0xF0},
 204 {VIASR, SR1E, 0xFF, 0x01},
 205 {VIASR, SR2A, 0xFF, 0x00},
 206 {VIASR, SR2D, 0xFF, 0xFF},      /* VCK and LCK PLL power on.           */
 207 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
 208 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
 209 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 210 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 211 {VIACR, CR32, 0xFF, 0x00},
 212 {VIACR, CR33, 0xFF, 0x00},
 213 {VIACR, CR35, 0xFF, 0x00},
 214 {VIACR, CR36, 0x08, 0x00},
 215 {VIACR, CR47, 0xC8, 0x00},      /* Clear VCK Plus. */
 216 {VIACR, CR69, 0xFF, 0x00},
 217 {VIACR, CR6A, 0xFF, 0x40},
 218 {VIACR, CR6B, 0xFF, 0x00},
 219 {VIACR, CR6C, 0xFF, 0x00},
 220 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1             */
 221 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2             */
 222 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3             */
 223 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4             */
 224 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5             */
 225 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6             */
 226 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7             */
 227 {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8             */
 228 {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9             */
 229 {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10            */
 230 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11            */
 231 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12            */
 232 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13            */
 233 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14            */
 234 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 235 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 236 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
 237 {VIACR, CRD4, 0xFF, 0x81},      /* Second power sequence control       */
 238 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0        */
 239 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1        */
 240 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2        */
 241 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3        */
 242 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4        */
 243 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5        */
 244 {VIACR, CR91, 0xFF, 0x80},      /* 24/12 bit LVDS Data off             */
 245 {VIACR, CR96, 0xFF, 0x00},
 246 {VIACR, CR97, 0xFF, 0x00},
 247 {VIACR, CR99, 0xFF, 0x00},
 248 {VIACR, CR9B, 0xFF, 0x00}
 249 };
 250
 251 struct io_reg VX855_ModeXregs[] = {
 252 {VIASR, SR10, 0xFF, 0x01},
 253 {VIASR, SR15, 0x02, 0x02},
 254 {VIASR, SR16, 0xBF, 0x08},
 255 {VIASR, SR17, 0xFF, 0x1F},
 256 {VIASR, SR18, 0xFF, 0x4E},
 257 {VIASR, SR1A, 0xFB, 0x08},
 258 {VIASR, SR1B, 0xFF, 0xF0},
 259 {VIASR, SR1E, 0x07, 0x01},
 260 {VIASR, SR2A, 0xF0, 0x00},
 261 {VIASR, SR58, 0xFF, 0x00},
 262 {VIASR, SR59, 0xFF, 0x00},
 263 {VIASR, SR2D, 0xFF, 0xFF},      /* VCK and LCK PLL power on.           */
 264 {VIACR, CR09, 0xFF, 0x00},      /* Initial CR09=0*/
 265 {VIACR, CR11, 0x8F, 0x00},      /* IGA1 initial  Vertical end       */
 266 {VIACR, CR17, 0x7F, 0x00},      /* IGA1 CRT Mode control init   */
 267 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
 268 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
 269 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 270 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 271 {VIACR, CR32, 0xFF, 0x00},
 272 {VIACR, CR33, 0x7F, 0x00},
 273 {VIACR, CR35, 0xFF, 0x00},
 274 {VIACR, CR36, 0x08, 0x00},
 275 {VIACR, CR69, 0xFF, 0x00},
 276 {VIACR, CR6A, 0xFD, 0x60},
 277 {VIACR, CR6B, 0xFF, 0x00},
 278 {VIACR, CR6C, 0xFF, 0x00},
 279 {VIACR, CR7A, 0xFF, 0x01},          /* LCD Scaling Parameter 1             */
 280 {VIACR, CR7B, 0xFF, 0x02},          /* LCD Scaling Parameter 2             */
 281 {VIACR, CR7C, 0xFF, 0x03},          /* LCD Scaling Parameter 3             */
 282 {VIACR, CR7D, 0xFF, 0x04},          /* LCD Scaling Parameter 4             */
 283 {VIACR, CR7E, 0xFF, 0x07},          /* LCD Scaling Parameter 5             */
 284 {VIACR, CR7F, 0xFF, 0x0A},          /* LCD Scaling Parameter 6             */
 285 {VIACR, CR80, 0xFF, 0x0D},          /* LCD Scaling Parameter 7             */
 286 {VIACR, CR81, 0xFF, 0x13},          /* LCD Scaling Parameter 8             */
 287 {VIACR, CR82, 0xFF, 0x16},          /* LCD Scaling Parameter 9             */
 288 {VIACR, CR83, 0xFF, 0x19},          /* LCD Scaling Parameter 10            */
 289 {VIACR, CR84, 0xFF, 0x1C},          /* LCD Scaling Parameter 11            */
 290 {VIACR, CR85, 0xFF, 0x1D},          /* LCD Scaling Parameter 12            */
 291 {VIACR, CR86, 0xFF, 0x1E},          /* LCD Scaling Parameter 13            */
 292 {VIACR, CR87, 0xFF, 0x1F},          /* LCD Scaling Parameter 14            */
 293 {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
 294 {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
 295 {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
 296 {VIACR, CRD4, 0xFF, 0x81},          /* Second power sequence control       */
 297 {VIACR, CR91, 0xFF, 0x80},          /* 24/12 bit LVDS Data off             */
 298 {VIACR, CR96, 0xFF, 0x00},
 299 {VIACR, CR97, 0xFF, 0x00},
 300 {VIACR, CR99, 0xFF, 0x00},
 301 {VIACR, CR9B, 0xFF, 0x00},
 302 {VIACR, CRD2, 0xFF, 0xFF}           /* TMDS/LVDS control register.         */
 303 };
 304
 305 /* Video Mode Table */
 306 /* Common Setting for Video Mode */
 307 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
 308 {VIASR, SR2A, 0x0F, 0x00},
 309 {VIASR, SR15, 0x02, 0x02},
 310 {VIASR, SR16, 0xBF, 0x08},
 311 {VIASR, SR17, 0xFF, 0x1F},
 312 {VIASR, SR18, 0xFF, 0x4E},
 313 {VIASR, SR1A, 0xFB, 0x08},
 314
 315 {VIACR, CR32, 0xFF, 0x00},
 316 {VIACR, CR35, 0xFF, 0x00},
 317 {VIACR, CR36, 0x08, 0x00},
 318 {VIACR, CR6A, 0xFF, 0x80},
 319 {VIACR, CR6A, 0xFF, 0xC0},
 320
 321 {VIACR, CR55, 0x80, 0x00},
 322 {VIACR, CR5D, 0x80, 0x00},
 323
 324 {VIAGR, GR20, 0xFF, 0x00},
 325 {VIAGR, GR21, 0xFF, 0x00},
 326 {VIAGR, GR22, 0xFF, 0x00},
 327         /* LCD Parameters */
 328 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Parameter 1 */
 329 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Parameter 2 */
 330 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Parameter 3 */
 331 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Parameter 4 */
 332 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Parameter 5 */
 333 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Parameter 6 */
 334 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Parameter 7 */
 335 {VIACR, CR81, 0xFF, 0x13},      /* LCD Parameter 8 */
 336 {VIACR, CR82, 0xFF, 0x16},      /* LCD Parameter 9 */
 337 {VIACR, CR83, 0xFF, 0x19},      /* LCD Parameter 10 */
 338 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Parameter 11 */
 339 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Parameter 12 */
 340 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Parameter 13 */
 341 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Parameter 14 */
 342
 343 };
 344
 345 /* Mode:1024X768 */
 346 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
 347 {VIASR, 0x18, 0xFF, 0x4C}
 348 };
 349
 350 struct patch_table res_patch_table[] = {
 351         {ARRAY_SIZE(PM1024x768), PM1024x768}
 352 };
 353
 354 /* struct VPITTable {
 355         unsigned char  Misc;
 356         unsigned char  SR[StdSR];
 357         unsigned char  CR[StdCR];
 358         unsigned char  GR[StdGR];
 359         unsigned char  AR[StdAR];
 360  };*/
 361
 362 struct VPITTable VPIT = {
 363         /* Msic */
 364         0xC7,
 365         /* Sequencer */
 366         {0x01, 0x0F, 0x00, 0x0E},
 367         /* Graphic Controller */
 368         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
 369         /* Attribute Controller */
 370         {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 371          0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 372          0x01, 0x00, 0x0F, 0x00}
 373 };
 374
 375 /********************/
 376 /* Mode Table       */
 377 /********************/
 378
 379 /* 480x640 */
 380 static struct crt_mode_table CRTM480x640[] = {
 381         /* r_rate,              hsp,             vsp   */
 382         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 383         {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
 384          {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} }     /* GTF*/
 385 };
 386
 387 /* 640x480*/
 388 static struct crt_mode_table CRTM640x480[] = {
 389         /*r_rate,hsp,vsp */
 390         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 391         {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
 392          {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
 393         {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
 394          {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
 395         {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
 396          {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
 397         {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
 398          {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
 399         {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
 400          {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
 401 };
 402
 403 /*720x480 (GTF)*/
 404 static struct crt_mode_table CRTM720x480[] = {
 405         /*r_rate,hsp,vsp      */
 406         /*HT, HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 407         {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
 408          {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
 409
 410 };
 411
 412 /*720x576 (GTF)*/
 413 static struct crt_mode_table CRTM720x576[] = {
 414         /*r_rate,hsp,vsp */
 415         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 416         {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
 417          {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
 418 };
 419
 420 /* 800x480 (CVT) */
 421 static struct crt_mode_table CRTM800x480[] = {
 422         /* r_rate,              hsp,             vsp   */
 423         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 424         {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
 425          {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
 426 };
 427
 428 /* 800x600*/
 429 static struct crt_mode_table CRTM800x600[] = {
 430         /*r_rate,hsp,vsp     */
 431         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 432         {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
 433          {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
 434         {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
 435          {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
 436         {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
 437          {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
 438         {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
 439          {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
 440         {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
 441          {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
 442 };
 443
 444 /* 848x480 (CVT) */
 445 static struct crt_mode_table CRTM848x480[] = {
 446         /* r_rate,              hsp,             vsp   */
 447         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 448         {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
 449          {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
 450 };
 451
 452 /*856x480 (GTF) convert to 852x480*/
 453 static struct crt_mode_table CRTM852x480[] = {
 454         /*r_rate,hsp,vsp     */
 455         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 456         {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
 457         {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
 458 };
 459
 460 /*1024x512 (GTF)*/
 461 static struct crt_mode_table CRTM1024x512[] = {
 462         /*r_rate,hsp,vsp     */
 463         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 464         {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
 465          {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
 466
 467 };
 468
 469 /* 1024x600*/
 470 static struct crt_mode_table CRTM1024x600[] = {
 471         /*r_rate,hsp,vsp */
 472         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 473         {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
 474          {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
 475 };
 476
 477 /* 1024x768*/
 478 static struct crt_mode_table CRTM1024x768[] = {
 479         /*r_rate,hsp,vsp */
 480         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 481         {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
 482         {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
 483         {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
 484         {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
 485         {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
 486         {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
 487         {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
 488         {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
 489 };
 490
 491 /* 1152x864*/
 492 static struct crt_mode_table CRTM1152x864[] = {
 493         /*r_rate,hsp,vsp      */
 494         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 495         {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
 496          {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
 497
 498 };
 499
 500 /* 1280x720 (HDMI 720P)*/
 501 static struct crt_mode_table CRTM1280x720[] = {
 502         /*r_rate,hsp,vsp */
 503         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE      */
 504         {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
 505          {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
 506         {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
 507          {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
 508 };
 509
 510 /*1280x768 (GTF)*/
 511 static struct crt_mode_table CRTM1280x768[] = {
 512         /*r_rate,hsp,vsp     */
 513         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 514         {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
 515          {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
 516         {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
 517          {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
 518 };
 519
 520 /* 1280x800 (CVT) */
 521 static struct crt_mode_table CRTM1280x800[] = {
 522         /* r_rate,              hsp,             vsp   */
 523         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 524         {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
 525          {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
 526 };
 527
 528 /*1280x960*/
 529 static struct crt_mode_table CRTM1280x960[] = {
 530         /*r_rate,hsp,vsp */
 531         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 532         {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
 533          {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
 534 };
 535
 536 /* 1280x1024*/
 537 static struct crt_mode_table CRTM1280x1024[] = {
 538         /*r_rate,hsp,vsp */
 539         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 540         {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
 541          {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
 542           3} },
 543         {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
 544          {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
 545           3} },
 546         {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
 547          {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
 548 };
 549
 550 /* 1368x768 (GTF) */
 551 static struct crt_mode_table CRTM1368x768[] = {
 552         /* r_rate,  hsp, vsp */
 553         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 554         {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
 555          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
 556 };
 557
 558 /*1440x1050 (GTF)*/
 559 static struct crt_mode_table CRTM1440x1050[] = {
 560         /*r_rate,hsp,vsp      */
 561         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 562         {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
 563          {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
 564 };
 565
 566 /* 1600x1200*/
 567 static struct crt_mode_table CRTM1600x1200[] = {
 568         /*r_rate,hsp,vsp */
 569         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 570         {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
 571          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
 572           3} },
 573         {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
 574          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
 575
 576 };
 577
 578 /* 1680x1050 (CVT) */
 579 static struct crt_mode_table CRTM1680x1050[] = {
 580         /* r_rate,              hsp,             vsp  */
 581         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 582         {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
 583          {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
 584           6} },
 585         {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
 586          {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
 587 };
 588
 589 /* 1680x1050 (CVT Reduce Blanking) */
 590 static struct crt_mode_table CRTM1680x1050_RB[] = {
 591         /* r_rate,              hsp,             vsp   */
 592         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 593         {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
 594          {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
 595 };
 596
 597 /* 1920x1080 (CVT)*/
 598 static struct crt_mode_table CRTM1920x1080[] = {
 599         /*r_rate,hsp,vsp */
 600         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 601         {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
 602          {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
 603 };
 604
 605 /* 1920x1080 (CVT with Reduce Blanking) */
 606 static struct crt_mode_table CRTM1920x1080_RB[] = {
 607         /* r_rate,              hsp,             vsp   */
 608         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 609         {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
 610          {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
 611 };
 612
 613 /* 1920x1440*/
 614 static struct crt_mode_table CRTM1920x1440[] = {
 615         /*r_rate,hsp,vsp */
 616         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 617         {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
 618          {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
 619           3} },
 620         {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
 621          {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
 622 };
 623
 624 /* 1400x1050 (CVT) */
 625 static struct crt_mode_table CRTM1400x1050[] = {
 626         /* r_rate,              hsp,             vsp   */
 627         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 628         {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
 629          {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
 630           4} },
 631         {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
 632          {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
 633 };
 634
 635 /* 1400x1050 (CVT Reduce Blanking) */
 636 static struct crt_mode_table CRTM1400x1050_RB[] = {
 637         /* r_rate,              hsp,             vsp   */
 638         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 639         {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
 640          {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
 641 };
 642
 643 /* 960x600 (CVT) */
 644 static struct crt_mode_table CRTM960x600[] = {
 645         /* r_rate,          hsp,             vsp   */
 646         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 647         {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
 648          {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
 649 };
 650
 651 /* 1000x600 (GTF) */
 652 static struct crt_mode_table CRTM1000x600[] = {
 653         /* r_rate,              hsp,             vsp   */
 654         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 655         {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
 656          {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
 657 };
 658
 659 /* 1024x576 (GTF) */
 660 static struct crt_mode_table CRTM1024x576[] = {
 661         /* r_rate,              hsp,             vsp   */
 662         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 663         {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
 664          {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
 665 };
 666
 667 /* 1088x612 (CVT) */
 668 static struct crt_mode_table CRTM1088x612[] = {
 669         /* r_rate,              hsp,             vsp   */
 670         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 671         {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
 672          {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
 673 };
 674
 675 /* 1152x720 (CVT) */
 676 static struct crt_mode_table CRTM1152x720[] = {
 677         /* r_rate,              hsp,             vsp   */
 678         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 679         {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
 680          {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
 681 };
 682
 683 /* 1200x720 (GTF) */
 684 static struct crt_mode_table CRTM1200x720[] = {
 685         /* r_rate,              hsp,             vsp   */
 686         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 687         {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
 688          {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
 689 };
 690
 691 /* 1200x900 (DCON) */
 692 static struct crt_mode_table DCON1200x900[] = {
 693         /* r_rate,               hsp,               vsp   */
 694         {REFRESH_60, M1200X900_R60_HSP, M1200X900_R60_VSP,
 695         /* The correct htotal is 1240, but this doesn't raster on VX855. */
 696         /* Via suggested changing to a multiple of 16, hence 1264.       */
 697         /*  HT,   HA,  HBS, HBE,  HSS, HSE,  VT,  VA, VBS, VBE, VSS, VSE */
 698          {1264, 1200, 1200,  64, 1211,  32, 912, 900, 900,  12, 901, 10} }
 699 };
 700
 701 /* 1280x600 (GTF) */
 702 static struct crt_mode_table CRTM1280x600[] = {
 703         /* r_rate,              hsp,             vsp   */
 704         /* HT,  HA,  HBS, HBE,  HSS, HSE, VT,  VA,  VBS, VBE,  VSS, VSE */
 705         {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
 706          {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
 707 };
 708
 709 /* 1360x768 (CVT) */
 710 static struct crt_mode_table CRTM1360x768[] = {
 711         /* r_rate,              hsp,             vsp   */
 712         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 713         {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
 714          {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
 715 };
 716
 717 /* 1360x768 (CVT Reduce Blanking) */
 718 static struct crt_mode_table CRTM1360x768_RB[] = {
 719         /* r_rate,              hsp,             vsp   */
 720         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 721         {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
 722          {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
 723 };
 724
 725 /* 1366x768 (GTF) */
 726 static struct crt_mode_table CRTM1366x768[] = {
 727         /* r_rate,          hsp,             vsp   */
 728         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 729         {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
 730          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
 731         {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
 732          {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
 733 };
 734
 735 /* 1440x900 (CVT) */
 736 static struct crt_mode_table CRTM1440x900[] = {
 737         /* r_rate,              hsp,             vsp   */
 738         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 739         {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
 740          {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
 741         {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
 742          {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
 743 };
 744
 745 /* 1440x900 (CVT Reduce Blanking) */
 746 static struct crt_mode_table CRTM1440x900_RB[] = {
 747         /* r_rate,              hsp,             vsp   */
 748         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 749         {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
 750          {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
 751 };
 752
 753 /* 1600x900 (CVT) */
 754 static struct crt_mode_table CRTM1600x900[] = {
 755         /* r_rate,          hsp,             vsp   */
 756         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 757         {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
 758          {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
 759 };
 760
 761 /* 1600x900 (CVT Reduce Blanking) */
 762 static struct crt_mode_table CRTM1600x900_RB[] = {
 763         /* r_rate,           hsp,        vsp   */
 764         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 765         {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
 766          {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
 767 };
 768
 769 /* 1600x1024 (GTF) */
 770 static struct crt_mode_table CRTM1600x1024[] = {
 771         /* r_rate,          hsp,             vsp   */
 772         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 773         {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
 774          {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
 775 };
 776
 777 /* 1792x1344 (DMT) */
 778 static struct crt_mode_table CRTM1792x1344[] = {
 779         /* r_rate,              hsp,             vsp   */
 780         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 781         {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
 782          {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
 783 };
 784
 785 /* 1856x1392 (DMT) */
 786 static struct crt_mode_table CRTM1856x1392[] = {
 787         /* r_rate,              hsp,             vsp   */
 788         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 789         {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
 790          {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
 791 };
 792
 793 /* 1920x1200 (CVT) */
 794 static struct crt_mode_table CRTM1920x1200[] = {
 795         /* r_rate,              hsp,             vsp   */
 796         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 797         {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
 798          {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
 799 };
 800
 801 /* 1920x1200 (CVT with Reduce Blanking) */
 802 static struct crt_mode_table CRTM1920x1200_RB[] = {
 803         /* r_rate,              hsp,             vsp   */
 804         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 805         {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
 806          {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
 807 };
 808
 809 /* 2048x1536 (CVT) */
 810 static struct crt_mode_table CRTM2048x1536[] = {
 811         /* r_rate,              hsp,             vsp   */
 812         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 813         {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
 814          {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
 815 };
 816
 817 static struct VideoModeTable viafb_modes[] = {
 818         /* Display : 480x640 (GTF) */
 819         {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
 820
 821         /* Display : 640x480 */
 822         {CRTM640x480, ARRAY_SIZE(CRTM640x480)},
 823
 824         /* Display : 720x480 (GTF) */
 825         {CRTM720x480, ARRAY_SIZE(CRTM720x480)},
 826
 827         /* Display : 720x576 (GTF) */
 828         {CRTM720x576, ARRAY_SIZE(CRTM720x576)},
 829
 830         /* Display : 800x600 */
 831         {CRTM800x600, ARRAY_SIZE(CRTM800x600)},
 832
 833         /* Display : 800x480 (CVT) */
 834         {CRTM800x480, ARRAY_SIZE(CRTM800x480)},
 835
 836         /* Display : 848x480 (CVT) */
 837         {CRTM848x480, ARRAY_SIZE(CRTM848x480)},
 838
 839         /* Display : 852x480 (GTF) */
 840         {CRTM852x480, ARRAY_SIZE(CRTM852x480)},
 841
 842         /* Display : 1024x512 (GTF) */
 843         {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
 844
 845         /* Display : 1024x600 */
 846         {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
 847
 848         /* Display : 1024x768 */
 849         {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
 850
 851         /* Display : 1152x864 */
 852         {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
 853
 854         /* Display : 1280x768 (GTF) */
 855         {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
 856
 857         /* Display : 960x600 (CVT) */
 858         {CRTM960x600, ARRAY_SIZE(CRTM960x600)},
 859
 860         /* Display : 1000x600 (GTF) */
 861         {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
 862
 863         /* Display : 1024x576 (GTF) */
 864         {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
 865
 866         /* Display : 1088x612 (GTF) */
 867         {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
 868
 869         /* Display : 1152x720 (CVT) */
 870         {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
 871
 872         /* Display : 1200x720 (GTF) */
 873         {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
 874
 875         /* Display : 1200x900 (DCON) */
 876         {DCON1200x900, ARRAY_SIZE(DCON1200x900)},
 877
 878         /* Display : 1280x600 (GTF) */
 879         {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
 880
 881         /* Display : 1280x800 (CVT) */
 882         {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
 883
 884         /* Display : 1280x960 */
 885         {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
 886
 887         /* Display : 1280x1024 */
 888         {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
 889
 890         /* Display : 1360x768 (CVT) */
 891         {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
 892
 893         /* Display : 1366x768 */
 894         {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
 895
 896         /* Display : 1368x768 (GTF) */
 897         {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
 898
 899         /* Display : 1440x900 (CVT) */
 900         {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
 901
 902         /* Display : 1440x1050 (GTF) */
 903         {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
 904
 905         /* Display : 1600x900 (CVT) */
 906         {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
 907
 908         /* Display : 1600x1024 (GTF) */
 909         {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
 910
 911         /* Display : 1600x1200 */
 912         {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
 913
 914         /* Display : 1680x1050 (CVT) */
 915         {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
 916
 917         /* Display : 1792x1344 (DMT) */
 918         {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
 919
 920         /* Display : 1856x1392 (DMT) */
 921         {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
 922
 923         /* Display : 1920x1440 */
 924         {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
 925
 926         /* Display : 2048x1536 */
 927         {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
 928
 929         /* Display : 1280x720 */
 930         {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
 931
 932         /* Display : 1920x1080 (CVT) */
 933         {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
 934
 935         /* Display : 1920x1200 (CVT) */
 936         {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
 937
 938         /* Display : 1400x1050 (CVT) */
 939         {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
 940 };
 941
 942 static struct VideoModeTable viafb_rb_modes[] = {
 943         /* Display : 1360x768 (CVT Reduce Blanking) */
 944         {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
 945
 946         /* Display : 1440x900 (CVT Reduce Blanking) */
 947         {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)},
 948
 949         /* Display : 1400x1050 (CVT Reduce Blanking) */
 950         {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)},
 951
 952         /* Display : 1600x900 (CVT Reduce Blanking) */
 953         {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)},
 954
 955         /* Display : 1680x1050 (CVT Reduce Blanking) */
 956         {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)},
 957
 958         /* Display : 1920x1080 (CVT Reduce Blanking) */
 959         {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)},
 960
 961         /* Display : 1920x1200 (CVT Reduce Blanking) */
 962         {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)}
 963 };
 964
 965 struct crt_mode_table CEAM1280x720[] = {
 966         {REFRESH_60, M1280X720_CEA_R60_HSP, M1280X720_CEA_R60_VSP,
 967          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,   VA,  VBS, VBE, VSS, VSE */
 968          {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
 969 };
 970 struct crt_mode_table CEAM1920x1080[] = {
 971         {REFRESH_60, M1920X1080_CEA_R60_HSP, M1920X1080_CEA_R60_VSP,
 972          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,  VA, VBS, VBE,  VSS, VSE */
 973          {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
 974 };
 975 struct VideoModeTable CEA_HDMI_Modes[] = {
 976         /* Display : 1280x720 */
 977         {CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
 978         {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
 979 };
 980
 981 int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
 982 int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
 983 int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
 984 int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
 985 int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
 986 int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
 987 int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
 988 int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
 989
 990
 991 struct VideoModeTable *viafb_get_mode(int hres, int vres)
 992 {
 993         u32 i;
 994         for (i = 0; i < ARRAY_SIZE(viafb_modes); i++)
 995                 if (viafb_modes[i].mode_array &&
 996                         viafb_modes[i].crtc[0].crtc.hor_addr == hres &&
 997                         viafb_modes[i].crtc[0].crtc.ver_addr == vres)
 998                         return &viafb_modes[i];
 999
1000         return NULL;
1001 }
1002
1003 struct VideoModeTable *viafb_get_rb_mode(int hres, int vres)
1004 {
1005         u32 i;
1006         for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++)
1007                 if (viafb_rb_modes[i].mode_array &&
1008                         viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres &&
1009                         viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres)
1010                         return &viafb_rb_modes[i];
1011
1012         return NULL;
1013 }