?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mmc: dw_mmc: add quirks for unreliable card detect, and capabilities
[linux-2.6/btrfs-unstable.git] / drivers / mmc / host / dw_mmc.c
blob94ec6502bdde1c018386d39aaa31109b671fa466
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/seq_file.h>
27 #include <linux/slab.h>
28 #include <linux/stat.h>
29 #include <linux/delay.h>
30 #include <linux/irq.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/dw_mmc.h>
34 #include <linux/bitops.h>
35
36 #include "dw_mmc.h"
37
38 /* Common flag combinations */
39 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
40 SDMMC_INT_HTO | SDMMC_INT_SBE | \
41 SDMMC_INT_EBE)
42 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
43 SDMMC_INT_RESP_ERR)
44 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
45 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
46 #define DW_MCI_SEND_STATUS 1
47 #define DW_MCI_RECV_STATUS 2
48 #define DW_MCI_DMA_THRESHOLD 16
49
50 #ifdef CONFIG_MMC_DW_IDMAC
51 struct idmac_desc {
52 u32 des0; /* Control Descriptor */
53 #define IDMAC_DES0_DIC BIT(1)
54 #define IDMAC_DES0_LD BIT(2)
55 #define IDMAC_DES0_FD BIT(3)
56 #define IDMAC_DES0_CH BIT(4)
57 #define IDMAC_DES0_ER BIT(5)
58 #define IDMAC_DES0_CES BIT(30)
59 #define IDMAC_DES0_OWN BIT(31)
60
61 u32 des1; /* Buffer sizes */
62 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
63 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
64
65 u32 des2; /* buffer 1 physical address */
66
67 u32 des3; /* buffer 2 physical address */
68 };
69 #endif /* CONFIG_MMC_DW_IDMAC */
70
71 /**
72 * struct dw_mci_slot - MMC slot state
73 * @mmc: The mmc_host representing this slot.
74 * @host: The MMC controller this slot is using.
75 * @ctype: Card type for this slot.
76 * @mrq: mmc_request currently being processed or waiting to be
77 * processed, or NULL when the slot is idle.
78 * @queue_node: List node for placing this node in the @queue list of
79 * &struct dw_mci.
80 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
81 * @flags: Random state bits associated with the slot.
82 * @id: Number of this slot.
83 * @last_detect_state: Most recently observed card detect state.
84 */
85 struct dw_mci_slot {
86 struct mmc_host *mmc;
87 struct dw_mci *host;
88
89 u32 ctype;
90
91 struct mmc_request *mrq;
92 struct list_head queue_node;
93
94 unsigned int clock;
95 unsigned long flags;
96 #define DW_MMC_CARD_PRESENT 0
97 #define DW_MMC_CARD_NEED_INIT 1
98 int id;
99 int last_detect_state;
100 };
101
102 #if defined(CONFIG_DEBUG_FS)
103 static int dw_mci_req_show(struct seq_file *s, void *v)
104 {
105 struct dw_mci_slot *slot = s->private;
106 struct mmc_request *mrq;
107 struct mmc_command *cmd;
108 struct mmc_command *stop;
109 struct mmc_data *data;
110
111 /* Make sure we get a consistent snapshot */
112 spin_lock_bh(&slot->host->lock);
113 mrq = slot->mrq;
114
115 if (mrq) {
116 cmd = mrq->cmd;
117 data = mrq->data;
118 stop = mrq->stop;
119
120 if (cmd)
121 seq_printf(s,
122 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
123 cmd->opcode, cmd->arg, cmd->flags,
124 cmd->resp[0], cmd->resp[1], cmd->resp[2],
125 cmd->resp[2], cmd->error);
126 if (data)
127 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
128 data->bytes_xfered, data->blocks,
129 data->blksz, data->flags, data->error);
130 if (stop)
131 seq_printf(s,
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 stop->opcode, stop->arg, stop->flags,
134 stop->resp[0], stop->resp[1], stop->resp[2],
135 stop->resp[2], stop->error);
136 }
137
138 spin_unlock_bh(&slot->host->lock);
139
140 return 0;
141 }
142
143 static int dw_mci_req_open(struct inode *inode, struct file *file)
144 {
145 return single_open(file, dw_mci_req_show, inode->i_private);
146 }
147
148 static const struct file_operations dw_mci_req_fops = {
149 .owner = THIS_MODULE,
150 .open = dw_mci_req_open,
151 .read = seq_read,
152 .llseek = seq_lseek,
153 .release = single_release,
154 };
155
156 static int dw_mci_regs_show(struct seq_file *s, void *v)
157 {
158 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
159 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
160 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
161 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
162 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
163 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
164
165 return 0;
166 }
167
168 static int dw_mci_regs_open(struct inode *inode, struct file *file)
169 {
170 return single_open(file, dw_mci_regs_show, inode->i_private);
171 }
172
173 static const struct file_operations dw_mci_regs_fops = {
174 .owner = THIS_MODULE,
175 .open = dw_mci_regs_open,
176 .read = seq_read,
177 .llseek = seq_lseek,
178 .release = single_release,
179 };
180
181 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
182 {
183 struct mmc_host *mmc = slot->mmc;
184 struct dw_mci *host = slot->host;
185 struct dentry *root;
186 struct dentry *node;
187
188 root = mmc->debugfs_root;
189 if (!root)
190 return;
191
192 node = debugfs_create_file("regs", S_IRUSR, root, host,
193 &dw_mci_regs_fops);
194 if (!node)
195 goto err;
196
197 node = debugfs_create_file("req", S_IRUSR, root, slot,
198 &dw_mci_req_fops);
199 if (!node)
200 goto err;
201
202 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
203 if (!node)
204 goto err;
205
206 node = debugfs_create_x32("pending_events", S_IRUSR, root,
207 (u32 *)&host->pending_events);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_x32("completed_events", S_IRUSR, root,
212 (u32 *)&host->completed_events);
213 if (!node)
214 goto err;
215
216 return;
217
218 err:
219 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
220 }
221 #endif /* defined(CONFIG_DEBUG_FS) */
222
223 static void dw_mci_set_timeout(struct dw_mci *host)
224 {
225 /* timeout (maximum) */
226 mci_writel(host, TMOUT, 0xffffffff);
227 }
228
229 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
230 {
231 struct mmc_data *data;
232 u32 cmdr;
233 cmd->error = -EINPROGRESS;
234
235 cmdr = cmd->opcode;
236
237 if (cmdr == MMC_STOP_TRANSMISSION)
238 cmdr |= SDMMC_CMD_STOP;
239 else
240 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
241
242 if (cmd->flags & MMC_RSP_PRESENT) {
243 /* We expect a response, so set this bit */
244 cmdr |= SDMMC_CMD_RESP_EXP;
245 if (cmd->flags & MMC_RSP_136)
246 cmdr |= SDMMC_CMD_RESP_LONG;
247 }
248
249 if (cmd->flags & MMC_RSP_CRC)
250 cmdr |= SDMMC_CMD_RESP_CRC;
251
252 data = cmd->data;
253 if (data) {
254 cmdr |= SDMMC_CMD_DAT_EXP;
255 if (data->flags & MMC_DATA_STREAM)
256 cmdr |= SDMMC_CMD_STRM_MODE;
257 if (data->flags & MMC_DATA_WRITE)
258 cmdr |= SDMMC_CMD_DAT_WR;
259 }
260
261 return cmdr;
262 }
263
264 static void dw_mci_start_command(struct dw_mci *host,
265 struct mmc_command *cmd, u32 cmd_flags)
266 {
267 host->cmd = cmd;
268 dev_vdbg(&host->pdev->dev,
269 "start command: ARGR=0x%08x CMDR=0x%08x\n",
270 cmd->arg, cmd_flags);
271
272 mci_writel(host, CMDARG, cmd->arg);
273 wmb();
274
275 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
276 }
277
278 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
279 {
280 dw_mci_start_command(host, data->stop, host->stop_cmdr);
281 }
282
283 /* DMA interface functions */
284 static void dw_mci_stop_dma(struct dw_mci *host)
285 {
286 if (host->use_dma) {
287 host->dma_ops->stop(host);
288 host->dma_ops->cleanup(host);
289 } else {
290 /* Data transfer was stopped by the interrupt handler */
291 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
292 }
293 }
294
295 #ifdef CONFIG_MMC_DW_IDMAC
296 static void dw_mci_dma_cleanup(struct dw_mci *host)
297 {
298 struct mmc_data *data = host->data;
299
300 if (data)
301 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
302 ((data->flags & MMC_DATA_WRITE)
303 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
304 }
305
306 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
307 {
308 u32 temp;
309
310 /* Disable and reset the IDMAC interface */
311 temp = mci_readl(host, CTRL);
312 temp &= ~SDMMC_CTRL_USE_IDMAC;
313 temp |= SDMMC_CTRL_DMA_RESET;
314 mci_writel(host, CTRL, temp);
315
316 /* Stop the IDMAC running */
317 temp = mci_readl(host, BMOD);
318 temp &= ~SDMMC_IDMAC_ENABLE;
319 mci_writel(host, BMOD, temp);
320 }
321
322 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
323 {
324 struct mmc_data *data = host->data;
325
326 dev_vdbg(&host->pdev->dev, "DMA complete\n");
327
328 host->dma_ops->cleanup(host);
329
330 /*
331 * If the card was removed, data will be NULL. No point in trying to
332 * send the stop command or waiting for NBUSY in this case.
333 */
334 if (data) {
335 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
336 tasklet_schedule(&host->tasklet);
337 }
338 }
339
340 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
341 unsigned int sg_len)
342 {
343 int i;
344 struct idmac_desc *desc = host->sg_cpu;
345
346 for (i = 0; i < sg_len; i++, desc++) {
347 unsigned int length = sg_dma_len(&data->sg[i]);
348 u32 mem_addr = sg_dma_address(&data->sg[i]);
349
350 /* Set the OWN bit and disable interrupts for this descriptor */
351 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
352
353 /* Buffer length */
354 IDMAC_SET_BUFFER1_SIZE(desc, length);
355
356 /* Physical address to DMA to/from */
357 desc->des2 = mem_addr;
358 }
359
360 /* Set first descriptor */
361 desc = host->sg_cpu;
362 desc->des0 |= IDMAC_DES0_FD;
363
364 /* Set last descriptor */
365 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
366 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
367 desc->des0 |= IDMAC_DES0_LD;
368
369 wmb();
370 }
371
372 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
373 {
374 u32 temp;
375
376 dw_mci_translate_sglist(host, host->data, sg_len);
377
378 /* Select IDMAC interface */
379 temp = mci_readl(host, CTRL);
380 temp |= SDMMC_CTRL_USE_IDMAC;
381 mci_writel(host, CTRL, temp);
382
383 wmb();
384
385 /* Enable the IDMAC */
386 temp = mci_readl(host, BMOD);
387 temp |= SDMMC_IDMAC_ENABLE;
388 mci_writel(host, BMOD, temp);
389
390 /* Start it running */
391 mci_writel(host, PLDMND, 1);
392 }
393
394 static int dw_mci_idmac_init(struct dw_mci *host)
395 {
396 struct idmac_desc *p;
397 int i;
398
399 /* Number of descriptors in the ring buffer */
400 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
401
402 /* Forward link the descriptor list */
403 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
404 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
405
406 /* Set the last descriptor as the end-of-ring descriptor */
407 p->des3 = host->sg_dma;
408 p->des0 = IDMAC_DES0_ER;
409
410 /* Mask out interrupts - get Tx & Rx complete only */
411 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
412 SDMMC_IDMAC_INT_TI);
413
414 /* Set the descriptor base address */
415 mci_writel(host, DBADDR, host->sg_dma);
416 return 0;
417 }
418
419 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
420 .init = dw_mci_idmac_init,
421 .start = dw_mci_idmac_start_dma,
422 .stop = dw_mci_idmac_stop_dma,
423 .complete = dw_mci_idmac_complete_dma,
424 .cleanup = dw_mci_dma_cleanup,
425 };
426 #endif /* CONFIG_MMC_DW_IDMAC */
427
428 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
429 {
430 struct scatterlist *sg;
431 unsigned int i, direction, sg_len;
432 u32 temp;
433
434 /* If we don't have a channel, we can't do DMA */
435 if (!host->use_dma)
436 return -ENODEV;
437
438 /*
439 * We don't do DMA on "complex" transfers, i.e. with
440 * non-word-aligned buffers or lengths. Also, we don't bother
441 * with all the DMA setup overhead for short transfers.
442 */
443 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
444 return -EINVAL;
445 if (data->blksz & 3)
446 return -EINVAL;
447
448 for_each_sg(data->sg, sg, data->sg_len, i) {
449 if (sg->offset & 3 || sg->length & 3)
450 return -EINVAL;
451 }
452
453 if (data->flags & MMC_DATA_READ)
454 direction = DMA_FROM_DEVICE;
455 else
456 direction = DMA_TO_DEVICE;
457
458 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
459 direction);
460
461 dev_vdbg(&host->pdev->dev,
462 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
463 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
464 sg_len);
465
466 /* Enable the DMA interface */
467 temp = mci_readl(host, CTRL);
468 temp |= SDMMC_CTRL_DMA_ENABLE;
469 mci_writel(host, CTRL, temp);
470
471 /* Disable RX/TX IRQs, let DMA handle it */
472 temp = mci_readl(host, INTMASK);
473 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
474 mci_writel(host, INTMASK, temp);
475
476 host->dma_ops->start(host, sg_len);
477
478 return 0;
479 }
480
481 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
482 {
483 u32 temp;
484
485 data->error = -EINPROGRESS;
486
487 WARN_ON(host->data);
488 host->sg = NULL;
489 host->data = data;
490
491 if (dw_mci_submit_data_dma(host, data)) {
492 host->sg = data->sg;
493 host->pio_offset = 0;
494 if (data->flags & MMC_DATA_READ)
495 host->dir_status = DW_MCI_RECV_STATUS;
496 else
497 host->dir_status = DW_MCI_SEND_STATUS;
498
499 temp = mci_readl(host, INTMASK);
500 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
501 mci_writel(host, INTMASK, temp);
502
503 temp = mci_readl(host, CTRL);
504 temp &= ~SDMMC_CTRL_DMA_ENABLE;
505 mci_writel(host, CTRL, temp);
506 }
507 }
508
509 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
510 {
511 struct dw_mci *host = slot->host;
512 unsigned long timeout = jiffies + msecs_to_jiffies(500);
513 unsigned int cmd_status = 0;
514
515 mci_writel(host, CMDARG, arg);
516 wmb();
517 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
518
519 while (time_before(jiffies, timeout)) {
520 cmd_status = mci_readl(host, CMD);
521 if (!(cmd_status & SDMMC_CMD_START))
522 return;
523 }
524 dev_err(&slot->mmc->class_dev,
525 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
526 cmd, arg, cmd_status);
527 }
528
529 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
530 {
531 struct dw_mci *host = slot->host;
532 u32 div;
533
534 if (slot->clock != host->current_speed) {
535 if (host->bus_hz % slot->clock)
536 /*
537 * move the + 1 after the divide to prevent
538 * over-clocking the card.
539 */
540 div = ((host->bus_hz / slot->clock) >> 1) + 1;
541 else
542 div = (host->bus_hz / slot->clock) >> 1;
543
544 dev_info(&slot->mmc->class_dev,
545 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
546 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
547 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
548
549 /* disable clock */
550 mci_writel(host, CLKENA, 0);
551 mci_writel(host, CLKSRC, 0);
552
553 /* inform CIU */
554 mci_send_cmd(slot,
555 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
556
557 /* set clock to desired speed */
558 mci_writel(host, CLKDIV, div);
559
560 /* inform CIU */
561 mci_send_cmd(slot,
562 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
563
564 /* enable clock */
565 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
566 SDMMC_CLKEN_LOW_PWR);
567
568 /* inform CIU */
569 mci_send_cmd(slot,
570 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
571
572 host->current_speed = slot->clock;
573 }
574
575 /* Set the current slot bus width */
576 mci_writel(host, CTYPE, slot->ctype);
577 }
578
579 static void dw_mci_start_request(struct dw_mci *host,
580 struct dw_mci_slot *slot)
581 {
582 struct mmc_request *mrq;
583 struct mmc_command *cmd;
584 struct mmc_data *data;
585 u32 cmdflags;
586
587 mrq = slot->mrq;
588 if (host->pdata->select_slot)
589 host->pdata->select_slot(slot->id);
590
591 /* Slot specific timing and width adjustment */
592 dw_mci_setup_bus(slot);
593
594 host->cur_slot = slot;
595 host->mrq = mrq;
596
597 host->pending_events = 0;
598 host->completed_events = 0;
599 host->data_status = 0;
600
601 data = mrq->data;
602 if (data) {
603 dw_mci_set_timeout(host);
604 mci_writel(host, BYTCNT, data->blksz*data->blocks);
605 mci_writel(host, BLKSIZ, data->blksz);
606 }
607
608 cmd = mrq->cmd;
609 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
610
611 /* this is the first command, send the initialization clock */
612 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
613 cmdflags |= SDMMC_CMD_INIT;
614
615 if (data) {
616 dw_mci_submit_data(host, data);
617 wmb();
618 }
619
620 dw_mci_start_command(host, cmd, cmdflags);
621
622 if (mrq->stop)
623 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
624 }
625
626 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
627 struct mmc_request *mrq)
628 {
629 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
630 host->state);
631
632 spin_lock_bh(&host->lock);
633 slot->mrq = mrq;
634
635 if (host->state == STATE_IDLE) {
636 host->state = STATE_SENDING_CMD;
637 dw_mci_start_request(host, slot);
638 } else {
639 list_add_tail(&slot->queue_node, &host->queue);
640 }
641
642 spin_unlock_bh(&host->lock);
643 }
644
645 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
646 {
647 struct dw_mci_slot *slot = mmc_priv(mmc);
648 struct dw_mci *host = slot->host;
649
650 WARN_ON(slot->mrq);
651
652 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
653 mrq->cmd->error = -ENOMEDIUM;
654 mmc_request_done(mmc, mrq);
655 return;
656 }
657
658 /* We don't support multiple blocks of weird lengths. */
659 dw_mci_queue_request(host, slot, mrq);
660 }
661
662 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
663 {
664 struct dw_mci_slot *slot = mmc_priv(mmc);
665 u32 regs;
666
667 /* set default 1 bit mode */
668 slot->ctype = SDMMC_CTYPE_1BIT;
669
670 switch (ios->bus_width) {
671 case MMC_BUS_WIDTH_1:
672 slot->ctype = SDMMC_CTYPE_1BIT;
673 break;
674 case MMC_BUS_WIDTH_4:
675 slot->ctype = SDMMC_CTYPE_4BIT;
676 break;
677 case MMC_BUS_WIDTH_8:
678 slot->ctype = SDMMC_CTYPE_8BIT;
679 break;
680 }
681
682 /* DDR mode set */
683 if (ios->ddr) {
684 regs = mci_readl(slot->host, UHS_REG);
685 regs |= (0x1 << slot->id) << 16;
686 mci_writel(slot->host, UHS_REG, regs);
687 }
688
689 if (ios->clock) {
690 /*
691 * Use mirror of ios->clock to prevent race with mmc
692 * core ios update when finding the minimum.
693 */
694 slot->clock = ios->clock;
695 }
696
697 switch (ios->power_mode) {
698 case MMC_POWER_UP:
699 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
700 break;
701 default:
702 break;
703 }
704 }
705
706 static int dw_mci_get_ro(struct mmc_host *mmc)
707 {
708 int read_only;
709 struct dw_mci_slot *slot = mmc_priv(mmc);
710 struct dw_mci_board *brd = slot->host->pdata;
711
712 /* Use platform get_ro function, else try on board write protect */
713 if (brd->get_ro)
714 read_only = brd->get_ro(slot->id);
715 else
716 read_only =
717 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
718
719 dev_dbg(&mmc->class_dev, "card is %s\n",
720 read_only ? "read-only" : "read-write");
721
722 return read_only;
723 }
724
725 static int dw_mci_get_cd(struct mmc_host *mmc)
726 {
727 int present;
728 struct dw_mci_slot *slot = mmc_priv(mmc);
729 struct dw_mci_board *brd = slot->host->pdata;
730
731 /* Use platform get_cd function, else try onboard card detect */
732 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
733 present = 1;
734 else if (brd->get_cd)
735 present = !brd->get_cd(slot->id);
736 else
737 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
738 == 0 ? 1 : 0;
739
740 if (present)
741 dev_dbg(&mmc->class_dev, "card is present\n");
742 else
743 dev_dbg(&mmc->class_dev, "card is not present\n");
744
745 return present;
746 }
747
748 static const struct mmc_host_ops dw_mci_ops = {
749 .request = dw_mci_request,
750 .set_ios = dw_mci_set_ios,
751 .get_ro = dw_mci_get_ro,
752 .get_cd = dw_mci_get_cd,
753 };
754
755 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
756 __releases(&host->lock)
757 __acquires(&host->lock)
758 {
759 struct dw_mci_slot *slot;
760 struct mmc_host *prev_mmc = host->cur_slot->mmc;
761
762 WARN_ON(host->cmd || host->data);
763
764 host->cur_slot->mrq = NULL;
765 host->mrq = NULL;
766 if (!list_empty(&host->queue)) {
767 slot = list_entry(host->queue.next,
768 struct dw_mci_slot, queue_node);
769 list_del(&slot->queue_node);
770 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
771 mmc_hostname(slot->mmc));
772 host->state = STATE_SENDING_CMD;
773 dw_mci_start_request(host, slot);
774 } else {
775 dev_vdbg(&host->pdev->dev, "list empty\n");
776 host->state = STATE_IDLE;
777 }
778
779 spin_unlock(&host->lock);
780 mmc_request_done(prev_mmc, mrq);
781 spin_lock(&host->lock);
782 }
783
784 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
785 {
786 u32 status = host->cmd_status;
787
788 host->cmd_status = 0;
789
790 /* Read the response from the card (up to 16 bytes) */
791 if (cmd->flags & MMC_RSP_PRESENT) {
792 if (cmd->flags & MMC_RSP_136) {
793 cmd->resp[3] = mci_readl(host, RESP0);
794 cmd->resp[2] = mci_readl(host, RESP1);
795 cmd->resp[1] = mci_readl(host, RESP2);
796 cmd->resp[0] = mci_readl(host, RESP3);
797 } else {
798 cmd->resp[0] = mci_readl(host, RESP0);
799 cmd->resp[1] = 0;
800 cmd->resp[2] = 0;
801 cmd->resp[3] = 0;
802 }
803 }
804
805 if (status & SDMMC_INT_RTO)
806 cmd->error = -ETIMEDOUT;
807 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
808 cmd->error = -EILSEQ;
809 else if (status & SDMMC_INT_RESP_ERR)
810 cmd->error = -EIO;
811 else
812 cmd->error = 0;
813
814 if (cmd->error) {
815 /* newer ip versions need a delay between retries */
816 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
817 mdelay(20);
818
819 if (cmd->data) {
820 host->data = NULL;
821 dw_mci_stop_dma(host);
822 }
823 }
824 }
825
826 static void dw_mci_tasklet_func(unsigned long priv)
827 {
828 struct dw_mci *host = (struct dw_mci *)priv;
829 struct mmc_data *data;
830 struct mmc_command *cmd;
831 enum dw_mci_state state;
832 enum dw_mci_state prev_state;
833 u32 status;
834
835 spin_lock(&host->lock);
836
837 state = host->state;
838 data = host->data;
839
840 do {
841 prev_state = state;
842
843 switch (state) {
844 case STATE_IDLE:
845 break;
846
847 case STATE_SENDING_CMD:
848 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
849 &host->pending_events))
850 break;
851
852 cmd = host->cmd;
853 host->cmd = NULL;
854 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
855 dw_mci_command_complete(host, host->mrq->cmd);
856 if (!host->mrq->data || cmd->error) {
857 dw_mci_request_end(host, host->mrq);
858 goto unlock;
859 }
860
861 prev_state = state = STATE_SENDING_DATA;
862 /* fall through */
863
864 case STATE_SENDING_DATA:
865 if (test_and_clear_bit(EVENT_DATA_ERROR,
866 &host->pending_events)) {
867 dw_mci_stop_dma(host);
868 if (data->stop)
869 send_stop_cmd(host, data);
870 state = STATE_DATA_ERROR;
871 break;
872 }
873
874 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
875 &host->pending_events))
876 break;
877
878 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
879 prev_state = state = STATE_DATA_BUSY;
880 /* fall through */
881
882 case STATE_DATA_BUSY:
883 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
884 &host->pending_events))
885 break;
886
887 host->data = NULL;
888 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
889 status = host->data_status;
890
891 if (status & DW_MCI_DATA_ERROR_FLAGS) {
892 if (status & SDMMC_INT_DTO) {
893 dev_err(&host->pdev->dev,
894 "data timeout error\n");
895 data->error = -ETIMEDOUT;
896 } else if (status & SDMMC_INT_DCRC) {
897 dev_err(&host->pdev->dev,
898 "data CRC error\n");
899 data->error = -EILSEQ;
900 } else {
901 dev_err(&host->pdev->dev,
902 "data FIFO error "
903 "(status=%08x)\n",
904 status);
905 data->error = -EIO;
906 }
907 } else {
908 data->bytes_xfered = data->blocks * data->blksz;
909 data->error = 0;
910 }
911
912 if (!data->stop) {
913 dw_mci_request_end(host, host->mrq);
914 goto unlock;
915 }
916
917 prev_state = state = STATE_SENDING_STOP;
918 if (!data->error)
919 send_stop_cmd(host, data);
920 /* fall through */
921
922 case STATE_SENDING_STOP:
923 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
924 &host->pending_events))
925 break;
926
927 host->cmd = NULL;
928 dw_mci_command_complete(host, host->mrq->stop);
929 dw_mci_request_end(host, host->mrq);
930 goto unlock;
931
932 case STATE_DATA_ERROR:
933 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
934 &host->pending_events))
935 break;
936
937 state = STATE_DATA_BUSY;
938 break;
939 }
940 } while (state != prev_state);
941
942 host->state = state;
943 unlock:
944 spin_unlock(&host->lock);
945
946 }
947
948 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
949 {
950 u16 *pdata = (u16 *)buf;
951
952 WARN_ON(cnt % 2 != 0);
953
954 cnt = cnt >> 1;
955 while (cnt > 0) {
956 mci_writew(host, DATA, *pdata++);
957 cnt--;
958 }
959 }
960
961 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
962 {
963 u16 *pdata = (u16 *)buf;
964
965 WARN_ON(cnt % 2 != 0);
966
967 cnt = cnt >> 1;
968 while (cnt > 0) {
969 *pdata++ = mci_readw(host, DATA);
970 cnt--;
971 }
972 }
973
974 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
975 {
976 u32 *pdata = (u32 *)buf;
977
978 WARN_ON(cnt % 4 != 0);
979 WARN_ON((unsigned long)pdata & 0x3);
980
981 cnt = cnt >> 2;
982 while (cnt > 0) {
983 mci_writel(host, DATA, *pdata++);
984 cnt--;
985 }
986 }
987
988 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
989 {
990 u32 *pdata = (u32 *)buf;
991
992 WARN_ON(cnt % 4 != 0);
993 WARN_ON((unsigned long)pdata & 0x3);
994
995 cnt = cnt >> 2;
996 while (cnt > 0) {
997 *pdata++ = mci_readl(host, DATA);
998 cnt--;
999 }
1000 }
1001
1002 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1003 {
1004 u64 *pdata = (u64 *)buf;
1005
1006 WARN_ON(cnt % 8 != 0);
1007
1008 cnt = cnt >> 3;
1009 while (cnt > 0) {
1010 mci_writeq(host, DATA, *pdata++);
1011 cnt--;
1012 }
1013 }
1014
1015 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1016 {
1017 u64 *pdata = (u64 *)buf;
1018
1019 WARN_ON(cnt % 8 != 0);
1020
1021 cnt = cnt >> 3;
1022 while (cnt > 0) {
1023 *pdata++ = mci_readq(host, DATA);
1024 cnt--;
1025 }
1026 }
1027
1028 static void dw_mci_read_data_pio(struct dw_mci *host)
1029 {
1030 struct scatterlist *sg = host->sg;
1031 void *buf = sg_virt(sg);
1032 unsigned int offset = host->pio_offset;
1033 struct mmc_data *data = host->data;
1034 int shift = host->data_shift;
1035 u32 status;
1036 unsigned int nbytes = 0, len;
1037
1038 do {
1039 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
1040 if (offset + len <= sg->length) {
1041 host->pull_data(host, (void *)(buf + offset), len);
1042
1043 offset += len;
1044 nbytes += len;
1045
1046 if (offset == sg->length) {
1047 flush_dcache_page(sg_page(sg));
1048 host->sg = sg = sg_next(sg);
1049 if (!sg)
1050 goto done;
1051
1052 offset = 0;
1053 buf = sg_virt(sg);
1054 }
1055 } else {
1056 unsigned int remaining = sg->length - offset;
1057 host->pull_data(host, (void *)(buf + offset),
1058 remaining);
1059 nbytes += remaining;
1060
1061 flush_dcache_page(sg_page(sg));
1062 host->sg = sg = sg_next(sg);
1063 if (!sg)
1064 goto done;
1065
1066 offset = len - remaining;
1067 buf = sg_virt(sg);
1068 host->pull_data(host, buf, offset);
1069 nbytes += offset;
1070 }
1071
1072 status = mci_readl(host, MINTSTS);
1073 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1074 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1075 host->data_status = status;
1076 data->bytes_xfered += nbytes;
1077 smp_wmb();
1078
1079 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1080
1081 tasklet_schedule(&host->tasklet);
1082 return;
1083 }
1084 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1085 len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1086 host->pio_offset = offset;
1087 data->bytes_xfered += nbytes;
1088 return;
1089
1090 done:
1091 data->bytes_xfered += nbytes;
1092 smp_wmb();
1093 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1094 }
1095
1096 static void dw_mci_write_data_pio(struct dw_mci *host)
1097 {
1098 struct scatterlist *sg = host->sg;
1099 void *buf = sg_virt(sg);
1100 unsigned int offset = host->pio_offset;
1101 struct mmc_data *data = host->data;
1102 int shift = host->data_shift;
1103 u32 status;
1104 unsigned int nbytes = 0, len;
1105
1106 do {
1107 len = SDMMC_FIFO_SZ -
1108 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1109 if (offset + len <= sg->length) {
1110 host->push_data(host, (void *)(buf + offset), len);
1111
1112 offset += len;
1113 nbytes += len;
1114 if (offset == sg->length) {
1115 host->sg = sg = sg_next(sg);
1116 if (!sg)
1117 goto done;
1118
1119 offset = 0;
1120 buf = sg_virt(sg);
1121 }
1122 } else {
1123 unsigned int remaining = sg->length - offset;
1124
1125 host->push_data(host, (void *)(buf + offset),
1126 remaining);
1127 nbytes += remaining;
1128
1129 host->sg = sg = sg_next(sg);
1130 if (!sg)
1131 goto done;
1132
1133 offset = len - remaining;
1134 buf = sg_virt(sg);
1135 host->push_data(host, (void *)buf, offset);
1136 nbytes += offset;
1137 }
1138
1139 status = mci_readl(host, MINTSTS);
1140 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1141 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1142 host->data_status = status;
1143 data->bytes_xfered += nbytes;
1144
1145 smp_wmb();
1146
1147 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1148
1149 tasklet_schedule(&host->tasklet);
1150 return;
1151 }
1152 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1153
1154 host->pio_offset = offset;
1155 data->bytes_xfered += nbytes;
1156
1157 return;
1158
1159 done:
1160 data->bytes_xfered += nbytes;
1161 smp_wmb();
1162 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1163 }
1164
1165 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1166 {
1167 if (!host->cmd_status)
1168 host->cmd_status = status;
1169
1170 smp_wmb();
1171
1172 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1173 tasklet_schedule(&host->tasklet);
1174 }
1175
1176 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1177 {
1178 struct dw_mci *host = dev_id;
1179 u32 status, pending;
1180 unsigned int pass_count = 0;
1181
1182 do {
1183 status = mci_readl(host, RINTSTS);
1184 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1185
1186 /*
1187 * DTO fix - version 2.10a and below, and only if internal DMA
1188 * is configured.
1189 */
1190 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1191 if (!pending &&
1192 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1193 pending |= SDMMC_INT_DATA_OVER;
1194 }
1195
1196 if (!pending)
1197 break;
1198
1199 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1200 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1201 host->cmd_status = status;
1202 smp_wmb();
1203 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1204 tasklet_schedule(&host->tasklet);
1205 }
1206
1207 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1208 /* if there is an error report DATA_ERROR */
1209 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1210 host->data_status = status;
1211 smp_wmb();
1212 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1213 tasklet_schedule(&host->tasklet);
1214 }
1215
1216 if (pending & SDMMC_INT_DATA_OVER) {
1217 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1218 if (!host->data_status)
1219 host->data_status = status;
1220 smp_wmb();
1221 if (host->dir_status == DW_MCI_RECV_STATUS) {
1222 if (host->sg != NULL)
1223 dw_mci_read_data_pio(host);
1224 }
1225 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1226 tasklet_schedule(&host->tasklet);
1227 }
1228
1229 if (pending & SDMMC_INT_RXDR) {
1230 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1231 if (host->sg)
1232 dw_mci_read_data_pio(host);
1233 }
1234
1235 if (pending & SDMMC_INT_TXDR) {
1236 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1237 if (host->sg)
1238 dw_mci_write_data_pio(host);
1239 }
1240
1241 if (pending & SDMMC_INT_CMD_DONE) {
1242 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1243 dw_mci_cmd_interrupt(host, status);
1244 }
1245
1246 if (pending & SDMMC_INT_CD) {
1247 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1248 tasklet_schedule(&host->card_tasklet);
1249 }
1250
1251 } while (pass_count++ < 5);
1252
1253 #ifdef CONFIG_MMC_DW_IDMAC
1254 /* Handle DMA interrupts */
1255 pending = mci_readl(host, IDSTS);
1256 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1257 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1258 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1259 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1260 host->dma_ops->complete(host);
1261 }
1262 #endif
1263
1264 return IRQ_HANDLED;
1265 }
1266
1267 static void dw_mci_tasklet_card(unsigned long data)
1268 {
1269 struct dw_mci *host = (struct dw_mci *)data;
1270 int i;
1271
1272 for (i = 0; i < host->num_slots; i++) {
1273 struct dw_mci_slot *slot = host->slot[i];
1274 struct mmc_host *mmc = slot->mmc;
1275 struct mmc_request *mrq;
1276 int present;
1277 u32 ctrl;
1278
1279 present = dw_mci_get_cd(mmc);
1280 while (present != slot->last_detect_state) {
1281 spin_lock(&host->lock);
1282
1283 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1284 present ? "inserted" : "removed");
1285
1286 /* Card change detected */
1287 slot->last_detect_state = present;
1288
1289 /* Power up slot */
1290 if (present != 0) {
1291 if (host->pdata->setpower)
1292 host->pdata->setpower(slot->id,
1293 mmc->ocr_avail);
1294
1295 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1296 }
1297
1298 /* Clean up queue if present */
1299 mrq = slot->mrq;
1300 if (mrq) {
1301 if (mrq == host->mrq) {
1302 host->data = NULL;
1303 host->cmd = NULL;
1304
1305 switch (host->state) {
1306 case STATE_IDLE:
1307 break;
1308 case STATE_SENDING_CMD:
1309 mrq->cmd->error = -ENOMEDIUM;
1310 if (!mrq->data)
1311 break;
1312 /* fall through */
1313 case STATE_SENDING_DATA:
1314 mrq->data->error = -ENOMEDIUM;
1315 dw_mci_stop_dma(host);
1316 break;
1317 case STATE_DATA_BUSY:
1318 case STATE_DATA_ERROR:
1319 if (mrq->data->error == -EINPROGRESS)
1320 mrq->data->error = -ENOMEDIUM;
1321 if (!mrq->stop)
1322 break;
1323 /* fall through */
1324 case STATE_SENDING_STOP:
1325 mrq->stop->error = -ENOMEDIUM;
1326 break;
1327 }
1328
1329 dw_mci_request_end(host, mrq);
1330 } else {
1331 list_del(&slot->queue_node);
1332 mrq->cmd->error = -ENOMEDIUM;
1333 if (mrq->data)
1334 mrq->data->error = -ENOMEDIUM;
1335 if (mrq->stop)
1336 mrq->stop->error = -ENOMEDIUM;
1337
1338 spin_unlock(&host->lock);
1339 mmc_request_done(slot->mmc, mrq);
1340 spin_lock(&host->lock);
1341 }
1342 }
1343
1344 /* Power down slot */
1345 if (present == 0) {
1346 if (host->pdata->setpower)
1347 host->pdata->setpower(slot->id, 0);
1348 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1349
1350 /*
1351 * Clear down the FIFO - doing so generates a
1352 * block interrupt, hence setting the
1353 * scatter-gather pointer to NULL.
1354 */
1355 host->sg = NULL;
1356
1357 ctrl = mci_readl(host, CTRL);
1358 ctrl |= SDMMC_CTRL_FIFO_RESET;
1359 mci_writel(host, CTRL, ctrl);
1360
1361 #ifdef CONFIG_MMC_DW_IDMAC
1362 ctrl = mci_readl(host, BMOD);
1363 ctrl |= 0x01; /* Software reset of DMA */
1364 mci_writel(host, BMOD, ctrl);
1365 #endif
1366
1367 }
1368
1369 spin_unlock(&host->lock);
1370 present = dw_mci_get_cd(mmc);
1371 }
1372
1373 mmc_detect_change(slot->mmc,
1374 msecs_to_jiffies(host->pdata->detect_delay_ms));
1375 }
1376 }
1377
1378 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1379 {
1380 struct mmc_host *mmc;
1381 struct dw_mci_slot *slot;
1382
1383 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1384 if (!mmc)
1385 return -ENOMEM;
1386
1387 slot = mmc_priv(mmc);
1388 slot->id = id;
1389 slot->mmc = mmc;
1390 slot->host = host;
1391
1392 mmc->ops = &dw_mci_ops;
1393 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1394 mmc->f_max = host->bus_hz;
1395
1396 if (host->pdata->get_ocr)
1397 mmc->ocr_avail = host->pdata->get_ocr(id);
1398 else
1399 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1400
1401 /*
1402 * Start with slot power disabled, it will be enabled when a card
1403 * is detected.
1404 */
1405 if (host->pdata->setpower)
1406 host->pdata->setpower(id, 0);
1407
1408 if (host->pdata->caps)
1409 mmc->caps = host->pdata->caps;
1410 else
1411 mmc->caps = 0;
1412
1413 if (host->pdata->get_bus_wd)
1414 if (host->pdata->get_bus_wd(slot->id) >= 4)
1415 mmc->caps |= MMC_CAP_4_BIT_DATA;
1416
1417 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1418 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1419
1420 #ifdef CONFIG_MMC_DW_IDMAC
1421 mmc->max_segs = host->ring_size;
1422 mmc->max_blk_size = 65536;
1423 mmc->max_blk_count = host->ring_size;
1424 mmc->max_seg_size = 0x1000;
1425 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1426 #else
1427 if (host->pdata->blk_settings) {
1428 mmc->max_segs = host->pdata->blk_settings->max_segs;
1429 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1430 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1431 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1432 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1433 } else {
1434 /* Useful defaults if platform data is unset. */
1435 mmc->max_segs = 64;
1436 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1437 mmc->max_blk_count = 512;
1438 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1439 mmc->max_seg_size = mmc->max_req_size;
1440 }
1441 #endif /* CONFIG_MMC_DW_IDMAC */
1442
1443 if (dw_mci_get_cd(mmc))
1444 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1445 else
1446 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1447
1448 host->slot[id] = slot;
1449 mmc_add_host(mmc);
1450
1451 #if defined(CONFIG_DEBUG_FS)
1452 dw_mci_init_debugfs(slot);
1453 #endif
1454
1455 /* Card initially undetected */
1456 slot->last_detect_state = 0;
1457
1458 /*
1459 * Card may have been plugged in prior to boot so we
1460 * need to run the detect tasklet
1461 */
1462 tasklet_schedule(&host->card_tasklet);
1463
1464 return 0;
1465 }
1466
1467 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1468 {
1469 /* Shutdown detect IRQ */
1470 if (slot->host->pdata->exit)
1471 slot->host->pdata->exit(id);
1472
1473 /* Debugfs stuff is cleaned up by mmc core */
1474 mmc_remove_host(slot->mmc);
1475 slot->host->slot[id] = NULL;
1476 mmc_free_host(slot->mmc);
1477 }
1478
1479 static void dw_mci_init_dma(struct dw_mci *host)
1480 {
1481 /* Alloc memory for sg translation */
1482 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1483 &host->sg_dma, GFP_KERNEL);
1484 if (!host->sg_cpu) {
1485 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1486 __func__);
1487 goto no_dma;
1488 }
1489
1490 /* Determine which DMA interface to use */
1491 #ifdef CONFIG_MMC_DW_IDMAC
1492 host->dma_ops = &dw_mci_idmac_ops;
1493 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1494 #endif
1495
1496 if (!host->dma_ops)
1497 goto no_dma;
1498
1499 if (host->dma_ops->init) {
1500 if (host->dma_ops->init(host)) {
1501 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1502 "DMA Controller.\n", __func__);
1503 goto no_dma;
1504 }
1505 } else {
1506 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1507 goto no_dma;
1508 }
1509
1510 host->use_dma = 1;
1511 return;
1512
1513 no_dma:
1514 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1515 host->use_dma = 0;
1516 return;
1517 }
1518
1519 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1520 {
1521 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1522 unsigned int ctrl;
1523
1524 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1525 SDMMC_CTRL_DMA_RESET));
1526
1527 /* wait till resets clear */
1528 do {
1529 ctrl = mci_readl(host, CTRL);
1530 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1531 SDMMC_CTRL_DMA_RESET)))
1532 return true;
1533 } while (time_before(jiffies, timeout));
1534
1535 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1536
1537 return false;
1538 }
1539
1540 static int dw_mci_probe(struct platform_device *pdev)
1541 {
1542 struct dw_mci *host;
1543 struct resource *regs;
1544 struct dw_mci_board *pdata;
1545 int irq, ret, i, width;
1546 u32 fifo_size;
1547
1548 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1549 if (!regs)
1550 return -ENXIO;
1551
1552 irq = platform_get_irq(pdev, 0);
1553 if (irq < 0)
1554 return irq;
1555
1556 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1557 if (!host)
1558 return -ENOMEM;
1559
1560 host->pdev = pdev;
1561 host->pdata = pdata = pdev->dev.platform_data;
1562 if (!pdata || !pdata->init) {
1563 dev_err(&pdev->dev,
1564 "Platform data must supply init function\n");
1565 ret = -ENODEV;
1566 goto err_freehost;
1567 }
1568
1569 if (!pdata->select_slot && pdata->num_slots > 1) {
1570 dev_err(&pdev->dev,
1571 "Platform data must supply select_slot function\n");
1572 ret = -ENODEV;
1573 goto err_freehost;
1574 }
1575
1576 if (!pdata->bus_hz) {
1577 dev_err(&pdev->dev,
1578 "Platform data must supply bus speed\n");
1579 ret = -ENODEV;
1580 goto err_freehost;
1581 }
1582
1583 host->bus_hz = pdata->bus_hz;
1584 host->quirks = pdata->quirks;
1585
1586 spin_lock_init(&host->lock);
1587 INIT_LIST_HEAD(&host->queue);
1588
1589 ret = -ENOMEM;
1590 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1591 if (!host->regs)
1592 goto err_freehost;
1593
1594 host->dma_ops = pdata->dma_ops;
1595 dw_mci_init_dma(host);
1596
1597 /*
1598 * Get the host data width - this assumes that HCON has been set with
1599 * the correct values.
1600 */
1601 i = (mci_readl(host, HCON) >> 7) & 0x7;
1602 if (!i) {
1603 host->push_data = dw_mci_push_data16;
1604 host->pull_data = dw_mci_pull_data16;
1605 width = 16;
1606 host->data_shift = 1;
1607 } else if (i == 2) {
1608 host->push_data = dw_mci_push_data64;
1609 host->pull_data = dw_mci_pull_data64;
1610 width = 64;
1611 host->data_shift = 3;
1612 } else {
1613 /* Check for a reserved value, and warn if it is */
1614 WARN((i != 1),
1615 "HCON reports a reserved host data width!\n"
1616 "Defaulting to 32-bit access.\n");
1617 host->push_data = dw_mci_push_data32;
1618 host->pull_data = dw_mci_pull_data32;
1619 width = 32;
1620 host->data_shift = 2;
1621 }
1622
1623 /* Reset all blocks */
1624 if (!mci_wait_reset(&pdev->dev, host)) {
1625 ret = -ENODEV;
1626 goto err_dmaunmap;
1627 }
1628
1629 /* Clear the interrupts for the host controller */
1630 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1631 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1632
1633 /* Put in max timeout */
1634 mci_writel(host, TMOUT, 0xFFFFFFFF);
1635
1636 /*
1637 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1638 * Tx Mark = fifo_size / 2 DMA Size = 8
1639 */
1640 fifo_size = mci_readl(host, FIFOTH);
1641 fifo_size = (fifo_size >> 16) & 0x7ff;
1642 mci_writel(host, FIFOTH, ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1643 ((fifo_size/2) << 0)));
1644
1645 /* disable clock to CIU */
1646 mci_writel(host, CLKENA, 0);
1647 mci_writel(host, CLKSRC, 0);
1648
1649 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1650 tasklet_init(&host->card_tasklet,
1651 dw_mci_tasklet_card, (unsigned long)host);
1652
1653 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1654 if (ret)
1655 goto err_dmaunmap;
1656
1657 platform_set_drvdata(pdev, host);
1658
1659 if (host->pdata->num_slots)
1660 host->num_slots = host->pdata->num_slots;
1661 else
1662 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1663
1664 /* We need at least one slot to succeed */
1665 for (i = 0; i < host->num_slots; i++) {
1666 ret = dw_mci_init_slot(host, i);
1667 if (ret) {
1668 ret = -ENODEV;
1669 goto err_init_slot;
1670 }
1671 }
1672
1673 /*
1674 * Enable interrupts for command done, data over, data empty, card det,
1675 * receive ready and error such as transmit, receive timeout, crc error
1676 */
1677 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1678 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1679 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1680 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1681 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1682
1683 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1684 "%d bit host data width\n", irq, width);
1685 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1686 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1687
1688 return 0;
1689
1690 err_init_slot:
1691 /* De-init any initialized slots */
1692 while (i > 0) {
1693 if (host->slot[i])
1694 dw_mci_cleanup_slot(host->slot[i], i);
1695 i--;
1696 }
1697 free_irq(irq, host);
1698
1699 err_dmaunmap:
1700 if (host->use_dma && host->dma_ops->exit)
1701 host->dma_ops->exit(host);
1702 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1703 host->sg_cpu, host->sg_dma);
1704 iounmap(host->regs);
1705
1706 err_freehost:
1707 kfree(host);
1708 return ret;
1709 }
1710
1711 static int __exit dw_mci_remove(struct platform_device *pdev)
1712 {
1713 struct dw_mci *host = platform_get_drvdata(pdev);
1714 int i;
1715
1716 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1717 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1718
1719 platform_set_drvdata(pdev, NULL);
1720
1721 for (i = 0; i < host->num_slots; i++) {
1722 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1723 if (host->slot[i])
1724 dw_mci_cleanup_slot(host->slot[i], i);
1725 }
1726
1727 /* disable clock to CIU */
1728 mci_writel(host, CLKENA, 0);
1729 mci_writel(host, CLKSRC, 0);
1730
1731 free_irq(platform_get_irq(pdev, 0), host);
1732 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1733
1734 if (host->use_dma && host->dma_ops->exit)
1735 host->dma_ops->exit(host);
1736
1737 iounmap(host->regs);
1738
1739 kfree(host);
1740 return 0;
1741 }
1742
1743 #ifdef CONFIG_PM
1744 /*
1745 * TODO: we should probably disable the clock to the card in the suspend path.
1746 */
1747 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1748 {
1749 int i, ret;
1750 struct dw_mci *host = platform_get_drvdata(pdev);
1751
1752 for (i = 0; i < host->num_slots; i++) {
1753 struct dw_mci_slot *slot = host->slot[i];
1754 if (!slot)
1755 continue;
1756 ret = mmc_suspend_host(slot->mmc);
1757 if (ret < 0) {
1758 while (--i >= 0) {
1759 slot = host->slot[i];
1760 if (slot)
1761 mmc_resume_host(host->slot[i]->mmc);
1762 }
1763 return ret;
1764 }
1765 }
1766
1767 return 0;
1768 }
1769
1770 static int dw_mci_resume(struct platform_device *pdev)
1771 {
1772 int i, ret;
1773 struct dw_mci *host = platform_get_drvdata(pdev);
1774
1775 for (i = 0; i < host->num_slots; i++) {
1776 struct dw_mci_slot *slot = host->slot[i];
1777 if (!slot)
1778 continue;
1779 ret = mmc_resume_host(host->slot[i]->mmc);
1780 if (ret < 0)
1781 return ret;
1782 }
1783
1784 return 0;
1785 }
1786 #else
1787 #define dw_mci_suspend NULL
1788 #define dw_mci_resume NULL
1789 #endif /* CONFIG_PM */
1790
1791 static struct platform_driver dw_mci_driver = {
1792 .remove = __exit_p(dw_mci_remove),
1793 .suspend = dw_mci_suspend,
1794 .resume = dw_mci_resume,
1795 .driver = {
1796 .name = "dw_mmc",
1797 },
1798 };
1799
1800 static int __init dw_mci_init(void)
1801 {
1802 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1803 }
1804
1805 static void __exit dw_mci_exit(void)
1806 {
1807 platform_driver_unregister(&dw_mci_driver);
1808 }
1809
1810 module_init(dw_mci_init);
1811 module_exit(dw_mci_exit);
1812
1813 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1814 MODULE_AUTHOR("NXP Semiconductor VietNam");
1815 MODULE_AUTHOR("Imagination Technologies Ltd");
1816 MODULE_LICENSE("GPL v2");
(deprecated) Btrfs devel tree