arch/sh/drivers/pci/pci-sh7780.c

   1 /*
   2  *      Low-Level PCI Support for the SH7780
   3  *
   4  *  Dustin McIntire (dustin@sensoria.com)
   5  *      Derived from arch/i386/kernel/pci-*.c which bore the message:
   6  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   7  *
   8  *  Ported to the new API by Paul Mundt <lethal@linux-sh.org>
   9  *  With cleanup by Paul van Gool <pvangool@mimotech.com>
  10  *
  11  *  May be copied or modified under the terms of the GNU General Public
  12  *  License.  See linux/COPYING for more information.
  13  *
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include "pci-sh4.h"
  24
  25 #define INTC_BASE       0xffd00000
  26 #define INTC_ICR0       (INTC_BASE+0x0)
  27 #define INTC_ICR1       (INTC_BASE+0x1c)
  28 #define INTC_INTPRI     (INTC_BASE+0x10)
  29 #define INTC_INTREQ     (INTC_BASE+0x24)
  30 #define INTC_INTMSK0    (INTC_BASE+0x44)
  31 #define INTC_INTMSK1    (INTC_BASE+0x48)
  32 #define INTC_INTMSK2    (INTC_BASE+0x40080)
  33 #define INTC_INTMSKCLR0 (INTC_BASE+0x64)
  34 #define INTC_INTMSKCLR1 (INTC_BASE+0x68)
  35 #define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
  36 #define INTC_INT2MSKR   (INTC_BASE+0x40038)
  37 #define INTC_INT2MSKCR  (INTC_BASE+0x4003c)
  38
  39 /*
  40  * Initialization. Try all known PCI access methods. Note that we support
  41  * using both PCI BIOS and direct access: in such cases, we use I/O ports
  42  * to access config space.
  43  *
  44  * Note that the platform specific initialization (BSC registers, and memory
  45  * space mapping) will be called via the platform defined function
  46  * pcibios_init_platform().
  47  */
  48 static int __init sh7780_pci_init(void)
  49 {
  50         unsigned int id;
  51         int ret, match = 0;
  52
  53         pr_debug("PCI: Starting intialization.\n");
  54
  55         outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
  56
  57         /* check for SH7780/SH7780R hardware */
  58         id = pci_read_reg(SH7780_PCIVID);
  59         if ((id & 0xffff) == SH7780_VENDOR_ID) {
  60                 switch ((id >> 16) & 0xffff) {
  61                 case SH7780_DEVICE_ID:
  62                 case SH7781_DEVICE_ID:
  63                 case SH7785_DEVICE_ID:
  64                         match = 1;
  65                         break;
  66                 }
  67         }
  68
  69         if (unlikely(!match)) {
  70                 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
  71                 return -ENODEV;
  72         }
  73
  74         /* Setup the INTC */
  75         if (mach_is_7780se()) {
  76                 /* ICR0: IRL=use separately */
  77                 ctrl_outl(0x00C00020, INTC_ICR0);
  78                 /* ICR1: detect low level(for 2ndcut) */
  79                 ctrl_outl(0xAAAA0000, INTC_ICR1);
  80                 /* INTPRI: priority=3(all) */
  81                 ctrl_outl(0x33333333, INTC_INTPRI);
  82         } else {
  83                 /* INTC SH-4 Mode */
  84                 ctrl_outl(0x00200000, INTC_ICR0);
  85                 /* enable PCIINTA - PCIINTD */
  86                 ctrl_outl(0x00078000, INTC_INT2MSKCR);
  87                 /* disable IRL4-7 Interrupt */
  88                 ctrl_outl(0x40000000, INTC_INTMSK1);
  89                 /* disable IRL4-7 Interrupt */
  90                 ctrl_outl(0x0000fffe, INTC_INTMSK2);
  91                 /* enable IRL0-3 Interrupt */
  92                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  93                 /* enable IRL0-3 Interrupt */
  94                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
  95         }
  96
  97         if ((ret = sh4_pci_check_direct()) != 0)
  98                 return ret;
  99
 100         return pcibios_init_platform();
 101 }
 102 core_initcall(sh7780_pci_init);
 103
 104 int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
 105 {
 106         u32 word;
 107
 108         /*
 109          * This code is unused for some boards as it is done in the
 110          * bootloader and doing it here means the MAC addresses loaded
 111          * by the bootloader get lost.
 112          */
 113         if (!(map->flags & SH4_PCIC_NO_RESET)) {
 114                 /* toggle PCI reset pin */
 115                 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
 116                 pci_write_reg(word, SH4_PCICR);
 117                 /* Wait for a long time... not 1 sec. but long enough */
 118                 mdelay(100);
 119                 word = SH4_PCICR_PREFIX;
 120                 pci_write_reg(word, SH4_PCICR);
 121         }
 122
 123         /* set the command/status bits to:
 124          * Wait Cycle Control + Parity Enable + Bus Master +
 125          * Mem space enable
 126          */
 127         pci_write_reg(0x00000046, SH7780_PCICMD);
 128
 129         /* define this host as the host bridge */
 130         word = PCI_BASE_CLASS_BRIDGE << 24;
 131         pci_write_reg(word, SH7780_PCIRID);
 132
 133         /* Set IO and Mem windows to local address
 134          * Make PCI and local address the same for easy 1 to 1 mapping
 135          * Window0 = map->window0.size @ non-cached area base = SDRAM
 136          * Window1 = map->window1.size @ cached area base = SDRAM
 137          */
 138         word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
 139         pci_write_reg(0x07f00001, SH4_PCILSR0);
 140         word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
 141         pci_write_reg(0x00000001, SH4_PCILSR1);
 142         /* Set the values on window 0 PCI config registers */
 143         word = P2SEGADDR(map->window0.base);
 144         pci_write_reg(0xa8000000, SH4_PCILAR0);
 145         pci_write_reg(0x08000000, SH7780_PCIMBAR0);
 146         /* Set the values on window 1 PCI config registers */
 147         word = P2SEGADDR(map->window1.base);
 148         pci_write_reg(0x00000000, SH4_PCILAR1);
 149         pci_write_reg(0x00000000, SH7780_PCIMBAR1);
 150
 151         /* Map IO space into PCI IO window
 152          * The IO window is 64K-PCIBIOS_MIN_IO in size
 153          * IO addresses will be translated to the
 154          * PCI IO window base address
 155          */
 156         pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
 157                  PCIBIOS_MIN_IO, (64 << 10),
 158                  SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
 159
 160         /* NOTE: I'm ignoring the PCI error IRQs for now..
 161          * TODO: add support for the internal error interrupts and
 162          * DMA interrupts...
 163          */
 164
 165         /* Apply any last-minute PCIC fixups */
 166         pci_fixup_pcic();
 167
 168         /* SH7780 init done, set central function init complete */
 169         /* use round robin mode to stop a device starving/overruning */
 170         word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
 171         pci_write_reg(word, SH4_PCICR);
 172
 173         return 1;
 174 }