drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37
  38 #define EDAC_MC_LABEL_LEN       31
  39 #define EDAC_DEVICE_NAME_LEN    31
  40 #define EDAC_ATTRIB_VALUE_LEN   15
  41 #define MC_PROC_NAME_MAX_LEN    7
  42
  43 #if PAGE_SHIFT < 20
  44 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  45 #else                           /* PAGE_SHIFT > 20 */
  46 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  47 #endif
  48
  49 #define edac_printk(level, prefix, fmt, arg...) \
  50         printk(level "EDAC " prefix ": " fmt, ##arg)
  51
  52 #define edac_printk_verbose(level, prefix, fmt, arg...) \
  53         printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt,     \
  54                __FILE__, __LINE__, ##arg)
  55
  56 #define edac_mc_printk(mci, level, fmt, arg...) \
  57         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  60         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  61
  62 /* edac_device printk */
  63 #define edac_device_printk(ctl, level, fmt, arg...) \
  64         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  65
  66 /* edac_pci printk */
  67 #define edac_pci_printk(ctl, level, fmt, arg...) \
  68         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  69
  70 /* prefixes for edac_printk() and edac_mc_printk() */
  71 #define EDAC_MC "MC"
  72 #define EDAC_PCI "PCI"
  73 #define EDAC_DEBUG "DEBUG"
  74
  75 #ifdef CONFIG_EDAC_DEBUG
  76 extern int edac_debug_level;
  77 extern const char *edac_mem_types[];
  78
  79 #ifndef CONFIG_EDAC_DEBUG_VERBOSE
  80 #define edac_debug_printk(level, fmt, arg...)                           \
  81         do {                                                            \
  82                 if (level <= edac_debug_level)                          \
  83                         edac_printk(KERN_DEBUG, EDAC_DEBUG,             \
  84                                     "%s: " fmt, __func__, ##arg);       \
  85         } while (0)
  86 #else  /* CONFIG_EDAC_DEBUG_VERBOSE */
  87 #define edac_debug_printk(level, fmt, arg...)                            \
  88         do {                                                             \
  89                 if (level <= edac_debug_level)                           \
  90                         edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \
  91                                             ##arg);                     \
  92         } while (0)
  93 #endif
  94
  95 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  96 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  97 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  98 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  99 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
 100
 101 #else                           /* !CONFIG_EDAC_DEBUG */
 102
 103 #define debugf0( ... )
 104 #define debugf1( ... )
 105 #define debugf2( ... )
 106 #define debugf3( ... )
 107 #define debugf4( ... )
 108
 109 #endif                          /* !CONFIG_EDAC_DEBUG */
 110
 111 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
 112         PCI_DEVICE_ID_ ## vend ## _ ## dev
 113
 114 #define edac_dev_name(dev) (dev)->dev_name
 115
 116 /* memory devices */
 117 enum dev_type {
 118         DEV_UNKNOWN = 0,
 119         DEV_X1,
 120         DEV_X2,
 121         DEV_X4,
 122         DEV_X8,
 123         DEV_X16,
 124         DEV_X32,                /* Do these parts exist? */
 125         DEV_X64                 /* Do these parts exist? */
 126 };
 127
 128 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 129 #define DEV_FLAG_X1             BIT(DEV_X1)
 130 #define DEV_FLAG_X2             BIT(DEV_X2)
 131 #define DEV_FLAG_X4             BIT(DEV_X4)
 132 #define DEV_FLAG_X8             BIT(DEV_X8)
 133 #define DEV_FLAG_X16            BIT(DEV_X16)
 134 #define DEV_FLAG_X32            BIT(DEV_X32)
 135 #define DEV_FLAG_X64            BIT(DEV_X64)
 136
 137 /* memory types */
 138 enum mem_type {
 139         MEM_EMPTY = 0,          /* Empty csrow */
 140         MEM_RESERVED,           /* Reserved csrow type */
 141         MEM_UNKNOWN,            /* Unknown csrow type */
 142         MEM_FPM,                /* Fast page mode */
 143         MEM_EDO,                /* Extended data out */
 144         MEM_BEDO,               /* Burst Extended data out */
 145         MEM_SDR,                /* Single data rate SDRAM */
 146         MEM_RDR,                /* Registered single data rate SDRAM */
 147         MEM_DDR,                /* Double data rate SDRAM */
 148         MEM_RDDR,               /* Registered Double data rate SDRAM */
 149         MEM_RMBS,               /* Rambus DRAM */
 150         MEM_DDR2,               /* DDR2 RAM */
 151         MEM_FB_DDR2,            /* fully buffered DDR2 */
 152         MEM_RDDR2,              /* Registered DDR2 RAM */
 153         MEM_XDR,                /* Rambus XDR */
 154         MEM_DDR3,               /* DDR3 RAM */
 155         MEM_RDDR3,              /* Registered DDR3 RAM */
 156 };
 157
 158 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 159 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 160 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 161 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 162 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 163 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 164 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 165 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 166 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 167 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 168 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 169 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 170 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 171 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 172 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 173 #define MEM_FLAG_DDR3            BIT(MEM_DDR3)
 174 #define MEM_FLAG_RDDR3           BIT(MEM_RDDR3)
 175
 176 /* chipset Error Detection and Correction capabilities and mode */
 177 enum edac_type {
 178         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 179         EDAC_NONE,              /* Doesnt support ECC */
 180         EDAC_RESERVED,          /* Reserved ECC type */
 181         EDAC_PARITY,            /* Detects parity errors */
 182         EDAC_EC,                /* Error Checking - no correction */
 183         EDAC_SECDED,            /* Single bit error correction, Double detection */
 184         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 185         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 186         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 187         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 188 };
 189
 190 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 191 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 192 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 193 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 194 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 195 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 196 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 197 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 198 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 199
 200 /* scrubbing capabilities */
 201 enum scrub_type {
 202         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 203         SCRUB_NONE,             /* No scrubber */
 204         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 205         SCRUB_SW_SRC,           /* Software scrub only errors */
 206         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 207         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 208         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 209         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 210         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 211         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 212 };
 213
 214 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 215 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 216 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 217 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 218 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 219 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 220 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 221 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 222
 223 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 224
 225 /* EDAC internal operation states */
 226 #define OP_ALLOC                0x100
 227 #define OP_RUNNING_POLL         0x201
 228 #define OP_RUNNING_INTERRUPT    0x202
 229 #define OP_RUNNING_POLL_INTR    0x203
 230 #define OP_OFFLINE              0x300
 231
 232 /*
 233  * There are several things to be aware of that aren't at all obvious:
 234  *
 235  *
 236  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 237  *
 238  * These are some of the many terms that are thrown about that don't always
 239  * mean what people think they mean (Inconceivable!).  In the interest of
 240  * creating a common ground for discussion, terms and their definitions
 241  * will be established.
 242  *
 243  * Memory devices:      The individual chip on a memory stick.  These devices
 244  *                      commonly output 4 and 8 bits each.  Grouping several
 245  *                      of these in parallel provides 64 bits which is common
 246  *                      for a memory stick.
 247  *
 248  * Memory Stick:        A printed circuit board that agregates multiple
 249  *                      memory devices in parallel.  This is the atomic
 250  *                      memory component that is purchaseable by Joe consumer
 251  *                      and loaded into a memory socket.
 252  *
 253  * Socket:              A physical connector on the motherboard that accepts
 254  *                      a single memory stick.
 255  *
 256  * Channel:             Set of memory devices on a memory stick that must be
 257  *                      grouped in parallel with one or more additional
 258  *                      channels from other memory sticks.  This parallel
 259  *                      grouping of the output from multiple channels are
 260  *                      necessary for the smallest granularity of memory access.
 261  *                      Some memory controllers are capable of single channel -
 262  *                      which means that memory sticks can be loaded
 263  *                      individually.  Other memory controllers are only
 264  *                      capable of dual channel - which means that memory
 265  *                      sticks must be loaded as pairs (see "socket set").
 266  *
 267  * Chip-select row:     All of the memory devices that are selected together.
 268  *                      for a single, minimum grain of memory access.
 269  *                      This selects all of the parallel memory devices across
 270  *                      all of the parallel channels.  Common chip-select rows
 271  *                      for single channel are 64 bits, for dual channel 128
 272  *                      bits.
 273  *
 274  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 275  *                      Motherboards commonly drive two chip-select pins to
 276  *                      a memory stick. A single-ranked stick, will occupy
 277  *                      only one of those rows. The other will be unused.
 278  *
 279  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 280  *                      access different sets of memory devices.  The two
 281  *                      rows cannot be accessed concurrently.
 282  *
 283  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 284  *                      A double-sided stick has two chip-select rows which
 285  *                      access different sets of memory devices.  The two
 286  *                      rows cannot be accessed concurrently.  "Double-sided"
 287  *                      is irrespective of the memory devices being mounted
 288  *                      on both sides of the memory stick.
 289  *
 290  * Socket set:          All of the memory sticks that are required for
 291  *                      a single memory access or all of the memory sticks
 292  *                      spanned by a chip-select row.  A single socket set
 293  *                      has two chip-select rows and if double-sided sticks
 294  *                      are used these will occupy those chip-select rows.
 295  *
 296  * Bank:                This term is avoided because it is unclear when
 297  *                      needing to distinguish between chip-select rows and
 298  *                      socket sets.
 299  *
 300  * Controller pages:
 301  *
 302  * Physical pages:
 303  *
 304  * Virtual pages:
 305  *
 306  *
 307  * STRUCTURE ORGANIZATION AND CHOICES
 308  *
 309  *
 310  *
 311  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 312  */
 313
 314 struct channel_info {
 315         int chan_idx;           /* channel index */
 316         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 317         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 318         struct csrow_info *csrow;       /* the parent */
 319 };
 320
 321 struct csrow_info {
 322         unsigned long first_page;       /* first page number in dimm */
 323         unsigned long last_page;        /* last page number in dimm */
 324         unsigned long page_mask;        /* used for interleaving -
 325                                          * 0UL for non intlv
 326                                          */
 327         u32 nr_pages;           /* number of pages in csrow */
 328         u32 grain;              /* granularity of reported error in bytes */
 329         int csrow_idx;          /* the chip-select row */
 330         enum dev_type dtype;    /* memory device type */
 331         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 332         u32 ce_count;           /* Correctable Errors for this csrow */
 333         enum mem_type mtype;    /* memory csrow type */
 334         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 335         struct mem_ctl_info *mci;       /* the parent */
 336
 337         struct kobject kobj;    /* sysfs kobject for this csrow */
 338
 339         /* channel information for this csrow */
 340         u32 nr_channels;
 341         struct channel_info *channels;
 342 };
 343
 344 struct mcidev_sysfs_group {
 345         const char *name;                               /* group name */
 346         struct mcidev_sysfs_attribute *mcidev_attr;     /* group attributes */
 347 };
 348
 349 struct mcidev_sysfs_group_kobj {
 350         struct list_head list;          /* list for all instances within a mc */
 351
 352         struct kobject kobj;            /* kobj for the group */
 353
 354         struct mcidev_sysfs_group *grp; /* group description table */
 355         struct mem_ctl_info *mci;       /* the parent */
 356 };
 357
 358 /* mcidev_sysfs_attribute structure
 359  *      used for driver sysfs attributes and in mem_ctl_info
 360  *      sysfs top level entries
 361  */
 362 struct mcidev_sysfs_attribute {
 363         /* It should use either attr or grp */
 364         struct attribute attr;
 365         struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
 366
 367         /* Ops for show/store values at the attribute - not used on group */
 368         ssize_t (*show)(struct mem_ctl_info *,char *);
 369         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 370 };
 371
 372 /* MEMORY controller information structure
 373  */
 374 struct mem_ctl_info {
 375         struct list_head link;  /* for global list of mem_ctl_info structs */
 376
 377         struct module *owner;   /* Module owner of this control struct */
 378
 379         unsigned long mtype_cap;        /* memory types supported by mc */
 380         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 381         unsigned long edac_cap; /* configuration capabilities - this is
 382                                  * closely related to edac_ctl_cap.  The
 383                                  * difference is that the controller may be
 384                                  * capable of s4ecd4ed which would be listed
 385                                  * in edac_ctl_cap, but if channels aren't
 386                                  * capable of s4ecd4ed then the edac_cap would
 387                                  * not have that capability.
 388                                  */
 389         unsigned long scrub_cap;        /* chipset scrub capabilities */
 390         enum scrub_type scrub_mode;     /* current scrub mode */
 391
 392         /* Translates sdram memory scrub rate given in bytes/sec to the
 393            internal representation and configures whatever else needs
 394            to be configured.
 395          */
 396         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 397
 398         /* Get the current sdram memory scrub rate from the internal
 399            representation and converts it to the closest matching
 400            bandwith in bytes/sec.
 401          */
 402         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 403
 404
 405         /* pointer to edac checking routine */
 406         void (*edac_check) (struct mem_ctl_info * mci);
 407
 408         /*
 409          * Remaps memory pages: controller pages to physical pages.
 410          * For most MC's, this will be NULL.
 411          */
 412         /* FIXME - why not send the phys page to begin with? */
 413         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 414                                            unsigned long page);
 415         int mc_idx;
 416         int nr_csrows;
 417         struct csrow_info *csrows;
 418         /*
 419          * FIXME - what about controllers on other busses? - IDs must be
 420          * unique.  dev pointer should be sufficiently unique, but
 421          * BUS:SLOT.FUNC numbers may not be unique.
 422          */
 423         struct device *dev;
 424         const char *mod_name;
 425         const char *mod_ver;
 426         const char *ctl_name;
 427         const char *dev_name;
 428         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 429         void *pvt_info;
 430         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 431         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 432         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 433         u32 ce_count;           /* Total Correctable Errors for this MC */
 434         unsigned long start_time;       /* mci load start time (in jiffies) */
 435
 436         /* this stuff is for safe removal of mc devices from global list while
 437          * NMI handlers may be traversing list
 438          */
 439         struct rcu_head rcu;
 440         struct completion complete;
 441
 442         /* edac sysfs device control */
 443         struct kobject edac_mci_kobj;
 444
 445         /* list for all grp instances within a mc */
 446         struct list_head grp_kobj_list;
 447
 448         /* Additional top controller level attributes, but specified
 449          * by the low level driver.
 450          *
 451          * Set by the low level driver to provide attributes at the
 452          * controller level, same level as 'ue_count' and 'ce_count' above.
 453          * An array of structures, NULL terminated
 454          *
 455          * If attributes are desired, then set to array of attributes
 456          * If no attributes are desired, leave NULL
 457          */
 458         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 459
 460         /* work struct for this MC */
 461         struct delayed_work work;
 462
 463         /* the internal state of this controller instance */
 464         int op_state;
 465 };
 466
 467 /*
 468  * The following are the structures to provide for a generic
 469  * or abstract 'edac_device'. This set of structures and the
 470  * code that implements the APIs for the same, provide for
 471  * registering EDAC type devices which are NOT standard memory.
 472  *
 473  * CPU caches (L1 and L2)
 474  * DMA engines
 475  * Core CPU swithces
 476  * Fabric switch units
 477  * PCIe interface controllers
 478  * other EDAC/ECC type devices that can be monitored for
 479  * errors, etc.
 480  *
 481  * It allows for a 2 level set of hiearchry. For example:
 482  *
 483  * cache could be composed of L1, L2 and L3 levels of cache.
 484  * Each CPU core would have its own L1 cache, while sharing
 485  * L2 and maybe L3 caches.
 486  *
 487  * View them arranged, via the sysfs presentation:
 488  * /sys/devices/system/edac/..
 489  *
 490  *      mc/             <existing memory device directory>
 491  *      cpu/cpu0/..     <L1 and L2 block directory>
 492  *              /L1-cache/ce_count
 493  *                       /ue_count
 494  *              /L2-cache/ce_count
 495  *                       /ue_count
 496  *      cpu/cpu1/..     <L1 and L2 block directory>
 497  *              /L1-cache/ce_count
 498  *                       /ue_count
 499  *              /L2-cache/ce_count
 500  *                       /ue_count
 501  *      ...
 502  *
 503  *      the L1 and L2 directories would be "edac_device_block's"
 504  */
 505
 506 struct edac_device_counter {
 507         u32 ue_count;
 508         u32 ce_count;
 509 };
 510
 511 /* forward reference */
 512 struct edac_device_ctl_info;
 513 struct edac_device_block;
 514
 515 /* edac_dev_sysfs_attribute structure
 516  *      used for driver sysfs attributes in mem_ctl_info
 517  *      for extra controls and attributes:
 518  *              like high level error Injection controls
 519  */
 520 struct edac_dev_sysfs_attribute {
 521         struct attribute attr;
 522         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 523         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 524 };
 525
 526 /* edac_dev_sysfs_block_attribute structure
 527  *
 528  *      used in leaf 'block' nodes for adding controls/attributes
 529  *
 530  *      each block in each instance of the containing control structure
 531  *      can have an array of the following. The show and store functions
 532  *      will be filled in with the show/store function in the
 533  *      low level driver.
 534  *
 535  *      The 'value' field will be the actual value field used for
 536  *      counting
 537  */
 538 struct edac_dev_sysfs_block_attribute {
 539         struct attribute attr;
 540         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 541         ssize_t (*store)(struct kobject *, struct attribute *,
 542                         const char *, size_t);
 543         struct edac_device_block *block;
 544
 545         unsigned int value;
 546 };
 547
 548 /* device block control structure */
 549 struct edac_device_block {
 550         struct edac_device_instance *instance;  /* Up Pointer */
 551         char name[EDAC_DEVICE_NAME_LEN + 1];
 552
 553         struct edac_device_counter counters;    /* basic UE and CE counters */
 554
 555         int nr_attribs;         /* how many attributes */
 556
 557         /* this block's attributes, could be NULL */
 558         struct edac_dev_sysfs_block_attribute *block_attributes;
 559
 560         /* edac sysfs device control */
 561         struct kobject kobj;
 562 };
 563
 564 /* device instance control structure */
 565 struct edac_device_instance {
 566         struct edac_device_ctl_info *ctl;       /* Up pointer */
 567         char name[EDAC_DEVICE_NAME_LEN + 4];
 568
 569         struct edac_device_counter counters;    /* instance counters */
 570
 571         u32 nr_blocks;          /* how many blocks */
 572         struct edac_device_block *blocks;       /* block array */
 573
 574         /* edac sysfs device control */
 575         struct kobject kobj;
 576 };
 577
 578
 579 /*
 580  * Abstract edac_device control info structure
 581  *
 582  */
 583 struct edac_device_ctl_info {
 584         /* for global list of edac_device_ctl_info structs */
 585         struct list_head link;
 586
 587         struct module *owner;   /* Module owner of this control struct */
 588
 589         int dev_idx;
 590
 591         /* Per instance controls for this edac_device */
 592         int log_ue;             /* boolean for logging UEs */
 593         int log_ce;             /* boolean for logging CEs */
 594         int panic_on_ue;        /* boolean for panic'ing on an UE */
 595         unsigned poll_msec;     /* number of milliseconds to poll interval */
 596         unsigned long delay;    /* number of jiffies for poll_msec */
 597
 598         /* Additional top controller level attributes, but specified
 599          * by the low level driver.
 600          *
 601          * Set by the low level driver to provide attributes at the
 602          * controller level, same level as 'ue_count' and 'ce_count' above.
 603          * An array of structures, NULL terminated
 604          *
 605          * If attributes are desired, then set to array of attributes
 606          * If no attributes are desired, leave NULL
 607          */
 608         struct edac_dev_sysfs_attribute *sysfs_attributes;
 609
 610         /* pointer to main 'edac' class in sysfs */
 611         struct sysdev_class *edac_class;
 612
 613         /* the internal state of this controller instance */
 614         int op_state;
 615         /* work struct for this instance */
 616         struct delayed_work work;
 617
 618         /* pointer to edac polling checking routine:
 619          *      If NOT NULL: points to polling check routine
 620          *      If NULL: Then assumes INTERRUPT operation, where
 621          *              MC driver will receive events
 622          */
 623         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 624
 625         struct device *dev;     /* pointer to device structure */
 626
 627         const char *mod_name;   /* module name */
 628         const char *ctl_name;   /* edac controller  name */
 629         const char *dev_name;   /* pci/platform/etc... name */
 630
 631         void *pvt_info;         /* pointer to 'private driver' info */
 632
 633         unsigned long start_time;       /* edac_device load start time (jiffies) */
 634
 635         /* these are for safe removal of mc devices from global list while
 636          * NMI handlers may be traversing list
 637          */
 638         struct rcu_head rcu;
 639         struct completion removal_complete;
 640
 641         /* sysfs top name under 'edac' directory
 642          * and instance name:
 643          *      cpu/cpu0/...
 644          *      cpu/cpu1/...
 645          *      cpu/cpu2/...
 646          *      ...
 647          */
 648         char name[EDAC_DEVICE_NAME_LEN + 1];
 649
 650         /* Number of instances supported on this control structure
 651          * and the array of those instances
 652          */
 653         u32 nr_instances;
 654         struct edac_device_instance *instances;
 655
 656         /* Event counters for the this whole EDAC Device */
 657         struct edac_device_counter counters;
 658
 659         /* edac sysfs device control for the 'name'
 660          * device this structure controls
 661          */
 662         struct kobject kobj;
 663 };
 664
 665 /* To get from the instance's wq to the beginning of the ctl structure */
 666 #define to_edac_mem_ctl_work(w) \
 667                 container_of(w, struct mem_ctl_info, work)
 668
 669 #define to_edac_device_ctl_work(w) \
 670                 container_of(w,struct edac_device_ctl_info,work)
 671
 672 /*
 673  * The alloc() and free() functions for the 'edac_device' control info
 674  * structure. A MC driver will allocate one of these for each edac_device
 675  * it is going to control/register with the EDAC CORE.
 676  */
 677 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 678                 unsigned sizeof_private,
 679                 char *edac_device_name, unsigned nr_instances,
 680                 char *edac_block_name, unsigned nr_blocks,
 681                 unsigned offset_value,
 682                 struct edac_dev_sysfs_block_attribute *block_attributes,
 683                 unsigned nr_attribs,
 684                 int device_index);
 685
 686 /* The offset value can be:
 687  *      -1 indicating no offset value
 688  *      0 for zero-based block numbers
 689  *      1 for 1-based block number
 690  *      other for other-based block number
 691  */
 692 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 693
 694 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 695
 696 #ifdef CONFIG_PCI
 697
 698 struct edac_pci_counter {
 699         atomic_t pe_count;
 700         atomic_t npe_count;
 701 };
 702
 703 /*
 704  * Abstract edac_pci control info structure
 705  *
 706  */
 707 struct edac_pci_ctl_info {
 708         /* for global list of edac_pci_ctl_info structs */
 709         struct list_head link;
 710
 711         int pci_idx;
 712
 713         struct sysdev_class *edac_class;        /* pointer to class */
 714
 715         /* the internal state of this controller instance */
 716         int op_state;
 717         /* work struct for this instance */
 718         struct delayed_work work;
 719
 720         /* pointer to edac polling checking routine:
 721          *      If NOT NULL: points to polling check routine
 722          *      If NULL: Then assumes INTERRUPT operation, where
 723          *              MC driver will receive events
 724          */
 725         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 726
 727         struct device *dev;     /* pointer to device structure */
 728
 729         const char *mod_name;   /* module name */
 730         const char *ctl_name;   /* edac controller  name */
 731         const char *dev_name;   /* pci/platform/etc... name */
 732
 733         void *pvt_info;         /* pointer to 'private driver' info */
 734
 735         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 736
 737         /* these are for safe removal of devices from global list while
 738          * NMI handlers may be traversing list
 739          */
 740         struct rcu_head rcu;
 741         struct completion complete;
 742
 743         /* sysfs top name under 'edac' directory
 744          * and instance name:
 745          *      cpu/cpu0/...
 746          *      cpu/cpu1/...
 747          *      cpu/cpu2/...
 748          *      ...
 749          */
 750         char name[EDAC_DEVICE_NAME_LEN + 1];
 751
 752         /* Event counters for the this whole EDAC Device */
 753         struct edac_pci_counter counters;
 754
 755         /* edac sysfs device control for the 'name'
 756          * device this structure controls
 757          */
 758         struct kobject kobj;
 759         struct completion kobj_complete;
 760 };
 761
 762 #define to_edac_pci_ctl_work(w) \
 763                 container_of(w, struct edac_pci_ctl_info,work)
 764
 765 /* write all or some bits in a byte-register*/
 766 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 767                                    u8 mask)
 768 {
 769         if (mask != 0xff) {
 770                 u8 buf;
 771
 772                 pci_read_config_byte(pdev, offset, &buf);
 773                 value &= mask;
 774                 buf &= ~mask;
 775                 value |= buf;
 776         }
 777
 778         pci_write_config_byte(pdev, offset, value);
 779 }
 780
 781 /* write all or some bits in a word-register*/
 782 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 783                                     u16 value, u16 mask)
 784 {
 785         if (mask != 0xffff) {
 786                 u16 buf;
 787
 788                 pci_read_config_word(pdev, offset, &buf);
 789                 value &= mask;
 790                 buf &= ~mask;
 791                 value |= buf;
 792         }
 793
 794         pci_write_config_word(pdev, offset, value);
 795 }
 796
 797 /*
 798  * pci_write_bits32
 799  *
 800  * edac local routine to do pci_write_config_dword, but adds
 801  * a mask parameter. If mask is all ones, ignore the mask.
 802  * Otherwise utilize the mask to isolate specified bits
 803  *
 804  * write all or some bits in a dword-register
 805  */
 806 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 807                                     u32 value, u32 mask)
 808 {
 809         if (mask != 0xffffffff) {
 810                 u32 buf;
 811
 812                 pci_read_config_dword(pdev, offset, &buf);
 813                 value &= mask;
 814                 buf &= ~mask;
 815                 value |= buf;
 816         }
 817
 818         pci_write_config_dword(pdev, offset, value);
 819 }
 820
 821 #endif                          /* CONFIG_PCI */
 822
 823 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 824                                           unsigned nr_chans, int edac_index);
 825 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 826 extern void edac_mc_free(struct mem_ctl_info *mci);
 827 extern struct mem_ctl_info *edac_mc_find(int idx);
 828 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 829 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 830                                       unsigned long page);
 831
 832 /*
 833  * The no info errors are used when error overflows are reported.
 834  * There are a limited number of error logging registers that can
 835  * be exausted.  When all registers are exhausted and an additional
 836  * error occurs then an error overflow register records that an
 837  * error occured and the type of error, but doesn't have any
 838  * further information.  The ce/ue versions make for cleaner
 839  * reporting logic and function interface - reduces conditional
 840  * statement clutter and extra function arguments.
 841  */
 842 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 843                               unsigned long page_frame_number,
 844                               unsigned long offset_in_page,
 845                               unsigned long syndrome, int row, int channel,
 846                               const char *msg);
 847 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 848                                       const char *msg);
 849 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 850                               unsigned long page_frame_number,
 851                               unsigned long offset_in_page, int row,
 852                               const char *msg);
 853 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 854                                       const char *msg);
 855 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 856                                   unsigned int channel0, unsigned int channel1,
 857                                   char *msg);
 858 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 859                                   unsigned int channel, char *msg);
 860
 861 /*
 862  * edac_device APIs
 863  */
 864 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 865 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 866 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 867                                 int inst_nr, int block_nr, const char *msg);
 868 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 869                                 int inst_nr, int block_nr, const char *msg);
 870 extern int edac_device_alloc_index(void);
 871
 872 /*
 873  * edac_pci APIs
 874  */
 875 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 876                                 const char *edac_pci_name);
 877
 878 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 879
 880 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 881                                 unsigned long value);
 882
 883 extern int edac_pci_alloc_index(void);
 884 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 885 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 886
 887 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 888                                 struct device *dev,
 889                                 const char *mod_name);
 890
 891 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 892 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 893 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 894
 895 /*
 896  * edac misc APIs
 897  */
 898 extern char *edac_op_state_to_string(int op_state);
 899
 900 #endif                          /* _EDAC_CORE_H_ */